Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	362610	1			T1	17		T2	39		T3	27
all_values[1]	362610	1			T1	17		T2	39		T3	27
all_values[2]	362610	1			T1	17		T2	39		T3	27
all_values[3]	362610	1			T1	17		T2	39		T3	27

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

722303

1

T2

70

T3

52

T12

62

auto[1]

728137

1

T1

68

T2

86

T3

56

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

852068

1

T1

60

T2

83

T3

95

auto[1]

598372

1

T1

8

T2

73

T3

13

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	101195	1			T2	9		T3	7		T12	6
all_values[0]	auto[0]	auto[1]	78725	1			T2	8		T3	7		T12	5
all_values[0]	auto[1]	auto[0]	103177	1			T1	13		T2	11		T3	7
all_values[0]	auto[1]	auto[1]	79513	1			T1	4		T2	11		T3	6
all_values[1]	auto[0]	auto[0]	106599	1			T2	12		T3	7		T12	15
all_values[1]	auto[0]	auto[1]	74123	1			T2	11		T7	252		T8	309
all_values[1]	auto[1]	auto[0]	107928	1			T1	17		T2	8		T3	20
all_values[1]	auto[1]	auto[1]	73960	1			T2	8		T7	247		T8	295
all_values[2]	auto[0]	auto[0]	107903	1			T2	11		T3	19		T12	21
all_values[2]	auto[0]	auto[1]	73484	1			T2	5		T7	1		T8	268
all_values[2]	auto[1]	auto[0]	108240	1			T1	13		T2	12		T3	8
all_values[2]	auto[1]	auto[1]	72983	1			T1	4		T2	11		T8	323
all_values[3]	auto[0]	auto[0]	107542	1			T2	7		T3	12		T12	15
all_values[3]	auto[0]	auto[1]	72732	1			T2	7		T8	280		T15	11
all_values[3]	auto[1]	auto[0]	109484	1			T1	17		T2	13		T3	15
all_values[3]	auto[1]	auto[1]	72852	1			T2	12		T7	2		T8	311