Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	362610	1			T1	17		T2	39		T3	27
all_pins[1]	362610	1			T1	17		T2	39		T3	27
all_pins[2]	362610	1			T1	17		T2	39		T3	27
all_pins[3]	362610	1			T1	17		T2	39		T3	27

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1151132	1			T1	60		T2	114		T3	102
values[0x1]	299308	1			T1	8		T2	42		T3	6
transitions[0x0=>0x1]	199010	1			T1	8		T2	25		T3	5
transitions[0x1=>0x0]	199288	1			T1	8		T2	25		T3	6

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	283097	1			T1	13		T2	28		T3	21
all_pins[0]	values[0x1]	79513	1			T1	4		T2	11		T3	6
all_pins[0]	transitions[0x0=>0x1]	78874	1			T1	4		T2	11		T3	5
all_pins[0]	transitions[0x1=>0x0]	72491	1			T2	12		T7	1		T8	311
all_pins[1]	values[0x0]	288650	1			T1	17		T2	31		T3	27
all_pins[1]	values[0x1]	73960	1			T2	8		T7	247		T8	295
all_pins[1]	transitions[0x0=>0x1]	40149	1			T2	5		T7	158		T8	163
all_pins[1]	transitions[0x1=>0x0]	45702	1			T1	4		T2	8		T3	6
all_pins[2]	values[0x0]	289627	1			T1	13		T2	28		T3	27
all_pins[2]	values[0x1]	72983	1			T1	4		T2	11		T8	323
all_pins[2]	transitions[0x0=>0x1]	40102	1			T1	4		T2	7		T8	152
all_pins[2]	transitions[0x1=>0x0]	41079	1			T2	4		T7	247		T8	124
all_pins[3]	values[0x0]	289758	1			T1	17		T2	27		T3	27
all_pins[3]	values[0x1]	72852	1			T2	12		T7	2		T8	311
all_pins[3]	transitions[0x0=>0x1]	39885	1			T2	2		T7	2		T8	148
all_pins[3]	transitions[0x1=>0x0]	40016	1			T1	4		T2	1		T8	160