Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	269	1			T178	4		T179	4		T180	4
all_values[1]	269	1			T178	4		T179	4		T180	4
all_values[2]	269	1			T178	4		T179	4		T180	4
all_values[3]	269	1			T178	4		T179	4		T180	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

596

1

T178

6

T179

12

T180

7

auto[1]

480

1

T178

10

T179

4

T180

9

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

428

1

T178

6

T179

5

T180

4

auto[1]

648

1

T178

10

T179

11

T180

12

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

643

1

T178

10

T179

9

T180

10

auto[1]

433

1

T178

6

T179

7

T180

6

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	24	0	24	100.00
Automatically Generated Cross Bins	24	0	24	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

58

1

T178

1

T362

1

T257

2

all_values[0]

auto[0]

auto[0]

auto[1]

33

1

T179

2

T362

1

T363

1

all_values[0]

auto[0]

auto[1]

auto[0]

42

1

T257

5

T363

3

T364

1

all_values[0]

auto[0]

auto[1]

auto[1]

26

1

T178

1

T179

1

T180

1

all_values[0]

auto[1]

auto[0]

auto[1]

52

1

T179

1

T362

2

T363

1

all_values[0]

auto[1]

auto[1]

auto[1]

58

1

T178

2

T180

3

T363

1

all_values[1]

auto[0]

auto[0]

auto[0]

58

1

T178

1

T179

2

T257

1

all_values[1]

auto[0]

auto[0]

auto[1]

31

1

T180

1

T362

1

T363

1

all_values[1]

auto[0]

auto[1]

auto[0]

35

1

T180

2

T257

2

T363

2

all_values[1]

auto[0]

auto[1]

auto[1]

35

1

T178

1

T362

1

T364

1

all_values[1]

auto[1]

auto[0]

auto[1]

67

1

T179

1

T180

1

T362

2

all_values[1]

auto[1]

auto[1]

auto[1]

43

1

T178

2

T179

1

T257

3

all_values[2]

auto[0]

auto[0]

auto[0]

65

1

T178

1

T179

1

T180

2

all_values[2]

auto[0]

auto[0]

auto[1]

27

1

T180

1

T257

2

T365

1

all_values[2]

auto[0]

auto[1]

auto[0]

64

1

T179

1

T362

1

T257

1

all_values[2]

auto[0]

auto[1]

auto[1]

14

1

T178

2

T366

1

T367

1

all_values[2]

auto[1]

auto[0]

auto[1]

62

1

T179

2

T180

1

T362

1

all_values[2]

auto[1]

auto[1]

auto[1]

37

1

T178

1

T362

2

T257

1

all_values[3]

auto[0]

auto[0]

auto[0]

60

1

T178

2

T179

1

T257

2

all_values[3]

auto[0]

auto[0]

auto[1]

27

1

T179

1

T180

1

T362

1

all_values[3]

auto[0]

auto[1]

auto[0]

46

1

T178

1

T257

2

T363

2

all_values[3]

auto[0]

auto[1]

auto[1]

22

1

T180

2

T362

1

T363

2

all_values[3]

auto[1]

auto[0]

auto[1]

56

1

T178

1

T179

1

T362

1

all_values[3]

auto[1]

auto[1]

auto[1]

58

1

T179

1

T180

1

T362

1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal