Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	86060	1			T8	690		T19	120		T20	201
accum_cnt_1000	233378	1			T7	1328		T8	1433		T15	1
accum_cnt_100	29252	1			T2	10		T7	74		T8	61
accum_cnt_50	76396	1			T2	22		T3	11		T12	12
accum_cnt_10	204031	1			T1	19		T2	46		T3	3
accum_cnt_0	399183	1			T1	25		T2	74		T3	54

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	267396	1			T1	11		T2	38		T3	17
class_index[0x1]	267396	1			T1	11		T2	38		T3	17
class_index[0x2]	267396	1			T1	11		T2	38		T3	17
class_index[0x3]	267396	1			T1	11		T2	38		T3	17

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	23079	1			T5	383		T51	288		T52	391
class_index[0x0]	accum_cnt_1000	70125	1			T7	1328		T5	662		T21	44
class_index[0x0]	accum_cnt_100	10702	1			T2	10		T7	74		T4	5
class_index[0x0]	accum_cnt_50	25514	1			T2	22		T3	11		T12	12
class_index[0x0]	accum_cnt_10	46042	1			T1	8		T2	6		T3	3
class_index[0x0]	accum_cnt_0	82706	1			T1	3		T3	3		T12	3
class_index[0x1]	accum_cnt_2000	21213	1			T8	219		T20	201		T71	609
class_index[0x1]	accum_cnt_1000	52862	1			T8	212		T20	194		T16	681
class_index[0x1]	accum_cnt_100	5675	1			T8	6		T4	3		T20	15
class_index[0x1]	accum_cnt_50	13888	1			T8	9		T13	28		T46	14
class_index[0x1]	accum_cnt_10	59696	1			T2	38		T8	4		T13	7
class_index[0x1]	accum_cnt_0	102752	1			T1	11		T3	17		T12	22
class_index[0x2]	accum_cnt_2000	24100	1			T8	270		T5	481		T51	524
class_index[0x2]	accum_cnt_1000	63962	1			T8	565		T15	1		T22	11
class_index[0x2]	accum_cnt_100	7329	1			T8	31		T5	36		T16	133
class_index[0x2]	accum_cnt_50	16574	1			T8	19		T15	19		T14	698
class_index[0x2]	accum_cnt_10	46655	1			T1	11		T2	1		T8	17
class_index[0x2]	accum_cnt_0	96365	1			T2	37		T3	17		T12	22
class_index[0x3]	accum_cnt_2000	17668	1			T8	201		T19	120		T240	283
class_index[0x3]	accum_cnt_1000	46429	1			T8	656		T19	107		T4	8
class_index[0x3]	accum_cnt_100	5546	1			T8	24		T19	10		T4	18
class_index[0x3]	accum_cnt_50	20420	1			T8	8		T13	26		T22	3
class_index[0x3]	accum_cnt_10	51638	1			T2	1		T7	230		T8	17
class_index[0x3]	accum_cnt_0	117360	1			T1	11		T2	37		T3	17