Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	4869	1			T20	16		T5	107		T25	53
alert[0x1]	8340	1			T8	901		T22	4		T19	42
alert[0x2]	8594	1			T85	910		T132	1246		T38	20
alert[0x3]	6148	1			T19	21		T17	1		T25	250
alert[0x4]	5577	1			T22	2		T20	45		T5	331
alert[0x5]	5861	1			T20	75		T52	1		T25	76
alert[0x6]	2724	1			T1	1		T19	43		T4	2
alert[0x7]	5419	1			T20	7		T90	1		T119	512
alert[0x8]	6883	1			T8	8		T19	101		T5	68
alert[0x9]	5028	1			T15	1		T20	612		T79	129
alert[0xa]	8583	1			T8	84		T15	1		T19	42
alert[0xb]	6782	1			T8	1882		T22	7		T19	4
alert[0xc]	10626	1			T8	339		T22	2		T5	53
alert[0xd]	5645	1			T5	31		T25	260		T90	1
alert[0xe]	12051	1			T8	51		T19	311		T50	1
alert[0xf]	4627	1			T8	174		T20	17		T82	29
alert[0x10]	6305	1			T15	2		T19	942		T5	15
alert[0x11]	9161	1			T8	453		T19	127		T25	87
alert[0x12]	11307	1			T19	3728		T5	37		T28	4
alert[0x13]	2899	1			T19	469		T5	32		T16	1
alert[0x14]	4009	1			T242	1		T307	1		T119	489
alert[0x15]	4131	1			T8	16		T19	100		T52	1
alert[0x16]	4199	1			T4	1		T25	25		T240	615
alert[0x17]	6078	1			T8	2488		T20	305		T5	40
alert[0x18]	8283	1			T8	19		T20	366		T17	1
alert[0x19]	6365	1			T8	39		T20	23		T25	40
alert[0x1a]	3490	1			T7	1		T20	148		T5	42
alert[0x1b]	3650	1			T8	36		T5	1		T50	2
alert[0x1c]	3636	1			T25	335		T18	1		T242	1
alert[0x1d]	2287	1			T19	47		T20	446		T5	9
alert[0x1e]	3090	1			T8	48		T19	306		T20	75
alert[0x1f]	7480	1			T1	1		T19	674		T20	51
alert[0x20]	8660	1			T8	382		T20	117		T17	1
alert[0x21]	7480	1			T79	216		T82	169		T241	4
alert[0x22]	8874	1			T19	32		T5	7		T310	1
alert[0x23]	6300	1			T5	322		T18	1		T90	1
alert[0x24]	8233	1			T19	17		T5	31		T25	1
alert[0x25]	4432	1			T8	39		T5	66		T69	1
alert[0x26]	13009	1			T8	24		T19	97		T20	303
alert[0x27]	6042	1			T19	265		T20	9		T90	2
alert[0x28]	11672	1			T22	22		T19	3748		T16	1
alert[0x29]	7690	1			T69	1		T18	1		T242	1
alert[0x2a]	14169	1			T19	15		T4	16		T20	32
alert[0x2b]	5432	1			T8	38		T20	32		T5	18
alert[0x2c]	14997	1			T8	163		T79	251		T81	6
alert[0x2d]	9181	1			T19	6		T25	168		T307	1
alert[0x2e]	7937	1			T19	676		T20	85		T5	70
alert[0x2f]	5240	1			T20	420		T5	59		T25	171
alert[0x30]	2759	1			T8	244		T18	2		T90	1
alert[0x31]	4596	1			T20	221		T25	3		T85	1170
alert[0x32]	7969	1			T8	100		T19	523		T25	63
alert[0x33]	3522	1			T20	27		T50	4		T310	1
alert[0x34]	3045	1			T1	2		T8	188		T19	35
alert[0x35]	3539	1			T8	417		T22	7		T19	39
alert[0x36]	10544	1			T19	1		T50	1		T69	4
alert[0x37]	7770	1			T8	1		T19	1512		T50	3
alert[0x38]	1770	1			T5	15		T79	38		T82	70
alert[0x39]	6761	1			T1	1		T22	44		T19	213
alert[0x3a]	4292	1			T20	1373		T82	64		T132	12
alert[0x3b]	2948	1			T8	93		T19	77		T5	19
alert[0x3c]	6574	1			T8	32		T19	176		T4	3
alert[0x3d]	12342	1			T8	51		T22	10		T20	458
alert[0x3e]	15341	1			T8	27		T5	8		T54	6
alert[0x3f]	4785	1			T20	33		T5	79		T25	5
alert[0x40]	6396	1			T8	436		T19	26		T5	171

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	127967	1			T1	4		T8	8571		T15	4
class_i[0x1]	136534	1			T8	68		T20	6906		T50	3
class_i[0x2]	53901	1			T1	1		T8	29		T16	2
class_i[0x3]	120026	1			T7	1		T8	105		T19	14415

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

437709

1

T8

8773

T15

4

T22

98

alert_ping_fail

719

1

T1

5

T7

1

T16

2

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	4858	1			T20	16		T5	107		T25	53
alert_integrity_fail	alert[0x1]	8331	1			T8	901		T22	4		T19	42
alert_integrity_fail	alert[0x2]	8585	1			T85	910		T132	1246		T38	20
alert_integrity_fail	alert[0x3]	6136	1			T19	21		T25	250		T54	10
alert_integrity_fail	alert[0x4]	5564	1			T22	2		T20	45		T5	331
alert_integrity_fail	alert[0x5]	5848	1			T20	75		T52	1		T25	76
alert_integrity_fail	alert[0x6]	2712	1			T19	43		T4	2		T20	361
alert_integrity_fail	alert[0x7]	5400	1			T20	7		T119	512		T85	110
alert_integrity_fail	alert[0x8]	6871	1			T8	8		T19	101		T5	68
alert_integrity_fail	alert[0x9]	5016	1			T15	1		T20	612		T79	129
alert_integrity_fail	alert[0xa]	8566	1			T8	84		T15	1		T19	42
alert_integrity_fail	alert[0xb]	6773	1			T8	1882		T22	7		T19	4
alert_integrity_fail	alert[0xc]	10615	1			T8	339		T22	2		T5	53
alert_integrity_fail	alert[0xd]	5635	1			T5	31		T25	260		T240	68
alert_integrity_fail	alert[0xe]	12040	1			T8	51		T19	311		T50	1
alert_integrity_fail	alert[0xf]	4619	1			T8	174		T20	17		T82	29
alert_integrity_fail	alert[0x10]	6296	1			T15	2		T19	942		T5	15
alert_integrity_fail	alert[0x11]	9154	1			T8	453		T19	127		T25	87
alert_integrity_fail	alert[0x12]	11299	1			T19	3728		T5	37		T28	4
alert_integrity_fail	alert[0x13]	2881	1			T19	469		T5	32		T25	18
alert_integrity_fail	alert[0x14]	4000	1			T119	489		T85	10		T28	1
alert_integrity_fail	alert[0x15]	4116	1			T8	16		T19	100		T52	1
alert_integrity_fail	alert[0x16]	4186	1			T4	1		T25	25		T240	615
alert_integrity_fail	alert[0x17]	6066	1			T8	2488		T20	305		T5	40
alert_integrity_fail	alert[0x18]	8268	1			T8	19		T20	366		T25	75
alert_integrity_fail	alert[0x19]	6353	1			T8	39		T20	23		T25	40
alert_integrity_fail	alert[0x1a]	3481	1			T20	148		T5	42		T25	230
alert_integrity_fail	alert[0x1b]	3636	1			T8	36		T5	1		T50	2
alert_integrity_fail	alert[0x1c]	3621	1			T25	335		T54	1		T240	92
alert_integrity_fail	alert[0x1d]	2281	1			T19	47		T20	446		T5	9
alert_integrity_fail	alert[0x1e]	3082	1			T8	48		T19	306		T20	75
alert_integrity_fail	alert[0x1f]	7470	1			T19	674		T20	51		T25	13
alert_integrity_fail	alert[0x20]	8643	1			T8	382		T20	117		T25	135
alert_integrity_fail	alert[0x21]	7467	1			T79	216		T82	169		T241	4
alert_integrity_fail	alert[0x22]	8856	1			T19	32		T5	7		T81	25
alert_integrity_fail	alert[0x23]	6291	1			T5	322		T240	416		T241	1
alert_integrity_fail	alert[0x24]	8225	1			T19	17		T5	31		T25	1
alert_integrity_fail	alert[0x25]	4422	1			T8	39		T5	66		T69	1
alert_integrity_fail	alert[0x26]	12999	1			T8	24		T19	97		T20	303
alert_integrity_fail	alert[0x27]	6029	1			T19	265		T20	9		T240	58
alert_integrity_fail	alert[0x28]	11652	1			T22	22		T19	3748		T81	3
alert_integrity_fail	alert[0x29]	7680	1			T69	1		T81	1		T82	39
alert_integrity_fail	alert[0x2a]	14163	1			T19	15		T4	16		T20	32
alert_integrity_fail	alert[0x2b]	5421	1			T8	38		T20	32		T5	18
alert_integrity_fail	alert[0x2c]	14985	1			T8	163		T79	251		T81	6
alert_integrity_fail	alert[0x2d]	9167	1			T19	6		T25	168		T82	317
alert_integrity_fail	alert[0x2e]	7928	1			T19	676		T20	85		T5	70
alert_integrity_fail	alert[0x2f]	5228	1			T20	420		T5	59		T25	171
alert_integrity_fail	alert[0x30]	2749	1			T8	244		T79	9		T240	22
alert_integrity_fail	alert[0x31]	4588	1			T20	221		T25	3		T85	1170
alert_integrity_fail	alert[0x32]	7961	1			T8	100		T19	523		T25	63
alert_integrity_fail	alert[0x33]	3507	1			T20	27		T50	4		T79	407
alert_integrity_fail	alert[0x34]	3030	1			T8	188		T19	35		T5	162
alert_integrity_fail	alert[0x35]	3528	1			T8	417		T22	7		T19	39
alert_integrity_fail	alert[0x36]	10538	1			T19	1		T50	1		T69	4
alert_integrity_fail	alert[0x37]	7757	1			T8	1		T19	1512		T50	3
alert_integrity_fail	alert[0x38]	1760	1			T5	15		T79	38		T82	70
alert_integrity_fail	alert[0x39]	6755	1			T22	44		T19	213		T20	29
alert_integrity_fail	alert[0x3a]	4283	1			T20	1373		T82	64		T132	12
alert_integrity_fail	alert[0x3b]	2938	1			T8	93		T19	77		T5	19
alert_integrity_fail	alert[0x3c]	6564	1			T8	32		T19	176		T4	3
alert_integrity_fail	alert[0x3d]	12335	1			T8	51		T22	10		T20	458
alert_integrity_fail	alert[0x3e]	15330	1			T8	27		T5	8		T54	6
alert_integrity_fail	alert[0x3f]	4782	1			T20	33		T5	79		T25	5
alert_integrity_fail	alert[0x40]	6389	1			T8	436		T19	26		T5	171
alert_ping_fail	alert[0x0]	11	1			T311	1		T312	2		T313	1
alert_ping_fail	alert[0x1]	9	1			T90	1		T242	2		T312	1
alert_ping_fail	alert[0x2]	9	1			T239	1		T314	1		T315	1
alert_ping_fail	alert[0x3]	12	1			T17	1		T242	1		T310	1
alert_ping_fail	alert[0x4]	13	1			T18	1		T242	1		T311	1
alert_ping_fail	alert[0x5]	13	1			T316	2		T317	1		T311	1
alert_ping_fail	alert[0x6]	12	1			T1	1		T131	1		T318	1
alert_ping_fail	alert[0x7]	19	1			T90	1		T318	1		T319	1
alert_ping_fail	alert[0x8]	12	1			T18	1		T242	1		T318	1
alert_ping_fail	alert[0x9]	12	1			T319	1		T320	1		T313	1
alert_ping_fail	alert[0xa]	17	1			T318	1		T316	1		T311	1
alert_ping_fail	alert[0xb]	9	1			T311	1		T321	1		T322	1
alert_ping_fail	alert[0xc]	11	1			T18	1		T90	1		T323	1
alert_ping_fail	alert[0xd]	10	1			T90	1		T312	1		T324	1
alert_ping_fail	alert[0xe]	11	1			T319	2		T320	1		T325	1
alert_ping_fail	alert[0xf]	8	1			T326	1		T323	1		T313	1
alert_ping_fail	alert[0x10]	9	1			T18	1		T242	1		T316	1
alert_ping_fail	alert[0x11]	7	1			T311	1		T323	1		T321	2
alert_ping_fail	alert[0x12]	8	1			T327	1		T328	1		T329	1
alert_ping_fail	alert[0x13]	18	1			T16	1		T17	1		T90	2
alert_ping_fail	alert[0x14]	9	1			T242	1		T307	1		T328	1
alert_ping_fail	alert[0x15]	15	1			T68	2		T237	2		T319	1
alert_ping_fail	alert[0x16]	13	1			T330	1		T326	1		T331	1
alert_ping_fail	alert[0x17]	12	1			T318	1		T316	1		T331	1
alert_ping_fail	alert[0x18]	15	1			T17	1		T323	2		T320	1
alert_ping_fail	alert[0x19]	12	1			T18	1		T90	1		T242	1
alert_ping_fail	alert[0x1a]	9	1			T7	1		T319	1		T331	1
alert_ping_fail	alert[0x1b]	14	1			T316	1		T311	1		T324	1
alert_ping_fail	alert[0x1c]	15	1			T18	1		T242	1		T319	1
alert_ping_fail	alert[0x1d]	6	1			T316	1		T313	1		T324	1
alert_ping_fail	alert[0x1e]	8	1			T242	1		T312	1		T332	1
alert_ping_fail	alert[0x1f]	10	1			T1	1		T90	1		T333	1
alert_ping_fail	alert[0x20]	17	1			T17	1		T18	1		T90	2
alert_ping_fail	alert[0x21]	13	1			T317	1		T311	2		T334	1
alert_ping_fail	alert[0x22]	18	1			T310	1		T317	1		T320	2
alert_ping_fail	alert[0x23]	9	1			T18	1		T90	1		T312	1
alert_ping_fail	alert[0x24]	8	1			T242	1		T311	1		T323	1
alert_ping_fail	alert[0x25]	10	1			T311	1		T320	1		T239	1
alert_ping_fail	alert[0x26]	10	1			T17	2		T319	1		T311	1
alert_ping_fail	alert[0x27]	13	1			T90	2		T310	1		T319	1
alert_ping_fail	alert[0x28]	20	1			T16	1		T18	1		T242	1
alert_ping_fail	alert[0x29]	10	1			T18	1		T242	1		T318	2
alert_ping_fail	alert[0x2a]	6	1			T325	1		T328	1		T335	1
alert_ping_fail	alert[0x2b]	11	1			T18	1		T334	1		T324	1
alert_ping_fail	alert[0x2c]	12	1			T307	1		T300	1		T320	1
alert_ping_fail	alert[0x2d]	14	1			T307	1		T312	1		T323	1
alert_ping_fail	alert[0x2e]	9	1			T90	1		T239	1		T325	1
alert_ping_fail	alert[0x2f]	12	1			T18	1		T317	1		T200	1
alert_ping_fail	alert[0x30]	10	1			T18	2		T90	1		T317	1
alert_ping_fail	alert[0x31]	8	1			T319	2		T331	1		T325	1
alert_ping_fail	alert[0x32]	8	1			T90	2		T242	1		T332	1
alert_ping_fail	alert[0x33]	15	1			T310	1		T311	1		T320	1
alert_ping_fail	alert[0x34]	15	1			T1	2		T318	1		T327	1
alert_ping_fail	alert[0x35]	11	1			T318	1		T319	1		T326	1
alert_ping_fail	alert[0x36]	6	1			T90	1		T311	1		T320	1
alert_ping_fail	alert[0x37]	13	1			T326	1		T312	1		T320	2
alert_ping_fail	alert[0x38]	10	1			T239	2		T328	1		T332	1
alert_ping_fail	alert[0x39]	6	1			T1	1		T17	1		T312	1
alert_ping_fail	alert[0x3a]	9	1			T319	1		T312	1		T324	1
alert_ping_fail	alert[0x3b]	10	1			T313	1		T328	1		T332	1
alert_ping_fail	alert[0x3c]	10	1			T318	1		T319	2		T316	1
alert_ping_fail	alert[0x3d]	7	1			T320	1		T324	1		T314	1
alert_ping_fail	alert[0x3e]	11	1			T318	1		T319	1		T316	1
alert_ping_fail	alert[0x3f]	3	1			T335	1		T336	1		T337	1
alert_ping_fail	alert[0x40]	7	1			T18	1		T242	1		T331	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	127756	1			T8	8571		T15	4		T22	98
alert_integrity_fail	class_i[0x1]	136387	1			T8	68		T20	6906		T50	3
alert_integrity_fail	class_i[0x2]	53704	1			T8	29		T50	7		T69	5
alert_integrity_fail	class_i[0x3]	119862	1			T8	105		T19	14415		T5	2100
alert_ping_fail	class_i[0x0]	211	1			T1	4		T18	10		T90	12
alert_ping_fail	class_i[0x1]	147	1			T17	7		T18	1		T90	2
alert_ping_fail	class_i[0x2]	197	1			T1	1		T16	2		T68	2
alert_ping_fail	class_i[0x3]	164	1			T7	1		T18	2		T90	2