Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.22 99.99 98.63 97.09 100.00 100.00 99.38 99.44


Total test records in report: 829
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html
T772 /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.1353778431 Jul 29 05:48:15 PM PDT 24 Jul 29 05:48:20 PM PDT 24 114786728 ps
T773 /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.295513731 Jul 29 05:49:27 PM PDT 24 Jul 29 05:49:34 PM PDT 24 435295230 ps
T774 /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.2531043377 Jul 29 05:48:00 PM PDT 24 Jul 29 05:48:40 PM PDT 24 2503777212 ps
T775 /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.924851470 Jul 29 05:48:10 PM PDT 24 Jul 29 05:48:24 PM PDT 24 368053590 ps
T185 /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.181621570 Jul 29 05:48:43 PM PDT 24 Jul 29 05:49:21 PM PDT 24 1443794268 ps
T776 /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.3781549251 Jul 29 05:48:57 PM PDT 24 Jul 29 05:49:04 PM PDT 24 217018181 ps
T777 /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.4225768896 Jul 29 05:49:34 PM PDT 24 Jul 29 05:50:07 PM PDT 24 1907185502 ps
T778 /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.1587137691 Jul 29 05:49:03 PM PDT 24 Jul 29 05:49:12 PM PDT 24 413236900 ps
T779 /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.658158417 Jul 29 05:49:11 PM PDT 24 Jul 29 05:49:52 PM PDT 24 1022435041 ps
T780 /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.2608186751 Jul 29 05:49:02 PM PDT 24 Jul 29 05:49:47 PM PDT 24 2958192195 ps
T781 /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.2522068111 Jul 29 05:49:07 PM PDT 24 Jul 29 05:49:14 PM PDT 24 183588905 ps
T782 /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.599269265 Jul 29 05:49:25 PM PDT 24 Jul 29 05:49:26 PM PDT 24 22687221 ps
T783 /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.2529961822 Jul 29 05:49:24 PM PDT 24 Jul 29 05:49:46 PM PDT 24 334699228 ps
T784 /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.1789361718 Jul 29 05:48:13 PM PDT 24 Jul 29 05:48:30 PM PDT 24 237266415 ps
T785 /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.3248286440 Jul 29 05:49:10 PM PDT 24 Jul 29 05:49:17 PM PDT 24 234564395 ps
T786 /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.2557484224 Jul 29 05:48:47 PM PDT 24 Jul 29 05:48:55 PM PDT 24 60741037 ps
T787 /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.645233634 Jul 29 05:49:38 PM PDT 24 Jul 29 05:49:39 PM PDT 24 36737741 ps
T788 /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.3667702169 Jul 29 05:49:44 PM PDT 24 Jul 29 05:49:45 PM PDT 24 16847811 ps
T166 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.3867279716 Jul 29 05:49:14 PM PDT 24 Jul 29 05:54:21 PM PDT 24 7916421767 ps
T789 /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.1903559348 Jul 29 05:49:09 PM PDT 24 Jul 29 05:49:10 PM PDT 24 10578739 ps
T370 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.2210957473 Jul 29 05:48:49 PM PDT 24 Jul 29 05:58:17 PM PDT 24 12118307449 ps
T790 /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.2315366514 Jul 29 05:48:57 PM PDT 24 Jul 29 05:49:34 PM PDT 24 644368311 ps
T791 /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.1710404946 Jul 29 05:48:37 PM PDT 24 Jul 29 05:48:58 PM PDT 24 335758584 ps
T792 /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.1834053331 Jul 29 05:49:29 PM PDT 24 Jul 29 05:49:51 PM PDT 24 182881634 ps
T793 /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.405901899 Jul 29 05:49:17 PM PDT 24 Jul 29 05:49:22 PM PDT 24 110447145 ps
T794 /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.3269015217 Jul 29 05:49:29 PM PDT 24 Jul 29 05:49:33 PM PDT 24 164855140 ps
T795 /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.62506144 Jul 29 05:48:43 PM PDT 24 Jul 29 05:48:46 PM PDT 24 41994181 ps
T796 /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.545825027 Jul 29 05:48:35 PM PDT 24 Jul 29 05:48:37 PM PDT 24 21312687 ps
T797 /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.2044435081 Jul 29 05:49:44 PM PDT 24 Jul 29 05:49:45 PM PDT 24 7571229 ps
T183 /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.853999284 Jul 29 05:48:14 PM PDT 24 Jul 29 05:48:45 PM PDT 24 477459321 ps
T798 /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.1553363289 Jul 29 05:49:36 PM PDT 24 Jul 29 05:49:38 PM PDT 24 15230598 ps
T799 /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.2720778944 Jul 29 05:48:53 PM PDT 24 Jul 29 05:48:59 PM PDT 24 144558599 ps
T182 /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.1844043335 Jul 29 05:48:23 PM PDT 24 Jul 29 05:49:04 PM PDT 24 357131491 ps
T800 /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.973284145 Jul 29 05:49:26 PM PDT 24 Jul 29 05:49:32 PM PDT 24 109769158 ps
T160 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.1175773075 Jul 29 05:48:29 PM PDT 24 Jul 29 05:50:59 PM PDT 24 7507939015 ps
T801 /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.2252047745 Jul 29 05:49:43 PM PDT 24 Jul 29 05:49:45 PM PDT 24 10815928 ps
T802 /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.3126568677 Jul 29 05:49:13 PM PDT 24 Jul 29 05:49:34 PM PDT 24 591045813 ps
T803 /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.2938026997 Jul 29 05:48:23 PM PDT 24 Jul 29 05:48:29 PM PDT 24 79909154 ps
T804 /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.1996520868 Jul 29 05:49:12 PM PDT 24 Jul 29 05:49:20 PM PDT 24 381243799 ps
T805 /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.1296860599 Jul 29 05:48:06 PM PDT 24 Jul 29 05:48:16 PM PDT 24 122545806 ps
T806 /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.1486916934 Jul 29 05:47:55 PM PDT 24 Jul 29 05:50:42 PM PDT 24 25512633358 ps
T807 /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.2466558465 Jul 29 05:48:08 PM PDT 24 Jul 29 05:48:14 PM PDT 24 33026077 ps
T173 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.3603717813 Jul 29 05:49:04 PM PDT 24 Jul 29 05:54:29 PM PDT 24 8924571080 ps
T371 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.1265774586 Jul 29 05:49:19 PM PDT 24 Jul 29 06:02:00 PM PDT 24 11244151739 ps
T190 /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.3087827195 Jul 29 05:47:55 PM PDT 24 Jul 29 05:49:02 PM PDT 24 4413025287 ps
T808 /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.1777205848 Jul 29 05:48:22 PM PDT 24 Jul 29 05:48:28 PM PDT 24 36381938 ps
T809 /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.237471438 Jul 29 05:49:44 PM PDT 24 Jul 29 05:49:46 PM PDT 24 10631905 ps
T810 /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.3416903279 Jul 29 05:48:26 PM PDT 24 Jul 29 05:48:48 PM PDT 24 3401769092 ps
T811 /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.3563548219 Jul 29 05:49:40 PM PDT 24 Jul 29 05:49:41 PM PDT 24 10522440 ps
T174 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.376265092 Jul 29 05:48:30 PM PDT 24 Jul 29 05:53:39 PM PDT 24 2151881772 ps
T192 /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.477880231 Jul 29 05:49:23 PM PDT 24 Jul 29 05:50:01 PM PDT 24 595362732 ps
T181 /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.1520440109 Jul 29 05:48:41 PM PDT 24 Jul 29 05:48:44 PM PDT 24 119771216 ps
T812 /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.1088045861 Jul 29 05:48:28 PM PDT 24 Jul 29 05:50:46 PM PDT 24 1122657306 ps
T813 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.1186114831 Jul 29 05:48:49 PM PDT 24 Jul 29 05:52:12 PM PDT 24 2224518563 ps
T814 /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.83827228 Jul 29 05:48:13 PM PDT 24 Jul 29 05:48:20 PM PDT 24 461032822 ps
T815 /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.443071998 Jul 29 05:49:14 PM PDT 24 Jul 29 05:49:29 PM PDT 24 189346327 ps
T172 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.86542596 Jul 29 05:48:39 PM PDT 24 Jul 29 06:08:07 PM PDT 24 17417663694 ps
T288 /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.3122111626 Jul 29 05:49:23 PM PDT 24 Jul 29 05:50:11 PM PDT 24 1312945237 ps
T816 /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.2539571598 Jul 29 05:49:10 PM PDT 24 Jul 29 05:49:31 PM PDT 24 315612057 ps
T817 /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.964423070 Jul 29 05:48:09 PM PDT 24 Jul 29 05:48:14 PM PDT 24 135430465 ps
T158 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.838408543 Jul 29 05:49:24 PM PDT 24 Jul 29 05:55:03 PM PDT 24 21437229446 ps
T818 /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.517422010 Jul 29 05:49:16 PM PDT 24 Jul 29 05:49:23 PM PDT 24 48648042 ps
T819 /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.3799962793 Jul 29 05:49:20 PM PDT 24 Jul 29 05:49:21 PM PDT 24 10028475 ps
T170 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.1450479408 Jul 29 05:49:24 PM PDT 24 Jul 29 06:07:43 PM PDT 24 12983412955 ps
T820 /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.2220157464 Jul 29 05:49:17 PM PDT 24 Jul 29 05:49:20 PM PDT 24 54080042 ps
T821 /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.341836522 Jul 29 05:48:33 PM PDT 24 Jul 29 05:48:37 PM PDT 24 182503671 ps
T822 /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.1680208801 Jul 29 05:48:43 PM PDT 24 Jul 29 05:49:17 PM PDT 24 2101571456 ps
T823 /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.2193850710 Jul 29 05:48:22 PM PDT 24 Jul 29 05:48:24 PM PDT 24 8968345 ps
T186 /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.592408311 Jul 29 05:48:03 PM PDT 24 Jul 29 05:49:09 PM PDT 24 1070309715 ps
T824 /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.2272531630 Jul 29 05:49:01 PM PDT 24 Jul 29 05:49:08 PM PDT 24 333064066 ps
T825 /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.2133353259 Jul 29 05:49:08 PM PDT 24 Jul 29 05:49:13 PM PDT 24 34576870 ps
T167 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.412351718 Jul 29 05:48:09 PM PDT 24 Jul 29 05:58:54 PM PDT 24 4388252286 ps
T171 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.1518186354 Jul 29 05:48:57 PM PDT 24 Jul 29 06:05:45 PM PDT 24 41010938255 ps
T826 /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.3868065868 Jul 29 05:48:32 PM PDT 24 Jul 29 05:49:10 PM PDT 24 2045039027 ps
T827 /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.1530124454 Jul 29 05:49:10 PM PDT 24 Jul 29 05:49:17 PM PDT 24 1764710364 ps
T828 /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.143716730 Jul 29 05:48:33 PM PDT 24 Jul 29 05:48:52 PM PDT 24 1260950297 ps
T168 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.3636098025 Jul 29 05:49:14 PM PDT 24 Jul 29 05:55:24 PM PDT 24 8822629837 ps
T829 /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.3337252106 Jul 29 05:49:24 PM PDT 24 Jul 29 05:49:35 PM PDT 24 511685496 ps
T188 /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.2546361014 Jul 29 05:49:24 PM PDT 24 Jul 29 05:49:27 PM PDT 24 42460108 ps

Test location /workspace/coverage/default/47.alert_handler_entropy.2962176626
Short name T8
Test name
Test status
Simulation time 48825152268 ps
CPU time 1750.73 seconds
Started Jul 29 05:55:23 PM PDT 24
Finished Jul 29 06:24:34 PM PDT 24
Peak memory 272896 kb
Host smart-93b96bca-3110-47c5-9e05-3072b6b7cb8a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962176626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.2962176626
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.3597325249
Short name T25
Test name
Test status
Simulation time 166163281033 ps
CPU time 1579.71 seconds
Started Jul 29 05:52:02 PM PDT 24
Finished Jul 29 06:18:22 PM PDT 24
Peak memory 289444 kb
Host smart-f10b21b0-7635-4b40-9455-78f05ed2dfb3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597325249 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.3597325249
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.3722549590
Short name T34
Test name
Test status
Simulation time 357948393 ps
CPU time 22.71 seconds
Started Jul 29 05:50:51 PM PDT 24
Finished Jul 29 05:51:14 PM PDT 24
Peak memory 270636 kb
Host smart-1ca20f10-07a1-4727-b7ad-7066de585fce
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3722549590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.3722549590
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.3777789728
Short name T191
Test name
Test status
Simulation time 7415545167 ps
CPU time 374.49 seconds
Started Jul 29 05:48:30 PM PDT 24
Finished Jul 29 05:54:45 PM PDT 24
Peak memory 240784 kb
Host smart-8963fd9a-e153-40a4-bdcd-2a81a77366b8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3777789728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.3777789728
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.131391411
Short name T19
Test name
Test status
Simulation time 135126887567 ps
CPU time 1448.57 seconds
Started Jul 29 05:52:55 PM PDT 24
Finished Jul 29 06:17:04 PM PDT 24
Peak memory 289116 kb
Host smart-1165a445-f910-4153-8cce-25116324276e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131391411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.131391411
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.529977699
Short name T28
Test name
Test status
Simulation time 48278705886 ps
CPU time 1118.05 seconds
Started Jul 29 05:50:56 PM PDT 24
Finished Jul 29 06:09:34 PM PDT 24
Peak memory 286808 kb
Host smart-dd2d7914-9ff4-488f-a956-4f85f1e0c9bf
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529977699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_hand
ler_stress_all.529977699
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.1990904191
Short name T16
Test name
Test status
Simulation time 56311531362 ps
CPU time 1549.73 seconds
Started Jul 29 05:52:34 PM PDT 24
Finished Jul 29 06:18:24 PM PDT 24
Peak memory 272860 kb
Host smart-3df8257b-9b87-4d23-b644-7b432e55b42e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990904191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.1990904191
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.3272223998
Short name T6
Test name
Test status
Simulation time 8508873935 ps
CPU time 54.98 seconds
Started Jul 29 05:50:53 PM PDT 24
Finished Jul 29 05:51:48 PM PDT 24
Peak memory 248388 kb
Host smart-19487510-b497-446a-bbea-9574a5ad425e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3272223998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.3272223998
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.1121354604
Short name T142
Test name
Test status
Simulation time 5057314150 ps
CPU time 341.88 seconds
Started Jul 29 05:48:10 PM PDT 24
Finished Jul 29 05:53:52 PM PDT 24
Peak memory 266676 kb
Host smart-db387e63-d8da-458a-8ea4-be60e43dfef6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1121354604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.1121354604
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.1783130678
Short name T52
Test name
Test status
Simulation time 61189377319 ps
CPU time 1205.3 seconds
Started Jul 29 05:55:16 PM PDT 24
Finished Jul 29 06:15:21 PM PDT 24
Peak memory 289252 kb
Host smart-c6e4ccb0-835e-4b20-95d5-634603b145f4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783130678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.1783130678
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.1794539475
Short name T98
Test name
Test status
Simulation time 79542113340 ps
CPU time 7984.09 seconds
Started Jul 29 05:51:06 PM PDT 24
Finished Jul 29 08:04:11 PM PDT 24
Peak memory 403436 kb
Host smart-7faa88a0-7874-4ccd-8c05-27b26aa733d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794539475 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.1794539475
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.4182209329
Short name T20
Test name
Test status
Simulation time 180391076471 ps
CPU time 1257.47 seconds
Started Jul 29 05:51:17 PM PDT 24
Finished Jul 29 06:12:15 PM PDT 24
Peak memory 283892 kb
Host smart-52581810-7ffc-4e36-9383-ebd8730dfe50
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182209329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.4182209329
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.2537970393
Short name T106
Test name
Test status
Simulation time 87595421645 ps
CPU time 1546.26 seconds
Started Jul 29 05:53:00 PM PDT 24
Finished Jul 29 06:18:47 PM PDT 24
Peak memory 288820 kb
Host smart-c43ae959-e6e7-40d3-a560-56931fdf3e84
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537970393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.2537970393
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.4111472459
Short name T155
Test name
Test status
Simulation time 25023855219 ps
CPU time 689.85 seconds
Started Jul 29 05:48:03 PM PDT 24
Finished Jul 29 05:59:33 PM PDT 24
Peak memory 273724 kb
Host smart-453af9a2-9a6b-4cd7-89c9-f4b430df2d4d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111472459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.4111472459
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.3902683882
Short name T102
Test name
Test status
Simulation time 528727874264 ps
CPU time 1428.3 seconds
Started Jul 29 05:53:29 PM PDT 24
Finished Jul 29 06:17:18 PM PDT 24
Peak memory 282620 kb
Host smart-93bedf26-f35e-4b35-948b-95f189681114
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902683882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.3902683882
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.274639741
Short name T29
Test name
Test status
Simulation time 127085730143 ps
CPU time 2106.97 seconds
Started Jul 29 05:53:57 PM PDT 24
Finished Jul 29 06:29:05 PM PDT 24
Peak memory 289024 kb
Host smart-d3d75331-7516-4049-94cf-c7ae10397b7d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274639741 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.274639741
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.2125886837
Short name T140
Test name
Test status
Simulation time 17782111942 ps
CPU time 316.81 seconds
Started Jul 29 05:49:15 PM PDT 24
Finished Jul 29 05:54:32 PM PDT 24
Peak memory 265664 kb
Host smart-adb6d27f-0da1-4066-8bde-20b7d1bc255a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2125886837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.2125886837
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.1279529990
Short name T4
Test name
Test status
Simulation time 3180581720 ps
CPU time 198.49 seconds
Started Jul 29 05:51:27 PM PDT 24
Finished Jul 29 05:54:45 PM PDT 24
Peak memory 256536 kb
Host smart-9737fe38-5599-481d-a4df-34773b78f65b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279529990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.1279529990
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.2048184266
Short name T147
Test name
Test status
Simulation time 34013556546 ps
CPU time 1100.91 seconds
Started Jul 29 05:48:42 PM PDT 24
Finished Jul 29 06:07:03 PM PDT 24
Peak memory 265708 kb
Host smart-63b87e1f-e58a-41a8-ad32-0439056155c1
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048184266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.2048184266
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.1190125384
Short name T351
Test name
Test status
Simulation time 213688603906 ps
CPU time 2948.07 seconds
Started Jul 29 05:54:20 PM PDT 24
Finished Jul 29 06:43:28 PM PDT 24
Peak memory 288940 kb
Host smart-67f78753-6dab-4fa4-a5a3-a750b6d44230
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190125384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.1190125384
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.3469036138
Short name T366
Test name
Test status
Simulation time 6466683 ps
CPU time 1.39 seconds
Started Jul 29 05:49:38 PM PDT 24
Finished Jul 29 05:49:39 PM PDT 24
Peak memory 237720 kb
Host smart-71dc6e7d-4640-484b-943a-ef8370ad31ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3469036138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.3469036138
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.1157680203
Short name T90
Test name
Test status
Simulation time 42083035372 ps
CPU time 564.02 seconds
Started Jul 29 05:52:08 PM PDT 24
Finished Jul 29 06:01:32 PM PDT 24
Peak memory 248076 kb
Host smart-a535679e-bf90-4f04-a430-19d37d594213
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157680203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.1157680203
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.776457077
Short name T139
Test name
Test status
Simulation time 24906324908 ps
CPU time 948.83 seconds
Started Jul 29 05:47:55 PM PDT 24
Finished Jul 29 06:03:44 PM PDT 24
Peak memory 265784 kb
Host smart-ab1f829a-9809-436f-9d50-3cee703faf35
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776457077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.776457077
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.3867279716
Short name T166
Test name
Test status
Simulation time 7916421767 ps
CPU time 307.1 seconds
Started Jul 29 05:49:14 PM PDT 24
Finished Jul 29 05:54:21 PM PDT 24
Peak memory 265616 kb
Host smart-915686ec-4241-4700-89ad-c40eb68b9f47
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867279716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.3867279716
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.11019952
Short name T7
Test name
Test status
Simulation time 58775346694 ps
CPU time 3015.16 seconds
Started Jul 29 05:51:22 PM PDT 24
Finished Jul 29 06:41:37 PM PDT 24
Peak memory 288548 kb
Host smart-b542af71-eda9-4f60-9433-bfffa171c93a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11019952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.11019952
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.3035414196
Short name T324
Test name
Test status
Simulation time 15895440200 ps
CPU time 610.33 seconds
Started Jul 29 05:50:55 PM PDT 24
Finished Jul 29 06:01:06 PM PDT 24
Peak memory 248272 kb
Host smart-f841b67b-f868-425c-85b0-7c7797ead630
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035414196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.3035414196
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.2677355638
Short name T153
Test name
Test status
Simulation time 1755766739 ps
CPU time 247.64 seconds
Started Jul 29 05:49:04 PM PDT 24
Finished Jul 29 05:53:12 PM PDT 24
Peak memory 265716 kb
Host smart-d82174ba-b66e-4eee-b109-2dba75c2e161
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2677355638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.2677355638
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.1132840523
Short name T175
Test name
Test status
Simulation time 158524210 ps
CPU time 19.05 seconds
Started Jul 29 05:49:36 PM PDT 24
Finished Jul 29 05:49:55 PM PDT 24
Peak memory 248868 kb
Host smart-8aaa101a-e198-4a05-bef1-ba4e56ec73b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1132840523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.1132840523
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.2253307737
Short name T317
Test name
Test status
Simulation time 72935081555 ps
CPU time 2220.61 seconds
Started Jul 29 05:51:05 PM PDT 24
Finished Jul 29 06:28:06 PM PDT 24
Peak memory 272200 kb
Host smart-950da6f7-78bd-4b7c-8fa4-62da5a207875
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253307737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.2253307737
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.119781856
Short name T242
Test name
Test status
Simulation time 7698633321 ps
CPU time 339.33 seconds
Started Jul 29 05:55:10 PM PDT 24
Finished Jul 29 06:00:50 PM PDT 24
Peak memory 248256 kb
Host smart-a2052466-6355-4e7f-a936-64fc44f4ee19
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119781856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.119781856
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.1621774418
Short name T585
Test name
Test status
Simulation time 63996322466 ps
CPU time 667.51 seconds
Started Jul 29 05:54:53 PM PDT 24
Finished Jul 29 06:06:01 PM PDT 24
Peak memory 248368 kb
Host smart-2e8fc776-9fa5-401c-afcf-5cd2dbd8354e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621774418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.1621774418
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.406567777
Short name T164
Test name
Test status
Simulation time 91543806808 ps
CPU time 1269.66 seconds
Started Jul 29 05:48:23 PM PDT 24
Finished Jul 29 06:09:32 PM PDT 24
Peak memory 265668 kb
Host smart-f0cbe0b0-1105-4695-8edc-6d0ceacddff7
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406567777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.406567777
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.1509576778
Short name T342
Test name
Test status
Simulation time 44048535208 ps
CPU time 2911.63 seconds
Started Jul 29 05:51:43 PM PDT 24
Finished Jul 29 06:40:15 PM PDT 24
Peak memory 288504 kb
Host smart-1665b980-f9e3-4be2-9f9e-dbb3aeb0001f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509576778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.1509576778
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.4127445023
Short name T268
Test name
Test status
Simulation time 74595378240 ps
CPU time 2500.48 seconds
Started Jul 29 05:53:30 PM PDT 24
Finished Jul 29 06:35:11 PM PDT 24
Peak memory 288920 kb
Host smart-7fbe6c30-2f28-461a-bb5c-129071decd77
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127445023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.4127445023
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.2258236854
Short name T161
Test name
Test status
Simulation time 2380276360 ps
CPU time 179.01 seconds
Started Jul 29 05:49:22 PM PDT 24
Finished Jul 29 05:52:21 PM PDT 24
Peak memory 272912 kb
Host smart-d68b9204-2071-42d8-bb62-1dc85f8334a4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2258236854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.2258236854
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.2893349525
Short name T99
Test name
Test status
Simulation time 279590746053 ps
CPU time 5688.51 seconds
Started Jul 29 05:51:46 PM PDT 24
Finished Jul 29 07:26:36 PM PDT 24
Peak memory 353764 kb
Host smart-283efa38-6852-4b0d-998a-fc4b017d4d09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893349525 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.2893349525
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.19066082
Short name T712
Test name
Test status
Simulation time 292620457556 ps
CPU time 3046.09 seconds
Started Jul 29 05:50:56 PM PDT 24
Finished Jul 29 06:41:43 PM PDT 24
Peak memory 288608 kb
Host smart-876315ef-2c0a-4376-b619-15b49398c8d1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19066082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.19066082
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.1084122283
Short name T337
Test name
Test status
Simulation time 12065220470 ps
CPU time 494.41 seconds
Started Jul 29 05:53:24 PM PDT 24
Finished Jul 29 06:01:39 PM PDT 24
Peak memory 248428 kb
Host smart-8e19926b-a69a-4f27-88d4-9b6fdb5a3565
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084122283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.1084122283
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.2748257356
Short name T71
Test name
Test status
Simulation time 73914297237 ps
CPU time 1381.02 seconds
Started Jul 29 05:51:22 PM PDT 24
Finished Jul 29 06:14:23 PM PDT 24
Peak memory 288716 kb
Host smart-3672e5e5-7832-4f13-9c3b-6426adbf114a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748257356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.2748257356
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.911817417
Short name T293
Test name
Test status
Simulation time 52705459307 ps
CPU time 2859.57 seconds
Started Jul 29 05:51:32 PM PDT 24
Finished Jul 29 06:39:12 PM PDT 24
Peak memory 288332 kb
Host smart-1d103f41-9b90-470c-b18d-1bc475421747
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911817417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_han
dler_stress_all.911817417
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.1306866542
Short name T272
Test name
Test status
Simulation time 252396565380 ps
CPU time 3564.8 seconds
Started Jul 29 05:55:28 PM PDT 24
Finished Jul 29 06:54:53 PM PDT 24
Peak memory 288864 kb
Host smart-561e728a-d1dc-4ade-9a44-3e3fd09d8778
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306866542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.1306866542
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.396366492
Short name T195
Test name
Test status
Simulation time 85101147 ps
CPU time 5.2 seconds
Started Jul 29 05:49:01 PM PDT 24
Finished Jul 29 05:49:06 PM PDT 24
Peak memory 236820 kb
Host smart-c1b78c26-bd04-446a-bedb-161495a2fd21
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=396366492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.396366492
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.2507033821
Short name T721
Test name
Test status
Simulation time 9070390 ps
CPU time 1.52 seconds
Started Jul 29 05:49:47 PM PDT 24
Finished Jul 29 05:49:49 PM PDT 24
Peak memory 236772 kb
Host smart-06ed7359-1558-40db-9c14-341f71d3eb0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2507033821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.2507033821
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.3004489269
Short name T119
Test name
Test status
Simulation time 19317902597 ps
CPU time 1653.69 seconds
Started Jul 29 05:51:32 PM PDT 24
Finished Jul 29 06:19:06 PM PDT 24
Peak memory 289120 kb
Host smart-c6229237-29cf-46a0-b85e-1d360eb2485d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004489269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.3004489269
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.1753323195
Short name T149
Test name
Test status
Simulation time 8248541864 ps
CPU time 304.88 seconds
Started Jul 29 05:49:16 PM PDT 24
Finished Jul 29 05:54:21 PM PDT 24
Peak memory 265624 kb
Host smart-14016b4b-242b-406c-81ce-0af2ff8e87ae
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1753323195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.1753323195
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.489474271
Short name T357
Test name
Test status
Simulation time 57098188366 ps
CPU time 3144.74 seconds
Started Jul 29 05:51:20 PM PDT 24
Finished Jul 29 06:43:45 PM PDT 24
Peak memory 289392 kb
Host smart-f6df4485-5103-4ae6-a510-a52c6e40944f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489474271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.489474271
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.3081300118
Short name T267
Test name
Test status
Simulation time 3466353628 ps
CPU time 36.44 seconds
Started Jul 29 05:51:42 PM PDT 24
Finished Jul 29 05:52:18 PM PDT 24
Peak memory 248136 kb
Host smart-d31b7043-b158-49aa-b129-c87189c72d98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30813
00118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.3081300118
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.940878160
Short name T699
Test name
Test status
Simulation time 10226439965 ps
CPU time 440.95 seconds
Started Jul 29 05:51:44 PM PDT 24
Finished Jul 29 05:59:06 PM PDT 24
Peak memory 248388 kb
Host smart-825947b9-cb5b-4123-af7d-afd5503c9985
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940878160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.940878160
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.2964843089
Short name T14
Test name
Test status
Simulation time 41630629845 ps
CPU time 1151.68 seconds
Started Jul 29 05:52:52 PM PDT 24
Finished Jul 29 06:12:04 PM PDT 24
Peak memory 272004 kb
Host smart-799d385f-d807-488b-86c8-5052d49eb71c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964843089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.2964843089
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.1776387617
Short name T214
Test name
Test status
Simulation time 283562082744 ps
CPU time 7555.88 seconds
Started Jul 29 05:53:29 PM PDT 24
Finished Jul 29 07:59:25 PM PDT 24
Peak memory 371132 kb
Host smart-d9b5b347-bcf6-4cfe-afc0-d4b0fbee362f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776387617 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.1776387617
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.821501319
Short name T319
Test name
Test status
Simulation time 12083880810 ps
CPU time 495.68 seconds
Started Jul 29 05:52:54 PM PDT 24
Finished Jul 29 06:01:10 PM PDT 24
Peak memory 247276 kb
Host smart-6942bb59-3c55-43ae-98e0-c832ae5a40f0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821501319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.821501319
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.3697410040
Short name T81
Test name
Test status
Simulation time 2676816034 ps
CPU time 168.44 seconds
Started Jul 29 05:55:33 PM PDT 24
Finished Jul 29 05:58:22 PM PDT 24
Peak memory 256548 kb
Host smart-893d60d4-401d-4f53-98ae-dc4ffd1d790d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697410040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.3697410040
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.838408543
Short name T158
Test name
Test status
Simulation time 21437229446 ps
CPU time 338.58 seconds
Started Jul 29 05:49:24 PM PDT 24
Finished Jul 29 05:55:03 PM PDT 24
Peak memory 273192 kb
Host smart-a1271237-4741-4f26-999d-7da007a1da0b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=838408543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_erro
rs.838408543
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.3575198951
Short name T219
Test name
Test status
Simulation time 66319859 ps
CPU time 3.59 seconds
Started Jul 29 05:50:51 PM PDT 24
Finished Jul 29 05:50:54 PM PDT 24
Peak memory 248656 kb
Host smart-868a9262-be78-476c-94ed-c3910d8887b1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3575198951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.3575198951
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.793161395
Short name T232
Test name
Test status
Simulation time 142785674 ps
CPU time 3.52 seconds
Started Jul 29 05:51:32 PM PDT 24
Finished Jul 29 05:51:36 PM PDT 24
Peak memory 248660 kb
Host smart-96db1c49-a327-4704-bdf0-69db66ae5b66
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=793161395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.793161395
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.573790274
Short name T91
Test name
Test status
Simulation time 140275106 ps
CPU time 3.63 seconds
Started Jul 29 05:51:45 PM PDT 24
Finished Jul 29 05:51:48 PM PDT 24
Peak memory 248636 kb
Host smart-cf803f6c-3c32-420f-917e-586917459006
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=573790274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.573790274
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.3318151596
Short name T235
Test name
Test status
Simulation time 127391478 ps
CPU time 3.34 seconds
Started Jul 29 05:51:45 PM PDT 24
Finished Jul 29 05:51:49 PM PDT 24
Peak memory 248596 kb
Host smart-c073cdea-a135-4965-b24b-c4b12b207a53
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3318151596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.3318151596
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.1897351130
Short name T280
Test name
Test status
Simulation time 23284564819 ps
CPU time 1654.1 seconds
Started Jul 29 05:50:50 PM PDT 24
Finished Jul 29 06:18:24 PM PDT 24
Peak memory 288716 kb
Host smart-0849eb58-261b-4d42-b7cb-877ee997c21b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897351130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.1897351130
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.2622708353
Short name T291
Test name
Test status
Simulation time 10632718956 ps
CPU time 58.55 seconds
Started Jul 29 05:51:44 PM PDT 24
Finished Jul 29 05:52:43 PM PDT 24
Peak memory 248436 kb
Host smart-3466d05b-04d3-480c-a586-acaeeb7a02db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26227
08353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.2622708353
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.3175368236
Short name T350
Test name
Test status
Simulation time 65026895030 ps
CPU time 1955.96 seconds
Started Jul 29 05:52:23 PM PDT 24
Finished Jul 29 06:25:00 PM PDT 24
Peak memory 284520 kb
Host smart-2fc7ba50-543f-4c95-97aa-5b597d45c407
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175368236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.3175368236
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.2185036902
Short name T549
Test name
Test status
Simulation time 22308220300 ps
CPU time 474.23 seconds
Started Jul 29 05:54:29 PM PDT 24
Finished Jul 29 06:02:23 PM PDT 24
Peak memory 248384 kb
Host smart-1cd6756c-3c01-4938-a0c8-85040464391f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185036902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.2185036902
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.146481907
Short name T706
Test name
Test status
Simulation time 67793009221 ps
CPU time 3018.87 seconds
Started Jul 29 05:55:10 PM PDT 24
Finished Jul 29 06:45:30 PM PDT 24
Peak memory 288608 kb
Host smart-0a800904-c033-454e-8c93-05c07a76136e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146481907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.146481907
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.1518186354
Short name T171
Test name
Test status
Simulation time 41010938255 ps
CPU time 1007.56 seconds
Started Jul 29 05:48:57 PM PDT 24
Finished Jul 29 06:05:45 PM PDT 24
Peak memory 273076 kb
Host smart-227fed1b-90b4-4b5b-8686-2e795ddbfea1
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518186354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.1518186354
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.592408311
Short name T186
Test name
Test status
Simulation time 1070309715 ps
CPU time 65.63 seconds
Started Jul 29 05:48:03 PM PDT 24
Finished Jul 29 05:49:09 PM PDT 24
Peak memory 237784 kb
Host smart-3520543d-473c-4927-9a85-7a70914ad688
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=592408311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.592408311
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.1486916934
Short name T806
Test name
Test status
Simulation time 25512633358 ps
CPU time 166.78 seconds
Started Jul 29 05:47:55 PM PDT 24
Finished Jul 29 05:50:42 PM PDT 24
Peak memory 265672 kb
Host smart-c63dfc65-f646-406b-9481-38e836440c33
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1486916934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.1486916934
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.1421431581
Short name T24
Test name
Test status
Simulation time 376157057 ps
CPU time 11.6 seconds
Started Jul 29 05:50:51 PM PDT 24
Finished Jul 29 05:51:02 PM PDT 24
Peak memory 247736 kb
Host smart-92c5369d-3d27-4a57-81c3-7c4449ecc0ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14214
31581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.1421431581
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.2800764032
Short name T271
Test name
Test status
Simulation time 8092804791 ps
CPU time 821.22 seconds
Started Jul 29 05:50:51 PM PDT 24
Finished Jul 29 06:04:33 PM PDT 24
Peak memory 268392 kb
Host smart-6494a264-6431-411f-8916-6236d1a5819f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800764032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.2800764032
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all_with_rand_reset.56596681
Short name T244
Test name
Test status
Simulation time 258040807014 ps
CPU time 4064.86 seconds
Started Jul 29 05:51:33 PM PDT 24
Finished Jul 29 06:59:18 PM PDT 24
Peak memory 289204 kb
Host smart-f8ffd76e-3586-4fb8-8e86-3759af5011b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56596681 -assert nopostproc +UVM_TESTNAME=alert_
handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 11.alert_handler_stress_all_with_rand_reset.56596681
Directory /workspace/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.1561618282
Short name T269
Test name
Test status
Simulation time 2163788682 ps
CPU time 56.76 seconds
Started Jul 29 05:51:57 PM PDT 24
Finished Jul 29 05:52:54 PM PDT 24
Peak memory 255648 kb
Host smart-3072beaf-940c-46c8-9160-e8eb89bb73df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15616
18282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.1561618282
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.293706418
Short name T334
Test name
Test status
Simulation time 194332249632 ps
CPU time 2678.52 seconds
Started Jul 29 05:52:02 PM PDT 24
Finished Jul 29 06:36:41 PM PDT 24
Peak memory 286716 kb
Host smart-b61ab1b9-440d-4c84-9e5d-aa8ce03af61d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293706418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.293706418
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.4102615144
Short name T215
Test name
Test status
Simulation time 98178904819 ps
CPU time 4847.36 seconds
Started Jul 29 05:52:46 PM PDT 24
Finished Jul 29 07:13:34 PM PDT 24
Peak memory 353760 kb
Host smart-d2fd166a-0792-4569-867d-b70dfa4a2a51
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102615144 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.4102615144
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.2123594621
Short name T265
Test name
Test status
Simulation time 258717017633 ps
CPU time 3996.45 seconds
Started Jul 29 05:52:47 PM PDT 24
Finished Jul 29 06:59:24 PM PDT 24
Peak memory 304732 kb
Host smart-aaaae024-35d1-44e2-9088-23a70abd6fc2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123594621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.2123594621
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.664690937
Short name T206
Test name
Test status
Simulation time 1790298341 ps
CPU time 50.22 seconds
Started Jul 29 05:50:56 PM PDT 24
Finished Jul 29 05:51:47 PM PDT 24
Peak memory 248300 kb
Host smart-98ef4e02-6f9f-45ad-be62-512bc5d9a879
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66469
0937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.664690937
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.3090939574
Short name T283
Test name
Test status
Simulation time 35829869085 ps
CPU time 3926.34 seconds
Started Jul 29 05:53:35 PM PDT 24
Finished Jul 29 06:59:01 PM PDT 24
Peak memory 335748 kb
Host smart-6e9c95e1-2ea2-4697-bad7-b35d463147e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090939574 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.3090939574
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.2718818757
Short name T277
Test name
Test status
Simulation time 3171169775 ps
CPU time 46.07 seconds
Started Jul 29 05:54:41 PM PDT 24
Finished Jul 29 05:55:27 PM PDT 24
Peak memory 255632 kb
Host smart-ae9e2a6e-905b-408d-b08c-41ad0b958428
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27188
18757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.2718818757
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.2494466504
Short name T135
Test name
Test status
Simulation time 78167448111 ps
CPU time 1685.27 seconds
Started Jul 29 05:55:07 PM PDT 24
Finished Jul 29 06:23:13 PM PDT 24
Peak memory 289360 kb
Host smart-437f0339-05c0-4f18-8906-ebfb3690a619
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494466504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.2494466504
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.4155193098
Short name T290
Test name
Test status
Simulation time 7446410740 ps
CPU time 227.55 seconds
Started Jul 29 05:55:33 PM PDT 24
Finished Jul 29 05:59:21 PM PDT 24
Peak memory 256608 kb
Host smart-7185d0fe-1572-4a45-a4e5-027f83cfbac9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41551
93098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.4155193098
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.1503272227
Short name T38
Test name
Test status
Simulation time 8334668247 ps
CPU time 960.21 seconds
Started Jul 29 05:51:44 PM PDT 24
Finished Jul 29 06:07:44 PM PDT 24
Peak memory 272936 kb
Host smart-a8f2c2fa-b944-4478-bbc0-5aeb58a584c9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503272227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.1503272227
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.1175773075
Short name T160
Test name
Test status
Simulation time 7507939015 ps
CPU time 149.77 seconds
Started Jul 29 05:48:29 PM PDT 24
Finished Jul 29 05:50:59 PM PDT 24
Peak memory 265556 kb
Host smart-e3fabbdb-1705-4cb8-a7cc-a903d793f798
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1175773075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.1175773075
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.181621570
Short name T185
Test name
Test status
Simulation time 1443794268 ps
CPU time 38.27 seconds
Started Jul 29 05:48:43 PM PDT 24
Finished Jul 29 05:49:21 PM PDT 24
Peak memory 240628 kb
Host smart-c754105e-b318-448a-af54-49b41347a897
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=181621570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.181621570
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.3087827195
Short name T190
Test name
Test status
Simulation time 4413025287 ps
CPU time 66.72 seconds
Started Jul 29 05:47:55 PM PDT 24
Finished Jul 29 05:49:02 PM PDT 24
Peak memory 248884 kb
Host smart-c33f304e-c4a5-4d3b-97d3-fb141457d6a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3087827195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.3087827195
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.853999284
Short name T183
Test name
Test status
Simulation time 477459321 ps
CPU time 31.8 seconds
Started Jul 29 05:48:14 PM PDT 24
Finished Jul 29 05:48:45 PM PDT 24
Peak memory 248836 kb
Host smart-45e9012c-9f04-4bc8-9f48-ebd05bf7f764
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=853999284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.853999284
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.1844043335
Short name T182
Test name
Test status
Simulation time 357131491 ps
CPU time 41.22 seconds
Started Jul 29 05:48:23 PM PDT 24
Finished Jul 29 05:49:04 PM PDT 24
Peak memory 237896 kb
Host smart-b7443849-2bd7-4d9c-8d18-af7f058e7b84
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1844043335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.1844043335
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.3633490432
Short name T189
Test name
Test status
Simulation time 54770518 ps
CPU time 2.52 seconds
Started Jul 29 05:48:27 PM PDT 24
Finished Jul 29 05:48:30 PM PDT 24
Peak memory 238000 kb
Host smart-ef3f5514-9649-4e2b-9826-bbe5ef58b5b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3633490432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.3633490432
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.2232542788
Short name T150
Test name
Test status
Simulation time 4356549145 ps
CPU time 286.79 seconds
Started Jul 29 05:48:37 PM PDT 24
Finished Jul 29 05:53:24 PM PDT 24
Peak memory 272572 kb
Host smart-ba4fbeb8-3672-4ea4-9b5f-c567e3c3e7a3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2232542788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.2232542788
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.1520440109
Short name T181
Test name
Test status
Simulation time 119771216 ps
CPU time 3.16 seconds
Started Jul 29 05:48:41 PM PDT 24
Finished Jul 29 05:48:44 PM PDT 24
Peak memory 238188 kb
Host smart-0d3d2ced-6f0c-4e80-b0e5-255489270312
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1520440109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.1520440109
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.2243242280
Short name T187
Test name
Test status
Simulation time 46591972 ps
CPU time 3.18 seconds
Started Jul 29 05:48:54 PM PDT 24
Finished Jul 29 05:48:57 PM PDT 24
Peak memory 237664 kb
Host smart-b397b6ac-68d8-4ff9-835c-3e806d4313cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2243242280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.2243242280
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.2343011862
Short name T196
Test name
Test status
Simulation time 2153685646 ps
CPU time 31.77 seconds
Started Jul 29 05:49:04 PM PDT 24
Finished Jul 29 05:49:36 PM PDT 24
Peak memory 237860 kb
Host smart-b2264852-dc59-4663-9620-9857698f8255
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2343011862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.2343011862
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.477880231
Short name T192
Test name
Test status
Simulation time 595362732 ps
CPU time 38.59 seconds
Started Jul 29 05:49:23 PM PDT 24
Finished Jul 29 05:50:01 PM PDT 24
Peak memory 240612 kb
Host smart-f9bc2f5e-3907-4f79-9bc8-bb7abab5a2d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=477880231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.477880231
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.2546361014
Short name T188
Test name
Test status
Simulation time 42460108 ps
CPU time 3.07 seconds
Started Jul 29 05:49:24 PM PDT 24
Finished Jul 29 05:49:27 PM PDT 24
Peak memory 237680 kb
Host smart-7e27f37d-5ce6-4304-84d5-5ccc5674b031
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2546361014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.2546361014
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.1478950083
Short name T184
Test name
Test status
Simulation time 221604127 ps
CPU time 3.64 seconds
Started Jul 29 05:48:49 PM PDT 24
Finished Jul 29 05:48:53 PM PDT 24
Peak memory 237716 kb
Host smart-1fa71537-ca8f-4338-b378-a301ad7b1f6d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1478950083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.1478950083
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.2729352561
Short name T209
Test name
Test status
Simulation time 1621219531 ps
CPU time 60.38 seconds
Started Jul 29 05:48:00 PM PDT 24
Finished Jul 29 05:49:01 PM PDT 24
Peak memory 240636 kb
Host smart-2e4596c6-bdac-44c1-8fe4-5561050b9a5d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2729352561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.2729352561
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.3170648266
Short name T256
Test name
Test status
Simulation time 77885427615 ps
CPU time 600.98 seconds
Started Jul 29 05:48:01 PM PDT 24
Finished Jul 29 05:58:02 PM PDT 24
Peak memory 237792 kb
Host smart-c1633c1d-c83e-41f3-94c4-9c4ac1cd3232
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3170648266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.3170648266
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.483911403
Short name T737
Test name
Test status
Simulation time 475350946 ps
CPU time 9.6 seconds
Started Jul 29 05:47:55 PM PDT 24
Finished Jul 29 05:48:04 PM PDT 24
Peak memory 249220 kb
Host smart-2e171f99-ff64-480b-8dd9-6e9bab3738f8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=483911403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.483911403
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.1176395746
Short name T368
Test name
Test status
Simulation time 573701563 ps
CPU time 11.78 seconds
Started Jul 29 05:48:07 PM PDT 24
Finished Jul 29 05:48:19 PM PDT 24
Peak memory 252056 kb
Host smart-5771f750-9da7-430c-9412-d977bdca4686
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176395746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.1176395746
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.2143825137
Short name T717
Test name
Test status
Simulation time 35028218 ps
CPU time 3.46 seconds
Started Jul 29 05:47:55 PM PDT 24
Finished Jul 29 05:47:59 PM PDT 24
Peak memory 237632 kb
Host smart-7b3871d6-8c4b-4b0c-8449-8ad50d0627db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2143825137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.2143825137
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.3223939932
Short name T179
Test name
Test status
Simulation time 23024195 ps
CPU time 1.27 seconds
Started Jul 29 05:47:56 PM PDT 24
Finished Jul 29 05:47:58 PM PDT 24
Peak memory 235804 kb
Host smart-fa230caa-3849-48de-a746-972b292a266c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3223939932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.3223939932
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.2531043377
Short name T774
Test name
Test status
Simulation time 2503777212 ps
CPU time 39.84 seconds
Started Jul 29 05:48:00 PM PDT 24
Finished Jul 29 05:48:40 PM PDT 24
Peak memory 248868 kb
Host smart-2aae7bcb-12ab-404b-b340-5da7202f6536
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2531043377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.2531043377
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.2399464389
Short name T255
Test name
Test status
Simulation time 92697825 ps
CPU time 7.39 seconds
Started Jul 29 05:47:56 PM PDT 24
Finished Jul 29 05:48:03 PM PDT 24
Peak memory 249008 kb
Host smart-05253ae8-7a1a-481d-81ec-b2fee17fcf81
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2399464389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.2399464389
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.2133895614
Short name T194
Test name
Test status
Simulation time 31447773940 ps
CPU time 135.06 seconds
Started Jul 29 05:48:08 PM PDT 24
Finished Jul 29 05:50:24 PM PDT 24
Peak memory 237820 kb
Host smart-dc15a3ff-3dd9-45bd-a8f2-6697edbe9284
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2133895614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.2133895614
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.2555804465
Short name T369
Test name
Test status
Simulation time 11659217565 ps
CPU time 206.8 seconds
Started Jul 29 05:48:10 PM PDT 24
Finished Jul 29 05:51:37 PM PDT 24
Peak memory 240916 kb
Host smart-747a7be1-34af-4aad-b259-88383016620a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2555804465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.2555804465
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.1296860599
Short name T805
Test name
Test status
Simulation time 122545806 ps
CPU time 9.98 seconds
Started Jul 29 05:48:06 PM PDT 24
Finished Jul 29 05:48:16 PM PDT 24
Peak memory 248844 kb
Host smart-52689d66-675f-4539-b363-cdae1c3578bf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1296860599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.1296860599
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.924851470
Short name T775
Test name
Test status
Simulation time 368053590 ps
CPU time 13.25 seconds
Started Jul 29 05:48:10 PM PDT 24
Finished Jul 29 05:48:24 PM PDT 24
Peak memory 243148 kb
Host smart-61fdd7aa-6f7a-4dd6-b4dc-dd3b452cd611
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924851470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 1.alert_handler_csr_mem_rw_with_rand_reset.924851470
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.2466558465
Short name T807
Test name
Test status
Simulation time 33026077 ps
CPU time 5.36 seconds
Started Jul 29 05:48:08 PM PDT 24
Finished Jul 29 05:48:14 PM PDT 24
Peak memory 237716 kb
Host smart-e38c8643-79e3-401b-8850-a10084df48af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2466558465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.2466558465
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.2183221448
Short name T742
Test name
Test status
Simulation time 6836149 ps
CPU time 1.45 seconds
Started Jul 29 05:48:04 PM PDT 24
Finished Jul 29 05:48:05 PM PDT 24
Peak memory 236740 kb
Host smart-e81aaeda-4c7c-42b6-afdb-e428b529db8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2183221448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.2183221448
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.3774275899
Short name T251
Test name
Test status
Simulation time 2696925672 ps
CPU time 42.17 seconds
Started Jul 29 05:48:09 PM PDT 24
Finished Jul 29 05:48:51 PM PDT 24
Peak memory 248916 kb
Host smart-d5a9493f-2b1c-4f56-9c16-ee204e7e3cca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3774275899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.3774275899
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.2429174688
Short name T152
Test name
Test status
Simulation time 2798248623 ps
CPU time 155.18 seconds
Started Jul 29 05:48:07 PM PDT 24
Finished Jul 29 05:50:42 PM PDT 24
Peak memory 265604 kb
Host smart-9424282c-d23a-4620-a6cb-c267949a35d2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2429174688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.2429174688
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.940962041
Short name T254
Test name
Test status
Simulation time 483091454 ps
CPU time 8.22 seconds
Started Jul 29 05:48:06 PM PDT 24
Finished Jul 29 05:48:14 PM PDT 24
Peak memory 248904 kb
Host smart-c7794100-3759-4215-b209-d355bd94347a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=940962041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.940962041
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.2794950515
Short name T756
Test name
Test status
Simulation time 148869808 ps
CPU time 11.67 seconds
Started Jul 29 05:48:56 PM PDT 24
Finished Jul 29 05:49:08 PM PDT 24
Peak memory 251860 kb
Host smart-ca45246a-bc35-4f34-a127-ff5d3c78c3ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794950515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.2794950515
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.3781549251
Short name T776
Test name
Test status
Simulation time 217018181 ps
CPU time 7.4 seconds
Started Jul 29 05:48:57 PM PDT 24
Finished Jul 29 05:49:04 PM PDT 24
Peak memory 236780 kb
Host smart-c798ba1c-286d-4836-883a-d107fb227b1f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3781549251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.3781549251
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.746318888
Short name T178
Test name
Test status
Simulation time 16736516 ps
CPU time 1.74 seconds
Started Jul 29 05:48:58 PM PDT 24
Finished Jul 29 05:48:59 PM PDT 24
Peak memory 237716 kb
Host smart-6ee4c156-4dac-4396-9059-b79b8c5e674f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=746318888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.746318888
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.2315366514
Short name T790
Test name
Test status
Simulation time 644368311 ps
CPU time 37.15 seconds
Started Jul 29 05:48:57 PM PDT 24
Finished Jul 29 05:49:34 PM PDT 24
Peak memory 245908 kb
Host smart-5d8b4f78-16e7-48c0-9f0c-050f0e5e531b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2315366514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.2315366514
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.2441430284
Short name T157
Test name
Test status
Simulation time 2999983512 ps
CPU time 177.08 seconds
Started Jul 29 05:48:55 PM PDT 24
Finished Jul 29 05:51:52 PM PDT 24
Peak memory 265600 kb
Host smart-15d86a69-793f-434b-8dd9-5613f80ef056
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2441430284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.2441430284
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.2694517040
Short name T169
Test name
Test status
Simulation time 24684894452 ps
CPU time 541.5 seconds
Started Jul 29 05:48:52 PM PDT 24
Finished Jul 29 05:57:54 PM PDT 24
Peak memory 265820 kb
Host smart-668f83c9-a21e-4c68-ad3e-87e3547db332
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694517040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.2694517040
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.2720778944
Short name T799
Test name
Test status
Simulation time 144558599 ps
CPU time 5.59 seconds
Started Jul 29 05:48:53 PM PDT 24
Finished Jul 29 05:48:59 PM PDT 24
Peak memory 248820 kb
Host smart-3dae96ab-c6f4-4002-a281-322793801009
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2720778944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.2720778944
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.2272531630
Short name T824
Test name
Test status
Simulation time 333064066 ps
CPU time 6.61 seconds
Started Jul 29 05:49:01 PM PDT 24
Finished Jul 29 05:49:08 PM PDT 24
Peak memory 239724 kb
Host smart-77499ce8-1aa0-48b3-953b-1a8421c67d5a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272531630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.2272531630
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.1253686022
Short name T252
Test name
Test status
Simulation time 258588408 ps
CPU time 5.67 seconds
Started Jul 29 05:49:00 PM PDT 24
Finished Jul 29 05:49:06 PM PDT 24
Peak memory 237708 kb
Host smart-a8210842-0ff4-4346-8021-87b439027e59
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1253686022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.1253686022
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.1129009973
Short name T362
Test name
Test status
Simulation time 12220889 ps
CPU time 1.7 seconds
Started Jul 29 05:49:03 PM PDT 24
Finished Jul 29 05:49:05 PM PDT 24
Peak memory 237680 kb
Host smart-023a8331-f66c-4502-81ab-1f0df9bdabe2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1129009973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.1129009973
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.2608186751
Short name T780
Test name
Test status
Simulation time 2958192195 ps
CPU time 44.79 seconds
Started Jul 29 05:49:02 PM PDT 24
Finished Jul 29 05:49:47 PM PDT 24
Peak memory 245964 kb
Host smart-b89c9260-de5e-4f90-8e59-eb55c243aac9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2608186751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.2608186751
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.3906886737
Short name T151
Test name
Test status
Simulation time 11374317351 ps
CPU time 188.64 seconds
Started Jul 29 05:49:02 PM PDT 24
Finished Jul 29 05:52:11 PM PDT 24
Peak memory 268876 kb
Host smart-d47a21f5-bb39-42e1-a786-cd51acb4702b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3906886737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.3906886737
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.1587137691
Short name T778
Test name
Test status
Simulation time 413236900 ps
CPU time 8.84 seconds
Started Jul 29 05:49:03 PM PDT 24
Finished Jul 29 05:49:12 PM PDT 24
Peak memory 248712 kb
Host smart-91687d13-b542-4bb5-9a9d-2c2dfb89a7f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1587137691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.1587137691
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.443071998
Short name T815
Test name
Test status
Simulation time 189346327 ps
CPU time 15.06 seconds
Started Jul 29 05:49:14 PM PDT 24
Finished Jul 29 05:49:29 PM PDT 24
Peak memory 251948 kb
Host smart-d6c37223-b5e2-4591-93e0-941a313a37d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443071998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 12.alert_handler_csr_mem_rw_with_rand_reset.443071998
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.1530124454
Short name T827
Test name
Test status
Simulation time 1764710364 ps
CPU time 7.7 seconds
Started Jul 29 05:49:10 PM PDT 24
Finished Jul 29 05:49:17 PM PDT 24
Peak memory 240648 kb
Host smart-88552190-c8c7-47e7-868d-081b7aaab8a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1530124454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.1530124454
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.382284163
Short name T765
Test name
Test status
Simulation time 17686786 ps
CPU time 1.56 seconds
Started Jul 29 05:49:09 PM PDT 24
Finished Jul 29 05:49:11 PM PDT 24
Peak memory 237624 kb
Host smart-a15f0c8e-b4e4-40ce-a148-4f0a620f6c8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=382284163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.382284163
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.658158417
Short name T779
Test name
Test status
Simulation time 1022435041 ps
CPU time 40.71 seconds
Started Jul 29 05:49:11 PM PDT 24
Finished Jul 29 05:49:52 PM PDT 24
Peak memory 248844 kb
Host smart-f5aaf2f8-cbf9-441f-8924-d3dbb8f74eb4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=658158417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_out
standing.658158417
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.3603717813
Short name T173
Test name
Test status
Simulation time 8924571080 ps
CPU time 325.04 seconds
Started Jul 29 05:49:04 PM PDT 24
Finished Jul 29 05:54:29 PM PDT 24
Peak memory 265584 kb
Host smart-c106d251-6e1a-4ccd-b75e-c3e3f0edfd56
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603717813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.3603717813
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.2522068111
Short name T781
Test name
Test status
Simulation time 183588905 ps
CPU time 6.93 seconds
Started Jul 29 05:49:07 PM PDT 24
Finished Jul 29 05:49:14 PM PDT 24
Peak memory 248876 kb
Host smart-71ba5f94-fbf8-48fc-84be-9b1b1e41472a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2522068111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.2522068111
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.2133353259
Short name T825
Test name
Test status
Simulation time 34576870 ps
CPU time 4.54 seconds
Started Jul 29 05:49:08 PM PDT 24
Finished Jul 29 05:49:13 PM PDT 24
Peak memory 241572 kb
Host smart-47c7952f-dd9a-4eaf-b881-91944b6b65cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133353259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.2133353259
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.226320599
Short name T749
Test name
Test status
Simulation time 25502358 ps
CPU time 3.26 seconds
Started Jul 29 05:49:11 PM PDT 24
Finished Jul 29 05:49:14 PM PDT 24
Peak memory 236776 kb
Host smart-a03cba22-0c04-4782-aff1-30e5e863c6c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=226320599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.226320599
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.1903559348
Short name T789
Test name
Test status
Simulation time 10578739 ps
CPU time 1.29 seconds
Started Jul 29 05:49:09 PM PDT 24
Finished Jul 29 05:49:10 PM PDT 24
Peak memory 235764 kb
Host smart-5dbe3e5f-ba72-4813-9c26-a85fe9f1325a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1903559348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.1903559348
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.2539571598
Short name T816
Test name
Test status
Simulation time 315612057 ps
CPU time 20.62 seconds
Started Jul 29 05:49:10 PM PDT 24
Finished Jul 29 05:49:31 PM PDT 24
Peak memory 244976 kb
Host smart-20a0f816-33a5-46cd-9545-417b3ab9767b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2539571598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.2539571598
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.2742355296
Short name T159
Test name
Test status
Simulation time 15153172968 ps
CPU time 151.34 seconds
Started Jul 29 05:49:10 PM PDT 24
Finished Jul 29 05:51:41 PM PDT 24
Peak memory 265808 kb
Host smart-3cdfeada-8668-4a71-a5ba-cdc531fea9c3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2742355296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.2742355296
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.3248286440
Short name T785
Test name
Test status
Simulation time 234564395 ps
CPU time 6.75 seconds
Started Jul 29 05:49:10 PM PDT 24
Finished Jul 29 05:49:17 PM PDT 24
Peak memory 253760 kb
Host smart-1fd4ebf0-e3b8-4d41-97df-89760ee0eb7d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3248286440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.3248286440
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.3534946540
Short name T218
Test name
Test status
Simulation time 44896724 ps
CPU time 2.55 seconds
Started Jul 29 05:49:11 PM PDT 24
Finished Jul 29 05:49:14 PM PDT 24
Peak memory 236752 kb
Host smart-cd04ac56-ffe7-4151-bdb1-c2924aa77f14
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3534946540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.3534946540
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.1996520868
Short name T804
Test name
Test status
Simulation time 381243799 ps
CPU time 8.27 seconds
Started Jul 29 05:49:12 PM PDT 24
Finished Jul 29 05:49:20 PM PDT 24
Peak memory 238436 kb
Host smart-48c3a3bb-51f7-4231-b3f3-9034254cca09
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996520868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.1996520868
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.128099008
Short name T212
Test name
Test status
Simulation time 143724313 ps
CPU time 3.25 seconds
Started Jul 29 05:49:16 PM PDT 24
Finished Jul 29 05:49:19 PM PDT 24
Peak memory 240828 kb
Host smart-fc62b56d-6deb-4519-8939-deedf93bec27
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=128099008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.128099008
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.1380324964
Short name T724
Test name
Test status
Simulation time 8657412 ps
CPU time 1.42 seconds
Started Jul 29 05:49:15 PM PDT 24
Finished Jul 29 05:49:16 PM PDT 24
Peak memory 237728 kb
Host smart-590bdb1f-8f67-418e-bb75-8e6f050153af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1380324964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.1380324964
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.3126568677
Short name T802
Test name
Test status
Simulation time 591045813 ps
CPU time 20.37 seconds
Started Jul 29 05:49:13 PM PDT 24
Finished Jul 29 05:49:34 PM PDT 24
Peak memory 248828 kb
Host smart-cf7305d2-036f-46aa-bf18-116d1891da12
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3126568677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.3126568677
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.111608666
Short name T156
Test name
Test status
Simulation time 12976195312 ps
CPU time 950.87 seconds
Started Jul 29 05:49:15 PM PDT 24
Finished Jul 29 06:05:06 PM PDT 24
Peak memory 265544 kb
Host smart-2dc6d14a-c90d-44fa-a7b7-6b347b27a4c3
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111608666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.111608666
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.2826402519
Short name T744
Test name
Test status
Simulation time 143303955 ps
CPU time 9.39 seconds
Started Jul 29 05:49:14 PM PDT 24
Finished Jul 29 05:49:23 PM PDT 24
Peak memory 248708 kb
Host smart-99c355d7-f704-4fa8-ba7d-0b032a574f5f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2826402519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.2826402519
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.2220157464
Short name T820
Test name
Test status
Simulation time 54080042 ps
CPU time 2.08 seconds
Started Jul 29 05:49:17 PM PDT 24
Finished Jul 29 05:49:20 PM PDT 24
Peak memory 237012 kb
Host smart-bf2303e0-d5d9-4256-bc7b-b1d2eb8b9547
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2220157464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.2220157464
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.405901899
Short name T793
Test name
Test status
Simulation time 110447145 ps
CPU time 4.98 seconds
Started Jul 29 05:49:17 PM PDT 24
Finished Jul 29 05:49:22 PM PDT 24
Peak memory 257100 kb
Host smart-ea0306a4-ed0a-4c2d-b37d-5c0f487e1701
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405901899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 15.alert_handler_csr_mem_rw_with_rand_reset.405901899
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.2703872682
Short name T247
Test name
Test status
Simulation time 187782095 ps
CPU time 9.08 seconds
Started Jul 29 05:49:18 PM PDT 24
Finished Jul 29 05:49:28 PM PDT 24
Peak memory 240676 kb
Host smart-050cf117-11ff-498f-a530-02c5be3605ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2703872682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.2703872682
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.3799962793
Short name T819
Test name
Test status
Simulation time 10028475 ps
CPU time 1.57 seconds
Started Jul 29 05:49:20 PM PDT 24
Finished Jul 29 05:49:21 PM PDT 24
Peak memory 237728 kb
Host smart-8cec075f-b1c5-445d-9fb3-4a7ab79401e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3799962793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.3799962793
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.1873374659
Short name T768
Test name
Test status
Simulation time 93455081 ps
CPU time 12.71 seconds
Started Jul 29 05:49:19 PM PDT 24
Finished Jul 29 05:49:32 PM PDT 24
Peak memory 245868 kb
Host smart-c62a75f4-0390-47fd-a358-b74ccccb343d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1873374659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.1873374659
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.3636098025
Short name T168
Test name
Test status
Simulation time 8822629837 ps
CPU time 370.32 seconds
Started Jul 29 05:49:14 PM PDT 24
Finished Jul 29 05:55:24 PM PDT 24
Peak memory 265768 kb
Host smart-17f8aeca-d841-446e-8fe2-64201a0d9fd1
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636098025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.3636098025
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.517422010
Short name T818
Test name
Test status
Simulation time 48648042 ps
CPU time 7.47 seconds
Started Jul 29 05:49:16 PM PDT 24
Finished Jul 29 05:49:23 PM PDT 24
Peak memory 248640 kb
Host smart-28dcfb5a-09c4-465e-ad88-0e5b9024685e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=517422010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.517422010
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.3122111626
Short name T288
Test name
Test status
Simulation time 1312945237 ps
CPU time 48.54 seconds
Started Jul 29 05:49:23 PM PDT 24
Finished Jul 29 05:50:11 PM PDT 24
Peak memory 240612 kb
Host smart-b4c6daaa-73b5-4a23-b785-5c4bf4f8d099
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3122111626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.3122111626
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.164795616
Short name T193
Test name
Test status
Simulation time 178055911 ps
CPU time 11.12 seconds
Started Jul 29 05:49:25 PM PDT 24
Finished Jul 29 05:49:37 PM PDT 24
Peak memory 251812 kb
Host smart-68ff9b0b-ca53-4898-91ec-44521d094465
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164795616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 16.alert_handler_csr_mem_rw_with_rand_reset.164795616
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.2599877525
Short name T732
Test name
Test status
Simulation time 184941566 ps
CPU time 5.38 seconds
Started Jul 29 05:49:21 PM PDT 24
Finished Jul 29 05:49:26 PM PDT 24
Peak memory 237672 kb
Host smart-f8e5c6bc-3ddd-493a-b42b-68072d502bcc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2599877525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.2599877525
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.294869894
Short name T180
Test name
Test status
Simulation time 8958242 ps
CPU time 1.23 seconds
Started Jul 29 05:49:18 PM PDT 24
Finished Jul 29 05:49:19 PM PDT 24
Peak memory 237672 kb
Host smart-eaf980f7-0bd7-4f84-b742-0c1eb75842f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=294869894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.294869894
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.530014174
Short name T752
Test name
Test status
Simulation time 88909771 ps
CPU time 11.4 seconds
Started Jul 29 05:49:19 PM PDT 24
Finished Jul 29 05:49:30 PM PDT 24
Peak memory 244988 kb
Host smart-72d23b7e-0812-4f9a-8c7b-bec4cb27138d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=530014174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_out
standing.530014174
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.1265774586
Short name T371
Test name
Test status
Simulation time 11244151739 ps
CPU time 761.08 seconds
Started Jul 29 05:49:19 PM PDT 24
Finished Jul 29 06:02:00 PM PDT 24
Peak memory 273208 kb
Host smart-a57af747-b5f7-4e7c-a858-59b4280806dd
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265774586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.1265774586
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.899956597
Short name T723
Test name
Test status
Simulation time 1215714565 ps
CPU time 18.06 seconds
Started Jul 29 05:49:19 PM PDT 24
Finished Jul 29 05:49:37 PM PDT 24
Peak memory 249920 kb
Host smart-54cf102c-e5b1-40d0-b673-7bb3fa7f7851
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=899956597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.899956597
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.3337252106
Short name T829
Test name
Test status
Simulation time 511685496 ps
CPU time 11.13 seconds
Started Jul 29 05:49:24 PM PDT 24
Finished Jul 29 05:49:35 PM PDT 24
Peak memory 248792 kb
Host smart-79f1408b-28b4-457c-8467-1621d56386ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337252106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.3337252106
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.117629522
Short name T746
Test name
Test status
Simulation time 234241906 ps
CPU time 4.48 seconds
Started Jul 29 05:49:23 PM PDT 24
Finished Jul 29 05:49:28 PM PDT 24
Peak memory 240644 kb
Host smart-2d817bbd-dacf-4ef3-ab19-3008fb9cce1d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=117629522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.117629522
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.2384685781
Short name T257
Test name
Test status
Simulation time 10203430 ps
CPU time 1.67 seconds
Started Jul 29 05:49:25 PM PDT 24
Finished Jul 29 05:49:27 PM PDT 24
Peak memory 236772 kb
Host smart-9d2744d6-8230-443b-8fbc-f478e13d749e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2384685781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.2384685781
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.3304266718
Short name T739
Test name
Test status
Simulation time 2691155685 ps
CPU time 20.43 seconds
Started Jul 29 05:49:23 PM PDT 24
Finished Jul 29 05:49:44 PM PDT 24
Peak memory 245064 kb
Host smart-60dcc8b0-3780-4706-bc35-f1ba703e1bd0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3304266718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.3304266718
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.624087045
Short name T154
Test name
Test status
Simulation time 1152846967 ps
CPU time 112.24 seconds
Started Jul 29 05:49:24 PM PDT 24
Finished Jul 29 05:51:16 PM PDT 24
Peak memory 257252 kb
Host smart-bdc42f42-89c8-44f1-a422-227c5a6353f7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=624087045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_erro
rs.624087045
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.4204304572
Short name T162
Test name
Test status
Simulation time 67016074687 ps
CPU time 1131.89 seconds
Started Jul 29 05:49:25 PM PDT 24
Finished Jul 29 06:08:17 PM PDT 24
Peak memory 265632 kb
Host smart-b1ada53c-d22c-4333-9dd3-354268be1e14
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204304572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.4204304572
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.2529961822
Short name T783
Test name
Test status
Simulation time 334699228 ps
CPU time 21.7 seconds
Started Jul 29 05:49:24 PM PDT 24
Finished Jul 29 05:49:46 PM PDT 24
Peak memory 254044 kb
Host smart-53e578f4-7774-4e0c-a93e-24d4d65cf5ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2529961822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.2529961822
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.295513731
Short name T773
Test name
Test status
Simulation time 435295230 ps
CPU time 7.52 seconds
Started Jul 29 05:49:27 PM PDT 24
Finished Jul 29 05:49:34 PM PDT 24
Peak memory 240712 kb
Host smart-f44e987e-6449-4645-8a92-7d75d41bec20
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295513731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 18.alert_handler_csr_mem_rw_with_rand_reset.295513731
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.3269015217
Short name T794
Test name
Test status
Simulation time 164855140 ps
CPU time 4.17 seconds
Started Jul 29 05:49:29 PM PDT 24
Finished Jul 29 05:49:33 PM PDT 24
Peak memory 236820 kb
Host smart-2dd436a4-9a79-41c5-8b10-f6afbb2d7922
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3269015217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.3269015217
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.599269265
Short name T782
Test name
Test status
Simulation time 22687221 ps
CPU time 1.38 seconds
Started Jul 29 05:49:25 PM PDT 24
Finished Jul 29 05:49:26 PM PDT 24
Peak memory 236676 kb
Host smart-2e591d71-38db-4a11-a353-c33c449f2649
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=599269265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.599269265
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.1834053331
Short name T792
Test name
Test status
Simulation time 182881634 ps
CPU time 22.5 seconds
Started Jul 29 05:49:29 PM PDT 24
Finished Jul 29 05:49:51 PM PDT 24
Peak memory 245900 kb
Host smart-79bb4550-96e7-4edb-88c4-5c9b3480b214
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1834053331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.1834053331
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.1450479408
Short name T170
Test name
Test status
Simulation time 12983412955 ps
CPU time 1098.88 seconds
Started Jul 29 05:49:24 PM PDT 24
Finished Jul 29 06:07:43 PM PDT 24
Peak memory 273768 kb
Host smart-4af22cd3-4d56-4854-addb-b518ddd44f84
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450479408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.1450479408
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.973284145
Short name T800
Test name
Test status
Simulation time 109769158 ps
CPU time 6.67 seconds
Started Jul 29 05:49:26 PM PDT 24
Finished Jul 29 05:49:32 PM PDT 24
Peak memory 248752 kb
Host smart-2afa5f56-3ec4-44c8-b31c-50c929c52f3c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=973284145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.973284145
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.2249697319
Short name T177
Test name
Test status
Simulation time 1861432004 ps
CPU time 34.08 seconds
Started Jul 29 05:49:24 PM PDT 24
Finished Jul 29 05:49:58 PM PDT 24
Peak memory 245820 kb
Host smart-38fa5a97-1176-4f3f-b44f-9c24f2ff1fe7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2249697319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.2249697319
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.26831535
Short name T767
Test name
Test status
Simulation time 543313056 ps
CPU time 9.9 seconds
Started Jul 29 05:49:36 PM PDT 24
Finished Jul 29 05:49:47 PM PDT 24
Peak memory 249888 kb
Host smart-956289dd-bbca-4993-b2cb-cccab14c062d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26831535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 19.alert_handler_csr_mem_rw_with_rand_reset.26831535
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.2239301035
Short name T373
Test name
Test status
Simulation time 169724311 ps
CPU time 4.95 seconds
Started Jul 29 05:49:35 PM PDT 24
Finished Jul 29 05:49:40 PM PDT 24
Peak memory 237680 kb
Host smart-51b2c866-4331-41ab-9d8e-ae81781f2959
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2239301035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.2239301035
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.3811289530
Short name T365
Test name
Test status
Simulation time 11341042 ps
CPU time 1.33 seconds
Started Jul 29 05:49:35 PM PDT 24
Finished Jul 29 05:49:36 PM PDT 24
Peak memory 236832 kb
Host smart-7ad11ad7-d845-4691-9b78-3c3df4c1f074
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3811289530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.3811289530
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.4225768896
Short name T777
Test name
Test status
Simulation time 1907185502 ps
CPU time 32.92 seconds
Started Jul 29 05:49:34 PM PDT 24
Finished Jul 29 05:50:07 PM PDT 24
Peak memory 245872 kb
Host smart-4a571c2b-e4cf-408f-b591-8061347e22f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4225768896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.4225768896
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.3967702650
Short name T165
Test name
Test status
Simulation time 2728115358 ps
CPU time 78.16 seconds
Started Jul 29 05:49:28 PM PDT 24
Finished Jul 29 05:50:46 PM PDT 24
Peak memory 265600 kb
Host smart-439fca07-28ca-4272-a964-17e25c9b0978
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3967702650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.3967702650
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.844745642
Short name T144
Test name
Test status
Simulation time 8839612525 ps
CPU time 353.64 seconds
Started Jul 29 05:49:29 PM PDT 24
Finished Jul 29 05:55:23 PM PDT 24
Peak memory 265616 kb
Host smart-726d1ee1-732a-409c-b034-01db215d0791
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844745642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.844745642
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.2451948397
Short name T250
Test name
Test status
Simulation time 182237566 ps
CPU time 13.18 seconds
Started Jul 29 05:49:28 PM PDT 24
Finished Jul 29 05:49:42 PM PDT 24
Peak memory 248852 kb
Host smart-0589dbb7-72d3-403e-af75-4e09f49add98
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2451948397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.2451948397
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.2964407673
Short name T211
Test name
Test status
Simulation time 5779122225 ps
CPU time 103.85 seconds
Started Jul 29 05:48:09 PM PDT 24
Finished Jul 29 05:49:53 PM PDT 24
Peak memory 240772 kb
Host smart-0fbbda32-29c9-4e82-856a-7d0b63d981db
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2964407673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.2964407673
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.2814564491
Short name T755
Test name
Test status
Simulation time 17816589880 ps
CPU time 195.84 seconds
Started Jul 29 05:48:10 PM PDT 24
Finished Jul 29 05:51:26 PM PDT 24
Peak memory 240780 kb
Host smart-70c50a5f-2b37-4abc-bdbe-e715fd3af7ed
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2814564491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.2814564491
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.964423070
Short name T817
Test name
Test status
Simulation time 135430465 ps
CPU time 5.21 seconds
Started Jul 29 05:48:09 PM PDT 24
Finished Jul 29 05:48:14 PM PDT 24
Peak memory 249180 kb
Host smart-bccf41af-981c-4b6c-9cca-888a4e82cd46
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=964423070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.964423070
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.1353778431
Short name T772
Test name
Test status
Simulation time 114786728 ps
CPU time 4.87 seconds
Started Jul 29 05:48:15 PM PDT 24
Finished Jul 29 05:48:20 PM PDT 24
Peak memory 242532 kb
Host smart-f540ad9a-59b3-40e0-8e61-45c660fda294
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353778431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.1353778431
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.2580634060
Short name T208
Test name
Test status
Simulation time 33764123 ps
CPU time 5.72 seconds
Started Jul 29 05:48:10 PM PDT 24
Finished Jul 29 05:48:16 PM PDT 24
Peak memory 240596 kb
Host smart-78a145b9-c37f-4d6a-a9f9-65d1d2c7ff01
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2580634060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.2580634060
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.3282407779
Short name T771
Test name
Test status
Simulation time 7294539 ps
CPU time 1.38 seconds
Started Jul 29 05:48:10 PM PDT 24
Finished Jul 29 05:48:11 PM PDT 24
Peak memory 237560 kb
Host smart-2beba458-9025-41b6-b164-a59c362df3ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3282407779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.3282407779
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.1789361718
Short name T784
Test name
Test status
Simulation time 237266415 ps
CPU time 16.36 seconds
Started Jul 29 05:48:13 PM PDT 24
Finished Jul 29 05:48:30 PM PDT 24
Peak memory 245876 kb
Host smart-bd749aca-481e-47dc-99c7-e605a8cbb12a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1789361718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.1789361718
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.412351718
Short name T167
Test name
Test status
Simulation time 4388252286 ps
CPU time 644.37 seconds
Started Jul 29 05:48:09 PM PDT 24
Finished Jul 29 05:58:54 PM PDT 24
Peak memory 265596 kb
Host smart-021ec0a1-42e4-4b0c-b0eb-60cb45635fd6
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412351718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.412351718
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.1743170094
Short name T763
Test name
Test status
Simulation time 484332834 ps
CPU time 12.53 seconds
Started Jul 29 05:48:08 PM PDT 24
Finished Jul 29 05:48:21 PM PDT 24
Peak memory 249096 kb
Host smart-affb7bb0-178e-4e05-a403-6fc023514f67
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1743170094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.1743170094
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.3415369551
Short name T176
Test name
Test status
Simulation time 106855134 ps
CPU time 2.95 seconds
Started Jul 29 05:48:08 PM PDT 24
Finished Jul 29 05:48:11 PM PDT 24
Peak memory 237708 kb
Host smart-cdcfee48-99e0-4c47-9cbb-3727a9e84476
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3415369551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.3415369551
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.610604682
Short name T726
Test name
Test status
Simulation time 11871140 ps
CPU time 1.27 seconds
Started Jul 29 05:49:35 PM PDT 24
Finished Jul 29 05:49:36 PM PDT 24
Peak memory 235632 kb
Host smart-dd724869-c254-40e4-af96-8ff92084798b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=610604682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.610604682
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.722580074
Short name T367
Test name
Test status
Simulation time 10786724 ps
CPU time 1.66 seconds
Started Jul 29 05:49:35 PM PDT 24
Finished Jul 29 05:49:37 PM PDT 24
Peak memory 236836 kb
Host smart-94f22adb-d23b-4c23-84aa-e4c23825adc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=722580074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.722580074
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.977950788
Short name T750
Test name
Test status
Simulation time 8218886 ps
CPU time 1.44 seconds
Started Jul 29 05:49:33 PM PDT 24
Finished Jul 29 05:49:35 PM PDT 24
Peak memory 237704 kb
Host smart-0dacb245-2f07-416c-b32b-768b75dc84da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=977950788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.977950788
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.1622663271
Short name T740
Test name
Test status
Simulation time 14715020 ps
CPU time 1.29 seconds
Started Jul 29 05:49:35 PM PDT 24
Finished Jul 29 05:49:36 PM PDT 24
Peak memory 235716 kb
Host smart-facff34d-7327-4b47-bd3f-f359558ab11d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1622663271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.1622663271
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.962458710
Short name T758
Test name
Test status
Simulation time 7970889 ps
CPU time 1.52 seconds
Started Jul 29 05:49:33 PM PDT 24
Finished Jul 29 05:49:34 PM PDT 24
Peak memory 235812 kb
Host smart-42ae0d88-dfef-4601-a24a-b34aff939600
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=962458710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.962458710
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.4103487766
Short name T363
Test name
Test status
Simulation time 19094452 ps
CPU time 1.46 seconds
Started Jul 29 05:49:33 PM PDT 24
Finished Jul 29 05:49:35 PM PDT 24
Peak memory 237652 kb
Host smart-a0a5d7c1-a9b2-457b-9e68-9f5c6189aeec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4103487766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.4103487766
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.3279292977
Short name T364
Test name
Test status
Simulation time 17893535 ps
CPU time 1.38 seconds
Started Jul 29 05:49:34 PM PDT 24
Finished Jul 29 05:49:36 PM PDT 24
Peak memory 236712 kb
Host smart-c64da1db-219d-4f12-b0ba-7f06746b202c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3279292977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.3279292977
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.1627248610
Short name T766
Test name
Test status
Simulation time 11003693 ps
CPU time 1.24 seconds
Started Jul 29 05:49:38 PM PDT 24
Finished Jul 29 05:49:39 PM PDT 24
Peak memory 237680 kb
Host smart-d6b6c4fb-41a3-4a8c-9349-5a18883e5cf4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1627248610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.1627248610
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.3563548219
Short name T811
Test name
Test status
Simulation time 10522440 ps
CPU time 1.56 seconds
Started Jul 29 05:49:40 PM PDT 24
Finished Jul 29 05:49:41 PM PDT 24
Peak memory 237676 kb
Host smart-f0999868-da6d-44f2-b4d5-79b1847455c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3563548219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.3563548219
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.1607932068
Short name T738
Test name
Test status
Simulation time 14769565 ps
CPU time 1.42 seconds
Started Jul 29 05:49:36 PM PDT 24
Finished Jul 29 05:49:38 PM PDT 24
Peak memory 237684 kb
Host smart-9d03a94f-37e6-4583-8f83-3e1d62487ddc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1607932068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.1607932068
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.2395423245
Short name T722
Test name
Test status
Simulation time 1116402271 ps
CPU time 140.24 seconds
Started Jul 29 05:48:18 PM PDT 24
Finished Jul 29 05:50:39 PM PDT 24
Peak memory 240668 kb
Host smart-400f0e3b-5efb-459b-a967-51c6200e58c3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2395423245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.2395423245
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.741457174
Short name T725
Test name
Test status
Simulation time 3553400519 ps
CPU time 114.02 seconds
Started Jul 29 05:48:18 PM PDT 24
Finished Jul 29 05:50:12 PM PDT 24
Peak memory 237732 kb
Host smart-c48603d0-079c-4f9b-8b0f-982866e66e71
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=741457174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.741457174
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.1983162435
Short name T248
Test name
Test status
Simulation time 1151842911 ps
CPU time 9.51 seconds
Started Jul 29 05:48:19 PM PDT 24
Finished Jul 29 05:48:28 PM PDT 24
Peak memory 249228 kb
Host smart-31f80a0e-247c-4977-a1ec-bb4bf3fef8c0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1983162435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.1983162435
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.2938026997
Short name T803
Test name
Test status
Simulation time 79909154 ps
CPU time 6.1 seconds
Started Jul 29 05:48:23 PM PDT 24
Finished Jul 29 05:48:29 PM PDT 24
Peak memory 250016 kb
Host smart-817c999c-c0a3-49be-a29d-5623d4bf205f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938026997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.2938026997
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.1181099755
Short name T249
Test name
Test status
Simulation time 213682172 ps
CPU time 4.51 seconds
Started Jul 29 05:48:17 PM PDT 24
Finished Jul 29 05:48:22 PM PDT 24
Peak memory 240616 kb
Host smart-0549ab5e-cd7f-4c01-8d1a-40a99d3c7f20
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1181099755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.1181099755
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.964736855
Short name T743
Test name
Test status
Simulation time 12507523 ps
CPU time 1.24 seconds
Started Jul 29 05:48:14 PM PDT 24
Finished Jul 29 05:48:15 PM PDT 24
Peak memory 236596 kb
Host smart-1c946872-eb76-465e-a2fb-4a8530cfbce0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=964736855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.964736855
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.3940165570
Short name T727
Test name
Test status
Simulation time 174521189 ps
CPU time 22.63 seconds
Started Jul 29 05:48:17 PM PDT 24
Finished Jul 29 05:48:40 PM PDT 24
Peak memory 245900 kb
Host smart-3ed99fda-629a-4340-8a99-d2b25ef52ff4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3940165570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.3940165570
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.547243234
Short name T163
Test name
Test status
Simulation time 16538958379 ps
CPU time 287.85 seconds
Started Jul 29 05:48:15 PM PDT 24
Finished Jul 29 05:53:03 PM PDT 24
Peak memory 266692 kb
Host smart-759e3246-18fe-410a-91b2-f414e68fdc46
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=547243234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_error
s.547243234
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.2577404690
Short name T148
Test name
Test status
Simulation time 6393451281 ps
CPU time 425.69 seconds
Started Jul 29 05:48:12 PM PDT 24
Finished Jul 29 05:55:17 PM PDT 24
Peak memory 269576 kb
Host smart-be1b1d75-cd91-488d-834a-33970214656a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577404690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.2577404690
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.83827228
Short name T814
Test name
Test status
Simulation time 461032822 ps
CPU time 7.16 seconds
Started Jul 29 05:48:13 PM PDT 24
Finished Jul 29 05:48:20 PM PDT 24
Peak memory 251424 kb
Host smart-2ec107f3-1d52-479c-95c0-02a94ce66d40
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=83827228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.83827228
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.393428628
Short name T770
Test name
Test status
Simulation time 17855158 ps
CPU time 1.51 seconds
Started Jul 29 05:49:39 PM PDT 24
Finished Jul 29 05:49:40 PM PDT 24
Peak memory 237720 kb
Host smart-4a8290ee-0059-498e-ba4c-821a99200a3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=393428628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.393428628
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.2277218715
Short name T762
Test name
Test status
Simulation time 29548578 ps
CPU time 1.3 seconds
Started Jul 29 05:49:40 PM PDT 24
Finished Jul 29 05:49:41 PM PDT 24
Peak memory 236672 kb
Host smart-10723afb-2a8d-4fa4-b5c3-3c934c8c558d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2277218715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.2277218715
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.2183190938
Short name T735
Test name
Test status
Simulation time 6584086 ps
CPU time 1.41 seconds
Started Jul 29 05:49:39 PM PDT 24
Finished Jul 29 05:49:40 PM PDT 24
Peak memory 237688 kb
Host smart-30dc3f89-8b46-497c-8fc1-12ae8af21bda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2183190938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.2183190938
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.1553363289
Short name T798
Test name
Test status
Simulation time 15230598 ps
CPU time 1.47 seconds
Started Jul 29 05:49:36 PM PDT 24
Finished Jul 29 05:49:38 PM PDT 24
Peak memory 237680 kb
Host smart-c801f97d-4b91-43a5-a3e5-3830c8a02c6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1553363289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.1553363289
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.645233634
Short name T787
Test name
Test status
Simulation time 36737741 ps
CPU time 1.22 seconds
Started Jul 29 05:49:38 PM PDT 24
Finished Jul 29 05:49:39 PM PDT 24
Peak memory 237548 kb
Host smart-52f26b9b-9668-4a0b-a548-639ac822c144
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=645233634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.645233634
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.2494791168
Short name T734
Test name
Test status
Simulation time 8438652 ps
CPU time 1.48 seconds
Started Jul 29 05:49:39 PM PDT 24
Finished Jul 29 05:49:40 PM PDT 24
Peak memory 237704 kb
Host smart-a6972911-89b7-4025-a7f3-0f45a0c22e6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2494791168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.2494791168
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.4197761928
Short name T764
Test name
Test status
Simulation time 7365621 ps
CPU time 1.43 seconds
Started Jul 29 05:49:37 PM PDT 24
Finished Jul 29 05:49:39 PM PDT 24
Peak memory 237704 kb
Host smart-51110d84-d27f-48f9-aaf6-bc960b84ea85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4197761928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.4197761928
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.3005857068
Short name T716
Test name
Test status
Simulation time 20761334 ps
CPU time 1.35 seconds
Started Jul 29 05:49:39 PM PDT 24
Finished Jul 29 05:49:40 PM PDT 24
Peak memory 236736 kb
Host smart-d581611f-0f0a-400c-b09f-b6d654e7ae77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3005857068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.3005857068
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.1652198877
Short name T761
Test name
Test status
Simulation time 6068612 ps
CPU time 1.4 seconds
Started Jul 29 05:49:38 PM PDT 24
Finished Jul 29 05:49:39 PM PDT 24
Peak memory 237620 kb
Host smart-db702ec4-5ff0-46c6-a318-624259c985af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1652198877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.1652198877
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.1088045861
Short name T812
Test name
Test status
Simulation time 1122657306 ps
CPU time 137.6 seconds
Started Jul 29 05:48:28 PM PDT 24
Finished Jul 29 05:50:46 PM PDT 24
Peak memory 240612 kb
Host smart-26512bcb-bafa-48f7-af75-f0fe5862d4e7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1088045861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.1088045861
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.317274251
Short name T769
Test name
Test status
Simulation time 107562257 ps
CPU time 5.31 seconds
Started Jul 29 05:48:22 PM PDT 24
Finished Jul 29 05:48:28 PM PDT 24
Peak memory 240556 kb
Host smart-9f728ef0-6d75-4095-ab19-0d24f020dd02
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=317274251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.317274251
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.2861614306
Short name T736
Test name
Test status
Simulation time 183592909 ps
CPU time 12.71 seconds
Started Jul 29 05:48:27 PM PDT 24
Finished Jul 29 05:48:40 PM PDT 24
Peak memory 248960 kb
Host smart-2968d36f-e129-4c7f-ab06-78587787354d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861614306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.2861614306
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.4264084368
Short name T372
Test name
Test status
Simulation time 403937963 ps
CPU time 4.52 seconds
Started Jul 29 05:48:26 PM PDT 24
Finished Jul 29 05:48:31 PM PDT 24
Peak memory 237544 kb
Host smart-1edbf2c8-58af-49a3-81fb-1203f35e4862
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4264084368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.4264084368
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.2193850710
Short name T823
Test name
Test status
Simulation time 8968345 ps
CPU time 1.26 seconds
Started Jul 29 05:48:22 PM PDT 24
Finished Jul 29 05:48:24 PM PDT 24
Peak memory 235876 kb
Host smart-57008910-f54a-4c19-8f1f-52232ccbb281
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2193850710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.2193850710
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.3416903279
Short name T810
Test name
Test status
Simulation time 3401769092 ps
CPU time 22.38 seconds
Started Jul 29 05:48:26 PM PDT 24
Finished Jul 29 05:48:48 PM PDT 24
Peak memory 245812 kb
Host smart-c0bd4d80-1c34-4e1d-bfa0-60ce188a8ec9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3416903279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.3416903279
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.1744439039
Short name T146
Test name
Test status
Simulation time 4875233542 ps
CPU time 324.88 seconds
Started Jul 29 05:48:21 PM PDT 24
Finished Jul 29 05:53:46 PM PDT 24
Peak memory 265572 kb
Host smart-6899c85f-28e2-42f1-838d-43b7ba46412b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1744439039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.1744439039
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.1777205848
Short name T808
Test name
Test status
Simulation time 36381938 ps
CPU time 5.32 seconds
Started Jul 29 05:48:22 PM PDT 24
Finished Jul 29 05:48:28 PM PDT 24
Peak memory 248916 kb
Host smart-877757be-247a-4975-a5d0-a35633721466
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1777205848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.1777205848
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.580032513
Short name T720
Test name
Test status
Simulation time 9938902 ps
CPU time 1.59 seconds
Started Jul 29 05:49:40 PM PDT 24
Finished Jul 29 05:49:41 PM PDT 24
Peak memory 236784 kb
Host smart-9ea4bc16-8ab9-474e-b631-7b4322a43d6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=580032513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.580032513
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.387856733
Short name T754
Test name
Test status
Simulation time 6323635 ps
CPU time 1.4 seconds
Started Jul 29 05:49:44 PM PDT 24
Finished Jul 29 05:49:46 PM PDT 24
Peak memory 237676 kb
Host smart-7d8274a9-6ad3-4140-8710-8ed999ae5f6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=387856733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.387856733
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.2252047745
Short name T801
Test name
Test status
Simulation time 10815928 ps
CPU time 1.24 seconds
Started Jul 29 05:49:43 PM PDT 24
Finished Jul 29 05:49:45 PM PDT 24
Peak memory 236744 kb
Host smart-2f6b9cb0-4b6f-4427-a8d0-c6f3b4cbecc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2252047745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.2252047745
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.161806015
Short name T759
Test name
Test status
Simulation time 12720422 ps
CPU time 1.65 seconds
Started Jul 29 05:49:43 PM PDT 24
Finished Jul 29 05:49:45 PM PDT 24
Peak memory 237608 kb
Host smart-e8489290-4571-4687-be7e-31cee99b3871
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=161806015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.161806015
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.3667702169
Short name T788
Test name
Test status
Simulation time 16847811 ps
CPU time 1.24 seconds
Started Jul 29 05:49:44 PM PDT 24
Finished Jul 29 05:49:45 PM PDT 24
Peak memory 237568 kb
Host smart-81b75bfd-3c4e-496d-acc1-a83c35709289
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3667702169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.3667702169
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.2044435081
Short name T797
Test name
Test status
Simulation time 7571229 ps
CPU time 1.4 seconds
Started Jul 29 05:49:44 PM PDT 24
Finished Jul 29 05:49:45 PM PDT 24
Peak memory 235944 kb
Host smart-58a5573d-0e27-4046-b7d8-1679f61bcfea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2044435081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.2044435081
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.237471438
Short name T809
Test name
Test status
Simulation time 10631905 ps
CPU time 1.55 seconds
Started Jul 29 05:49:44 PM PDT 24
Finished Jul 29 05:49:46 PM PDT 24
Peak memory 237680 kb
Host smart-e0ca6a57-a7ce-4d17-88f6-fa9b0a0417e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=237471438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.237471438
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.1942592518
Short name T730
Test name
Test status
Simulation time 6700761 ps
CPU time 1.49 seconds
Started Jul 29 05:49:48 PM PDT 24
Finished Jul 29 05:49:49 PM PDT 24
Peak memory 235608 kb
Host smart-5a55aee6-64e7-4438-ba2b-6f4babb1b599
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1942592518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.1942592518
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.49490540
Short name T760
Test name
Test status
Simulation time 7986652 ps
CPU time 1.45 seconds
Started Jul 29 05:49:48 PM PDT 24
Finished Jul 29 05:49:49 PM PDT 24
Peak memory 237704 kb
Host smart-848f6e5e-ccfd-40e8-824a-a48556510df3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=49490540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.49490540
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.1768387239
Short name T747
Test name
Test status
Simulation time 40764213 ps
CPU time 4.94 seconds
Started Jul 29 05:48:32 PM PDT 24
Finished Jul 29 05:48:38 PM PDT 24
Peak memory 253140 kb
Host smart-7b5b0bf4-c3e8-4336-b5a1-f03d725f7f47
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768387239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.1768387239
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.341836522
Short name T821
Test name
Test status
Simulation time 182503671 ps
CPU time 4.17 seconds
Started Jul 29 05:48:33 PM PDT 24
Finished Jul 29 05:48:37 PM PDT 24
Peak memory 240632 kb
Host smart-964277df-fccc-49c3-bed0-80292ffcfed7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=341836522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.341836522
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.1526018052
Short name T748
Test name
Test status
Simulation time 8289615 ps
CPU time 1.45 seconds
Started Jul 29 05:48:32 PM PDT 24
Finished Jul 29 05:48:33 PM PDT 24
Peak memory 237676 kb
Host smart-eb8ac583-f55c-4561-8d15-4028bf17ee3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1526018052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.1526018052
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.2892938230
Short name T729
Test name
Test status
Simulation time 90310436 ps
CPU time 11.98 seconds
Started Jul 29 05:48:32 PM PDT 24
Finished Jul 29 05:48:45 PM PDT 24
Peak memory 245872 kb
Host smart-357fe3c7-cf5d-4097-9bc6-f21e9b35f33d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2892938230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.2892938230
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.376265092
Short name T174
Test name
Test status
Simulation time 2151881772 ps
CPU time 308.67 seconds
Started Jul 29 05:48:30 PM PDT 24
Finished Jul 29 05:53:39 PM PDT 24
Peak memory 265660 kb
Host smart-84518a06-bc0d-4e4f-8d1d-8b4701dfdce5
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376265092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.376265092
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.2622694083
Short name T757
Test name
Test status
Simulation time 617229740 ps
CPU time 10.44 seconds
Started Jul 29 05:48:28 PM PDT 24
Finished Jul 29 05:48:38 PM PDT 24
Peak memory 255708 kb
Host smart-42cc7383-84f4-4aa2-8edf-720eed9b97d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2622694083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.2622694083
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.1136660750
Short name T728
Test name
Test status
Simulation time 31325311 ps
CPU time 5.16 seconds
Started Jul 29 05:48:38 PM PDT 24
Finished Jul 29 05:48:44 PM PDT 24
Peak memory 241296 kb
Host smart-ed43b141-6829-41f7-badc-affd3950f668
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136660750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.1136660750
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.2912828285
Short name T210
Test name
Test status
Simulation time 121741484 ps
CPU time 4.77 seconds
Started Jul 29 05:48:39 PM PDT 24
Finished Jul 29 05:48:44 PM PDT 24
Peak memory 237708 kb
Host smart-6152b35d-7bf1-4cdb-8b0e-acfd19af58b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2912828285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.2912828285
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.545825027
Short name T796
Test name
Test status
Simulation time 21312687 ps
CPU time 1.46 seconds
Started Jul 29 05:48:35 PM PDT 24
Finished Jul 29 05:48:37 PM PDT 24
Peak memory 236768 kb
Host smart-8c4a4f9a-27da-41ab-b66d-ed80f34fd640
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=545825027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.545825027
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.1710404946
Short name T791
Test name
Test status
Simulation time 335758584 ps
CPU time 20.41 seconds
Started Jul 29 05:48:37 PM PDT 24
Finished Jul 29 05:48:58 PM PDT 24
Peak memory 248856 kb
Host smart-abeba2af-48df-4577-b678-28af96433d5e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1710404946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.1710404946
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.1690802935
Short name T143
Test name
Test status
Simulation time 3845016379 ps
CPU time 240.54 seconds
Started Jul 29 05:48:31 PM PDT 24
Finished Jul 29 05:52:32 PM PDT 24
Peak memory 266820 kb
Host smart-4252f71c-07a1-42cb-af25-28e6e02b1a44
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1690802935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.1690802935
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.847484898
Short name T141
Test name
Test status
Simulation time 2383324378 ps
CPU time 324.19 seconds
Started Jul 29 05:48:32 PM PDT 24
Finished Jul 29 05:53:57 PM PDT 24
Peak memory 265796 kb
Host smart-192b8f83-bb1d-47d0-96c4-ec0f661c69a4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847484898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.847484898
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.143716730
Short name T828
Test name
Test status
Simulation time 1260950297 ps
CPU time 19.31 seconds
Started Jul 29 05:48:33 PM PDT 24
Finished Jul 29 05:48:52 PM PDT 24
Peak memory 248884 kb
Host smart-733a502d-82c1-48e3-8390-74384ef5e4de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=143716730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.143716730
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.3868065868
Short name T826
Test name
Test status
Simulation time 2045039027 ps
CPU time 36.89 seconds
Started Jul 29 05:48:32 PM PDT 24
Finished Jul 29 05:49:10 PM PDT 24
Peak memory 240580 kb
Host smart-c4eda6f4-422d-4335-9f4b-7a0e0d58f620
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3868065868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.3868065868
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.1741337087
Short name T745
Test name
Test status
Simulation time 410558453 ps
CPU time 7.55 seconds
Started Jul 29 05:48:42 PM PDT 24
Finished Jul 29 05:48:49 PM PDT 24
Peak memory 239968 kb
Host smart-f5a2fb20-26ab-4a10-a709-f0d1887de341
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741337087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.1741337087
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.62506144
Short name T795
Test name
Test status
Simulation time 41994181 ps
CPU time 3.07 seconds
Started Jul 29 05:48:43 PM PDT 24
Finished Jul 29 05:48:46 PM PDT 24
Peak memory 237676 kb
Host smart-4f0c343c-ad3a-493c-aa80-221d1a9eb9d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=62506144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.62506144
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.3540683606
Short name T719
Test name
Test status
Simulation time 14139127 ps
CPU time 1.28 seconds
Started Jul 29 05:48:42 PM PDT 24
Finished Jul 29 05:48:43 PM PDT 24
Peak memory 236828 kb
Host smart-e73e1d26-d0f8-4605-8e1b-e7f21ee0ee52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3540683606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.3540683606
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.1680208801
Short name T822
Test name
Test status
Simulation time 2101571456 ps
CPU time 33.56 seconds
Started Jul 29 05:48:43 PM PDT 24
Finished Jul 29 05:49:17 PM PDT 24
Peak memory 244988 kb
Host smart-73cb0731-c51c-49b4-bd8a-ffd92ae49ef4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1680208801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.1680208801
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.86542596
Short name T172
Test name
Test status
Simulation time 17417663694 ps
CPU time 1167.92 seconds
Started Jul 29 05:48:39 PM PDT 24
Finished Jul 29 06:08:07 PM PDT 24
Peak memory 273596 kb
Host smart-5654dcac-ea1d-4624-b3c5-1e26c49eaed5
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86542596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.86542596
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.3712989788
Short name T715
Test name
Test status
Simulation time 111864062 ps
CPU time 8.58 seconds
Started Jul 29 05:48:39 PM PDT 24
Finished Jul 29 05:48:47 PM PDT 24
Peak memory 247924 kb
Host smart-df540113-acb2-4af8-9cac-b6922df44bcf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3712989788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.3712989788
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.2557484224
Short name T786
Test name
Test status
Simulation time 60741037 ps
CPU time 8.51 seconds
Started Jul 29 05:48:47 PM PDT 24
Finished Jul 29 05:48:55 PM PDT 24
Peak memory 257044 kb
Host smart-8aef5fdc-5b7a-4ecb-980f-e113ac382678
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557484224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.2557484224
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.90972177
Short name T733
Test name
Test status
Simulation time 166705680 ps
CPU time 5.05 seconds
Started Jul 29 05:48:48 PM PDT 24
Finished Jul 29 05:48:54 PM PDT 24
Peak memory 237640 kb
Host smart-09229525-6ec2-47a0-8dfd-3b7485307716
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=90972177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.90972177
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.1998022480
Short name T731
Test name
Test status
Simulation time 9658199 ps
CPU time 1.6 seconds
Started Jul 29 05:48:46 PM PDT 24
Finished Jul 29 05:48:48 PM PDT 24
Peak memory 235720 kb
Host smart-66f3e09c-51de-47e0-87d7-882a9b981058
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1998022480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.1998022480
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.753097300
Short name T741
Test name
Test status
Simulation time 311372497 ps
CPU time 20.69 seconds
Started Jul 29 05:48:48 PM PDT 24
Finished Jul 29 05:49:09 PM PDT 24
Peak memory 240616 kb
Host smart-d9438c5a-82d4-4536-a1a8-7657eea5859b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=753097300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_outs
tanding.753097300
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.2794855119
Short name T145
Test name
Test status
Simulation time 1826024090 ps
CPU time 202.27 seconds
Started Jul 29 05:48:43 PM PDT 24
Finished Jul 29 05:52:05 PM PDT 24
Peak memory 273716 kb
Host smart-99fc01f0-f038-4e40-a3e9-189b8d0ebfcc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2794855119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.2794855119
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.1772865195
Short name T753
Test name
Test status
Simulation time 144899342 ps
CPU time 9.16 seconds
Started Jul 29 05:48:42 PM PDT 24
Finished Jul 29 05:48:52 PM PDT 24
Peak memory 256604 kb
Host smart-0d207e1b-d99a-4948-b616-513afe3cc6f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1772865195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.1772865195
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.1683485952
Short name T751
Test name
Test status
Simulation time 130631235 ps
CPU time 9.99 seconds
Started Jul 29 05:48:52 PM PDT 24
Finished Jul 29 05:49:02 PM PDT 24
Peak memory 251952 kb
Host smart-ef174607-8a08-4cb9-ab24-c92053757d23
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683485952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.1683485952
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.1203158367
Short name T207
Test name
Test status
Simulation time 55703746 ps
CPU time 4.66 seconds
Started Jul 29 05:48:52 PM PDT 24
Finished Jul 29 05:48:57 PM PDT 24
Peak memory 237688 kb
Host smart-98e50841-6201-49cc-99fe-05f4974cf48a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1203158367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.1203158367
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.4127117183
Short name T718
Test name
Test status
Simulation time 11010899 ps
CPU time 1.34 seconds
Started Jul 29 05:48:47 PM PDT 24
Finished Jul 29 05:48:48 PM PDT 24
Peak memory 237716 kb
Host smart-a6a760d5-65e6-48e4-85da-3698ea79a0ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4127117183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.4127117183
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.3970878527
Short name T213
Test name
Test status
Simulation time 657458596 ps
CPU time 22.47 seconds
Started Jul 29 05:48:53 PM PDT 24
Finished Jul 29 05:49:16 PM PDT 24
Peak memory 248812 kb
Host smart-85a2a02e-a490-4712-9f89-971afa1b8d05
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3970878527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.3970878527
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.1186114831
Short name T813
Test name
Test status
Simulation time 2224518563 ps
CPU time 202.98 seconds
Started Jul 29 05:48:49 PM PDT 24
Finished Jul 29 05:52:12 PM PDT 24
Peak memory 265756 kb
Host smart-164d7537-a363-4a8b-a456-5e8e08fe1f5f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1186114831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.1186114831
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.2210957473
Short name T370
Test name
Test status
Simulation time 12118307449 ps
CPU time 568.65 seconds
Started Jul 29 05:48:49 PM PDT 24
Finished Jul 29 05:58:17 PM PDT 24
Peak memory 265604 kb
Host smart-73e99816-6acc-4dec-b63f-de1d91a3b204
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210957473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.2210957473
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.809471348
Short name T253
Test name
Test status
Simulation time 4551273982 ps
CPU time 27.77 seconds
Started Jul 29 05:48:47 PM PDT 24
Finished Jul 29 05:49:15 PM PDT 24
Peak memory 249040 kb
Host smart-90146c91-87dd-4bc7-af39-09fe9ea46512
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=809471348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.809471348
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.618956773
Short name T399
Test name
Test status
Simulation time 37874127069 ps
CPU time 2532.79 seconds
Started Jul 29 05:50:52 PM PDT 24
Finished Jul 29 06:33:05 PM PDT 24
Peak memory 289328 kb
Host smart-7678a331-3ab1-4548-a07b-9917de6430d6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618956773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.618956773
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.1498711609
Short name T503
Test name
Test status
Simulation time 1460215526 ps
CPU time 11.8 seconds
Started Jul 29 05:50:56 PM PDT 24
Finished Jul 29 05:51:07 PM PDT 24
Peak memory 248216 kb
Host smart-c4e3ec77-ff90-4f21-a172-5a6c9ac42036
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1498711609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.1498711609
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.3433415266
Short name T238
Test name
Test status
Simulation time 7408754827 ps
CPU time 128.91 seconds
Started Jul 29 05:50:50 PM PDT 24
Finished Jul 29 05:52:59 PM PDT 24
Peak memory 255972 kb
Host smart-caad2240-193e-493f-9c4a-141cdd349a4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34334
15266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.3433415266
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.2370228656
Short name T134
Test name
Test status
Simulation time 4406473837 ps
CPU time 25.78 seconds
Started Jul 29 05:50:51 PM PDT 24
Finished Jul 29 05:51:16 PM PDT 24
Peak memory 248352 kb
Host smart-047ed4bd-3a7d-4290-b6e5-087d6137a896
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23702
28656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.2370228656
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.2976507506
Short name T704
Test name
Test status
Simulation time 46874712940 ps
CPU time 2553.13 seconds
Started Jul 29 05:50:49 PM PDT 24
Finished Jul 29 06:33:22 PM PDT 24
Peak memory 288464 kb
Host smart-aba4e9b6-ca30-4e58-87cc-fba6d086157d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976507506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.2976507506
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.1818332469
Short name T609
Test name
Test status
Simulation time 222816453565 ps
CPU time 1358.69 seconds
Started Jul 29 05:50:50 PM PDT 24
Finished Jul 29 06:13:29 PM PDT 24
Peak memory 288476 kb
Host smart-ab6309ff-7885-4104-b617-5667aba34dd3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818332469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.1818332469
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.1899379898
Short name T602
Test name
Test status
Simulation time 56437627207 ps
CPU time 481.76 seconds
Started Jul 29 05:50:52 PM PDT 24
Finished Jul 29 05:58:54 PM PDT 24
Peak memory 248384 kb
Host smart-89d8594b-e93f-4c50-86bd-163ff637dc33
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899379898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.1899379898
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.747138541
Short name T386
Test name
Test status
Simulation time 453886615 ps
CPU time 22.62 seconds
Started Jul 29 05:50:47 PM PDT 24
Finished Jul 29 05:51:10 PM PDT 24
Peak memory 248372 kb
Host smart-75edd8a5-c38f-4b90-9bbd-540dc5bb4712
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74713
8541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.747138541
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.1815915524
Short name T31
Test name
Test status
Simulation time 5081588953 ps
CPU time 67.86 seconds
Started Jul 29 05:50:50 PM PDT 24
Finished Jul 29 05:51:58 PM PDT 24
Peak memory 256604 kb
Host smart-068026d7-bad2-473d-aad1-79b116320d62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18159
15524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.1815915524
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.464994773
Short name T10
Test name
Test status
Simulation time 397638761 ps
CPU time 12.07 seconds
Started Jul 29 05:50:49 PM PDT 24
Finished Jul 29 05:51:01 PM PDT 24
Peak memory 270808 kb
Host smart-c3488381-19fc-40a3-8d30-97135b12448e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=464994773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.464994773
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.250485371
Short name T128
Test name
Test status
Simulation time 160836801 ps
CPU time 6.36 seconds
Started Jul 29 05:50:55 PM PDT 24
Finished Jul 29 05:51:01 PM PDT 24
Peak memory 251532 kb
Host smart-d1a85393-1573-421e-848c-6bc12611f55d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25048
5371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.250485371
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.980099792
Short name T460
Test name
Test status
Simulation time 636002025 ps
CPU time 11.86 seconds
Started Jul 29 05:50:46 PM PDT 24
Finished Jul 29 05:50:58 PM PDT 24
Peak memory 248260 kb
Host smart-02cbe8b1-b30b-4491-85d2-7945129992e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98009
9792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.980099792
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.2063139387
Short name T234
Test name
Test status
Simulation time 170051841 ps
CPU time 3.07 seconds
Started Jul 29 05:50:52 PM PDT 24
Finished Jul 29 05:50:55 PM PDT 24
Peak memory 248644 kb
Host smart-227279cb-7b8e-4774-b20c-7eb911a29ea8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2063139387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.2063139387
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.4176294013
Short name T125
Test name
Test status
Simulation time 61429407462 ps
CPU time 1419.46 seconds
Started Jul 29 05:50:50 PM PDT 24
Finished Jul 29 06:14:29 PM PDT 24
Peak memory 286036 kb
Host smart-7cbf5b0c-7024-4eed-926b-4a5283df768f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176294013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.4176294013
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.3133204972
Short name T203
Test name
Test status
Simulation time 5601484188 ps
CPU time 69.87 seconds
Started Jul 29 05:50:55 PM PDT 24
Finished Jul 29 05:52:05 PM PDT 24
Peak memory 256480 kb
Host smart-934d509d-81e3-46b9-adcd-e4b691c7ee29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31332
04972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.3133204972
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.4243969795
Short name T416
Test name
Test status
Simulation time 34970572 ps
CPU time 4.25 seconds
Started Jul 29 05:50:50 PM PDT 24
Finished Jul 29 05:50:54 PM PDT 24
Peak memory 247872 kb
Host smart-7b1afd64-acd4-4ffa-884e-3efdaf304e0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42439
69795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.4243969795
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.871247658
Short name T675
Test name
Test status
Simulation time 61504800202 ps
CPU time 1225.16 seconds
Started Jul 29 05:50:50 PM PDT 24
Finished Jul 29 06:11:16 PM PDT 24
Peak memory 288292 kb
Host smart-87d04597-5e62-4626-be1d-73ea224914ea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871247658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.871247658
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.1679212376
Short name T686
Test name
Test status
Simulation time 61255685671 ps
CPU time 1213.03 seconds
Started Jul 29 05:50:52 PM PDT 24
Finished Jul 29 06:11:05 PM PDT 24
Peak memory 288296 kb
Host smart-8ef3b720-24e6-4049-949f-6b9fc49a3f6d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679212376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.1679212376
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.893651231
Short name T484
Test name
Test status
Simulation time 1064736927 ps
CPU time 34.03 seconds
Started Jul 29 05:50:52 PM PDT 24
Finished Jul 29 05:51:26 PM PDT 24
Peak memory 255712 kb
Host smart-b5ce557c-54a9-46fe-8b1e-07388975b977
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89365
1231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.893651231
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.153658766
Short name T660
Test name
Test status
Simulation time 1581658887 ps
CPU time 16.85 seconds
Started Jul 29 05:50:53 PM PDT 24
Finished Jul 29 05:51:10 PM PDT 24
Peak memory 254012 kb
Host smart-8ab84c24-4756-4d79-8e3d-70156f83735d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15365
8766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.153658766
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.2998700141
Short name T468
Test name
Test status
Simulation time 107608554 ps
CPU time 11.99 seconds
Started Jul 29 05:50:55 PM PDT 24
Finished Jul 29 05:51:07 PM PDT 24
Peak memory 255800 kb
Host smart-862c1eb4-c326-48d0-b147-72b8c6b01f7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29987
00141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.2998700141
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.2832259647
Short name T114
Test name
Test status
Simulation time 1100207289 ps
CPU time 59.88 seconds
Started Jul 29 05:50:52 PM PDT 24
Finished Jul 29 05:51:52 PM PDT 24
Peak memory 248584 kb
Host smart-f5a3d773-38d1-461a-85fa-5dc3192d15dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28322
59647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.2832259647
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.2870613067
Short name T216
Test name
Test status
Simulation time 278049686062 ps
CPU time 5982.01 seconds
Started Jul 29 05:50:50 PM PDT 24
Finished Jul 29 07:30:33 PM PDT 24
Peak memory 329944 kb
Host smart-1a4401e9-2a5b-42cd-aad2-e29d13278ff8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870613067 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.2870613067
Directory /workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.4028049826
Short name T230
Test name
Test status
Simulation time 74810233 ps
CPU time 3.35 seconds
Started Jul 29 05:51:27 PM PDT 24
Finished Jul 29 05:51:31 PM PDT 24
Peak memory 248644 kb
Host smart-1c230ceb-7884-4574-81db-dc95f9bb84a7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4028049826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.4028049826
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.1675959428
Short name T588
Test name
Test status
Simulation time 40190354428 ps
CPU time 2537.9 seconds
Started Jul 29 05:51:19 PM PDT 24
Finished Jul 29 06:33:37 PM PDT 24
Peak memory 281176 kb
Host smart-d6b67352-6be0-49e2-bb38-2175c298b33f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675959428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.1675959428
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.3835513875
Short name T690
Test name
Test status
Simulation time 2729441060 ps
CPU time 22.02 seconds
Started Jul 29 05:51:20 PM PDT 24
Finished Jul 29 05:51:42 PM PDT 24
Peak memory 248288 kb
Host smart-7d722421-2cda-449f-8ab8-d12d9e2538c3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3835513875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.3835513875
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.2660013754
Short name T580
Test name
Test status
Simulation time 1383544494 ps
CPU time 132.01 seconds
Started Jul 29 05:51:21 PM PDT 24
Finished Jul 29 05:53:33 PM PDT 24
Peak memory 256084 kb
Host smart-34e190d7-6098-4977-9c6c-1356aee44e3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26600
13754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.2660013754
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.1934573653
Short name T375
Test name
Test status
Simulation time 1392530551 ps
CPU time 25.52 seconds
Started Jul 29 05:51:20 PM PDT 24
Finished Jul 29 05:51:46 PM PDT 24
Peak memory 256080 kb
Host smart-866a4ecb-e701-4a31-9929-890f72036f79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19345
73653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.1934573653
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.2057513890
Short name T310
Test name
Test status
Simulation time 6555959986 ps
CPU time 136.44 seconds
Started Jul 29 05:51:21 PM PDT 24
Finished Jul 29 05:53:38 PM PDT 24
Peak memory 247172 kb
Host smart-2ce95744-80bf-44dd-8cdb-62daaf385579
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057513890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.2057513890
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.3271741929
Short name T446
Test name
Test status
Simulation time 432697458 ps
CPU time 16.25 seconds
Started Jul 29 05:51:20 PM PDT 24
Finished Jul 29 05:51:37 PM PDT 24
Peak memory 248328 kb
Host smart-60e22774-e903-412f-8927-62b514d72ca6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32717
41929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.3271741929
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.1696322690
Short name T611
Test name
Test status
Simulation time 426046979 ps
CPU time 35.28 seconds
Started Jul 29 05:51:20 PM PDT 24
Finished Jul 29 05:51:55 PM PDT 24
Peak memory 249364 kb
Host smart-e64e09c5-47e8-429c-8547-3f887378169b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16963
22690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.1696322690
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.1431576257
Short name T541
Test name
Test status
Simulation time 863653643 ps
CPU time 24.5 seconds
Started Jul 29 05:51:20 PM PDT 24
Finished Jul 29 05:51:45 PM PDT 24
Peak memory 255948 kb
Host smart-1f1c5dce-f90f-461a-9704-dd9e60e372c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14315
76257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.1431576257
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.2569028864
Short name T467
Test name
Test status
Simulation time 1128316656 ps
CPU time 24.23 seconds
Started Jul 29 05:51:21 PM PDT 24
Finished Jul 29 05:51:46 PM PDT 24
Peak memory 256432 kb
Host smart-80a6fda6-d16b-4672-90da-618726284107
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25690
28864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.2569028864
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.3641479224
Short name T82
Test name
Test status
Simulation time 251089925651 ps
CPU time 4179.36 seconds
Started Jul 29 05:51:26 PM PDT 24
Finished Jul 29 07:01:06 PM PDT 24
Peak memory 354668 kb
Host smart-76e69b6c-7ec0-4b91-8a38-415e84514ba5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641479224 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.3641479224
Directory /workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.2706426540
Short name T601
Test name
Test status
Simulation time 1558255755 ps
CPU time 34.57 seconds
Started Jul 29 05:51:32 PM PDT 24
Finished Jul 29 05:52:07 PM PDT 24
Peak memory 248340 kb
Host smart-451b7c63-14c7-4f04-9051-439a028e2e9a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2706426540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.2706426540
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.1404682054
Short name T565
Test name
Test status
Simulation time 1137620277 ps
CPU time 115.32 seconds
Started Jul 29 05:51:24 PM PDT 24
Finished Jul 29 05:53:20 PM PDT 24
Peak memory 256528 kb
Host smart-eaa09994-7338-40f4-8938-f6a51901a728
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14046
82054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.1404682054
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.1570764000
Short name T620
Test name
Test status
Simulation time 1381916730 ps
CPU time 47.05 seconds
Started Jul 29 05:51:27 PM PDT 24
Finished Jul 29 05:52:14 PM PDT 24
Peak memory 255380 kb
Host smart-ef9efaec-6284-483c-89ee-e08709656518
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15707
64000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.1570764000
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.974160261
Short name T359
Test name
Test status
Simulation time 33606949316 ps
CPU time 1941.78 seconds
Started Jul 29 05:51:32 PM PDT 24
Finished Jul 29 06:23:54 PM PDT 24
Peak memory 272240 kb
Host smart-5baa197b-da87-48e4-8906-dce7c6936c16
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974160261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.974160261
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.3488055084
Short name T665
Test name
Test status
Simulation time 13339009134 ps
CPU time 1365.41 seconds
Started Jul 29 05:51:31 PM PDT 24
Finished Jul 29 06:14:16 PM PDT 24
Peak memory 288816 kb
Host smart-521c2665-4183-47c5-b2d0-4b37793a8476
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488055084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.3488055084
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.497055406
Short name T512
Test name
Test status
Simulation time 88597437352 ps
CPU time 318.98 seconds
Started Jul 29 05:51:32 PM PDT 24
Finished Jul 29 05:56:51 PM PDT 24
Peak memory 248572 kb
Host smart-a4a1cfe0-a084-4b0b-8b45-53ac5ae4f7b0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497055406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.497055406
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.3230628470
Short name T576
Test name
Test status
Simulation time 2571727636 ps
CPU time 46.56 seconds
Started Jul 29 05:51:26 PM PDT 24
Finished Jul 29 05:52:13 PM PDT 24
Peak memory 256492 kb
Host smart-3dbe04dc-6e0d-4a3d-b219-939a5c559ee4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32306
28470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.3230628470
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.3563345696
Short name T120
Test name
Test status
Simulation time 131207328 ps
CPU time 12.46 seconds
Started Jul 29 05:51:27 PM PDT 24
Finished Jul 29 05:51:40 PM PDT 24
Peak memory 255808 kb
Host smart-00287dd6-d010-4e33-a802-12f6d07f6467
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35633
45696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.3563345696
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.1828704900
Short name T96
Test name
Test status
Simulation time 57425820 ps
CPU time 8.18 seconds
Started Jul 29 05:51:31 PM PDT 24
Finished Jul 29 05:51:40 PM PDT 24
Peak memory 252860 kb
Host smart-3d9bcebf-1341-4acd-990f-dfcbcc26acdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18287
04900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.1828704900
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.2491347493
Short name T521
Test name
Test status
Simulation time 329780430 ps
CPU time 23.44 seconds
Started Jul 29 05:51:27 PM PDT 24
Finished Jul 29 05:51:50 PM PDT 24
Peak memory 255748 kb
Host smart-64859d3e-669d-4f64-b1c6-782d0239cd32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24913
47493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.2491347493
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.3438780667
Short name T483
Test name
Test status
Simulation time 103462428628 ps
CPU time 1646.75 seconds
Started Jul 29 05:51:42 PM PDT 24
Finished Jul 29 06:19:09 PM PDT 24
Peak memory 272780 kb
Host smart-f4336bbe-3849-4ec4-beb5-c1c959625c1b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438780667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.3438780667
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.741096669
Short name T462
Test name
Test status
Simulation time 2525693985 ps
CPU time 27.07 seconds
Started Jul 29 05:51:43 PM PDT 24
Finished Jul 29 05:52:10 PM PDT 24
Peak memory 248384 kb
Host smart-53708015-a536-461a-aafe-8816c1830b9c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=741096669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.741096669
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.3887699886
Short name T305
Test name
Test status
Simulation time 5448758688 ps
CPU time 306.42 seconds
Started Jul 29 05:51:43 PM PDT 24
Finished Jul 29 05:56:50 PM PDT 24
Peak memory 256032 kb
Host smart-d55ac29f-25e7-4774-88e3-072086acb835
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38876
99886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.3887699886
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.183503047
Short name T490
Test name
Test status
Simulation time 2399817873 ps
CPU time 33.24 seconds
Started Jul 29 05:51:42 PM PDT 24
Finished Jul 29 05:52:15 PM PDT 24
Peak memory 256616 kb
Host smart-88ab73d4-180b-4668-a821-c5e04ad28418
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18350
3047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.183503047
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.1667711057
Short name T387
Test name
Test status
Simulation time 152885117111 ps
CPU time 2443.85 seconds
Started Jul 29 05:51:41 PM PDT 24
Finished Jul 29 06:32:25 PM PDT 24
Peak memory 289160 kb
Host smart-c0bfbab0-5434-41b2-8826-51a7d130da22
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667711057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.1667711057
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.3496670541
Short name T313
Test name
Test status
Simulation time 49516818840 ps
CPU time 573.46 seconds
Started Jul 29 05:51:43 PM PDT 24
Finished Jul 29 06:01:17 PM PDT 24
Peak memory 255076 kb
Host smart-cf99c9c8-729c-45f1-994e-ae0790095429
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496670541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.3496670541
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.1219829516
Short name T661
Test name
Test status
Simulation time 1255844170 ps
CPU time 24.37 seconds
Started Jul 29 05:51:41 PM PDT 24
Finished Jul 29 05:52:06 PM PDT 24
Peak memory 255692 kb
Host smart-16f52710-a69c-416b-a409-b47f2e85eb22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12198
29516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.1219829516
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.316703805
Short name T685
Test name
Test status
Simulation time 603827601 ps
CPU time 37.27 seconds
Started Jul 29 05:51:41 PM PDT 24
Finished Jul 29 05:52:18 PM PDT 24
Peak memory 248364 kb
Host smart-799596a8-7224-45eb-b4be-f54b21c5f23e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31670
3805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.316703805
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.558572062
Short name T626
Test name
Test status
Simulation time 607997160 ps
CPU time 33.6 seconds
Started Jul 29 05:51:32 PM PDT 24
Finished Jul 29 05:52:06 PM PDT 24
Peak memory 256404 kb
Host smart-7396c396-49d2-4093-adbd-08206e748c97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55857
2062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.558572062
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.1765722851
Short name T493
Test name
Test status
Simulation time 73864029476 ps
CPU time 1229.86 seconds
Started Jul 29 05:51:47 PM PDT 24
Finished Jul 29 06:12:17 PM PDT 24
Peak memory 272032 kb
Host smart-de3857d3-0bc7-406f-8fb7-a62ad4a7bad4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765722851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.1765722851
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.3347159514
Short name T66
Test name
Test status
Simulation time 4506076373 ps
CPU time 49.25 seconds
Started Jul 29 05:51:45 PM PDT 24
Finished Jul 29 05:52:34 PM PDT 24
Peak memory 248392 kb
Host smart-ada13e3f-81cb-4812-b43d-160acc1e0af0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3347159514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.3347159514
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.3043683327
Short name T450
Test name
Test status
Simulation time 1125566067 ps
CPU time 50.32 seconds
Started Jul 29 05:51:52 PM PDT 24
Finished Jul 29 05:52:42 PM PDT 24
Peak memory 255852 kb
Host smart-ce396479-9319-4de7-9670-71f79ecb8f1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30436
83327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.3043683327
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.4092751076
Short name T622
Test name
Test status
Simulation time 4505382903 ps
CPU time 60.42 seconds
Started Jul 29 05:51:44 PM PDT 24
Finished Jul 29 05:52:44 PM PDT 24
Peak memory 248424 kb
Host smart-b2b8aed6-aeec-4e11-b224-1ab55e54b356
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40927
51076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.4092751076
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.499238691
Short name T355
Test name
Test status
Simulation time 12638268231 ps
CPU time 1171.1 seconds
Started Jul 29 05:51:47 PM PDT 24
Finished Jul 29 06:11:18 PM PDT 24
Peak memory 283708 kb
Host smart-ab65bc37-852d-45ae-b28f-7f5b565e9f23
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499238691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.499238691
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.2460045694
Short name T400
Test name
Test status
Simulation time 9225156565 ps
CPU time 1223.6 seconds
Started Jul 29 05:51:44 PM PDT 24
Finished Jul 29 06:12:08 PM PDT 24
Peak memory 284212 kb
Host smart-b96f7514-f383-4957-ac36-ac143e3eefc2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460045694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.2460045694
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.1394034166
Short name T545
Test name
Test status
Simulation time 226207009 ps
CPU time 14.98 seconds
Started Jul 29 05:51:46 PM PDT 24
Finished Jul 29 05:52:01 PM PDT 24
Peak memory 255276 kb
Host smart-16e818ee-d034-436d-918e-98288bca9779
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13940
34166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.1394034166
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.3326864365
Short name T482
Test name
Test status
Simulation time 531048685 ps
CPU time 38.85 seconds
Started Jul 29 05:51:44 PM PDT 24
Finished Jul 29 05:52:23 PM PDT 24
Peak memory 247676 kb
Host smart-53a00a01-c40a-4326-9010-41ae5fb3df86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33268
64365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.3326864365
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.1596439547
Short name T659
Test name
Test status
Simulation time 227586997 ps
CPU time 4.78 seconds
Started Jul 29 05:51:43 PM PDT 24
Finished Jul 29 05:51:47 PM PDT 24
Peak memory 248352 kb
Host smart-8e327bc1-f0de-4126-8df0-42933199f3e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15964
39547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.1596439547
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.1312979403
Short name T79
Test name
Test status
Simulation time 17035714690 ps
CPU time 1592.9 seconds
Started Jul 29 05:51:47 PM PDT 24
Finished Jul 29 06:18:20 PM PDT 24
Peak memory 289072 kb
Host smart-b7b92a54-cb41-45fd-ba0f-10161847a736
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312979403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.1312979403
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.1967304401
Short name T220
Test name
Test status
Simulation time 42648602 ps
CPU time 2.17 seconds
Started Jul 29 05:51:51 PM PDT 24
Finished Jul 29 05:51:53 PM PDT 24
Peak memory 248588 kb
Host smart-5b3780a7-1ce8-4156-a693-e58c0c538eef
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1967304401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.1967304401
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.49157063
Short name T543
Test name
Test status
Simulation time 36063605350 ps
CPU time 1311.61 seconds
Started Jul 29 05:51:51 PM PDT 24
Finished Jul 29 06:13:43 PM PDT 24
Peak memory 272848 kb
Host smart-508ca689-b632-4cd7-a664-47d2ae91b562
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49157063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.49157063
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.2725439603
Short name T445
Test name
Test status
Simulation time 175943968 ps
CPU time 9.67 seconds
Started Jul 29 05:51:49 PM PDT 24
Finished Jul 29 05:51:59 PM PDT 24
Peak memory 248332 kb
Host smart-7c6f994a-4648-45cb-966b-08adc5cfdadb
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2725439603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.2725439603
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.2795033037
Short name T645
Test name
Test status
Simulation time 3786668586 ps
CPU time 232.33 seconds
Started Jul 29 05:51:51 PM PDT 24
Finished Jul 29 05:55:43 PM PDT 24
Peak memory 256500 kb
Host smart-102ec0a4-bd07-4dc5-b077-ce737298ce07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27950
33037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.2795033037
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.3881837205
Short name T84
Test name
Test status
Simulation time 2970835867 ps
CPU time 53.61 seconds
Started Jul 29 05:51:51 PM PDT 24
Finished Jul 29 05:52:45 PM PDT 24
Peak memory 248320 kb
Host smart-e28ccada-1022-45ac-817e-8d762adb1693
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38818
37205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.3881837205
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.3095684507
Short name T343
Test name
Test status
Simulation time 51210059042 ps
CPU time 3112.11 seconds
Started Jul 29 05:51:49 PM PDT 24
Finished Jul 29 06:43:42 PM PDT 24
Peak memory 288984 kb
Host smart-4b2beb48-3309-46bb-bfce-5471c2b4edbd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095684507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.3095684507
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.2301246217
Short name T126
Test name
Test status
Simulation time 207573534748 ps
CPU time 2242 seconds
Started Jul 29 05:51:50 PM PDT 24
Finished Jul 29 06:29:13 PM PDT 24
Peak memory 288704 kb
Host smart-6e1b0c10-e435-40e9-88f6-53dc5125ba76
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301246217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.2301246217
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.942592693
Short name T700
Test name
Test status
Simulation time 36316526473 ps
CPU time 372.89 seconds
Started Jul 29 05:51:50 PM PDT 24
Finished Jul 29 05:58:03 PM PDT 24
Peak memory 256000 kb
Host smart-fb35c97b-07a5-4875-ac86-a7aee9ba00c4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942592693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.942592693
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.451198712
Short name T443
Test name
Test status
Simulation time 513702995 ps
CPU time 8.25 seconds
Started Jul 29 05:51:50 PM PDT 24
Finished Jul 29 05:51:59 PM PDT 24
Peak memory 248320 kb
Host smart-55313776-002a-4114-86ad-b5e8d29845ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45119
8712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.451198712
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.980209140
Short name T531
Test name
Test status
Simulation time 240339488 ps
CPU time 11.48 seconds
Started Jul 29 05:51:51 PM PDT 24
Finished Jul 29 05:52:03 PM PDT 24
Peak memory 247732 kb
Host smart-8efc9494-6a68-47ad-94f0-8692695c9936
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98020
9140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.980209140
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.1811095443
Short name T241
Test name
Test status
Simulation time 453169152 ps
CPU time 34.31 seconds
Started Jul 29 05:51:49 PM PDT 24
Finished Jul 29 05:52:23 PM PDT 24
Peak memory 248072 kb
Host smart-5148fbd4-fbeb-45bc-a842-3ccd62098262
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18110
95443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.1811095443
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.1906660074
Short name T380
Test name
Test status
Simulation time 707367273 ps
CPU time 37.84 seconds
Started Jul 29 05:51:44 PM PDT 24
Finished Jul 29 05:52:22 PM PDT 24
Peak memory 256320 kb
Host smart-8a6cb820-545d-4d8d-8261-0940ed4673c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19066
60074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.1906660074
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.3140557076
Short name T496
Test name
Test status
Simulation time 133642096317 ps
CPU time 2616.4 seconds
Started Jul 29 05:51:51 PM PDT 24
Finished Jul 29 06:35:28 PM PDT 24
Peak memory 286452 kb
Host smart-ec49356a-8bf3-4083-97a5-57d08178858b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140557076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.3140557076
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.2698384067
Short name T223
Test name
Test status
Simulation time 40995341 ps
CPU time 3.31 seconds
Started Jul 29 05:51:58 PM PDT 24
Finished Jul 29 05:52:01 PM PDT 24
Peak memory 248580 kb
Host smart-187b812e-d9e5-4866-a63b-81c1dd1cd4ed
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2698384067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.2698384067
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.265716259
Short name T695
Test name
Test status
Simulation time 65877173069 ps
CPU time 1731.45 seconds
Started Jul 29 05:51:55 PM PDT 24
Finished Jul 29 06:20:47 PM PDT 24
Peak memory 272428 kb
Host smart-29abb54a-52f6-4958-830e-d90d8d6077ae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265716259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.265716259
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.4034925340
Short name T708
Test name
Test status
Simulation time 3277645540 ps
CPU time 11.55 seconds
Started Jul 29 05:51:56 PM PDT 24
Finished Jul 29 05:52:07 PM PDT 24
Peak memory 248328 kb
Host smart-05a9ae64-6ae3-4dbb-ab9d-151635d22b41
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4034925340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.4034925340
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.434992382
Short name T514
Test name
Test status
Simulation time 1087873926 ps
CPU time 107.32 seconds
Started Jul 29 05:51:58 PM PDT 24
Finished Jul 29 05:53:45 PM PDT 24
Peak memory 255876 kb
Host smart-6bda05a3-5254-43e7-a61b-103cb8421241
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43499
2382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.434992382
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.3659133345
Short name T497
Test name
Test status
Simulation time 462554474 ps
CPU time 10.35 seconds
Started Jul 29 05:51:57 PM PDT 24
Finished Jul 29 05:52:08 PM PDT 24
Peak memory 253060 kb
Host smart-27e6b29f-05dd-417a-a246-a7ddf38b4346
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36591
33345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.3659133345
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.1186995138
Short name T347
Test name
Test status
Simulation time 17650457274 ps
CPU time 1596.83 seconds
Started Jul 29 05:51:57 PM PDT 24
Finished Jul 29 06:18:34 PM PDT 24
Peak memory 288460 kb
Host smart-fe7bd025-1dac-4f75-a4b7-c982a66d74b8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186995138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.1186995138
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.4255821836
Short name T101
Test name
Test status
Simulation time 46050062786 ps
CPU time 1340.86 seconds
Started Jul 29 05:51:57 PM PDT 24
Finished Jul 29 06:14:18 PM PDT 24
Peak memory 265740 kb
Host smart-96f6a0e0-3d1e-4913-845b-f2b10d520719
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255821836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.4255821836
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.2831701821
Short name T239
Test name
Test status
Simulation time 18605878762 ps
CPU time 352.01 seconds
Started Jul 29 05:51:57 PM PDT 24
Finished Jul 29 05:57:49 PM PDT 24
Peak memory 248380 kb
Host smart-f7c00ce6-7530-4749-8814-3d8c21708b50
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831701821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.2831701821
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.936967493
Short name T523
Test name
Test status
Simulation time 2475208716 ps
CPU time 41.78 seconds
Started Jul 29 05:51:56 PM PDT 24
Finished Jul 29 05:52:37 PM PDT 24
Peak memory 256288 kb
Host smart-6b5b60ba-3e46-46bb-a20e-b0e704aa6164
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93696
7493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.936967493
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.4158839169
Short name T75
Test name
Test status
Simulation time 881058572 ps
CPU time 10.35 seconds
Started Jul 29 05:51:56 PM PDT 24
Finished Jul 29 05:52:07 PM PDT 24
Peak memory 252244 kb
Host smart-aa10f274-4817-4b2d-a610-7df2f1b10997
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41588
39169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.4158839169
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.2609007148
Short name T491
Test name
Test status
Simulation time 340482986 ps
CPU time 32.93 seconds
Started Jul 29 05:51:49 PM PDT 24
Finished Jul 29 05:52:22 PM PDT 24
Peak memory 256460 kb
Host smart-d830c1bb-6edf-4eb8-a6b7-4cdd7d04de8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26090
07148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.2609007148
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.3916064975
Short name T684
Test name
Test status
Simulation time 19510670034 ps
CPU time 1324.1 seconds
Started Jul 29 05:51:58 PM PDT 24
Finished Jul 29 06:14:02 PM PDT 24
Peak memory 272200 kb
Host smart-5c184402-2dba-4261-8c29-ca2598411719
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916064975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.3916064975
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.3316619801
Short name T226
Test name
Test status
Simulation time 29871524 ps
CPU time 2.61 seconds
Started Jul 29 05:52:03 PM PDT 24
Finished Jul 29 05:52:06 PM PDT 24
Peak memory 248532 kb
Host smart-a3fbd364-b650-489d-bb97-bbbcf55d5f5b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3316619801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.3316619801
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.4273197209
Short name T103
Test name
Test status
Simulation time 24469322097 ps
CPU time 1545.96 seconds
Started Jul 29 05:52:02 PM PDT 24
Finished Jul 29 06:17:49 PM PDT 24
Peak memory 272388 kb
Host smart-a3130155-9be1-455f-b5e6-0fdaa3f6f875
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273197209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.4273197209
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.3031484591
Short name T202
Test name
Test status
Simulation time 814356181 ps
CPU time 36.49 seconds
Started Jul 29 05:52:01 PM PDT 24
Finished Jul 29 05:52:37 PM PDT 24
Peak memory 248256 kb
Host smart-3f91123e-72e1-4dbe-b9a9-56dac17213c8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3031484591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.3031484591
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.3248264314
Short name T413
Test name
Test status
Simulation time 20257506602 ps
CPU time 309.21 seconds
Started Jul 29 05:52:01 PM PDT 24
Finished Jul 29 05:57:11 PM PDT 24
Peak memory 256176 kb
Host smart-2210fb15-e718-4e1c-9bc7-1d53162ea9b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32482
64314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.3248264314
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.2466672773
Short name T453
Test name
Test status
Simulation time 110262446 ps
CPU time 7.38 seconds
Started Jul 29 05:52:01 PM PDT 24
Finished Jul 29 05:52:09 PM PDT 24
Peak memory 252048 kb
Host smart-90effa0b-412f-4662-988e-d17f2bb214a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24666
72773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.2466672773
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.1738967040
Short name T407
Test name
Test status
Simulation time 7160572691 ps
CPU time 809.83 seconds
Started Jul 29 05:52:03 PM PDT 24
Finished Jul 29 06:05:33 PM PDT 24
Peak memory 272456 kb
Host smart-22cfa580-d958-49eb-9b23-b0d04ea6078d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738967040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.1738967040
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.2753664415
Short name T625
Test name
Test status
Simulation time 8632491868 ps
CPU time 367.46 seconds
Started Jul 29 05:52:03 PM PDT 24
Finished Jul 29 05:58:11 PM PDT 24
Peak memory 254640 kb
Host smart-d2824292-a058-4f29-8cdb-06ac6312b314
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753664415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.2753664415
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.3039293003
Short name T501
Test name
Test status
Simulation time 1220908454 ps
CPU time 29.86 seconds
Started Jul 29 05:52:03 PM PDT 24
Finished Jul 29 05:52:33 PM PDT 24
Peak memory 255744 kb
Host smart-1be2113a-792f-4963-8ba6-79b0fab6840e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30392
93003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.3039293003
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.1465230605
Short name T117
Test name
Test status
Simulation time 2063191945 ps
CPU time 31.66 seconds
Started Jul 29 05:52:01 PM PDT 24
Finished Jul 29 05:52:33 PM PDT 24
Peak memory 256056 kb
Host smart-b0108327-f85f-46f6-a567-68934374f8c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14652
30605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.1465230605
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.2972276239
Short name T87
Test name
Test status
Simulation time 2225670317 ps
CPU time 63.43 seconds
Started Jul 29 05:52:05 PM PDT 24
Finished Jul 29 05:53:09 PM PDT 24
Peak memory 255660 kb
Host smart-911dfb03-3904-47f2-8b4c-fdf6c22ff93f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29722
76239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.2972276239
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.3602549785
Short name T374
Test name
Test status
Simulation time 842895907 ps
CPU time 52.85 seconds
Started Jul 29 05:52:02 PM PDT 24
Finished Jul 29 05:52:55 PM PDT 24
Peak memory 256432 kb
Host smart-025762aa-89fb-483b-a202-8595081a5b3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36025
49785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.3602549785
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.3921605357
Short name T547
Test name
Test status
Simulation time 184196479641 ps
CPU time 2434.3 seconds
Started Jul 29 05:52:02 PM PDT 24
Finished Jul 29 06:32:37 PM PDT 24
Peak memory 289080 kb
Host smart-0266b3d5-5745-4ffa-bcba-5fe3d523d219
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921605357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.3921605357
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.1073635250
Short name T264
Test name
Test status
Simulation time 50692135212 ps
CPU time 5794.26 seconds
Started Jul 29 05:52:02 PM PDT 24
Finished Jul 29 07:28:37 PM PDT 24
Peak memory 354964 kb
Host smart-af7da92c-41ff-4486-a532-1f4d59140791
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073635250 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.1073635250
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.4097220465
Short name T48
Test name
Test status
Simulation time 116140827 ps
CPU time 3.38 seconds
Started Jul 29 05:52:08 PM PDT 24
Finished Jul 29 05:52:12 PM PDT 24
Peak memory 248560 kb
Host smart-6e8f7ef4-cd80-46da-982c-d6c591546bb1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4097220465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.4097220465
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.3556320027
Short name T205
Test name
Test status
Simulation time 72209050467 ps
CPU time 1475 seconds
Started Jul 29 05:52:09 PM PDT 24
Finished Jul 29 06:16:45 PM PDT 24
Peak memory 272364 kb
Host smart-f88383ec-76d3-401c-87ce-7bf9f981d5b8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556320027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.3556320027
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.2325648037
Short name T530
Test name
Test status
Simulation time 595983305 ps
CPU time 12.16 seconds
Started Jul 29 05:52:07 PM PDT 24
Finished Jul 29 05:52:19 PM PDT 24
Peak memory 248332 kb
Host smart-e2493110-569d-401b-b23f-7f08f9380405
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2325648037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.2325648037
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.1337625270
Short name T472
Test name
Test status
Simulation time 2112172601 ps
CPU time 161.41 seconds
Started Jul 29 05:52:07 PM PDT 24
Finished Jul 29 05:54:49 PM PDT 24
Peak memory 255852 kb
Host smart-552e6fa0-61f8-43e3-8cf4-eb8ee6fb30f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13376
25270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.1337625270
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.1101734649
Short name T502
Test name
Test status
Simulation time 1918824544 ps
CPU time 28.34 seconds
Started Jul 29 05:52:02 PM PDT 24
Finished Jul 29 05:52:31 PM PDT 24
Peak memory 248272 kb
Host smart-6b69d3a2-11b9-4869-9e51-762015b28f76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11017
34649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.1101734649
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.3972814568
Short name T349
Test name
Test status
Simulation time 152188404009 ps
CPU time 2024.11 seconds
Started Jul 29 05:52:09 PM PDT 24
Finished Jul 29 06:25:53 PM PDT 24
Peak memory 272120 kb
Host smart-0f154ea9-cabf-4d2c-a69e-cb49ca917af6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972814568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.3972814568
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.3416594317
Short name T113
Test name
Test status
Simulation time 70907460967 ps
CPU time 1189.59 seconds
Started Jul 29 05:52:10 PM PDT 24
Finished Jul 29 06:12:00 PM PDT 24
Peak memory 272908 kb
Host smart-76e350af-ce16-4a07-9e29-938b85cee334
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416594317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.3416594317
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.1293431448
Short name T529
Test name
Test status
Simulation time 3928016494 ps
CPU time 52.7 seconds
Started Jul 29 05:52:01 PM PDT 24
Finished Jul 29 05:52:54 PM PDT 24
Peak memory 248348 kb
Host smart-6fb768e2-8c85-49f9-9ab5-db4e44a854e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12934
31448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.1293431448
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.3638083855
Short name T564
Test name
Test status
Simulation time 1137673774 ps
CPU time 24.38 seconds
Started Jul 29 05:52:02 PM PDT 24
Finished Jul 29 05:52:27 PM PDT 24
Peak memory 248216 kb
Host smart-2f6b4233-27f9-4421-be80-3c14946379cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36380
83855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.3638083855
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.1366813222
Short name T56
Test name
Test status
Simulation time 1660064078 ps
CPU time 21.32 seconds
Started Jul 29 05:52:08 PM PDT 24
Finished Jul 29 05:52:30 PM PDT 24
Peak memory 255848 kb
Host smart-23c9058b-b460-499b-b810-f36c1b145a45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13668
13222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.1366813222
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.823267306
Short name T127
Test name
Test status
Simulation time 721138783 ps
CPU time 37.81 seconds
Started Jul 29 05:52:03 PM PDT 24
Finished Jul 29 05:52:41 PM PDT 24
Peak memory 256532 kb
Host smart-a85f6a50-917e-4955-9ab2-3e8a9d42e17a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82326
7306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.823267306
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.1792579213
Short name T60
Test name
Test status
Simulation time 34528286773 ps
CPU time 692.87 seconds
Started Jul 29 05:52:09 PM PDT 24
Finished Jul 29 06:03:42 PM PDT 24
Peak memory 264732 kb
Host smart-e5af239c-73c2-40c6-9ac7-f1a90d5c6fd7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792579213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.1792579213
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.3964908199
Short name T245
Test name
Test status
Simulation time 46135988848 ps
CPU time 2851.08 seconds
Started Jul 29 05:52:13 PM PDT 24
Finished Jul 29 06:39:45 PM PDT 24
Peak memory 286532 kb
Host smart-c30960cd-56a8-4c25-9be9-ec57bd329c86
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964908199 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.3964908199
Directory /workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.2024348264
Short name T222
Test name
Test status
Simulation time 42540858 ps
CPU time 2.5 seconds
Started Jul 29 05:52:15 PM PDT 24
Finished Jul 29 05:52:18 PM PDT 24
Peak memory 248620 kb
Host smart-b2a31850-029b-4ce1-b4a6-06dd474845f6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2024348264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.2024348264
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.2638295568
Short name T572
Test name
Test status
Simulation time 26815944742 ps
CPU time 723.85 seconds
Started Jul 29 05:52:15 PM PDT 24
Finished Jul 29 06:04:19 PM PDT 24
Peak memory 272600 kb
Host smart-5ae226f1-b682-4b1b-bef7-1bcead42a684
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638295568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.2638295568
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.1962236037
Short name T243
Test name
Test status
Simulation time 5563646300 ps
CPU time 54.29 seconds
Started Jul 29 05:52:13 PM PDT 24
Finished Jul 29 05:53:08 PM PDT 24
Peak memory 248280 kb
Host smart-5e108544-3386-415b-9c9f-7c1ac2a29cbf
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1962236037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.1962236037
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.4078027522
Short name T683
Test name
Test status
Simulation time 2069011983 ps
CPU time 181.07 seconds
Started Jul 29 05:52:15 PM PDT 24
Finished Jul 29 05:55:16 PM PDT 24
Peak memory 255540 kb
Host smart-aa053e4b-9d41-430d-b834-559fb5f16454
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40780
27522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.4078027522
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.1255236741
Short name T129
Test name
Test status
Simulation time 106309502 ps
CPU time 14.21 seconds
Started Jul 29 05:52:17 PM PDT 24
Finished Jul 29 05:52:32 PM PDT 24
Peak memory 247584 kb
Host smart-101b3eed-5138-4e44-b8f7-2c9ea31d0dee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12552
36741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.1255236741
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.3194844176
Short name T687
Test name
Test status
Simulation time 22369848973 ps
CPU time 954.62 seconds
Started Jul 29 05:52:14 PM PDT 24
Finished Jul 29 06:08:09 PM PDT 24
Peak memory 272984 kb
Host smart-852b0124-d1f4-4a8d-a970-4fab4288ed0e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194844176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.3194844176
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.2568879504
Short name T481
Test name
Test status
Simulation time 45777775475 ps
CPU time 1485.05 seconds
Started Jul 29 05:52:13 PM PDT 24
Finished Jul 29 06:16:59 PM PDT 24
Peak memory 288432 kb
Host smart-0b510a64-be6a-40ea-a531-17fca9a4e4c6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568879504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.2568879504
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.139216265
Short name T327
Test name
Test status
Simulation time 5725408822 ps
CPU time 119.39 seconds
Started Jul 29 05:52:16 PM PDT 24
Finished Jul 29 05:54:15 PM PDT 24
Peak memory 254808 kb
Host smart-74be32d7-7c89-4e21-80f9-c161cd97e003
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139216265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.139216265
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.4246237819
Short name T384
Test name
Test status
Simulation time 338023488 ps
CPU time 22.39 seconds
Started Jul 29 05:52:13 PM PDT 24
Finished Jul 29 05:52:35 PM PDT 24
Peak memory 248288 kb
Host smart-a0551fae-69bc-4fa1-b5a6-7bd8ab2918e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42462
37819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.4246237819
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.287943242
Short name T395
Test name
Test status
Simulation time 753712988 ps
CPU time 29.18 seconds
Started Jul 29 05:52:12 PM PDT 24
Finished Jul 29 05:52:41 PM PDT 24
Peak memory 256488 kb
Host smart-6a99fefe-d308-4ddf-a4a4-e7254bf55536
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28794
3242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.287943242
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.1473931641
Short name T274
Test name
Test status
Simulation time 435754746 ps
CPU time 25.2 seconds
Started Jul 29 05:52:14 PM PDT 24
Finished Jul 29 05:52:39 PM PDT 24
Peak memory 255556 kb
Host smart-a2632d5c-f346-4824-a9d0-e49f6230b7a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14739
31641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.1473931641
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.1005872898
Short name T581
Test name
Test status
Simulation time 2029954128 ps
CPU time 60.61 seconds
Started Jul 29 05:52:15 PM PDT 24
Finished Jul 29 05:53:16 PM PDT 24
Peak memory 256520 kb
Host smart-eeff343f-07dc-47ff-9a20-e3bd6f604016
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10058
72898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.1005872898
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.2562672588
Short name T100
Test name
Test status
Simulation time 65022619774 ps
CPU time 2126.29 seconds
Started Jul 29 05:52:16 PM PDT 24
Finished Jul 29 06:27:43 PM PDT 24
Peak memory 288116 kb
Host smart-453cc46d-4343-4ac6-818a-057a2505858f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562672588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.2562672588
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.807995104
Short name T197
Test name
Test status
Simulation time 233858304626 ps
CPU time 4026.08 seconds
Started Jul 29 05:52:13 PM PDT 24
Finished Jul 29 06:59:20 PM PDT 24
Peak memory 304528 kb
Host smart-e3de16e9-6c1b-43b3-9c83-734f32eb91de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807995104 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.807995104
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.3862604941
Short name T231
Test name
Test status
Simulation time 154815627 ps
CPU time 3.16 seconds
Started Jul 29 05:52:24 PM PDT 24
Finished Jul 29 05:52:27 PM PDT 24
Peak memory 248644 kb
Host smart-9a59b168-d01b-456d-a3fb-25032c401bb0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3862604941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.3862604941
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.822541380
Short name T464
Test name
Test status
Simulation time 119963456608 ps
CPU time 1804.14 seconds
Started Jul 29 05:52:19 PM PDT 24
Finished Jul 29 06:22:23 PM PDT 24
Peak memory 272092 kb
Host smart-79843618-1f4d-439d-b923-9602f44460ed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822541380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.822541380
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.3780502947
Short name T538
Test name
Test status
Simulation time 12265820867 ps
CPU time 43.79 seconds
Started Jul 29 05:52:25 PM PDT 24
Finished Jul 29 05:53:09 PM PDT 24
Peak memory 248388 kb
Host smart-4f7990f8-3e55-4bd2-9967-aa6880adfc3b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3780502947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.3780502947
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.3007333680
Short name T458
Test name
Test status
Simulation time 1306145579 ps
CPU time 72.39 seconds
Started Jul 29 05:52:18 PM PDT 24
Finished Jul 29 05:53:31 PM PDT 24
Peak memory 256508 kb
Host smart-a4d3e1c9-f1d1-4e86-be18-1833e7774937
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30073
33680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.3007333680
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.1019597643
Short name T137
Test name
Test status
Simulation time 2826552961 ps
CPU time 20.97 seconds
Started Jul 29 05:52:19 PM PDT 24
Finished Jul 29 05:52:40 PM PDT 24
Peak memory 248020 kb
Host smart-9c52651b-320d-4aec-810f-c15e6c3526ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10195
97643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.1019597643
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.2190042208
Short name T346
Test name
Test status
Simulation time 268289968520 ps
CPU time 1293.22 seconds
Started Jul 29 05:52:18 PM PDT 24
Finished Jul 29 06:13:52 PM PDT 24
Peak memory 288540 kb
Host smart-a75452fc-9561-44a4-84fe-fa787c681307
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190042208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.2190042208
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.2404099639
Short name T441
Test name
Test status
Simulation time 31261920083 ps
CPU time 1438.03 seconds
Started Jul 29 05:52:26 PM PDT 24
Finished Jul 29 06:16:24 PM PDT 24
Peak memory 289008 kb
Host smart-7b873ab1-35f6-4c4e-a46a-635a43a05d0c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404099639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.2404099639
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.304713427
Short name T323
Test name
Test status
Simulation time 37080096303 ps
CPU time 338.78 seconds
Started Jul 29 05:52:20 PM PDT 24
Finished Jul 29 05:57:59 PM PDT 24
Peak memory 256552 kb
Host smart-656ab817-e619-4ed5-a7b2-21391f2067ed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304713427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.304713427
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.1054383087
Short name T705
Test name
Test status
Simulation time 181022407 ps
CPU time 6.28 seconds
Started Jul 29 05:52:18 PM PDT 24
Finished Jul 29 05:52:25 PM PDT 24
Peak memory 251108 kb
Host smart-c557a613-94fb-4ddf-a508-463c397a9bdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10543
83087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.1054383087
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.718024220
Short name T198
Test name
Test status
Simulation time 933489517 ps
CPU time 61.87 seconds
Started Jul 29 05:52:21 PM PDT 24
Finished Jul 29 05:53:23 PM PDT 24
Peak memory 247904 kb
Host smart-49cdead6-2571-4485-b69b-df7fdf176275
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71802
4220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.718024220
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.3612607038
Short name T57
Test name
Test status
Simulation time 2750538719 ps
CPU time 40.99 seconds
Started Jul 29 05:52:18 PM PDT 24
Finished Jul 29 05:52:59 PM PDT 24
Peak memory 248440 kb
Host smart-2d00b827-1506-4c18-b28f-6a6dbfe75d15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36126
07038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.3612607038
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.3419572619
Short name T412
Test name
Test status
Simulation time 2158119843 ps
CPU time 37.12 seconds
Started Jul 29 05:52:21 PM PDT 24
Finished Jul 29 05:52:58 PM PDT 24
Peak memory 248584 kb
Host smart-03f5858b-02e8-46ed-bfc0-4978fa81f1b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34195
72619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.3419572619
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.979312614
Short name T76
Test name
Test status
Simulation time 780287966 ps
CPU time 7.23 seconds
Started Jul 29 05:52:26 PM PDT 24
Finished Jul 29 05:52:33 PM PDT 24
Peak memory 254356 kb
Host smart-a80bf0ad-69f4-4716-a836-617fd6e8f348
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979312614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_han
dler_stress_all.979312614
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.2411281034
Short name T221
Test name
Test status
Simulation time 35569554 ps
CPU time 3.26 seconds
Started Jul 29 05:50:56 PM PDT 24
Finished Jul 29 05:50:59 PM PDT 24
Peak memory 248548 kb
Host smart-2c038c9b-bd39-4e0e-8a6a-da3922fa9c12
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2411281034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.2411281034
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.563648616
Short name T409
Test name
Test status
Simulation time 25503548989 ps
CPU time 1361.67 seconds
Started Jul 29 05:50:55 PM PDT 24
Finished Jul 29 06:13:37 PM PDT 24
Peak memory 272376 kb
Host smart-e6440669-8cfc-4af6-853d-16baeca60969
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563648616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.563648616
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.1943162420
Short name T406
Test name
Test status
Simulation time 1446565611 ps
CPU time 31.12 seconds
Started Jul 29 05:50:57 PM PDT 24
Finished Jul 29 05:51:28 PM PDT 24
Peak memory 248280 kb
Host smart-cc469714-9492-41c3-8fb3-4916d3fa0e3e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1943162420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.1943162420
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.2240901268
Short name T377
Test name
Test status
Simulation time 3276097245 ps
CPU time 129.46 seconds
Started Jul 29 05:50:51 PM PDT 24
Finished Jul 29 05:53:01 PM PDT 24
Peak memory 256088 kb
Host smart-2a9ebba6-79b7-47be-8a9b-9780abac93ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22409
01268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.2240901268
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.149808367
Short name T619
Test name
Test status
Simulation time 594980021 ps
CPU time 18.85 seconds
Started Jul 29 05:50:53 PM PDT 24
Finished Jul 29 05:51:12 PM PDT 24
Peak memory 247676 kb
Host smart-f0d6e9f7-85ba-4e28-a469-3675e5fe4997
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14980
8367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.149808367
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.24868230
Short name T522
Test name
Test status
Simulation time 22521335868 ps
CPU time 1076.2 seconds
Started Jul 29 05:50:58 PM PDT 24
Finished Jul 29 06:08:54 PM PDT 24
Peak memory 282256 kb
Host smart-476c25e5-0534-486f-bb88-41ef39b6c5af
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24868230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.24868230
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.3678185832
Short name T605
Test name
Test status
Simulation time 87745355483 ps
CPU time 1278.24 seconds
Started Jul 29 05:50:57 PM PDT 24
Finished Jul 29 06:12:15 PM PDT 24
Peak memory 272832 kb
Host smart-5d9b6e32-588a-4454-aed6-4f82495ba4b7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678185832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.3678185832
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.2606819374
Short name T639
Test name
Test status
Simulation time 6089016647 ps
CPU time 128.83 seconds
Started Jul 29 05:50:54 PM PDT 24
Finished Jul 29 05:53:03 PM PDT 24
Peak memory 248364 kb
Host smart-13e8c275-686f-47fd-bc04-6924149b8f47
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606819374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.2606819374
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.653034022
Short name T61
Test name
Test status
Simulation time 1672870693 ps
CPU time 47.92 seconds
Started Jul 29 05:50:53 PM PDT 24
Finished Jul 29 05:51:41 PM PDT 24
Peak memory 256484 kb
Host smart-07eed62a-eac8-4b0e-85b9-0df461dc3e7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65303
4022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.653034022
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.3352171512
Short name T526
Test name
Test status
Simulation time 485681271 ps
CPU time 29.82 seconds
Started Jul 29 05:50:54 PM PDT 24
Finished Jul 29 05:51:24 PM PDT 24
Peak memory 256268 kb
Host smart-28303344-b05c-4094-8b4c-63289e0719bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33521
71512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.3352171512
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.3829809638
Short name T35
Test name
Test status
Simulation time 1713331582 ps
CPU time 25.37 seconds
Started Jul 29 05:50:55 PM PDT 24
Finished Jul 29 05:51:20 PM PDT 24
Peak memory 270424 kb
Host smart-5fe3f626-e01b-4870-a3ab-91d4d7c078a2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3829809638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.3829809638
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.2523726561
Short name T579
Test name
Test status
Simulation time 295529742 ps
CPU time 4.47 seconds
Started Jul 29 05:50:50 PM PDT 24
Finished Jul 29 05:50:54 PM PDT 24
Peak memory 248344 kb
Host smart-2a637913-da0b-4097-a3d7-e197434916e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25237
26561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.2523726561
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.3919243665
Short name T463
Test name
Test status
Simulation time 18127894401 ps
CPU time 969.89 seconds
Started Jul 29 05:52:25 PM PDT 24
Finished Jul 29 06:08:35 PM PDT 24
Peak memory 272620 kb
Host smart-f4e53327-4745-455f-8086-b1dfa820c98b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919243665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.3919243665
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.1755436186
Short name T379
Test name
Test status
Simulation time 300319106 ps
CPU time 20.59 seconds
Started Jul 29 05:52:25 PM PDT 24
Finished Jul 29 05:52:46 PM PDT 24
Peak memory 255892 kb
Host smart-757eb12f-a87e-476f-bd5e-dff0e6ac080a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17554
36186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.1755436186
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.4033693039
Short name T78
Test name
Test status
Simulation time 995330931 ps
CPU time 26.65 seconds
Started Jul 29 05:52:23 PM PDT 24
Finished Jul 29 05:52:50 PM PDT 24
Peak memory 248260 kb
Host smart-ff4cca36-7850-4740-90d2-fa52100b5957
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40336
93039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.4033693039
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.3217435147
Short name T425
Test name
Test status
Simulation time 24821393015 ps
CPU time 1157.63 seconds
Started Jul 29 05:52:33 PM PDT 24
Finished Jul 29 06:11:51 PM PDT 24
Peak memory 286372 kb
Host smart-c027ed07-55b4-4dda-82e3-961aafc229c9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217435147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.3217435147
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.3073938669
Short name T336
Test name
Test status
Simulation time 14648559419 ps
CPU time 281.54 seconds
Started Jul 29 05:52:26 PM PDT 24
Finished Jul 29 05:57:08 PM PDT 24
Peak memory 247256 kb
Host smart-6944caf3-79e9-44da-9645-20e57bcf2399
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073938669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.3073938669
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.3017584095
Short name T487
Test name
Test status
Simulation time 126512803 ps
CPU time 4.93 seconds
Started Jul 29 05:52:27 PM PDT 24
Finished Jul 29 05:52:32 PM PDT 24
Peak memory 250524 kb
Host smart-1c931cdb-3370-47a8-b4b6-8f7e1d698977
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30175
84095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.3017584095
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.4047628835
Short name T592
Test name
Test status
Simulation time 378208928 ps
CPU time 21.14 seconds
Started Jul 29 05:52:24 PM PDT 24
Finished Jul 29 05:52:45 PM PDT 24
Peak memory 254972 kb
Host smart-cdeb681e-24b0-4cc9-bed7-d43720912fab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40476
28835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.4047628835
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.765650190
Short name T575
Test name
Test status
Simulation time 1060562329 ps
CPU time 32.2 seconds
Started Jul 29 05:52:25 PM PDT 24
Finished Jul 29 05:52:57 PM PDT 24
Peak memory 255988 kb
Host smart-9f771a31-5279-4a8a-bdeb-34cc5fdd2b9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76565
0190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.765650190
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.3929185785
Short name T418
Test name
Test status
Simulation time 520122745 ps
CPU time 36.04 seconds
Started Jul 29 05:52:25 PM PDT 24
Finished Jul 29 05:53:02 PM PDT 24
Peak memory 256228 kb
Host smart-aa7a7bcb-ce50-4ca6-a562-8d9c43a97402
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39291
85785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.3929185785
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.1381912542
Short name T287
Test name
Test status
Simulation time 35700439497 ps
CPU time 2246.49 seconds
Started Jul 29 05:52:27 PM PDT 24
Finished Jul 29 06:29:54 PM PDT 24
Peak memory 288668 kb
Host smart-36a3e07e-a3a8-4d33-9d8b-ad11de1575c9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381912542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.1381912542
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.531382149
Short name T27
Test name
Test status
Simulation time 70708062887 ps
CPU time 1557.95 seconds
Started Jul 29 05:52:30 PM PDT 24
Finished Jul 29 06:18:29 PM PDT 24
Peak memory 288748 kb
Host smart-1f5d2239-9a96-460a-a494-bedd5ec9fe99
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531382149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.531382149
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.3993241314
Short name T618
Test name
Test status
Simulation time 12031273587 ps
CPU time 322.52 seconds
Started Jul 29 05:52:37 PM PDT 24
Finished Jul 29 05:57:59 PM PDT 24
Peak memory 251656 kb
Host smart-87de225c-39f2-4f61-a8af-7f62d8a94d4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39932
41314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.3993241314
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.152337938
Short name T560
Test name
Test status
Simulation time 43389007 ps
CPU time 4.79 seconds
Started Jul 29 05:52:28 PM PDT 24
Finished Jul 29 05:52:33 PM PDT 24
Peak memory 240016 kb
Host smart-940a2c88-bf3c-4279-ad05-b6812c0a8268
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15233
7938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.152337938
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.833881800
Short name T435
Test name
Test status
Simulation time 12741404761 ps
CPU time 653.28 seconds
Started Jul 29 05:52:35 PM PDT 24
Finished Jul 29 06:03:29 PM PDT 24
Peak memory 271784 kb
Host smart-103a3e0e-f44b-4192-97c0-5ac20edb7b63
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833881800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.833881800
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.1627669939
Short name T668
Test name
Test status
Simulation time 12600400131 ps
CPU time 517 seconds
Started Jul 29 05:52:34 PM PDT 24
Finished Jul 29 06:01:11 PM PDT 24
Peak memory 247520 kb
Host smart-13628c91-4315-44fd-ba9a-104abd8600e7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627669939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.1627669939
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.1147939266
Short name T486
Test name
Test status
Simulation time 558614671 ps
CPU time 13.09 seconds
Started Jul 29 05:52:31 PM PDT 24
Finished Jul 29 05:52:44 PM PDT 24
Peak memory 248352 kb
Host smart-8ea3513d-7960-4cb4-9c47-cba07094841e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11479
39266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.1147939266
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.3276300330
Short name T666
Test name
Test status
Simulation time 5412985166 ps
CPU time 72.28 seconds
Started Jul 29 05:52:30 PM PDT 24
Finished Jul 29 05:53:42 PM PDT 24
Peak memory 255996 kb
Host smart-0ff32ae4-6f36-4eaf-98f1-1f6ac3686f68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32763
00330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.3276300330
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.2575668153
Short name T22
Test name
Test status
Simulation time 983543969 ps
CPU time 37.59 seconds
Started Jul 29 05:52:37 PM PDT 24
Finished Jul 29 05:53:14 PM PDT 24
Peak memory 248400 kb
Host smart-70e456be-560b-4a50-9fcd-1bc074900c20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25756
68153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.2575668153
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.2394719108
Short name T381
Test name
Test status
Simulation time 81566139 ps
CPU time 6.34 seconds
Started Jul 29 05:52:26 PM PDT 24
Finished Jul 29 05:52:33 PM PDT 24
Peak memory 248232 kb
Host smart-55d3b9af-0fa0-4ca0-ad46-704289ed9c56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23947
19108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.2394719108
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.153837102
Short name T5
Test name
Test status
Simulation time 52121461327 ps
CPU time 1205.74 seconds
Started Jul 29 05:52:36 PM PDT 24
Finished Jul 29 06:12:42 PM PDT 24
Peak memory 288488 kb
Host smart-43a4af6b-6ca2-412c-835c-5714e4ad8e9e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153837102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_han
dler_stress_all.153837102
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.2978223563
Short name T30
Test name
Test status
Simulation time 24990998493 ps
CPU time 1470.63 seconds
Started Jul 29 05:52:36 PM PDT 24
Finished Jul 29 06:17:07 PM PDT 24
Peak memory 264780 kb
Host smart-7ab79d9b-bd9c-4114-97a3-4d91a88c01c4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978223563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.2978223563
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.2889973045
Short name T533
Test name
Test status
Simulation time 4849516228 ps
CPU time 69.12 seconds
Started Jul 29 05:52:36 PM PDT 24
Finished Jul 29 05:53:46 PM PDT 24
Peak memory 256120 kb
Host smart-95761439-4a78-4688-b563-cae1ecb38a99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28899
73045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.2889973045
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.2078262254
Short name T83
Test name
Test status
Simulation time 521016962 ps
CPU time 10.66 seconds
Started Jul 29 05:52:37 PM PDT 24
Finished Jul 29 05:52:48 PM PDT 24
Peak memory 252996 kb
Host smart-74711534-5d16-4e06-af68-e71295587427
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20782
62254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.2078262254
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.1280760563
Short name T131
Test name
Test status
Simulation time 29712503799 ps
CPU time 1805 seconds
Started Jul 29 05:52:40 PM PDT 24
Finished Jul 29 06:22:46 PM PDT 24
Peak memory 281052 kb
Host smart-8092952a-3f6b-40d7-a57b-dff7a88351d8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280760563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.1280760563
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.3885873641
Short name T644
Test name
Test status
Simulation time 34865777710 ps
CPU time 1146.98 seconds
Started Jul 29 05:52:42 PM PDT 24
Finished Jul 29 06:11:49 PM PDT 24
Peak memory 284008 kb
Host smart-c3b0bfa8-c61b-4261-b920-f5167a1804d9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885873641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.3885873641
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.1462867585
Short name T656
Test name
Test status
Simulation time 7147133528 ps
CPU time 151.92 seconds
Started Jul 29 05:52:41 PM PDT 24
Finished Jul 29 05:55:13 PM PDT 24
Peak memory 254272 kb
Host smart-83bd3923-0bc4-4034-a8ce-f6336d015dca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462867585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.1462867585
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.4202044468
Short name T199
Test name
Test status
Simulation time 223384613 ps
CPU time 24.97 seconds
Started Jul 29 05:52:37 PM PDT 24
Finished Jul 29 05:53:02 PM PDT 24
Peak memory 248320 kb
Host smart-387453da-72c7-4f05-9bb0-9b49a898833d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42020
44468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.4202044468
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.2871876287
Short name T398
Test name
Test status
Simulation time 406950846 ps
CPU time 9.29 seconds
Started Jul 29 05:52:34 PM PDT 24
Finished Jul 29 05:52:43 PM PDT 24
Peak memory 247472 kb
Host smart-759e727d-2d8c-4ebd-ba26-46c00c89d366
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28718
76287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.2871876287
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.2915564205
Short name T284
Test name
Test status
Simulation time 402553040 ps
CPU time 15.87 seconds
Started Jul 29 05:52:35 PM PDT 24
Finished Jul 29 05:52:51 PM PDT 24
Peak memory 248700 kb
Host smart-712c0d95-557f-462b-8b47-480677ad4d32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29155
64205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.2915564205
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.4271839454
Short name T432
Test name
Test status
Simulation time 522114360 ps
CPU time 32.45 seconds
Started Jul 29 05:52:36 PM PDT 24
Finished Jul 29 05:53:09 PM PDT 24
Peak memory 248320 kb
Host smart-5486a857-3a39-4f1a-a6ca-1298dfd902a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42718
39454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.4271839454
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.1453301342
Short name T104
Test name
Test status
Simulation time 137038954 ps
CPU time 10.5 seconds
Started Jul 29 05:52:40 PM PDT 24
Finished Jul 29 05:52:51 PM PDT 24
Peak memory 248340 kb
Host smart-58a98c9a-cfe5-4b00-80e1-c9c68b49454a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453301342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.1453301342
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all_with_rand_reset.4077314228
Short name T109
Test name
Test status
Simulation time 29424660020 ps
CPU time 2783.68 seconds
Started Jul 29 05:52:43 PM PDT 24
Finished Jul 29 06:39:07 PM PDT 24
Peak memory 288800 kb
Host smart-c5a82cc6-9eba-4e7e-957c-7b02ee350a27
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077314228 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.alert_handler_stress_all_with_rand_reset.4077314228
Directory /workspace/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.150187726
Short name T539
Test name
Test status
Simulation time 80002212846 ps
CPU time 2002.27 seconds
Started Jul 29 05:52:40 PM PDT 24
Finished Jul 29 06:26:03 PM PDT 24
Peak memory 287652 kb
Host smart-15c34e96-120c-4169-a7d4-0e88b9235c51
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150187726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.150187726
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.685595613
Short name T469
Test name
Test status
Simulation time 1784106254 ps
CPU time 111.06 seconds
Started Jul 29 05:52:41 PM PDT 24
Finished Jul 29 05:54:32 PM PDT 24
Peak memory 256208 kb
Host smart-809c1cb6-0d32-445f-a385-8b3e48a3b4ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68559
5613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.685595613
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.4126827228
Short name T583
Test name
Test status
Simulation time 2333309425 ps
CPU time 34.34 seconds
Started Jul 29 05:52:43 PM PDT 24
Finished Jul 29 05:53:17 PM PDT 24
Peak memory 248312 kb
Host smart-eeb6b314-b3e8-4c4b-99bd-9e2d353ce88a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41268
27228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.4126827228
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.702514492
Short name T340
Test name
Test status
Simulation time 81328120885 ps
CPU time 1398.61 seconds
Started Jul 29 05:52:40 PM PDT 24
Finished Jul 29 06:15:59 PM PDT 24
Peak memory 272136 kb
Host smart-dc32eb8c-9ed4-47b6-af06-d3dc5a593ed8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702514492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.702514492
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.935046795
Short name T479
Test name
Test status
Simulation time 30542219937 ps
CPU time 2058.06 seconds
Started Jul 29 05:52:42 PM PDT 24
Finished Jul 29 06:27:00 PM PDT 24
Peak memory 283532 kb
Host smart-80537686-5514-4d68-bc15-0cf0684a34bd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935046795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.935046795
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.3702878648
Short name T325
Test name
Test status
Simulation time 33470171728 ps
CPU time 372.31 seconds
Started Jul 29 05:52:41 PM PDT 24
Finished Jul 29 05:58:53 PM PDT 24
Peak memory 248384 kb
Host smart-8408d44f-2a13-4511-b226-f78f6ef3d5ee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702878648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.3702878648
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.3563889526
Short name T428
Test name
Test status
Simulation time 804922390 ps
CPU time 45.47 seconds
Started Jul 29 05:52:42 PM PDT 24
Finished Jul 29 05:53:27 PM PDT 24
Peak memory 256056 kb
Host smart-df65fef7-eda7-4b99-9512-bb90f2ec4e15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35638
89526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.3563889526
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.3656425987
Short name T110
Test name
Test status
Simulation time 2087858189 ps
CPU time 41.5 seconds
Started Jul 29 05:52:41 PM PDT 24
Finished Jul 29 05:53:23 PM PDT 24
Peak memory 255612 kb
Host smart-e51d020f-320f-41c4-89fe-eaa10aa6ca5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36564
25987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.3656425987
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.4281905117
Short name T459
Test name
Test status
Simulation time 84468265 ps
CPU time 11.84 seconds
Started Jul 29 05:52:41 PM PDT 24
Finished Jul 29 05:52:53 PM PDT 24
Peak memory 247892 kb
Host smart-a4157855-ad88-4135-a436-259a92ed5c59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42819
05117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.4281905117
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.3318917259
Short name T298
Test name
Test status
Simulation time 213433954 ps
CPU time 14.5 seconds
Started Jul 29 05:52:44 PM PDT 24
Finished Jul 29 05:52:59 PM PDT 24
Peak memory 254540 kb
Host smart-88a939c4-f263-4c35-9fb4-2898945b40e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33189
17259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.3318917259
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.3418639855
Short name T474
Test name
Test status
Simulation time 19726010765 ps
CPU time 862.48 seconds
Started Jul 29 05:52:47 PM PDT 24
Finished Jul 29 06:07:10 PM PDT 24
Peak memory 281884 kb
Host smart-648414c6-5f62-4d55-bc20-2b91b64d1a5a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418639855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.3418639855
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.1413813319
Short name T570
Test name
Test status
Simulation time 29190697458 ps
CPU time 1778.87 seconds
Started Jul 29 05:52:45 PM PDT 24
Finished Jul 29 06:22:24 PM PDT 24
Peak memory 272900 kb
Host smart-48681c08-d758-4a3a-8a47-aa90f5ff7efd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413813319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.1413813319
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.239414660
Short name T630
Test name
Test status
Simulation time 16504666598 ps
CPU time 214.22 seconds
Started Jul 29 05:52:48 PM PDT 24
Finished Jul 29 05:56:22 PM PDT 24
Peak memory 255824 kb
Host smart-faeb3ae6-bf9e-4fa3-afdf-b44fcf29d6e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23941
4660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.239414660
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.1200936544
Short name T13
Test name
Test status
Simulation time 1630028411 ps
CPU time 38.81 seconds
Started Jul 29 05:52:45 PM PDT 24
Finished Jul 29 05:53:24 PM PDT 24
Peak memory 255864 kb
Host smart-ad62daae-b890-42eb-8378-18252162b956
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12009
36544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.1200936544
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.1836544888
Short name T309
Test name
Test status
Simulation time 39157610106 ps
CPU time 812.62 seconds
Started Jul 29 05:52:47 PM PDT 24
Finished Jul 29 06:06:20 PM PDT 24
Peak memory 272964 kb
Host smart-90a8349e-a9af-45ac-88c0-2b5fc02cdc06
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836544888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.1836544888
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.3681825786
Short name T316
Test name
Test status
Simulation time 18256461945 ps
CPU time 202.65 seconds
Started Jul 29 05:52:48 PM PDT 24
Finished Jul 29 05:56:11 PM PDT 24
Peak memory 255040 kb
Host smart-e24d5a82-14b6-4fdd-a45f-37983d1fd6ad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681825786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.3681825786
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.507341643
Short name T59
Test name
Test status
Simulation time 943883605 ps
CPU time 29.13 seconds
Started Jul 29 05:52:48 PM PDT 24
Finished Jul 29 05:53:17 PM PDT 24
Peak memory 248288 kb
Host smart-9280980a-cac9-4c8b-bc3e-02f45b04d4a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50734
1643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.507341643
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.1513152213
Short name T598
Test name
Test status
Simulation time 2160105014 ps
CPU time 35.9 seconds
Started Jul 29 05:52:46 PM PDT 24
Finished Jul 29 05:53:22 PM PDT 24
Peak memory 256296 kb
Host smart-3933dac7-c577-4e8b-bfb4-7192455645d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15131
52213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.1513152213
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.1929136140
Short name T116
Test name
Test status
Simulation time 767137487 ps
CPU time 54.04 seconds
Started Jul 29 05:52:51 PM PDT 24
Finished Jul 29 05:53:45 PM PDT 24
Peak memory 256572 kb
Host smart-2ff6df76-fa30-4540-97f5-2ff4a383966f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19291
36140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.1929136140
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.3570779904
Short name T95
Test name
Test status
Simulation time 381555312 ps
CPU time 31.38 seconds
Started Jul 29 05:52:46 PM PDT 24
Finished Jul 29 05:53:18 PM PDT 24
Peak memory 255308 kb
Host smart-07496a65-a2ab-4709-bbb1-c787a56c3e16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35707
79904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.3570779904
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.4267350409
Short name T54
Test name
Test status
Simulation time 137516814061 ps
CPU time 2242.53 seconds
Started Jul 29 05:52:50 PM PDT 24
Finished Jul 29 06:30:13 PM PDT 24
Peak memory 289400 kb
Host smart-fec9ead9-14c1-4b1c-92c2-e4a03c70a066
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267350409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.4267350409
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.3689005101
Short name T651
Test name
Test status
Simulation time 5667640772 ps
CPU time 171.77 seconds
Started Jul 29 05:52:54 PM PDT 24
Finished Jul 29 05:55:46 PM PDT 24
Peak memory 256084 kb
Host smart-ab9bb76d-4889-4f33-b2ae-b15f78782353
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36890
05101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.3689005101
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.4005136995
Short name T429
Test name
Test status
Simulation time 1558367851 ps
CPU time 72.92 seconds
Started Jul 29 05:52:53 PM PDT 24
Finished Jul 29 05:54:06 PM PDT 24
Peak memory 256476 kb
Host smart-6168b3b6-972f-4f46-93ee-4d8735aa19aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40051
36995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.4005136995
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.3163951899
Short name T307
Test name
Test status
Simulation time 93331419132 ps
CPU time 1653.28 seconds
Started Jul 29 05:52:48 PM PDT 24
Finished Jul 29 06:20:22 PM PDT 24
Peak memory 288908 kb
Host smart-1a91c4e8-92ff-4f5e-99f2-239ef8652dd6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163951899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.3163951899
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.1008949142
Short name T586
Test name
Test status
Simulation time 11375835286 ps
CPU time 1301.56 seconds
Started Jul 29 05:52:51 PM PDT 24
Finished Jul 29 06:14:33 PM PDT 24
Peak memory 287792 kb
Host smart-5be88f94-72cb-491f-8993-9109c36c85f8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008949142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.1008949142
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.1115988290
Short name T314
Test name
Test status
Simulation time 11425985093 ps
CPU time 475.97 seconds
Started Jul 29 05:52:56 PM PDT 24
Finished Jul 29 06:00:52 PM PDT 24
Peak memory 248392 kb
Host smart-50b2b861-d10a-48fa-aef0-7623353d99bd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115988290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.1115988290
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.1432238251
Short name T498
Test name
Test status
Simulation time 288676262 ps
CPU time 20.94 seconds
Started Jul 29 05:52:52 PM PDT 24
Finished Jul 29 05:53:13 PM PDT 24
Peak memory 248392 kb
Host smart-af6ee875-0c4d-4fa1-a9a2-a5d2a4552908
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14322
38251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.1432238251
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.3071167545
Short name T457
Test name
Test status
Simulation time 301997193 ps
CPU time 10.15 seconds
Started Jul 29 05:52:52 PM PDT 24
Finished Jul 29 05:53:03 PM PDT 24
Peak memory 247732 kb
Host smart-95c7da1d-8f2d-4e9c-b9da-6966a49127a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30711
67545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.3071167545
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.4281514139
Short name T470
Test name
Test status
Simulation time 234105553 ps
CPU time 7.42 seconds
Started Jul 29 05:52:52 PM PDT 24
Finished Jul 29 05:53:00 PM PDT 24
Peak memory 252168 kb
Host smart-0fc09614-24bd-47cb-b302-214aac41eb48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42815
14139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.4281514139
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.2971121910
Short name T448
Test name
Test status
Simulation time 597456898 ps
CPU time 20.97 seconds
Started Jul 29 05:52:52 PM PDT 24
Finished Jul 29 05:53:13 PM PDT 24
Peak memory 248596 kb
Host smart-3b6f8018-c4c7-463a-862d-f6cd43bf7de9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29711
21910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.2971121910
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.1625836117
Short name T561
Test name
Test status
Simulation time 247396211917 ps
CPU time 3812.85 seconds
Started Jul 29 05:52:50 PM PDT 24
Finished Jul 29 06:56:23 PM PDT 24
Peak memory 305440 kb
Host smart-7000529f-f62c-4cac-a7c6-f84d1b259537
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625836117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.1625836117
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.3509578369
Short name T378
Test name
Test status
Simulation time 642216654 ps
CPU time 42.74 seconds
Started Jul 29 05:52:57 PM PDT 24
Finished Jul 29 05:53:40 PM PDT 24
Peak memory 256528 kb
Host smart-9207d8c9-c0d0-4a41-89d6-1ccc15ff9bb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35095
78369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.3509578369
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.117257355
Short name T511
Test name
Test status
Simulation time 902688888 ps
CPU time 27.45 seconds
Started Jul 29 05:52:55 PM PDT 24
Finished Jul 29 05:53:23 PM PDT 24
Peak memory 248236 kb
Host smart-ee48dee9-fed2-4b41-bc44-8c943e162885
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11725
7355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.117257355
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.2168207143
Short name T296
Test name
Test status
Simulation time 11473415132 ps
CPU time 876.2 seconds
Started Jul 29 05:52:56 PM PDT 24
Finished Jul 29 06:07:32 PM PDT 24
Peak memory 272936 kb
Host smart-db9d75ec-9d71-4a02-b00e-a698796186f1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168207143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.2168207143
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.3347852848
Short name T421
Test name
Test status
Simulation time 38773318832 ps
CPU time 2740.06 seconds
Started Jul 29 05:53:00 PM PDT 24
Finished Jul 29 06:38:41 PM PDT 24
Peak memory 288936 kb
Host smart-6fd4ab48-5824-4f7a-be3a-741970322f33
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347852848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.3347852848
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.3857116622
Short name T397
Test name
Test status
Simulation time 3896791161 ps
CPU time 58.79 seconds
Started Jul 29 05:52:57 PM PDT 24
Finished Jul 29 05:53:56 PM PDT 24
Peak memory 256012 kb
Host smart-baf9881a-e14d-43a4-a45b-f8b866810a86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38571
16622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.3857116622
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.163134643
Short name T437
Test name
Test status
Simulation time 434358196 ps
CPU time 18.79 seconds
Started Jul 29 05:52:56 PM PDT 24
Finished Jul 29 05:53:15 PM PDT 24
Peak memory 247364 kb
Host smart-7601d031-600b-4187-b906-bfaa20b583ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16313
4643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.163134643
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.505133956
Short name T389
Test name
Test status
Simulation time 260962130 ps
CPU time 9.49 seconds
Started Jul 29 05:52:59 PM PDT 24
Finished Jul 29 05:53:09 PM PDT 24
Peak memory 248288 kb
Host smart-285c00b9-3f07-4f6d-8473-51382e498f26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50513
3956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.505133956
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.9298323
Short name T297
Test name
Test status
Simulation time 1529953230 ps
CPU time 51.49 seconds
Started Jul 29 05:52:55 PM PDT 24
Finished Jul 29 05:53:47 PM PDT 24
Peak memory 255488 kb
Host smart-c8044d30-ce47-41e1-855f-e14f932eb3fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92983
23 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.9298323
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.391015717
Short name T693
Test name
Test status
Simulation time 75955853808 ps
CPU time 1674.71 seconds
Started Jul 29 05:53:06 PM PDT 24
Finished Jul 29 06:21:01 PM PDT 24
Peak memory 288608 kb
Host smart-b0a07075-9f98-4423-90d1-aa9567e116b4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391015717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.391015717
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.3963061246
Short name T698
Test name
Test status
Simulation time 965689633 ps
CPU time 62.53 seconds
Started Jul 29 05:53:06 PM PDT 24
Finished Jul 29 05:54:09 PM PDT 24
Peak memory 256084 kb
Host smart-1f7a4973-5ae4-4f31-a7be-6cec03079d5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39630
61246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.3963061246
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.644097874
Short name T640
Test name
Test status
Simulation time 235034824 ps
CPU time 21.11 seconds
Started Jul 29 05:53:09 PM PDT 24
Finished Jul 29 05:53:30 PM PDT 24
Peak memory 248304 kb
Host smart-ac0f7852-f868-478d-86eb-8039fc635875
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64409
7874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.644097874
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.2898690528
Short name T353
Test name
Test status
Simulation time 59747704279 ps
CPU time 1105.88 seconds
Started Jul 29 05:53:07 PM PDT 24
Finished Jul 29 06:11:33 PM PDT 24
Peak memory 272988 kb
Host smart-f6ae4f86-aae7-4967-8eac-e10eb054db8a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898690528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.2898690528
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.3791787007
Short name T591
Test name
Test status
Simulation time 72141175798 ps
CPU time 1989.49 seconds
Started Jul 29 05:53:06 PM PDT 24
Finished Jul 29 06:26:16 PM PDT 24
Peak memory 272904 kb
Host smart-e5b96442-d760-40e6-9af6-dbf031c4e615
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791787007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.3791787007
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.3595420957
Short name T525
Test name
Test status
Simulation time 15348122105 ps
CPU time 191.03 seconds
Started Jul 29 05:53:09 PM PDT 24
Finished Jul 29 05:56:20 PM PDT 24
Peak memory 254936 kb
Host smart-27b07d4e-631e-4287-ad06-0558f5dc37be
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595420957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.3595420957
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.1582004138
Short name T65
Test name
Test status
Simulation time 282906634 ps
CPU time 25.35 seconds
Started Jul 29 05:53:09 PM PDT 24
Finished Jul 29 05:53:35 PM PDT 24
Peak memory 255884 kb
Host smart-01861f0e-f629-4dc5-87be-50c9feb72fd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15820
04138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.1582004138
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.3981258077
Short name T23
Test name
Test status
Simulation time 1835104895 ps
CPU time 11.77 seconds
Started Jul 29 05:53:06 PM PDT 24
Finished Jul 29 05:53:17 PM PDT 24
Peak memory 247588 kb
Host smart-bf8313a5-f4c1-4192-94c0-53a01cbd61e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39812
58077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.3981258077
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.1163925100
Short name T628
Test name
Test status
Simulation time 197318532 ps
CPU time 20.23 seconds
Started Jul 29 05:53:05 PM PDT 24
Finished Jul 29 05:53:25 PM PDT 24
Peak memory 256672 kb
Host smart-05f404ae-f607-4c4e-9d88-11b3d316d3e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11639
25100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.1163925100
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.97172553
Short name T376
Test name
Test status
Simulation time 1531941925 ps
CPU time 20.14 seconds
Started Jul 29 05:52:58 PM PDT 24
Finished Jul 29 05:53:19 PM PDT 24
Peak memory 256380 kb
Host smart-816163bc-fae5-4545-86fe-87a7846036b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97172
553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.97172553
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.2234930035
Short name T36
Test name
Test status
Simulation time 4110084789 ps
CPU time 200.41 seconds
Started Jul 29 05:53:08 PM PDT 24
Finished Jul 29 05:56:29 PM PDT 24
Peak memory 256612 kb
Host smart-f68f625a-9e76-4247-b4b5-d44a7afe0449
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234930035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.2234930035
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.3098813575
Short name T259
Test name
Test status
Simulation time 120541634461 ps
CPU time 3292.03 seconds
Started Jul 29 05:53:06 PM PDT 24
Finished Jul 29 06:47:59 PM PDT 24
Peak memory 337936 kb
Host smart-d044ea8a-f411-477f-bf84-d475f504a808
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098813575 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.3098813575
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.481788459
Short name T69
Test name
Test status
Simulation time 177893455807 ps
CPU time 1446.64 seconds
Started Jul 29 05:53:09 PM PDT 24
Finished Jul 29 06:17:16 PM PDT 24
Peak memory 272860 kb
Host smart-5b8198aa-d2cf-44fb-8303-2ac8d020b412
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481788459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.481788459
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.1782582272
Short name T408
Test name
Test status
Simulation time 2374586054 ps
CPU time 145.5 seconds
Started Jul 29 05:53:13 PM PDT 24
Finished Jul 29 05:55:38 PM PDT 24
Peak memory 255820 kb
Host smart-a58adecf-ed4c-4cab-8f6c-2cd6301d4dc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17825
82272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.1782582272
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.3415484480
Short name T508
Test name
Test status
Simulation time 1132722332 ps
CPU time 29.51 seconds
Started Jul 29 05:53:06 PM PDT 24
Finished Jul 29 05:53:35 PM PDT 24
Peak memory 256060 kb
Host smart-1af48a9b-2783-44e9-be5e-7347fc7a7a14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34154
84480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.3415484480
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.3962113565
Short name T344
Test name
Test status
Simulation time 139627526172 ps
CPU time 2131.08 seconds
Started Jul 29 05:53:10 PM PDT 24
Finished Jul 29 06:28:41 PM PDT 24
Peak memory 272956 kb
Host smart-d6e0fd25-d3dd-4c5d-8990-a297f3bd728f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962113565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.3962113565
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.181362825
Short name T495
Test name
Test status
Simulation time 36373255591 ps
CPU time 1949.25 seconds
Started Jul 29 05:53:10 PM PDT 24
Finished Jul 29 06:25:39 PM PDT 24
Peak memory 289248 kb
Host smart-3a14f747-9781-478a-94c5-6d03c8e4f8fa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181362825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.181362825
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.1270013369
Short name T322
Test name
Test status
Simulation time 29375400582 ps
CPU time 82.93 seconds
Started Jul 29 05:53:14 PM PDT 24
Finished Jul 29 05:54:37 PM PDT 24
Peak memory 254476 kb
Host smart-316e6479-ad3d-463d-81cc-cc89e8d710fb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270013369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.1270013369
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.2424678389
Short name T393
Test name
Test status
Simulation time 215719287 ps
CPU time 28.75 seconds
Started Jul 29 05:53:08 PM PDT 24
Finished Jul 29 05:53:37 PM PDT 24
Peak memory 256452 kb
Host smart-d2daabd5-eb0e-43c4-b8f6-ecb9a7fafbbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24246
78389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.2424678389
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.1252469282
Short name T471
Test name
Test status
Simulation time 147993801 ps
CPU time 9.99 seconds
Started Jul 29 05:53:06 PM PDT 24
Finished Jul 29 05:53:16 PM PDT 24
Peak memory 253952 kb
Host smart-1b51d4d9-2424-4b8c-a3ea-a99de5517757
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12524
69282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.1252469282
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.2524222504
Short name T50
Test name
Test status
Simulation time 1314039678 ps
CPU time 21.08 seconds
Started Jul 29 05:53:10 PM PDT 24
Finished Jul 29 05:53:31 PM PDT 24
Peak memory 256096 kb
Host smart-26d5a352-7010-4c07-bafd-f5b7bd5f7498
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25242
22504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.2524222504
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.3730257325
Short name T657
Test name
Test status
Simulation time 1060665331 ps
CPU time 18.11 seconds
Started Jul 29 05:53:09 PM PDT 24
Finished Jul 29 05:53:27 PM PDT 24
Peak memory 256500 kb
Host smart-a002af82-60b3-4a51-bc2e-da643d650b2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37302
57325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.3730257325
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.426027177
Short name T438
Test name
Test status
Simulation time 72211726862 ps
CPU time 1523 seconds
Started Jul 29 05:53:10 PM PDT 24
Finished Jul 29 06:18:33 PM PDT 24
Peak memory 288800 kb
Host smart-c22fe20c-c317-4509-acbc-60030cb2571c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426027177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_han
dler_stress_all.426027177
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.1969030422
Short name T246
Test name
Test status
Simulation time 149855284260 ps
CPU time 4699.34 seconds
Started Jul 29 05:53:09 PM PDT 24
Finished Jul 29 07:11:29 PM PDT 24
Peak memory 321952 kb
Host smart-605a67ec-6e61-49bd-9a36-2478d0d28840
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969030422 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.1969030422
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.1833258205
Short name T85
Test name
Test status
Simulation time 36058732864 ps
CPU time 2162.43 seconds
Started Jul 29 05:53:14 PM PDT 24
Finished Jul 29 06:29:17 PM PDT 24
Peak memory 288348 kb
Host smart-b2a17050-7e9b-4ce5-9e3e-1f448d76534a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833258205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.1833258205
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.1308963976
Short name T638
Test name
Test status
Simulation time 596766439 ps
CPU time 13.77 seconds
Started Jul 29 05:53:14 PM PDT 24
Finished Jul 29 05:53:28 PM PDT 24
Peak memory 256072 kb
Host smart-f274ea00-6152-4f0f-89a3-3f9f38442acb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13089
63976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.1308963976
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.960725875
Short name T415
Test name
Test status
Simulation time 58450531 ps
CPU time 4.68 seconds
Started Jul 29 05:53:14 PM PDT 24
Finished Jul 29 05:53:19 PM PDT 24
Peak memory 248756 kb
Host smart-21cb39a0-6147-441c-a247-98ac2ab1b91c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96072
5875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.960725875
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.1836711831
Short name T68
Test name
Test status
Simulation time 40256360152 ps
CPU time 1440.69 seconds
Started Jul 29 05:53:16 PM PDT 24
Finished Jul 29 06:17:17 PM PDT 24
Peak memory 265732 kb
Host smart-dbb1b8d9-0067-4893-9659-119f94775033
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836711831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.1836711831
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.601591621
Short name T506
Test name
Test status
Simulation time 160670578061 ps
CPU time 1144.72 seconds
Started Jul 29 05:53:16 PM PDT 24
Finished Jul 29 06:12:21 PM PDT 24
Peak memory 281036 kb
Host smart-8e0a8d99-fa3b-41cf-8fd0-c6fc55cd6908
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601591621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.601591621
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.3319069659
Short name T329
Test name
Test status
Simulation time 4210847453 ps
CPU time 180.21 seconds
Started Jul 29 05:53:15 PM PDT 24
Finished Jul 29 05:56:15 PM PDT 24
Peak memory 248132 kb
Host smart-07ee09e4-aac5-4761-a144-bafc9742db60
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319069659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.3319069659
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.2949484732
Short name T703
Test name
Test status
Simulation time 683940381 ps
CPU time 31.49 seconds
Started Jul 29 05:53:12 PM PDT 24
Finished Jul 29 05:53:43 PM PDT 24
Peak memory 248476 kb
Host smart-2418f73d-f717-4948-8c40-c50d0046e068
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29494
84732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.2949484732
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.724742318
Short name T33
Test name
Test status
Simulation time 2588503531 ps
CPU time 40.99 seconds
Started Jul 29 05:53:14 PM PDT 24
Finished Jul 29 05:53:55 PM PDT 24
Peak memory 248376 kb
Host smart-fff18b27-ed76-4259-8830-6fd244c58641
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72474
2318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.724742318
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.1834255050
Short name T39
Test name
Test status
Simulation time 593129952 ps
CPU time 37.3 seconds
Started Jul 29 05:53:18 PM PDT 24
Finished Jul 29 05:53:55 PM PDT 24
Peak memory 256080 kb
Host smart-302171f8-30e0-470d-b02f-4e00b3e9b32b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18342
55050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.1834255050
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.1155596019
Short name T414
Test name
Test status
Simulation time 826535265 ps
CPU time 47.49 seconds
Started Jul 29 05:53:13 PM PDT 24
Finished Jul 29 05:54:01 PM PDT 24
Peak memory 256704 kb
Host smart-24880c28-29f4-41d2-9dbf-eba4241b0737
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11555
96019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.1155596019
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.3385743421
Short name T240
Test name
Test status
Simulation time 169920045582 ps
CPU time 2205.02 seconds
Started Jul 29 05:53:15 PM PDT 24
Finished Jul 29 06:30:00 PM PDT 24
Peak memory 288708 kb
Host smart-fa4c172b-d118-4038-add6-bb6cd88d4b51
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385743421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.3385743421
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.295499849
Short name T557
Test name
Test status
Simulation time 51819139346 ps
CPU time 2795.39 seconds
Started Jul 29 05:53:20 PM PDT 24
Finished Jul 29 06:39:56 PM PDT 24
Peak memory 305728 kb
Host smart-8498609a-d29e-48e0-b0c6-233137a1b205
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295499849 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.295499849
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.1011156955
Short name T225
Test name
Test status
Simulation time 46020723 ps
CPU time 3.77 seconds
Started Jul 29 05:51:00 PM PDT 24
Finished Jul 29 05:51:04 PM PDT 24
Peak memory 248588 kb
Host smart-3984392d-2e56-4c2d-a018-cb1109114824
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1011156955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.1011156955
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.733258018
Short name T97
Test name
Test status
Simulation time 23231755722 ps
CPU time 1444.1 seconds
Started Jul 29 05:50:56 PM PDT 24
Finished Jul 29 06:15:01 PM PDT 24
Peak memory 288432 kb
Host smart-2eaba003-1575-45f5-b065-297e2ee8feea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733258018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.733258018
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.2731355291
Short name T505
Test name
Test status
Simulation time 711361640 ps
CPU time 28.67 seconds
Started Jul 29 05:50:55 PM PDT 24
Finished Jul 29 05:51:24 PM PDT 24
Peak memory 248216 kb
Host smart-c2caef4b-222b-49d5-b010-204b8a6f4872
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2731355291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.2731355291
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.3520689215
Short name T519
Test name
Test status
Simulation time 5096732207 ps
CPU time 69.28 seconds
Started Jul 29 05:50:54 PM PDT 24
Finished Jul 29 05:52:03 PM PDT 24
Peak memory 248332 kb
Host smart-e95d6764-c09b-4b23-962c-be80397b9789
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35206
89215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.3520689215
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.3330059262
Short name T652
Test name
Test status
Simulation time 388550009 ps
CPU time 7.64 seconds
Started Jul 29 05:50:56 PM PDT 24
Finished Jul 29 05:51:04 PM PDT 24
Peak memory 247900 kb
Host smart-d661a7a5-86c9-451d-99f3-89403a052a81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33300
59262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.3330059262
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.832619236
Short name T385
Test name
Test status
Simulation time 20312255007 ps
CPU time 1132.37 seconds
Started Jul 29 05:50:57 PM PDT 24
Finished Jul 29 06:09:50 PM PDT 24
Peak memory 281528 kb
Host smart-889c9a57-b805-44ab-975d-6ea18ba859e5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832619236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.832619236
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.3522086481
Short name T332
Test name
Test status
Simulation time 13306333818 ps
CPU time 565.33 seconds
Started Jul 29 05:50:56 PM PDT 24
Finished Jul 29 06:00:21 PM PDT 24
Peak memory 248312 kb
Host smart-74a77069-d8ca-48db-9b74-8823411ab1b5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522086481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.3522086481
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.4284397323
Short name T433
Test name
Test status
Simulation time 199410007 ps
CPU time 18.99 seconds
Started Jul 29 05:50:56 PM PDT 24
Finished Jul 29 05:51:15 PM PDT 24
Peak memory 248288 kb
Host smart-dfd0e963-5f06-48b9-84c1-1267a536c9eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42843
97323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.4284397323
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.3211698665
Short name T621
Test name
Test status
Simulation time 723469950 ps
CPU time 45.82 seconds
Started Jul 29 05:50:57 PM PDT 24
Finished Jul 29 05:51:43 PM PDT 24
Peak memory 248308 kb
Host smart-03598b87-8ef4-4235-899f-ee99b4abdffa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32116
98665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.3211698665
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.1079188932
Short name T11
Test name
Test status
Simulation time 237445005 ps
CPU time 14.8 seconds
Started Jul 29 05:51:00 PM PDT 24
Finished Jul 29 05:51:14 PM PDT 24
Peak memory 269584 kb
Host smart-9f76de0d-bbaa-47a4-9e77-2a0208faed77
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1079188932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.1079188932
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.3497151243
Short name T589
Test name
Test status
Simulation time 1037664798 ps
CPU time 51.53 seconds
Started Jul 29 05:50:57 PM PDT 24
Finished Jul 29 05:51:49 PM PDT 24
Peak memory 248336 kb
Host smart-4df8510e-e13d-42cc-bb87-3f8d976d99fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34971
51243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.3497151243
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.4255602547
Short name T494
Test name
Test status
Simulation time 22048389834 ps
CPU time 1643.11 seconds
Started Jul 29 05:50:54 PM PDT 24
Finished Jul 29 06:18:17 PM PDT 24
Peak memory 301720 kb
Host smart-3406df01-b809-4e1d-8bab-ed3aec1efa24
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255602547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.4255602547
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.345794918
Short name T556
Test name
Test status
Simulation time 5491450688 ps
CPU time 658.28 seconds
Started Jul 29 05:53:19 PM PDT 24
Finished Jul 29 06:04:17 PM PDT 24
Peak memory 272332 kb
Host smart-06b4ab50-7a49-4a60-b2dd-3e1219538bcf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345794918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.345794918
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.1075655861
Short name T422
Test name
Test status
Simulation time 3076632608 ps
CPU time 54.79 seconds
Started Jul 29 05:53:20 PM PDT 24
Finished Jul 29 05:54:15 PM PDT 24
Peak memory 256588 kb
Host smart-225167a9-0681-412e-b2ca-99b9e81ab096
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10756
55861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.1075655861
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.2758967044
Short name T201
Test name
Test status
Simulation time 989540591 ps
CPU time 57.61 seconds
Started Jul 29 05:53:23 PM PDT 24
Finished Jul 29 05:54:20 PM PDT 24
Peak memory 248344 kb
Host smart-8cfc5950-69c6-4dfd-b397-1c6c3b49a920
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27589
67044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.2758967044
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.1183799864
Short name T354
Test name
Test status
Simulation time 118993031549 ps
CPU time 1857.28 seconds
Started Jul 29 05:53:25 PM PDT 24
Finished Jul 29 06:24:22 PM PDT 24
Peak memory 281068 kb
Host smart-52c7238e-ba5e-4e9c-9701-7eeaaea553a6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183799864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.1183799864
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.3134544592
Short name T427
Test name
Test status
Simulation time 79976040898 ps
CPU time 3002.34 seconds
Started Jul 29 05:53:26 PM PDT 24
Finished Jul 29 06:43:28 PM PDT 24
Peak memory 289300 kb
Host smart-813572ec-b364-442d-a5e3-bd7996c331f8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134544592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.3134544592
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.3761588129
Short name T3
Test name
Test status
Simulation time 3146553688 ps
CPU time 50.53 seconds
Started Jul 29 05:53:19 PM PDT 24
Finished Jul 29 05:54:09 PM PDT 24
Peak memory 256528 kb
Host smart-e98fd4f9-b447-48cb-bfbf-d02d507e597e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37615
88129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.3761588129
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.557119983
Short name T294
Test name
Test status
Simulation time 831175743 ps
CPU time 62.09 seconds
Started Jul 29 05:53:19 PM PDT 24
Finished Jul 29 05:54:22 PM PDT 24
Peak memory 248108 kb
Host smart-1a96b0b2-3f91-45d6-9beb-43376d450958
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55711
9983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.557119983
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.3424819598
Short name T642
Test name
Test status
Simulation time 1214990710 ps
CPU time 43.36 seconds
Started Jul 29 05:53:21 PM PDT 24
Finished Jul 29 05:54:04 PM PDT 24
Peak memory 247660 kb
Host smart-626d6b7d-0396-4626-a41e-b23679f8e17f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34248
19598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.3424819598
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.1777048489
Short name T627
Test name
Test status
Simulation time 702466468 ps
CPU time 25.1 seconds
Started Jul 29 05:53:20 PM PDT 24
Finished Jul 29 05:53:46 PM PDT 24
Peak memory 248728 kb
Host smart-34227a8f-ea4e-4aba-8e2c-35fb6a9ca977
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17770
48489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.1777048489
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.2254106709
Short name T654
Test name
Test status
Simulation time 13025189144 ps
CPU time 783.36 seconds
Started Jul 29 05:53:24 PM PDT 24
Finished Jul 29 06:06:28 PM PDT 24
Peak memory 264820 kb
Host smart-44b6f87b-1c80-4c97-b29e-3b9d2eb5eb85
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254106709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.2254106709
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.799417855
Short name T136
Test name
Test status
Simulation time 81884530062 ps
CPU time 2920.34 seconds
Started Jul 29 05:53:24 PM PDT 24
Finished Jul 29 06:42:05 PM PDT 24
Peak memory 303056 kb
Host smart-944d9d0b-3a64-4806-a978-4f8bf101354a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799417855 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.799417855
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.3990996869
Short name T636
Test name
Test status
Simulation time 3967711611 ps
CPU time 247.03 seconds
Started Jul 29 05:53:25 PM PDT 24
Finished Jul 29 05:57:32 PM PDT 24
Peak memory 256132 kb
Host smart-fe4f9fbb-df4e-4a85-8e82-16fe422c52b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39909
96869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.3990996869
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.2967614227
Short name T419
Test name
Test status
Simulation time 171381963 ps
CPU time 16.54 seconds
Started Jul 29 05:53:25 PM PDT 24
Finished Jul 29 05:53:41 PM PDT 24
Peak memory 256512 kb
Host smart-03195500-47de-40db-bd41-1d3eea3d5d71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29676
14227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.2967614227
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.3644456120
Short name T339
Test name
Test status
Simulation time 34642760209 ps
CPU time 807.87 seconds
Started Jul 29 05:53:30 PM PDT 24
Finished Jul 29 06:06:58 PM PDT 24
Peak memory 272960 kb
Host smart-a36cb126-382c-4469-b849-8b35e8869545
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644456120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.3644456120
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.3992144922
Short name T107
Test name
Test status
Simulation time 68547141665 ps
CPU time 1213.03 seconds
Started Jul 29 05:53:28 PM PDT 24
Finished Jul 29 06:13:41 PM PDT 24
Peak memory 272904 kb
Host smart-f74b4475-196e-4b10-a2e1-b34acf1e498b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992144922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.3992144922
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.556072886
Short name T655
Test name
Test status
Simulation time 4126596966 ps
CPU time 154.73 seconds
Started Jul 29 05:53:29 PM PDT 24
Finished Jul 29 05:56:04 PM PDT 24
Peak memory 256160 kb
Host smart-ba8e53bd-d269-49a0-988c-8f75545c1bc4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556072886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.556072886
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.1922514687
Short name T643
Test name
Test status
Simulation time 8990251110 ps
CPU time 70.34 seconds
Started Jul 29 05:53:23 PM PDT 24
Finished Jul 29 05:54:33 PM PDT 24
Peak memory 248348 kb
Host smart-e6d5fc54-3584-4684-bf6d-2852fd502be2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19225
14687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.1922514687
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.4127538916
Short name T436
Test name
Test status
Simulation time 5281779764 ps
CPU time 38.22 seconds
Started Jul 29 05:53:23 PM PDT 24
Finished Jul 29 05:54:01 PM PDT 24
Peak memory 256604 kb
Host smart-5478af92-bc95-43cb-a44d-8b2f8d904629
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41275
38916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.4127538916
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.23589275
Short name T664
Test name
Test status
Simulation time 1694488441 ps
CPU time 36.93 seconds
Started Jul 29 05:53:28 PM PDT 24
Finished Jul 29 05:54:05 PM PDT 24
Peak memory 256408 kb
Host smart-6bd28bd7-8c63-4df4-98f2-f5820543b519
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23589
275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.23589275
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.2079734198
Short name T410
Test name
Test status
Simulation time 529267285 ps
CPU time 10.13 seconds
Started Jul 29 05:53:22 PM PDT 24
Finished Jul 29 05:53:32 PM PDT 24
Peak memory 255092 kb
Host smart-83b0901d-ebec-4ce0-82c4-173f73fdaf15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20797
34198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.2079734198
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.3012193239
Short name T680
Test name
Test status
Simulation time 148989491508 ps
CPU time 1636.72 seconds
Started Jul 29 05:53:32 PM PDT 24
Finished Jul 29 06:20:49 PM PDT 24
Peak memory 272552 kb
Host smart-54772d9b-a23e-4e99-97b0-85420bccf7e7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012193239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.3012193239
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.3563048803
Short name T569
Test name
Test status
Simulation time 2493780598 ps
CPU time 45.21 seconds
Started Jul 29 05:53:34 PM PDT 24
Finished Jul 29 05:54:19 PM PDT 24
Peak memory 256120 kb
Host smart-291340b5-18e0-4602-b565-5d103dc914e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35630
48803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.3563048803
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.2198360947
Short name T488
Test name
Test status
Simulation time 4023291881 ps
CPU time 63.73 seconds
Started Jul 29 05:53:31 PM PDT 24
Finished Jul 29 05:54:35 PM PDT 24
Peak memory 248348 kb
Host smart-06b71596-04ed-4638-bc3c-b78dbaa2114c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21983
60947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.2198360947
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.2540067988
Short name T709
Test name
Test status
Simulation time 22413224026 ps
CPU time 1273.43 seconds
Started Jul 29 05:53:35 PM PDT 24
Finished Jul 29 06:14:49 PM PDT 24
Peak memory 272948 kb
Host smart-4a606b1e-917a-4cdc-9169-09214808b361
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540067988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.2540067988
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.2307228883
Short name T555
Test name
Test status
Simulation time 41895011621 ps
CPU time 2244.09 seconds
Started Jul 29 05:53:37 PM PDT 24
Finished Jul 29 06:31:01 PM PDT 24
Peak memory 281128 kb
Host smart-df2b667e-cc0c-4209-9686-d3dbb36f7c2d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307228883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.2307228883
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.2436737548
Short name T608
Test name
Test status
Simulation time 55768216998 ps
CPU time 543.29 seconds
Started Jul 29 05:53:34 PM PDT 24
Finished Jul 29 06:02:37 PM PDT 24
Peak memory 248388 kb
Host smart-dbf2fc3f-5385-4887-9112-053c3f2821a2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436737548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.2436737548
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.630505671
Short name T559
Test name
Test status
Simulation time 523503895 ps
CPU time 20.79 seconds
Started Jul 29 05:53:32 PM PDT 24
Finished Jul 29 05:53:53 PM PDT 24
Peak memory 255808 kb
Host smart-196584f3-ba97-4482-8285-d94a0d47e80d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63050
5671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.630505671
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.2343014165
Short name T504
Test name
Test status
Simulation time 981705260 ps
CPU time 55.68 seconds
Started Jul 29 05:53:32 PM PDT 24
Finished Jul 29 05:54:28 PM PDT 24
Peak memory 255936 kb
Host smart-95e95660-1eb5-464a-a3c8-d463dd65cac3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23430
14165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.2343014165
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.3407113450
Short name T266
Test name
Test status
Simulation time 1984991656 ps
CPU time 37.54 seconds
Started Jul 29 05:53:32 PM PDT 24
Finished Jul 29 05:54:10 PM PDT 24
Peak memory 256480 kb
Host smart-4fff995f-f155-4b64-9aef-5e1cb817d633
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34071
13450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.3407113450
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.585967404
Short name T499
Test name
Test status
Simulation time 1109681053 ps
CPU time 38.19 seconds
Started Jul 29 05:53:34 PM PDT 24
Finished Jul 29 05:54:12 PM PDT 24
Peak memory 256288 kb
Host smart-106f3c4a-7ff9-4835-bad7-1015d976ce86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58596
7404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.585967404
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.4008252353
Short name T670
Test name
Test status
Simulation time 125721760602 ps
CPU time 3145.62 seconds
Started Jul 29 05:53:34 PM PDT 24
Finished Jul 29 06:46:00 PM PDT 24
Peak memory 289344 kb
Host smart-663622d6-5171-4488-a6c7-7f5733d740dd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008252353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.4008252353
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.2847288103
Short name T404
Test name
Test status
Simulation time 21226123070 ps
CPU time 1271.09 seconds
Started Jul 29 05:53:43 PM PDT 24
Finished Jul 29 06:14:54 PM PDT 24
Peak memory 272976 kb
Host smart-44a96f07-3fee-4c7c-b922-18102af31c04
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847288103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.2847288103
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.1214519259
Short name T45
Test name
Test status
Simulation time 26865653182 ps
CPU time 137.64 seconds
Started Jul 29 05:53:43 PM PDT 24
Finished Jul 29 05:56:01 PM PDT 24
Peak memory 255960 kb
Host smart-4925a544-c7f5-415a-8100-f18838d91cfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12145
19259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.1214519259
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.2384030062
Short name T74
Test name
Test status
Simulation time 142260408 ps
CPU time 16.48 seconds
Started Jul 29 05:53:41 PM PDT 24
Finished Jul 29 05:53:58 PM PDT 24
Peak memory 255620 kb
Host smart-c41be497-721f-4317-ba98-7b72f532bbe6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23840
30062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.2384030062
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.2198108067
Short name T43
Test name
Test status
Simulation time 17506862793 ps
CPU time 926.78 seconds
Started Jul 29 05:53:42 PM PDT 24
Finished Jul 29 06:09:09 PM PDT 24
Peak memory 272364 kb
Host smart-9163d7b7-b070-48ac-8cd4-e3b6cca2c9b4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198108067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.2198108067
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.1534600199
Short name T392
Test name
Test status
Simulation time 24247661475 ps
CPU time 1529.05 seconds
Started Jul 29 05:53:42 PM PDT 24
Finished Jul 29 06:19:11 PM PDT 24
Peak memory 272916 kb
Host smart-a74250b3-37e3-49d3-97a8-726c2d4938d0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534600199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.1534600199
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.2287440546
Short name T679
Test name
Test status
Simulation time 22342095152 ps
CPU time 228.64 seconds
Started Jul 29 05:53:42 PM PDT 24
Finished Jul 29 05:57:30 PM PDT 24
Peak memory 248336 kb
Host smart-d7b8931d-9d87-4330-9bbd-85db4ab75f92
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287440546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.2287440546
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.116696772
Short name T669
Test name
Test status
Simulation time 4847778430 ps
CPU time 64.22 seconds
Started Jul 29 05:53:41 PM PDT 24
Finished Jul 29 05:54:45 PM PDT 24
Peak memory 248404 kb
Host smart-e5d29e1b-e749-45de-8544-42237478b4eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11669
6772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.116696772
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.1241440232
Short name T72
Test name
Test status
Simulation time 67527045 ps
CPU time 12 seconds
Started Jul 29 05:53:41 PM PDT 24
Finished Jul 29 05:53:53 PM PDT 24
Peak memory 255468 kb
Host smart-9098fea6-6e55-4fe0-a0c8-ce2f80be9cbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12414
40232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.1241440232
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.3878854568
Short name T677
Test name
Test status
Simulation time 206615982 ps
CPU time 13.62 seconds
Started Jul 29 05:53:43 PM PDT 24
Finished Jul 29 05:53:57 PM PDT 24
Peak memory 248752 kb
Host smart-1cf503da-bcd5-4d16-89e9-8fd67813d674
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38788
54568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.3878854568
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.435859964
Short name T401
Test name
Test status
Simulation time 1773282299 ps
CPU time 38.52 seconds
Started Jul 29 05:53:33 PM PDT 24
Finished Jul 29 05:54:12 PM PDT 24
Peak memory 256452 kb
Host smart-35590812-ea20-4e64-b043-eafda1fd6f3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43585
9964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.435859964
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.3049820230
Short name T279
Test name
Test status
Simulation time 139226954428 ps
CPU time 1555.61 seconds
Started Jul 29 05:53:43 PM PDT 24
Finished Jul 29 06:19:39 PM PDT 24
Peak memory 281504 kb
Host smart-4f662e06-4321-45de-9d34-bb72ec32df1d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049820230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.3049820230
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.512763876
Short name T426
Test name
Test status
Simulation time 6269056321 ps
CPU time 719.77 seconds
Started Jul 29 05:53:49 PM PDT 24
Finished Jul 29 06:05:49 PM PDT 24
Peak memory 272944 kb
Host smart-ea689fbf-e72d-4925-a21d-cf77420527c4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512763876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.512763876
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.3149779376
Short name T382
Test name
Test status
Simulation time 535029813 ps
CPU time 32.41 seconds
Started Jul 29 05:53:52 PM PDT 24
Finished Jul 29 05:54:25 PM PDT 24
Peak memory 255492 kb
Host smart-2b8b041b-beae-4f8c-bfd5-b0d776d1236a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31497
79376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.3149779376
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.2700825996
Short name T614
Test name
Test status
Simulation time 1541538786 ps
CPU time 56.25 seconds
Started Jul 29 05:53:45 PM PDT 24
Finished Jul 29 05:54:42 PM PDT 24
Peak memory 248276 kb
Host smart-3cab1094-50cc-4b24-a92c-abcd5dd3411c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27008
25996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.2700825996
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.3613704628
Short name T356
Test name
Test status
Simulation time 220021730194 ps
CPU time 3181.05 seconds
Started Jul 29 05:53:52 PM PDT 24
Finished Jul 29 06:46:54 PM PDT 24
Peak memory 288672 kb
Host smart-1f63c8ff-9009-4090-8073-bbb50492f003
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613704628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.3613704628
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.769801534
Short name T430
Test name
Test status
Simulation time 220381358724 ps
CPU time 3103.23 seconds
Started Jul 29 05:53:50 PM PDT 24
Finished Jul 29 06:45:33 PM PDT 24
Peak memory 288692 kb
Host smart-02ed0e98-4754-4925-8328-f2fde34b1407
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769801534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.769801534
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.1107383173
Short name T558
Test name
Test status
Simulation time 36130368944 ps
CPU time 392.44 seconds
Started Jul 29 05:53:47 PM PDT 24
Finished Jul 29 06:00:20 PM PDT 24
Peak memory 248420 kb
Host smart-bb1277e3-fd0f-4481-96da-13ccac5ec9b3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107383173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.1107383173
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.883144635
Short name T420
Test name
Test status
Simulation time 156534525 ps
CPU time 18.98 seconds
Started Jul 29 05:53:47 PM PDT 24
Finished Jul 29 05:54:07 PM PDT 24
Peak memory 255992 kb
Host smart-6fab5fc4-0e75-4fca-8fb7-458248853a64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88314
4635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.883144635
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.2706115943
Short name T477
Test name
Test status
Simulation time 1112607511 ps
CPU time 36.07 seconds
Started Jul 29 05:53:48 PM PDT 24
Finished Jul 29 05:54:24 PM PDT 24
Peak memory 255748 kb
Host smart-e0ab9879-525e-4551-997a-e5089f0e3c90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27061
15943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.2706115943
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.1014146648
Short name T41
Test name
Test status
Simulation time 214545512 ps
CPU time 8.03 seconds
Started Jul 29 05:53:48 PM PDT 24
Finished Jul 29 05:53:56 PM PDT 24
Peak memory 248316 kb
Host smart-5b037285-8b86-4db7-b42d-638384262700
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10141
46648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.1014146648
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.1045983702
Short name T431
Test name
Test status
Simulation time 1153352060 ps
CPU time 68.14 seconds
Started Jul 29 05:53:42 PM PDT 24
Finished Jul 29 05:54:50 PM PDT 24
Peak memory 255928 kb
Host smart-30ac17bb-6ffc-46d1-bd92-891d8ee1145b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10459
83702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.1045983702
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.449613135
Short name T281
Test name
Test status
Simulation time 18573947030 ps
CPU time 243.65 seconds
Started Jul 29 05:53:52 PM PDT 24
Finished Jul 29 05:57:56 PM PDT 24
Peak memory 256604 kb
Host smart-8d3f6f02-eceb-4127-9765-3848d04c7e04
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449613135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_han
dler_stress_all.449613135
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.466371772
Short name T121
Test name
Test status
Simulation time 128496848084 ps
CPU time 2051.05 seconds
Started Jul 29 05:53:51 PM PDT 24
Finished Jul 29 06:28:03 PM PDT 24
Peak memory 287724 kb
Host smart-d25d7fae-8dcc-4c22-99b1-f42d0bc5fccf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466371772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.466371772
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.1092436157
Short name T456
Test name
Test status
Simulation time 17860155160 ps
CPU time 239.28 seconds
Started Jul 29 05:53:52 PM PDT 24
Finished Jul 29 05:57:52 PM PDT 24
Peak memory 256568 kb
Host smart-277bc779-4af4-4c77-b175-91053a08a4a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10924
36157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.1092436157
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.3709887667
Short name T537
Test name
Test status
Simulation time 1672882460 ps
CPU time 27.86 seconds
Started Jul 29 05:53:52 PM PDT 24
Finished Jul 29 05:54:20 PM PDT 24
Peak memory 256504 kb
Host smart-192f1c0f-a93c-4b0a-97ad-1475947ef1ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37098
87667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.3709887667
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.2435175880
Short name T352
Test name
Test status
Simulation time 87091691884 ps
CPU time 1875.76 seconds
Started Jul 29 05:53:52 PM PDT 24
Finished Jul 29 06:25:09 PM PDT 24
Peak memory 289344 kb
Host smart-5d438b90-e99d-49ff-8668-22e4ac9aa691
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435175880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.2435175880
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.60133015
Short name T682
Test name
Test status
Simulation time 41080173382 ps
CPU time 1064.16 seconds
Started Jul 29 05:53:52 PM PDT 24
Finished Jul 29 06:11:36 PM PDT 24
Peak memory 272368 kb
Host smart-224dd592-dddb-400c-ba62-3f2573ecbf8b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60133015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.60133015
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.2987489671
Short name T318
Test name
Test status
Simulation time 6881474208 ps
CPU time 272.7 seconds
Started Jul 29 05:53:52 PM PDT 24
Finished Jul 29 05:58:25 PM PDT 24
Peak memory 254648 kb
Host smart-b48431bf-f086-4dcd-b98a-07b581a5871c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987489671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.2987489671
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.4031172016
Short name T411
Test name
Test status
Simulation time 1132618428 ps
CPU time 21.47 seconds
Started Jul 29 05:53:48 PM PDT 24
Finished Jul 29 05:54:10 PM PDT 24
Peak memory 248204 kb
Host smart-ddac93bc-2d86-46a4-a1c0-cd06cb9be449
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40311
72016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.4031172016
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.711289878
Short name T46
Test name
Test status
Simulation time 4102504910 ps
CPU time 53.21 seconds
Started Jul 29 05:53:51 PM PDT 24
Finished Jul 29 05:54:44 PM PDT 24
Peak memory 256592 kb
Host smart-ae2f0313-3b00-4b29-ad97-655d23384d6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71128
9878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.711289878
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.2192387777
Short name T478
Test name
Test status
Simulation time 560937715 ps
CPU time 30.52 seconds
Started Jul 29 05:53:51 PM PDT 24
Finished Jul 29 05:54:22 PM PDT 24
Peak memory 255652 kb
Host smart-a54e0622-6761-48f4-9a2b-73ba6131f93c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21923
87777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.2192387777
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.1424663341
Short name T650
Test name
Test status
Simulation time 1198664688 ps
CPU time 28.42 seconds
Started Jul 29 05:53:50 PM PDT 24
Finished Jul 29 05:54:19 PM PDT 24
Peak memory 256492 kb
Host smart-648d4029-0df7-46d6-8659-3e843ad6642a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14246
63341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.1424663341
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.3467389504
Short name T278
Test name
Test status
Simulation time 80411678442 ps
CPU time 4309.74 seconds
Started Jul 29 05:53:58 PM PDT 24
Finished Jul 29 07:05:48 PM PDT 24
Peak memory 305356 kb
Host smart-ba75a08b-ce69-4164-ae81-68e1b6fc1944
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467389504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.3467389504
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.2383534140
Short name T624
Test name
Test status
Simulation time 41708862738 ps
CPU time 1748.52 seconds
Started Jul 29 05:54:03 PM PDT 24
Finished Jul 29 06:23:11 PM PDT 24
Peak memory 289012 kb
Host smart-855edd80-5860-4415-b078-0693e9185e82
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383534140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.2383534140
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.916211751
Short name T635
Test name
Test status
Simulation time 85052407 ps
CPU time 11.29 seconds
Started Jul 29 05:53:57 PM PDT 24
Finished Jul 29 05:54:08 PM PDT 24
Peak memory 256020 kb
Host smart-fe619bfa-3777-4ee4-ad1f-5c7be370078a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91621
1751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.916211751
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.2323837049
Short name T713
Test name
Test status
Simulation time 374706474 ps
CPU time 31.23 seconds
Started Jul 29 05:53:57 PM PDT 24
Finished Jul 29 05:54:28 PM PDT 24
Peak memory 247888 kb
Host smart-0e404f92-1b96-447a-a42b-8254cc5cb2fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23238
37049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.2323837049
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.79172906
Short name T300
Test name
Test status
Simulation time 11013759574 ps
CPU time 738.75 seconds
Started Jul 29 05:54:02 PM PDT 24
Finished Jul 29 06:06:21 PM PDT 24
Peak memory 272712 kb
Host smart-35bb7289-b598-46fb-855f-971f03bc0e61
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79172906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.79172906
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.4205902414
Short name T390
Test name
Test status
Simulation time 98705130283 ps
CPU time 2039.44 seconds
Started Jul 29 05:54:03 PM PDT 24
Finished Jul 29 06:28:03 PM PDT 24
Peak memory 283388 kb
Host smart-60d576be-0979-42cb-85ba-bd1a25622102
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205902414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.4205902414
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.3717991201
Short name T311
Test name
Test status
Simulation time 41422613735 ps
CPU time 418.29 seconds
Started Jul 29 05:54:03 PM PDT 24
Finished Jul 29 06:01:02 PM PDT 24
Peak memory 248388 kb
Host smart-93ee4b06-70f9-48a3-aaa9-c1ad8f2590b0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717991201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.3717991201
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.3771865062
Short name T466
Test name
Test status
Simulation time 1079954047 ps
CPU time 13.03 seconds
Started Jul 29 05:53:58 PM PDT 24
Finished Jul 29 05:54:11 PM PDT 24
Peak memory 248348 kb
Host smart-6323710a-d497-4a73-be8f-f6aa7aab4a6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37718
65062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.3771865062
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.832528554
Short name T663
Test name
Test status
Simulation time 3295674646 ps
CPU time 51.73 seconds
Started Jul 29 05:53:58 PM PDT 24
Finished Jul 29 05:54:49 PM PDT 24
Peak memory 248100 kb
Host smart-7385ca4d-242e-48de-89f5-29e2b1ca4b20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83252
8554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.832528554
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.2794450925
Short name T15
Test name
Test status
Simulation time 1486956766 ps
CPU time 52.88 seconds
Started Jul 29 05:54:04 PM PDT 24
Finished Jul 29 05:54:57 PM PDT 24
Peak memory 248344 kb
Host smart-d5da1d03-d326-4d3e-8313-5cd1a36950af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27944
50925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.2794450925
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.1026568620
Short name T442
Test name
Test status
Simulation time 14699021978 ps
CPU time 62.09 seconds
Started Jul 29 05:53:58 PM PDT 24
Finished Jul 29 05:55:01 PM PDT 24
Peak memory 256540 kb
Host smart-adfed01d-86f0-440f-adea-9bf09a34b4f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10265
68620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.1026568620
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.273386961
Short name T306
Test name
Test status
Simulation time 30241014905 ps
CPU time 952.95 seconds
Started Jul 29 05:54:03 PM PDT 24
Finished Jul 29 06:09:56 PM PDT 24
Peak memory 282228 kb
Host smart-2f37a33e-083a-433b-a714-989c9f0e62cd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273386961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_han
dler_stress_all.273386961
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.4138154429
Short name T132
Test name
Test status
Simulation time 34394769575 ps
CPU time 2127.59 seconds
Started Jul 29 05:54:08 PM PDT 24
Finished Jul 29 06:29:36 PM PDT 24
Peak memory 272716 kb
Host smart-a7c1226e-a3b5-4bb0-8eb5-b0e3328ba822
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138154429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.4138154429
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.2716048819
Short name T475
Test name
Test status
Simulation time 3716858697 ps
CPU time 146.9 seconds
Started Jul 29 05:54:08 PM PDT 24
Finished Jul 29 05:56:35 PM PDT 24
Peak memory 256092 kb
Host smart-af86dfeb-0df0-403c-bf1d-79166fb87bdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27160
48819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.2716048819
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.1764160422
Short name T465
Test name
Test status
Simulation time 3454689990 ps
CPU time 52.46 seconds
Started Jul 29 05:54:08 PM PDT 24
Finished Jul 29 05:55:01 PM PDT 24
Peak memory 255900 kb
Host smart-8c1acf65-e654-42c5-8640-99341b68fe00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17641
60422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.1764160422
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.3628341476
Short name T360
Test name
Test status
Simulation time 43273890526 ps
CPU time 953.87 seconds
Started Jul 29 05:54:08 PM PDT 24
Finished Jul 29 06:10:02 PM PDT 24
Peak memory 272912 kb
Host smart-369855d5-6aa3-49b2-9204-bc6f2a66a53e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628341476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.3628341476
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.2770487312
Short name T507
Test name
Test status
Simulation time 7472044710 ps
CPU time 1093.72 seconds
Started Jul 29 05:54:15 PM PDT 24
Finished Jul 29 06:12:29 PM PDT 24
Peak memory 273048 kb
Host smart-4a1d1f0c-c0ab-47e2-8912-e21054a71e27
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770487312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.2770487312
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.3893858026
Short name T331
Test name
Test status
Simulation time 10897690401 ps
CPU time 249.35 seconds
Started Jul 29 05:54:08 PM PDT 24
Finished Jul 29 05:58:18 PM PDT 24
Peak memory 248312 kb
Host smart-daf5dc91-ec96-4088-aac0-a9e3643ff648
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893858026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.3893858026
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.3068734859
Short name T546
Test name
Test status
Simulation time 556275808 ps
CPU time 32.15 seconds
Started Jul 29 05:54:10 PM PDT 24
Finished Jul 29 05:54:42 PM PDT 24
Peak memory 248308 kb
Host smart-006d54d0-e04c-4fc0-bdae-ab0b23b9f48e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30687
34859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.3068734859
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.1556998358
Short name T623
Test name
Test status
Simulation time 559942856 ps
CPU time 38.85 seconds
Started Jul 29 05:54:08 PM PDT 24
Finished Jul 29 05:54:47 PM PDT 24
Peak memory 247800 kb
Host smart-b7cda4f5-d8c4-4c82-b1eb-941270b685b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15569
98358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.1556998358
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.3772105866
Short name T516
Test name
Test status
Simulation time 134412864 ps
CPU time 14.34 seconds
Started Jul 29 05:54:09 PM PDT 24
Finished Jul 29 05:54:23 PM PDT 24
Peak memory 248748 kb
Host smart-c43bce4e-37a7-4c0d-be15-9352f48cddc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37721
05866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.3772105866
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.1557839301
Short name T517
Test name
Test status
Simulation time 171675159 ps
CPU time 4.55 seconds
Started Jul 29 05:54:03 PM PDT 24
Finished Jul 29 05:54:08 PM PDT 24
Peak memory 248272 kb
Host smart-fccd5b37-4ecc-4195-ad07-4495464c9d2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15578
39301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.1557839301
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.2051389714
Short name T94
Test name
Test status
Simulation time 28356031137 ps
CPU time 1892.04 seconds
Started Jul 29 05:54:16 PM PDT 24
Finished Jul 29 06:25:48 PM PDT 24
Peak memory 289312 kb
Host smart-a57c39d1-ca19-40ac-892c-c324e79a93ba
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051389714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.2051389714
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.3551386483
Short name T123
Test name
Test status
Simulation time 19314614790 ps
CPU time 1365.7 seconds
Started Jul 29 05:54:19 PM PDT 24
Finished Jul 29 06:17:05 PM PDT 24
Peak memory 289288 kb
Host smart-aadf347b-b087-4d4c-bcd1-651c3cb358e3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551386483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.3551386483
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.804767236
Short name T707
Test name
Test status
Simulation time 1830920673 ps
CPU time 132.17 seconds
Started Jul 29 05:54:16 PM PDT 24
Finished Jul 29 05:56:28 PM PDT 24
Peak memory 256492 kb
Host smart-79aaf0f2-2a8f-4dbd-93b3-ff2d8036e199
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80476
7236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.804767236
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.3527607395
Short name T2
Test name
Test status
Simulation time 625436768 ps
CPU time 29.46 seconds
Started Jul 29 05:54:13 PM PDT 24
Finished Jul 29 05:54:43 PM PDT 24
Peak memory 248320 kb
Host smart-d8b253ec-597a-4f46-b22a-9942597dbc58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35276
07395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.3527607395
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.2324316041
Short name T595
Test name
Test status
Simulation time 86798896903 ps
CPU time 1559.54 seconds
Started Jul 29 05:54:21 PM PDT 24
Finished Jul 29 06:20:21 PM PDT 24
Peak memory 267852 kb
Host smart-cdf7e21d-4b5a-4eeb-a50e-e4fa9b0a15e2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324316041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.2324316041
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.743463826
Short name T312
Test name
Test status
Simulation time 36321859199 ps
CPU time 352.33 seconds
Started Jul 29 05:54:18 PM PDT 24
Finished Jul 29 06:00:10 PM PDT 24
Peak memory 256400 kb
Host smart-a78f1cef-9fda-4a46-971f-b9fa5a5afe13
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743463826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.743463826
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.1831160008
Short name T93
Test name
Test status
Simulation time 1139299685 ps
CPU time 33.1 seconds
Started Jul 29 05:54:14 PM PDT 24
Finished Jul 29 05:54:47 PM PDT 24
Peak memory 248368 kb
Host smart-ebecd7e4-4bbc-448d-91ac-d735a683a3ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18311
60008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.1831160008
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.1605295949
Short name T648
Test name
Test status
Simulation time 532451710 ps
CPU time 4.79 seconds
Started Jul 29 05:54:15 PM PDT 24
Finished Jul 29 05:54:20 PM PDT 24
Peak memory 239664 kb
Host smart-c8133581-4fec-4174-82f4-5d4c6daa6b99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16052
95949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.1605295949
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.597517137
Short name T634
Test name
Test status
Simulation time 72680183 ps
CPU time 4.2 seconds
Started Jul 29 05:54:15 PM PDT 24
Finished Jul 29 05:54:20 PM PDT 24
Peak memory 251168 kb
Host smart-5f28dff2-2c8f-4929-91ea-cba297099e22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59751
7137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.597517137
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.667458432
Short name T62
Test name
Test status
Simulation time 391064303 ps
CPU time 20.7 seconds
Started Jul 29 05:54:16 PM PDT 24
Finished Jul 29 05:54:37 PM PDT 24
Peak memory 248344 kb
Host smart-238f8e64-4729-4c8b-ace8-afbd27bf2258
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66745
8432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.667458432
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.2118856240
Short name T302
Test name
Test status
Simulation time 97760580840 ps
CPU time 1796.97 seconds
Started Jul 29 05:54:19 PM PDT 24
Finished Jul 29 06:24:17 PM PDT 24
Peak memory 289332 kb
Host smart-de098d46-c981-4804-a1bf-856c0585812d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118856240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.2118856240
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.1861342000
Short name T692
Test name
Test status
Simulation time 52186997584 ps
CPU time 2871.1 seconds
Started Jul 29 05:54:24 PM PDT 24
Finished Jul 29 06:42:16 PM PDT 24
Peak memory 287284 kb
Host smart-8f80254d-867e-46f0-abb6-ea245e3925c4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861342000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.1861342000
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.1292787380
Short name T37
Test name
Test status
Simulation time 635094324 ps
CPU time 24.17 seconds
Started Jul 29 05:54:26 PM PDT 24
Finished Jul 29 05:54:51 PM PDT 24
Peak memory 247840 kb
Host smart-b0f08371-a33b-4522-884b-a9213f80f9b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12927
87380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.1292787380
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.729723703
Short name T461
Test name
Test status
Simulation time 955818918 ps
CPU time 58.09 seconds
Started Jul 29 05:54:26 PM PDT 24
Finished Jul 29 05:55:24 PM PDT 24
Peak memory 248028 kb
Host smart-0d7be486-27df-4694-9f11-e86301bd4231
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72972
3703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.729723703
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.2101954824
Short name T333
Test name
Test status
Simulation time 35787163430 ps
CPU time 962.25 seconds
Started Jul 29 05:54:33 PM PDT 24
Finished Jul 29 06:10:36 PM PDT 24
Peak memory 272264 kb
Host smart-798b74f9-fb68-4350-8e01-cb19acf2c3c4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101954824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.2101954824
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.1934900373
Short name T112
Test name
Test status
Simulation time 49052053532 ps
CPU time 2171.67 seconds
Started Jul 29 05:54:30 PM PDT 24
Finished Jul 29 06:30:42 PM PDT 24
Peak memory 289264 kb
Host smart-b66970c6-991f-41ca-86a6-587d37557437
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934900373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.1934900373
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.122959044
Short name T328
Test name
Test status
Simulation time 26001367660 ps
CPU time 534.06 seconds
Started Jul 29 05:54:24 PM PDT 24
Finished Jul 29 06:03:18 PM PDT 24
Peak memory 248420 kb
Host smart-d222eb97-89c2-466d-a0ec-b8f986ada2ed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122959044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.122959044
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.3330023777
Short name T423
Test name
Test status
Simulation time 1831881051 ps
CPU time 14.36 seconds
Started Jul 29 05:54:20 PM PDT 24
Finished Jul 29 05:54:35 PM PDT 24
Peak memory 248280 kb
Host smart-c1e32a61-799a-47de-a327-14b305017200
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33300
23777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.3330023777
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.526727608
Short name T26
Test name
Test status
Simulation time 2568995315 ps
CPU time 22.5 seconds
Started Jul 29 05:54:20 PM PDT 24
Finished Jul 29 05:54:42 PM PDT 24
Peak memory 248436 kb
Host smart-9917afb0-fe52-4fa0-a070-96a9b7233325
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52672
7608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.526727608
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.2386258479
Short name T289
Test name
Test status
Simulation time 1158548948 ps
CPU time 45.84 seconds
Started Jul 29 05:54:26 PM PDT 24
Finished Jul 29 05:55:12 PM PDT 24
Peak memory 256068 kb
Host smart-d3644f51-23d5-4391-8a06-be70a81aaaaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23862
58479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.2386258479
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.2907652853
Short name T566
Test name
Test status
Simulation time 902273414 ps
CPU time 13.76 seconds
Started Jul 29 05:54:20 PM PDT 24
Finished Jul 29 05:54:34 PM PDT 24
Peak memory 248368 kb
Host smart-631c1618-af32-42e6-9066-7286028dfa5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29076
52853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.2907652853
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.1371178316
Short name T295
Test name
Test status
Simulation time 47815949209 ps
CPU time 2933.85 seconds
Started Jul 29 05:54:28 PM PDT 24
Finished Jul 29 06:43:22 PM PDT 24
Peak memory 297576 kb
Host smart-3748c591-db71-478d-bad0-9a8a8fd20cca
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371178316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.1371178316
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.1219501216
Short name T485
Test name
Test status
Simulation time 44760080495 ps
CPU time 4241.42 seconds
Started Jul 29 05:54:28 PM PDT 24
Finished Jul 29 07:05:09 PM PDT 24
Peak memory 305756 kb
Host smart-787089a9-43a9-4a36-a794-6d94769c7dcd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219501216 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.1219501216
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.680443324
Short name T224
Test name
Test status
Simulation time 49885708 ps
CPU time 4.12 seconds
Started Jul 29 05:51:01 PM PDT 24
Finished Jul 29 05:51:05 PM PDT 24
Peak memory 248636 kb
Host smart-55a0a2de-cd34-4781-8789-648e7796a833
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=680443324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.680443324
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.2252449967
Short name T301
Test name
Test status
Simulation time 11299565045 ps
CPU time 935.31 seconds
Started Jul 29 05:50:59 PM PDT 24
Finished Jul 29 06:06:35 PM PDT 24
Peak memory 272552 kb
Host smart-d31139ae-b516-40e2-b6ee-17f09b046ee6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252449967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.2252449967
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.1390350787
Short name T567
Test name
Test status
Simulation time 501572799 ps
CPU time 23.77 seconds
Started Jul 29 05:51:01 PM PDT 24
Finished Jul 29 05:51:25 PM PDT 24
Peak memory 248328 kb
Host smart-3850f43d-b040-46fc-b2bb-2191ee9684b3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1390350787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.1390350787
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.1161087336
Short name T603
Test name
Test status
Simulation time 8550107748 ps
CPU time 237.36 seconds
Started Jul 29 05:51:00 PM PDT 24
Finished Jul 29 05:54:57 PM PDT 24
Peak memory 256580 kb
Host smart-c7e743ac-622c-4f18-a192-c76bf207dffc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11610
87336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.1161087336
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.373008541
Short name T594
Test name
Test status
Simulation time 198225187 ps
CPU time 11.6 seconds
Started Jul 29 05:51:01 PM PDT 24
Finished Jul 29 05:51:13 PM PDT 24
Peak memory 248056 kb
Host smart-843ccdac-56d7-45dc-ad89-dd857c08754e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37300
8541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.373008541
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.539591966
Short name T694
Test name
Test status
Simulation time 22307013959 ps
CPU time 1381.63 seconds
Started Jul 29 05:51:01 PM PDT 24
Finished Jul 29 06:14:02 PM PDT 24
Peak memory 272264 kb
Host smart-93136791-03aa-42d8-834a-88950613b298
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539591966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.539591966
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.306548547
Short name T320
Test name
Test status
Simulation time 42019853060 ps
CPU time 464.46 seconds
Started Jul 29 05:51:01 PM PDT 24
Finished Jul 29 05:58:46 PM PDT 24
Peak memory 248388 kb
Host smart-6dbdfb07-5c44-4033-aad9-eb9427bce07b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306548547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.306548547
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.274506737
Short name T32
Test name
Test status
Simulation time 409943171 ps
CPU time 11.71 seconds
Started Jul 29 05:51:01 PM PDT 24
Finished Jul 29 05:51:12 PM PDT 24
Peak memory 254348 kb
Host smart-191b0249-2606-4512-ac30-ae7e0b6a778e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27450
6737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.274506737
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.21375906
Short name T615
Test name
Test status
Simulation time 1311848522 ps
CPU time 38.05 seconds
Started Jul 29 05:51:01 PM PDT 24
Finished Jul 29 05:51:39 PM PDT 24
Peak memory 248352 kb
Host smart-ec0d64c6-b14d-4f40-96b3-44b6cd9e47dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21375
906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.21375906
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.614113738
Short name T9
Test name
Test status
Simulation time 1719629061 ps
CPU time 26.55 seconds
Started Jul 29 05:51:02 PM PDT 24
Finished Jul 29 05:51:29 PM PDT 24
Peak memory 269908 kb
Host smart-a7610247-2338-4197-ba03-370a7a9890e6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=614113738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.614113738
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.4236586957
Short name T480
Test name
Test status
Simulation time 140313423 ps
CPU time 16.41 seconds
Started Jul 29 05:51:02 PM PDT 24
Finished Jul 29 05:51:18 PM PDT 24
Peak memory 255616 kb
Host smart-de60e715-dcf0-43d3-9fed-21ba13bee13f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42365
86957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.4236586957
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.4070744381
Short name T599
Test name
Test status
Simulation time 1324999327 ps
CPU time 46.24 seconds
Started Jul 29 05:51:04 PM PDT 24
Finished Jul 29 05:51:51 PM PDT 24
Peak memory 248324 kb
Host smart-bbeb85f9-1903-4423-9bd2-0a27ab7e9033
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40707
44381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.4070744381
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.521198923
Short name T637
Test name
Test status
Simulation time 39480428584 ps
CPU time 746.07 seconds
Started Jul 29 05:51:00 PM PDT 24
Finished Jul 29 06:03:26 PM PDT 24
Peak memory 272992 kb
Host smart-b5124a80-483b-4e0f-8062-86a86f522de5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521198923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_hand
ler_stress_all.521198923
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.314211794
Short name T568
Test name
Test status
Simulation time 14051903738 ps
CPU time 617.56 seconds
Started Jul 29 05:54:28 PM PDT 24
Finished Jul 29 06:04:46 PM PDT 24
Peak memory 271748 kb
Host smart-0c68d5b3-bf3c-425f-817f-5a8c4d5e50a1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314211794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.314211794
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.1852502437
Short name T388
Test name
Test status
Simulation time 80415080581 ps
CPU time 297.56 seconds
Started Jul 29 05:54:30 PM PDT 24
Finished Jul 29 05:59:28 PM PDT 24
Peak memory 255824 kb
Host smart-dd0ce24b-6de5-4db7-9447-4fbb4169b2aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18525
02437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.1852502437
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.586849969
Short name T590
Test name
Test status
Simulation time 94339549 ps
CPU time 4.06 seconds
Started Jul 29 05:54:32 PM PDT 24
Finished Jul 29 05:54:36 PM PDT 24
Peak memory 239764 kb
Host smart-5c4033e1-80d5-478c-9954-f3ec998c8654
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58684
9969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.586849969
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.3421098071
Short name T345
Test name
Test status
Simulation time 93955680791 ps
CPU time 1457.15 seconds
Started Jul 29 05:54:30 PM PDT 24
Finished Jul 29 06:18:48 PM PDT 24
Peak memory 272228 kb
Host smart-1ff15961-e40f-4301-8091-6adc84a78553
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421098071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.3421098071
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.2579295472
Short name T108
Test name
Test status
Simulation time 40471790344 ps
CPU time 2481.28 seconds
Started Jul 29 05:54:33 PM PDT 24
Finished Jul 29 06:35:55 PM PDT 24
Peak memory 284212 kb
Host smart-2cb01ec1-07ff-416e-863b-bfba374aeb7d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579295472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.2579295472
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.2610415781
Short name T610
Test name
Test status
Simulation time 1510631235 ps
CPU time 27.33 seconds
Started Jul 29 05:54:28 PM PDT 24
Finished Jul 29 05:54:56 PM PDT 24
Peak memory 248260 kb
Host smart-e81e557f-d62b-43df-9a28-dea94bf73a97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26104
15781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.2610415781
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.3911707244
Short name T304
Test name
Test status
Simulation time 835302517 ps
CPU time 46.81 seconds
Started Jul 29 05:54:27 PM PDT 24
Finished Jul 29 05:55:14 PM PDT 24
Peak memory 256480 kb
Host smart-4d198d17-c80a-4058-9900-b23519b48565
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39117
07244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.3911707244
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.4123368193
Short name T632
Test name
Test status
Simulation time 920299999 ps
CPU time 27.9 seconds
Started Jul 29 05:54:29 PM PDT 24
Finished Jul 29 05:54:57 PM PDT 24
Peak memory 248880 kb
Host smart-40d44bee-b10f-459d-a712-7375c0270a80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41233
68193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.4123368193
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.3139930815
Short name T672
Test name
Test status
Simulation time 577738029 ps
CPU time 25.87 seconds
Started Jul 29 05:54:30 PM PDT 24
Finished Jul 29 05:54:55 PM PDT 24
Peak memory 256476 kb
Host smart-29f4f72f-bfd7-44e8-9368-7fbab2582b80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31399
30815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.3139930815
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.1719510388
Short name T577
Test name
Test status
Simulation time 2067224978 ps
CPU time 114.57 seconds
Started Jul 29 05:54:28 PM PDT 24
Finished Jul 29 05:56:22 PM PDT 24
Peak memory 256724 kb
Host smart-1e014b02-edf0-4581-909c-03665e97975c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719510388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.1719510388
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.915491264
Short name T540
Test name
Test status
Simulation time 40778082677 ps
CPU time 2760.9 seconds
Started Jul 29 05:54:36 PM PDT 24
Finished Jul 29 06:40:38 PM PDT 24
Peak memory 288572 kb
Host smart-d5d4da09-3f80-4b30-826a-6b27e64b456f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915491264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.915491264
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.322722271
Short name T403
Test name
Test status
Simulation time 5353286856 ps
CPU time 105.3 seconds
Started Jul 29 05:54:35 PM PDT 24
Finished Jul 29 05:56:20 PM PDT 24
Peak memory 249404 kb
Host smart-127dbfb5-0596-4566-a9d0-50e3d57d2309
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32272
2271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.322722271
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.2008263148
Short name T528
Test name
Test status
Simulation time 83529589 ps
CPU time 3.88 seconds
Started Jul 29 05:54:34 PM PDT 24
Finished Jul 29 05:54:38 PM PDT 24
Peak memory 240084 kb
Host smart-90cfb4da-678e-45dc-9db8-ccc17ae3a4b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20082
63148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.2008263148
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.2690248921
Short name T200
Test name
Test status
Simulation time 190373931439 ps
CPU time 2577.25 seconds
Started Jul 29 05:54:40 PM PDT 24
Finished Jul 29 06:37:37 PM PDT 24
Peak memory 288788 kb
Host smart-4ccca589-3742-4d45-b915-057a21a42ecf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690248921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.2690248921
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.2600059182
Short name T292
Test name
Test status
Simulation time 38640703511 ps
CPU time 1169.42 seconds
Started Jul 29 05:54:39 PM PDT 24
Finished Jul 29 06:14:09 PM PDT 24
Peak memory 272928 kb
Host smart-83c3fb96-db53-4430-802f-86c6c3697711
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600059182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.2600059182
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.1157675411
Short name T335
Test name
Test status
Simulation time 33397758770 ps
CPU time 364.72 seconds
Started Jul 29 05:54:37 PM PDT 24
Finished Jul 29 06:00:42 PM PDT 24
Peak memory 248548 kb
Host smart-987d849a-54c9-4915-85c4-983eb444a650
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157675411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.1157675411
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.3310645793
Short name T562
Test name
Test status
Simulation time 58965304 ps
CPU time 8.57 seconds
Started Jul 29 05:54:33 PM PDT 24
Finished Jul 29 05:54:41 PM PDT 24
Peak memory 248352 kb
Host smart-cd61ede1-dffb-482d-b9e5-8c905d1870cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33106
45793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.3310645793
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.4178113543
Short name T551
Test name
Test status
Simulation time 241266154 ps
CPU time 24.2 seconds
Started Jul 29 05:54:31 PM PDT 24
Finished Jul 29 05:54:56 PM PDT 24
Peak memory 248112 kb
Host smart-4ec173a7-4090-41b0-bba6-1743ac10aaae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41781
13543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.4178113543
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.1680626833
Short name T273
Test name
Test status
Simulation time 537434793 ps
CPU time 33.65 seconds
Started Jul 29 05:54:34 PM PDT 24
Finished Jul 29 05:55:08 PM PDT 24
Peak memory 247880 kb
Host smart-ca3fd9b0-9869-4792-b5e4-45b56aebd5f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16806
26833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.1680626833
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.2600649784
Short name T473
Test name
Test status
Simulation time 1405088134 ps
CPU time 27.92 seconds
Started Jul 29 05:54:32 PM PDT 24
Finished Jul 29 05:55:00 PM PDT 24
Peak memory 248348 kb
Host smart-b62298e1-14cf-491b-983c-fbc136d80e90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26006
49784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.2600649784
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.3251205620
Short name T258
Test name
Test status
Simulation time 48076238075 ps
CPU time 1614.14 seconds
Started Jul 29 05:54:37 PM PDT 24
Finished Jul 29 06:21:31 PM PDT 24
Peak memory 289048 kb
Host smart-fab03f27-6f64-4864-849e-5cdaa0087904
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251205620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.3251205620
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all_with_rand_reset.1678440570
Short name T58
Test name
Test status
Simulation time 76386212046 ps
CPU time 4693.06 seconds
Started Jul 29 05:54:40 PM PDT 24
Finished Jul 29 07:12:54 PM PDT 24
Peak memory 353244 kb
Host smart-163495d9-12bb-4a04-b925-37f1130897c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678440570 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.alert_handler_stress_all_with_rand_reset.1678440570
Directory /workspace/41.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.4146423366
Short name T542
Test name
Test status
Simulation time 10089493939 ps
CPU time 1042.83 seconds
Started Jul 29 05:54:44 PM PDT 24
Finished Jul 29 06:12:07 PM PDT 24
Peak memory 281100 kb
Host smart-0674d023-b037-49eb-9381-eeffbe7b8a3d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146423366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.4146423366
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.3117768747
Short name T21
Test name
Test status
Simulation time 2309679256 ps
CPU time 131.59 seconds
Started Jul 29 05:54:41 PM PDT 24
Finished Jul 29 05:56:52 PM PDT 24
Peak memory 256176 kb
Host smart-69b8b1bc-6df8-4489-b3c9-456b2c9c6c8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31177
68747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.3117768747
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.3759636666
Short name T674
Test name
Test status
Simulation time 122620158 ps
CPU time 11.17 seconds
Started Jul 29 05:54:42 PM PDT 24
Finished Jul 29 05:54:54 PM PDT 24
Peak memory 254840 kb
Host smart-1ed21def-5db7-47e0-b690-3303d88e59c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37596
36666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.3759636666
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.2602375642
Short name T330
Test name
Test status
Simulation time 196137706843 ps
CPU time 2881.76 seconds
Started Jul 29 05:54:43 PM PDT 24
Finished Jul 29 06:42:46 PM PDT 24
Peak memory 281072 kb
Host smart-c26394cf-fce3-4234-a468-b9f21b49db2a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602375642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.2602375642
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.2420217734
Short name T439
Test name
Test status
Simulation time 71450695716 ps
CPU time 2203.37 seconds
Started Jul 29 05:54:42 PM PDT 24
Finished Jul 29 06:31:26 PM PDT 24
Peak memory 288528 kb
Host smart-57abc31b-9ae2-4fe8-a780-16ee04e46459
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420217734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.2420217734
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.49399885
Short name T691
Test name
Test status
Simulation time 22672327494 ps
CPU time 214.59 seconds
Started Jul 29 05:54:44 PM PDT 24
Finished Jul 29 05:58:18 PM PDT 24
Peak memory 248124 kb
Host smart-31c100f9-04c8-472c-bc55-cb831dcb0c36
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49399885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.49399885
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.2905480058
Short name T510
Test name
Test status
Simulation time 465488027 ps
CPU time 8.64 seconds
Started Jul 29 05:54:36 PM PDT 24
Finished Jul 29 05:54:45 PM PDT 24
Peak memory 250976 kb
Host smart-7e8a36ca-55a8-464e-bee0-cacaf062a7ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29054
80058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.2905480058
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.852037283
Short name T681
Test name
Test status
Simulation time 2396051611 ps
CPU time 42.97 seconds
Started Jul 29 05:54:38 PM PDT 24
Finished Jul 29 05:55:21 PM PDT 24
Peak memory 256452 kb
Host smart-5ee846c6-bce9-4821-a3d5-fbd4e57cf7e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85203
7283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.852037283
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.2197084842
Short name T452
Test name
Test status
Simulation time 5858254717 ps
CPU time 33.78 seconds
Started Jul 29 05:54:38 PM PDT 24
Finished Jul 29 05:55:12 PM PDT 24
Peak memory 256528 kb
Host smart-36aed961-75b2-4301-a10d-ba1acf4d9bb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21970
84842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.2197084842
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.2267179641
Short name T513
Test name
Test status
Simulation time 2848729573 ps
CPU time 114.89 seconds
Started Jul 29 05:54:43 PM PDT 24
Finished Jul 29 05:56:38 PM PDT 24
Peak memory 256548 kb
Host smart-8c4442ff-64e0-4e21-bd50-49cde5a0e01b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267179641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.2267179641
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all_with_rand_reset.2033865873
Short name T124
Test name
Test status
Simulation time 305236403865 ps
CPU time 5224.06 seconds
Started Jul 29 05:54:43 PM PDT 24
Finished Jul 29 07:21:48 PM PDT 24
Peak memory 305940 kb
Host smart-bc3fb957-d1cb-4bc2-b1b8-9818da3b850e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033865873 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.alert_handler_stress_all_with_rand_reset.2033865873
Directory /workspace/42.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.4166227061
Short name T702
Test name
Test status
Simulation time 157519082520 ps
CPU time 2315.66 seconds
Started Jul 29 05:54:48 PM PDT 24
Finished Jul 29 06:33:24 PM PDT 24
Peak memory 281768 kb
Host smart-f3228e25-4397-4e30-8e59-49e7d6ef0050
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166227061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.4166227061
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.3946355983
Short name T49
Test name
Test status
Simulation time 1368627112 ps
CPU time 18.9 seconds
Started Jul 29 05:54:50 PM PDT 24
Finished Jul 29 05:55:09 PM PDT 24
Peak memory 255756 kb
Host smart-9c47d9a9-5084-4dc2-8072-736e44abf1ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39463
55983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.3946355983
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.1263679036
Short name T70
Test name
Test status
Simulation time 673185447 ps
CPU time 17.4 seconds
Started Jul 29 05:54:47 PM PDT 24
Finished Jul 29 05:55:05 PM PDT 24
Peak memory 247808 kb
Host smart-04fac590-59ef-48e3-a150-c539c815d142
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12636
79036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.1263679036
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.2706639772
Short name T358
Test name
Test status
Simulation time 20937064474 ps
CPU time 1330.65 seconds
Started Jul 29 05:54:46 PM PDT 24
Finished Jul 29 06:16:57 PM PDT 24
Peak memory 272192 kb
Host smart-bf151efe-fd8f-4719-8aad-460c4c235d59
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706639772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.2706639772
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.1305797693
Short name T51
Test name
Test status
Simulation time 13199085603 ps
CPU time 1366.52 seconds
Started Jul 29 05:54:55 PM PDT 24
Finished Jul 29 06:17:42 PM PDT 24
Peak memory 288576 kb
Host smart-474b4ed3-5cf3-4c0d-bd28-4fd9743e1976
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305797693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.1305797693
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.3824148302
Short name T520
Test name
Test status
Simulation time 28442983136 ps
CPU time 370.81 seconds
Started Jul 29 05:54:49 PM PDT 24
Finished Jul 29 06:01:00 PM PDT 24
Peak memory 255272 kb
Host smart-a9f404e7-65e1-4c2d-bff9-42630f55a98e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824148302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.3824148302
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.893677173
Short name T236
Test name
Test status
Simulation time 9112503092 ps
CPU time 74.19 seconds
Started Jul 29 05:54:43 PM PDT 24
Finished Jul 29 05:55:58 PM PDT 24
Peak memory 248344 kb
Host smart-30f9ded2-d6e6-4d94-8c14-f5b1040b5ed4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89367
7173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.893677173
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.1648123735
Short name T553
Test name
Test status
Simulation time 216848774 ps
CPU time 15.83 seconds
Started Jul 29 05:54:42 PM PDT 24
Finished Jul 29 05:54:58 PM PDT 24
Peak memory 254452 kb
Host smart-1d493504-a095-44cb-b8c6-73bff37524f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16481
23735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.1648123735
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.1524104603
Short name T286
Test name
Test status
Simulation time 7636627845 ps
CPU time 56.17 seconds
Started Jul 29 05:54:48 PM PDT 24
Finished Jul 29 05:55:45 PM PDT 24
Peak memory 256524 kb
Host smart-678fdffd-f5c4-49a1-acf9-0bd8fdb57e4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15241
04603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.1524104603
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.848952105
Short name T617
Test name
Test status
Simulation time 53070253 ps
CPU time 9.85 seconds
Started Jul 29 05:54:45 PM PDT 24
Finished Jul 29 05:54:55 PM PDT 24
Peak memory 254224 kb
Host smart-4f31bc64-51cb-4fa4-9253-ea2116f1a382
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84895
2105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.848952105
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.3836215114
Short name T260
Test name
Test status
Simulation time 5315538110 ps
CPU time 333.92 seconds
Started Jul 29 05:54:54 PM PDT 24
Finished Jul 29 06:00:28 PM PDT 24
Peak memory 256536 kb
Host smart-6536e473-6b85-4cde-b5fe-67842f8855b6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836215114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.3836215114
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.2959751900
Short name T276
Test name
Test status
Simulation time 91754982683 ps
CPU time 5580.87 seconds
Started Jul 29 05:54:53 PM PDT 24
Finished Jul 29 07:27:55 PM PDT 24
Peak memory 322128 kb
Host smart-2f6c30db-b362-4eec-b0ea-c2d413d018d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959751900 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.2959751900
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.2075605190
Short name T578
Test name
Test status
Simulation time 72592642619 ps
CPU time 2025.74 seconds
Started Jul 29 05:54:53 PM PDT 24
Finished Jul 29 06:28:39 PM PDT 24
Peak memory 272904 kb
Host smart-845df136-9b04-4fd6-b07d-1bb9311feb3a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075605190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.2075605190
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.2288427252
Short name T667
Test name
Test status
Simulation time 4177108337 ps
CPU time 290.23 seconds
Started Jul 29 05:54:53 PM PDT 24
Finished Jul 29 05:59:43 PM PDT 24
Peak memory 256076 kb
Host smart-0734c98c-7e08-462e-9917-db63a3d79dcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22884
27252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.2288427252
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.1137318223
Short name T80
Test name
Test status
Simulation time 661722297 ps
CPU time 50.32 seconds
Started Jul 29 05:54:55 PM PDT 24
Finished Jul 29 05:55:46 PM PDT 24
Peak memory 248276 kb
Host smart-951978b7-239b-4d41-b323-21e889a76950
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11373
18223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.1137318223
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.1547245328
Short name T361
Test name
Test status
Simulation time 67381085049 ps
CPU time 1361.74 seconds
Started Jul 29 05:54:56 PM PDT 24
Finished Jul 29 06:17:38 PM PDT 24
Peak memory 288568 kb
Host smart-f22b257c-a143-4760-a814-c05af1074ec3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547245328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.1547245328
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.3117967134
Short name T405
Test name
Test status
Simulation time 81362785424 ps
CPU time 2580.1 seconds
Started Jul 29 05:54:59 PM PDT 24
Finished Jul 29 06:38:00 PM PDT 24
Peak memory 288540 kb
Host smart-e46baf97-4dd3-4639-b38f-15e3b8875408
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117967134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.3117967134
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.3963878783
Short name T396
Test name
Test status
Simulation time 1741422940 ps
CPU time 23.93 seconds
Started Jul 29 05:54:52 PM PDT 24
Finished Jul 29 05:55:16 PM PDT 24
Peak memory 255552 kb
Host smart-4d7d55b8-034d-4e05-b335-16acf0a7b76b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39638
78783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.3963878783
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.181753099
Short name T115
Test name
Test status
Simulation time 202225135 ps
CPU time 20.62 seconds
Started Jul 29 05:54:55 PM PDT 24
Finished Jul 29 05:55:15 PM PDT 24
Peak memory 248200 kb
Host smart-3f7c0550-2f56-4e8a-b910-5e8b88e2c625
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18175
3099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.181753099
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.2016928703
Short name T582
Test name
Test status
Simulation time 2098759541 ps
CPU time 41.4 seconds
Started Jul 29 05:54:54 PM PDT 24
Finished Jul 29 05:55:35 PM PDT 24
Peak memory 256492 kb
Host smart-a6de6089-ac78-449b-979f-1f3672f8e742
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20169
28703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.2016928703
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.1884286280
Short name T534
Test name
Test status
Simulation time 1929644185 ps
CPU time 29.39 seconds
Started Jul 29 05:54:54 PM PDT 24
Finished Jul 29 05:55:24 PM PDT 24
Peak memory 248500 kb
Host smart-d3696633-4f59-419e-b1c4-c73dd2a46072
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18842
86280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.1884286280
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.1365873033
Short name T492
Test name
Test status
Simulation time 111176469332 ps
CPU time 3163.02 seconds
Started Jul 29 05:55:00 PM PDT 24
Finished Jul 29 06:47:44 PM PDT 24
Peak memory 288852 kb
Host smart-45fbdee8-6c87-4c3c-a7bd-c308f2680cf0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365873033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.1365873033
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.3945856595
Short name T262
Test name
Test status
Simulation time 154964503560 ps
CPU time 3047.55 seconds
Started Jul 29 05:55:00 PM PDT 24
Finished Jul 29 06:45:48 PM PDT 24
Peak memory 321504 kb
Host smart-b648fae7-e6b2-4bef-b85e-33fb33a8ecdf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945856595 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.3945856595
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.3220456757
Short name T303
Test name
Test status
Simulation time 31915345280 ps
CPU time 2082.46 seconds
Started Jul 29 05:55:05 PM PDT 24
Finished Jul 29 06:29:48 PM PDT 24
Peak memory 286040 kb
Host smart-221c0210-74e7-4490-8944-d2916ed7369b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220456757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.3220456757
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.1008683148
Short name T515
Test name
Test status
Simulation time 6519595223 ps
CPU time 126.11 seconds
Started Jul 29 05:55:01 PM PDT 24
Finished Jul 29 05:57:07 PM PDT 24
Peak memory 256132 kb
Host smart-bbd67655-24b2-4eb1-a525-7cead227ffd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10086
83148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.1008683148
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.3993056203
Short name T77
Test name
Test status
Simulation time 1720959960 ps
CPU time 20.02 seconds
Started Jul 29 05:55:00 PM PDT 24
Finished Jul 29 05:55:20 PM PDT 24
Peak memory 254956 kb
Host smart-523cda07-15cc-4000-a259-3e5367326c4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39930
56203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.3993056203
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.3442401755
Short name T237
Test name
Test status
Simulation time 83142630582 ps
CPU time 2391.84 seconds
Started Jul 29 05:55:07 PM PDT 24
Finished Jul 29 06:35:00 PM PDT 24
Peak memory 288636 kb
Host smart-22c11617-1f69-4307-b624-8b08ce75aa9a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442401755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.3442401755
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.2706631087
Short name T402
Test name
Test status
Simulation time 248263063497 ps
CPU time 3350.73 seconds
Started Jul 29 05:55:07 PM PDT 24
Finished Jul 29 06:50:58 PM PDT 24
Peak memory 289056 kb
Host smart-f5a2dada-72b6-4bb6-b550-3123ec737069
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706631087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.2706631087
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.675250650
Short name T554
Test name
Test status
Simulation time 35387779500 ps
CPU time 474.85 seconds
Started Jul 29 05:55:06 PM PDT 24
Finished Jul 29 06:03:01 PM PDT 24
Peak memory 248416 kb
Host smart-24e1b9b3-0cee-4312-a23a-de24307c1f0f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675250650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.675250650
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.2750202461
Short name T89
Test name
Test status
Simulation time 211182181 ps
CPU time 14.45 seconds
Started Jul 29 05:54:59 PM PDT 24
Finished Jul 29 05:55:14 PM PDT 24
Peak memory 248356 kb
Host smart-728515fc-0d39-4d88-ac0e-e23eec5312f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27502
02461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.2750202461
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.3757546716
Short name T73
Test name
Test status
Simulation time 1178016553 ps
CPU time 16.68 seconds
Started Jul 29 05:55:00 PM PDT 24
Finished Jul 29 05:55:17 PM PDT 24
Peak memory 247864 kb
Host smart-ac56642d-9631-4d48-9478-afe67f5dda04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37575
46716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.3757546716
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.2688471701
Short name T604
Test name
Test status
Simulation time 391416593 ps
CPU time 19.14 seconds
Started Jul 29 05:55:00 PM PDT 24
Finished Jul 29 05:55:19 PM PDT 24
Peak memory 255896 kb
Host smart-810bec06-7197-4392-9456-3e85951b9862
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26884
71701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.2688471701
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.3026518527
Short name T454
Test name
Test status
Simulation time 650785181 ps
CPU time 14.61 seconds
Started Jul 29 05:55:00 PM PDT 24
Finished Jul 29 05:55:15 PM PDT 24
Peak memory 255304 kb
Host smart-99aa13a9-5973-4a2b-b4cb-5869326f649b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30265
18527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.3026518527
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.3380539633
Short name T261
Test name
Test status
Simulation time 63609081776 ps
CPU time 2332.99 seconds
Started Jul 29 05:55:05 PM PDT 24
Finished Jul 29 06:33:58 PM PDT 24
Peak memory 289372 kb
Host smart-a01dd09a-5725-46b7-b862-fc5d4be02fc5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380539633 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.3380539633
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.3134536214
Short name T451
Test name
Test status
Simulation time 33198786990 ps
CPU time 1534.79 seconds
Started Jul 29 05:55:12 PM PDT 24
Finished Jul 29 06:20:47 PM PDT 24
Peak memory 268064 kb
Host smart-ff426ae8-6d93-4ecd-a3ee-bdc809c07283
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134536214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.3134536214
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.787343864
Short name T383
Test name
Test status
Simulation time 1695194720 ps
CPU time 95.81 seconds
Started Jul 29 05:55:11 PM PDT 24
Finished Jul 29 05:56:47 PM PDT 24
Peak memory 255928 kb
Host smart-ec3b2b18-1ad6-478a-9c74-fd1431b3cb7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78734
3864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.787343864
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.2216441997
Short name T552
Test name
Test status
Simulation time 3825396911 ps
CPU time 46.48 seconds
Started Jul 29 05:55:11 PM PDT 24
Finished Jul 29 05:55:58 PM PDT 24
Peak memory 255344 kb
Host smart-df3740bf-a697-4683-a63d-940224732f58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22164
41997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.2216441997
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.1130822843
Short name T391
Test name
Test status
Simulation time 244103483514 ps
CPU time 2214.31 seconds
Started Jul 29 05:55:12 PM PDT 24
Finished Jul 29 06:32:07 PM PDT 24
Peak memory 287936 kb
Host smart-d1cea095-862d-4ec8-80be-e7f67fc4a07f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130822843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.1130822843
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.1565978424
Short name T587
Test name
Test status
Simulation time 486893628 ps
CPU time 10.26 seconds
Started Jul 29 05:55:11 PM PDT 24
Finished Jul 29 05:55:22 PM PDT 24
Peak memory 248468 kb
Host smart-030b31cd-55f1-4c36-b5a9-41488e218d80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15659
78424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.1565978424
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.2564980237
Short name T607
Test name
Test status
Simulation time 18461584 ps
CPU time 3.07 seconds
Started Jul 29 05:55:10 PM PDT 24
Finished Jul 29 05:55:14 PM PDT 24
Peak memory 239448 kb
Host smart-d9c5fd0f-b959-411e-b784-7d6218f20bb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25649
80237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.2564980237
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.915149680
Short name T536
Test name
Test status
Simulation time 588101038 ps
CPU time 30.71 seconds
Started Jul 29 05:55:11 PM PDT 24
Finished Jul 29 05:55:42 PM PDT 24
Peak memory 247720 kb
Host smart-c0770d0e-8e7f-44b3-b46e-349a67bbf9d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91514
9680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.915149680
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.3884865676
Short name T88
Test name
Test status
Simulation time 1101164080 ps
CPU time 36.33 seconds
Started Jul 29 05:55:05 PM PDT 24
Finished Jul 29 05:55:41 PM PDT 24
Peak memory 248524 kb
Host smart-186330ce-7000-490a-a23f-6f455c2162b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38848
65676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.3884865676
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all_with_rand_reset.1578797612
Short name T86
Test name
Test status
Simulation time 75204811916 ps
CPU time 1642.1 seconds
Started Jul 29 05:55:16 PM PDT 24
Finished Jul 29 06:22:38 PM PDT 24
Peak memory 305020 kb
Host smart-8624d197-0475-4dcd-b944-cb89bac0f960
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578797612 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.alert_handler_stress_all_with_rand_reset.1578797612
Directory /workspace/46.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.3489365988
Short name T544
Test name
Test status
Simulation time 2135665296 ps
CPU time 74.82 seconds
Started Jul 29 05:55:16 PM PDT 24
Finished Jul 29 05:56:31 PM PDT 24
Peak memory 256276 kb
Host smart-c9cf4901-caa2-42e4-8ffd-4263180345c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34893
65988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.3489365988
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.2501296723
Short name T711
Test name
Test status
Simulation time 192068563 ps
CPU time 7.16 seconds
Started Jul 29 05:55:17 PM PDT 24
Finished Jul 29 05:55:24 PM PDT 24
Peak memory 247872 kb
Host smart-0f3e0824-1fe6-49dd-ab12-288c53dad242
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25012
96723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.2501296723
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.293025217
Short name T348
Test name
Test status
Simulation time 49856506704 ps
CPU time 2822.16 seconds
Started Jul 29 05:55:27 PM PDT 24
Finished Jul 29 06:42:29 PM PDT 24
Peak memory 281068 kb
Host smart-234e30e4-bc1b-438f-9d1c-3a8a4b27c17e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293025217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.293025217
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.3999639963
Short name T524
Test name
Test status
Simulation time 19735207535 ps
CPU time 1221.48 seconds
Started Jul 29 05:55:23 PM PDT 24
Finished Jul 29 06:15:45 PM PDT 24
Peak memory 284996 kb
Host smart-298d66ab-3c4f-45f1-84dc-be62015614a7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999639963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.3999639963
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.3167273719
Short name T1
Test name
Test status
Simulation time 4856997653 ps
CPU time 146.42 seconds
Started Jul 29 05:55:22 PM PDT 24
Finished Jul 29 05:57:48 PM PDT 24
Peak memory 248248 kb
Host smart-6d951689-1bde-4b36-bafc-7460426b80cb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167273719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.3167273719
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.4111394257
Short name T55
Test name
Test status
Simulation time 216143305 ps
CPU time 12.11 seconds
Started Jul 29 05:55:16 PM PDT 24
Finished Jul 29 05:55:28 PM PDT 24
Peak memory 248352 kb
Host smart-5f459c59-c391-49e6-8a6b-0b24f93fc265
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41113
94257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.4111394257
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.3244601978
Short name T47
Test name
Test status
Simulation time 408586689 ps
CPU time 22.85 seconds
Started Jul 29 05:55:18 PM PDT 24
Finished Jul 29 05:55:41 PM PDT 24
Peak memory 247576 kb
Host smart-9bc10e00-d224-4b66-afc1-a5f7ddd70b7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32446
01978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.3244601978
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.2767394912
Short name T282
Test name
Test status
Simulation time 368174323 ps
CPU time 27.18 seconds
Started Jul 29 05:55:20 PM PDT 24
Finished Jul 29 05:55:48 PM PDT 24
Peak memory 256032 kb
Host smart-38ce36c4-327b-4a4f-ace1-8b59c8d9565b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27673
94912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.2767394912
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.3116469327
Short name T696
Test name
Test status
Simulation time 47503943 ps
CPU time 2.76 seconds
Started Jul 29 05:55:19 PM PDT 24
Finished Jul 29 05:55:22 PM PDT 24
Peak memory 248496 kb
Host smart-5bf61fcd-aab2-4076-b27b-40c6687cfb8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31164
69327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.3116469327
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.2322606194
Short name T263
Test name
Test status
Simulation time 124068075589 ps
CPU time 3778.59 seconds
Started Jul 29 05:55:22 PM PDT 24
Finished Jul 29 06:58:21 PM PDT 24
Peak memory 305120 kb
Host smart-f5b745dd-5a45-4ff2-a558-9b1d164755e1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322606194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.2322606194
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.2978896721
Short name T217
Test name
Test status
Simulation time 8032173963 ps
CPU time 857.45 seconds
Started Jul 29 05:55:21 PM PDT 24
Finished Jul 29 06:09:39 PM PDT 24
Peak memory 287504 kb
Host smart-3ab68e07-cd83-4185-aebe-19ebb2a811ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978896721 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.2978896721
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.2231866759
Short name T509
Test name
Test status
Simulation time 81513852166 ps
CPU time 1287.11 seconds
Started Jul 29 05:55:30 PM PDT 24
Finished Jul 29 06:16:57 PM PDT 24
Peak memory 272304 kb
Host smart-30d90c25-6c84-4000-af3c-49f8dd4c6b38
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231866759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.2231866759
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.564641549
Short name T447
Test name
Test status
Simulation time 3888590339 ps
CPU time 229.8 seconds
Started Jul 29 05:55:24 PM PDT 24
Finished Jul 29 05:59:14 PM PDT 24
Peak memory 256056 kb
Host smart-7b1826fd-dd32-461f-bcbb-0ca3e42ac6f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56464
1549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.564641549
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.3003688021
Short name T671
Test name
Test status
Simulation time 135854428 ps
CPU time 8 seconds
Started Jul 29 05:55:22 PM PDT 24
Finished Jul 29 05:55:30 PM PDT 24
Peak memory 252948 kb
Host smart-7607df13-3c8d-40d6-887a-64d53af8a3f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30036
88021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.3003688021
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.1103953482
Short name T612
Test name
Test status
Simulation time 18701425676 ps
CPU time 1165.25 seconds
Started Jul 29 05:55:29 PM PDT 24
Finished Jul 29 06:14:54 PM PDT 24
Peak memory 271936 kb
Host smart-2f082016-5a0d-45d1-a050-517af85434d9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103953482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.1103953482
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.2216181466
Short name T92
Test name
Test status
Simulation time 48368461423 ps
CPU time 1864.72 seconds
Started Jul 29 05:55:30 PM PDT 24
Finished Jul 29 06:26:35 PM PDT 24
Peak memory 281980 kb
Host smart-3683ee16-013c-4b6d-ab1a-87225f19532d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216181466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.2216181466
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.2351870059
Short name T326
Test name
Test status
Simulation time 4477710962 ps
CPU time 189.03 seconds
Started Jul 29 05:55:29 PM PDT 24
Finished Jul 29 05:58:38 PM PDT 24
Peak memory 248388 kb
Host smart-7e247c5b-d97a-4dbc-818d-e3c9ee5479a9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351870059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.2351870059
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.2368643968
Short name T646
Test name
Test status
Simulation time 204953384 ps
CPU time 4.99 seconds
Started Jul 29 05:55:22 PM PDT 24
Finished Jul 29 05:55:27 PM PDT 24
Peak memory 248280 kb
Host smart-9c12a07e-be01-4fc0-84b8-56c9c64a3f3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23686
43968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.2368643968
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.2026642389
Short name T40
Test name
Test status
Simulation time 157016293 ps
CPU time 10.86 seconds
Started Jul 29 05:55:21 PM PDT 24
Finished Jul 29 05:55:32 PM PDT 24
Peak memory 247640 kb
Host smart-34d2cc55-6cba-41b6-b217-5d0fedc9ae1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20266
42389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.2026642389
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.1359434777
Short name T449
Test name
Test status
Simulation time 9717619974 ps
CPU time 57.71 seconds
Started Jul 29 05:55:21 PM PDT 24
Finished Jul 29 05:56:19 PM PDT 24
Peak memory 255500 kb
Host smart-98122cf2-ed56-4051-bfe0-d2991f4cdca3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13594
34777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.1359434777
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.4098787956
Short name T550
Test name
Test status
Simulation time 681017306 ps
CPU time 19.62 seconds
Started Jul 29 05:55:23 PM PDT 24
Finished Jul 29 05:55:42 PM PDT 24
Peak memory 256536 kb
Host smart-a4412e0d-22dc-4e76-8acc-4a633a99aaf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40987
87956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.4098787956
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all_with_rand_reset.2685317162
Short name T118
Test name
Test status
Simulation time 50842637406 ps
CPU time 1786.92 seconds
Started Jul 29 05:55:27 PM PDT 24
Finished Jul 29 06:25:14 PM PDT 24
Peak memory 289368 kb
Host smart-9b260f96-8f51-4dda-b67a-2bdfaabf55bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685317162 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.alert_handler_stress_all_with_rand_reset.2685317162
Directory /workspace/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.2714833088
Short name T584
Test name
Test status
Simulation time 30973275690 ps
CPU time 1765.79 seconds
Started Jul 29 05:55:35 PM PDT 24
Finished Jul 29 06:25:01 PM PDT 24
Peak memory 272944 kb
Host smart-5f38bdcb-f11c-46b9-8bba-f08e4e315c5b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714833088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.2714833088
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.4002470675
Short name T527
Test name
Test status
Simulation time 210245153 ps
CPU time 21.36 seconds
Started Jul 29 05:55:29 PM PDT 24
Finished Jul 29 05:55:51 PM PDT 24
Peak memory 248288 kb
Host smart-7791d80a-a8df-42e0-9ecd-98a189a96dea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40024
70675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.4002470675
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.3533600773
Short name T633
Test name
Test status
Simulation time 166578202252 ps
CPU time 3247.32 seconds
Started Jul 29 05:55:34 PM PDT 24
Finished Jul 29 06:49:42 PM PDT 24
Peak memory 288604 kb
Host smart-ac3891dd-46e0-4295-b59e-c0220cc6d48f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533600773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.3533600773
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.4250252541
Short name T606
Test name
Test status
Simulation time 8665024535 ps
CPU time 735.77 seconds
Started Jul 29 05:55:35 PM PDT 24
Finished Jul 29 06:07:50 PM PDT 24
Peak memory 271196 kb
Host smart-df9767ab-1b92-4bcd-beb8-6221e4f10245
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250252541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.4250252541
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.36045644
Short name T18
Test name
Test status
Simulation time 42198952386 ps
CPU time 443.9 seconds
Started Jul 29 05:55:33 PM PDT 24
Finished Jul 29 06:02:58 PM PDT 24
Peak memory 248392 kb
Host smart-1dddeb0d-ac5b-4154-9d55-eacb7c79ebd3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36045644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.36045644
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.869952173
Short name T710
Test name
Test status
Simulation time 126433190 ps
CPU time 5.19 seconds
Started Jul 29 05:55:30 PM PDT 24
Finished Jul 29 05:55:35 PM PDT 24
Peak memory 240088 kb
Host smart-d0bc5e70-158d-4c5a-b2f6-bad66554d98a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86995
2173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.869952173
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.2367274747
Short name T138
Test name
Test status
Simulation time 421931836 ps
CPU time 24.58 seconds
Started Jul 29 05:55:28 PM PDT 24
Finished Jul 29 05:55:52 PM PDT 24
Peak memory 247848 kb
Host smart-dafe0e36-b2a6-4bc5-a1ff-5270224fa343
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23672
74747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.2367274747
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.1677982564
Short name T563
Test name
Test status
Simulation time 761657412 ps
CPU time 32.03 seconds
Started Jul 29 05:55:32 PM PDT 24
Finished Jul 29 05:56:04 PM PDT 24
Peak memory 248312 kb
Host smart-42c556ba-1a00-4123-8735-f5a8a1c7ab68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16779
82564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.1677982564
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.3094872882
Short name T631
Test name
Test status
Simulation time 5361171146 ps
CPU time 36.18 seconds
Started Jul 29 05:55:29 PM PDT 24
Finished Jul 29 05:56:05 PM PDT 24
Peak memory 256424 kb
Host smart-f83922e9-7df2-4077-a792-60b42542cc7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30948
72882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.3094872882
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.3200567256
Short name T228
Test name
Test status
Simulation time 45468329 ps
CPU time 3.83 seconds
Started Jul 29 05:51:06 PM PDT 24
Finished Jul 29 05:51:10 PM PDT 24
Peak memory 248576 kb
Host smart-457adc82-5961-49d6-9eca-a1b5e27f50c2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3200567256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.3200567256
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.2142738653
Short name T476
Test name
Test status
Simulation time 49985874584 ps
CPU time 1226.34 seconds
Started Jul 29 05:51:05 PM PDT 24
Finished Jul 29 06:11:32 PM PDT 24
Peak memory 288568 kb
Host smart-e4df83e1-7b17-4173-9ca3-c737079d1167
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142738653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.2142738653
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.3544379682
Short name T394
Test name
Test status
Simulation time 5558860014 ps
CPU time 56.86 seconds
Started Jul 29 05:51:07 PM PDT 24
Finished Jul 29 05:52:03 PM PDT 24
Peak memory 248388 kb
Host smart-502f8a0c-ec75-47da-a133-a63a1eeb88c8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3544379682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.3544379682
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.1044953983
Short name T597
Test name
Test status
Simulation time 4297211133 ps
CPU time 71.8 seconds
Started Jul 29 05:50:59 PM PDT 24
Finished Jul 29 05:52:11 PM PDT 24
Peak memory 255916 kb
Host smart-00806499-3746-4595-8df6-db6a944368bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10449
53983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.1044953983
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.1034026236
Short name T535
Test name
Test status
Simulation time 511406476 ps
CPU time 19.78 seconds
Started Jul 29 05:51:01 PM PDT 24
Finished Jul 29 05:51:21 PM PDT 24
Peak memory 255936 kb
Host smart-29e720ca-0847-4157-ba12-d7bebb445a60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10340
26236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.1034026236
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.3990321211
Short name T341
Test name
Test status
Simulation time 146031100606 ps
CPU time 2080.29 seconds
Started Jul 29 05:51:04 PM PDT 24
Finished Jul 29 06:25:45 PM PDT 24
Peak memory 272856 kb
Host smart-e7163f23-3877-4818-8221-404eb45eb208
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990321211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.3990321211
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.1981121618
Short name T417
Test name
Test status
Simulation time 48038974328 ps
CPU time 1842.03 seconds
Started Jul 29 05:51:07 PM PDT 24
Finished Jul 29 06:21:49 PM PDT 24
Peak memory 272984 kb
Host smart-a7e62a73-e7be-4754-939f-7c8cb34936fb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981121618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.1981121618
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.1794366350
Short name T315
Test name
Test status
Simulation time 17370575017 ps
CPU time 372.6 seconds
Started Jul 29 05:51:08 PM PDT 24
Finished Jul 29 05:57:21 PM PDT 24
Peak memory 248224 kb
Host smart-8ec3b2dd-38b7-4eb2-b1c9-67826bc7f2d2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794366350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.1794366350
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.370955158
Short name T12
Test name
Test status
Simulation time 1282488705 ps
CPU time 25.14 seconds
Started Jul 29 05:51:00 PM PDT 24
Finished Jul 29 05:51:25 PM PDT 24
Peak memory 248372 kb
Host smart-124292af-096a-46ad-a105-cc5371165fa2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37095
5158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.370955158
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.3939094743
Short name T678
Test name
Test status
Simulation time 584742052 ps
CPU time 17.66 seconds
Started Jul 29 05:51:01 PM PDT 24
Finished Jul 29 05:51:18 PM PDT 24
Peak memory 255452 kb
Host smart-5677b89b-ce97-4c0c-997c-6a85bf480b50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39390
94743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.3939094743
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.4082664726
Short name T338
Test name
Test status
Simulation time 1165915845 ps
CPU time 29.48 seconds
Started Jul 29 05:51:01 PM PDT 24
Finished Jul 29 05:51:30 PM PDT 24
Peak memory 256292 kb
Host smart-c8363d5e-ad64-4d17-b10c-ba4833ac8822
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40826
64726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.4082664726
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.917967283
Short name T596
Test name
Test status
Simulation time 540545148 ps
CPU time 20.46 seconds
Started Jul 29 05:51:03 PM PDT 24
Finished Jul 29 05:51:23 PM PDT 24
Peak memory 256508 kb
Host smart-49f73703-c24c-497b-aea0-4ebf81dcb9c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91796
7283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.917967283
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.3570265292
Short name T275
Test name
Test status
Simulation time 27576072211 ps
CPU time 1631.1 seconds
Started Jul 29 05:51:07 PM PDT 24
Finished Jul 29 06:18:18 PM PDT 24
Peak memory 298492 kb
Host smart-f8e5e079-d32b-4802-95bc-adb9d5364070
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570265292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.3570265292
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.3532919331
Short name T67
Test name
Test status
Simulation time 84475026 ps
CPU time 3.28 seconds
Started Jul 29 05:51:11 PM PDT 24
Finished Jul 29 05:51:14 PM PDT 24
Peak memory 248540 kb
Host smart-5e0347c2-a8b2-4378-b763-5f56a683576d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3532919331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.3532919331
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.892840880
Short name T489
Test name
Test status
Simulation time 449593728016 ps
CPU time 3590.61 seconds
Started Jul 29 05:51:10 PM PDT 24
Finished Jul 29 06:51:01 PM PDT 24
Peak memory 288312 kb
Host smart-77a2cb63-f818-4191-8c54-2c24b67a7839
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892840880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.892840880
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.3053652242
Short name T455
Test name
Test status
Simulation time 1293717544 ps
CPU time 16.15 seconds
Started Jul 29 05:51:11 PM PDT 24
Finished Jul 29 05:51:27 PM PDT 24
Peak memory 248312 kb
Host smart-6bab9ce8-4eca-48a4-aa90-97c5311bf573
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3053652242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.3053652242
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.1874946480
Short name T111
Test name
Test status
Simulation time 3693524062 ps
CPU time 222.27 seconds
Started Jul 29 05:51:11 PM PDT 24
Finished Jul 29 05:54:53 PM PDT 24
Peak memory 251616 kb
Host smart-509fcec8-c2ff-430b-9c45-b9c4e6c69098
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18749
46480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.1874946480
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.3080634205
Short name T662
Test name
Test status
Simulation time 72246071 ps
CPU time 4.72 seconds
Started Jul 29 05:51:12 PM PDT 24
Finished Jul 29 05:51:17 PM PDT 24
Peak memory 240124 kb
Host smart-7bdf9c3c-3592-41f7-89f3-7bb2efb53f9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30806
34205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.3080634205
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.139579837
Short name T308
Test name
Test status
Simulation time 38564746298 ps
CPU time 1819.37 seconds
Started Jul 29 05:51:10 PM PDT 24
Finished Jul 29 06:21:29 PM PDT 24
Peak memory 288396 kb
Host smart-bb005114-c75d-4b6e-a605-c8972e5bc052
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139579837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.139579837
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.2696421722
Short name T593
Test name
Test status
Simulation time 588548564080 ps
CPU time 1689.65 seconds
Started Jul 29 05:51:12 PM PDT 24
Finished Jul 29 06:19:22 PM PDT 24
Peak memory 272572 kb
Host smart-78eb7790-a97d-4364-87f1-945a987f9cee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696421722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.2696421722
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.3619302116
Short name T17
Test name
Test status
Simulation time 34732199507 ps
CPU time 172.49 seconds
Started Jul 29 05:51:11 PM PDT 24
Finished Jul 29 05:54:04 PM PDT 24
Peak memory 248384 kb
Host smart-53ab0cda-7c84-4c42-9889-063664efc97d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619302116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.3619302116
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.325423063
Short name T444
Test name
Test status
Simulation time 17213462 ps
CPU time 2.98 seconds
Started Jul 29 05:51:08 PM PDT 24
Finished Jul 29 05:51:11 PM PDT 24
Peak memory 248336 kb
Host smart-c294859e-0078-4341-9ea1-2d4952bc807e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32542
3063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.325423063
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.1374512064
Short name T689
Test name
Test status
Simulation time 823880845 ps
CPU time 21.31 seconds
Started Jul 29 05:51:12 PM PDT 24
Finished Jul 29 05:51:34 PM PDT 24
Peak memory 255988 kb
Host smart-01783c9a-6ff8-490e-8ab2-3711331ff44a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13745
12064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.1374512064
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.993826700
Short name T285
Test name
Test status
Simulation time 675739252 ps
CPU time 20.25 seconds
Started Jul 29 05:51:10 PM PDT 24
Finished Jul 29 05:51:31 PM PDT 24
Peak memory 247896 kb
Host smart-5b8c3f89-8ca1-4a78-9c34-d43586333d07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99382
6700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.993826700
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.4022183709
Short name T518
Test name
Test status
Simulation time 221118305 ps
CPU time 7.42 seconds
Started Jul 29 05:51:06 PM PDT 24
Finished Jul 29 05:51:14 PM PDT 24
Peak memory 248352 kb
Host smart-2c2be4e7-2832-4e98-8585-97e66a5b788c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40221
83709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.4022183709
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.3371458382
Short name T714
Test name
Test status
Simulation time 306687400416 ps
CPU time 4862.12 seconds
Started Jul 29 05:51:12 PM PDT 24
Finished Jul 29 07:12:14 PM PDT 24
Peak memory 304468 kb
Host smart-3a1e2b91-5f0e-4b4e-a328-61f8405eb43a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371458382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.3371458382
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.1609866894
Short name T299
Test name
Test status
Simulation time 65322392720 ps
CPU time 1945.38 seconds
Started Jul 29 05:51:12 PM PDT 24
Finished Jul 29 06:23:38 PM PDT 24
Peak memory 304868 kb
Host smart-9f6a2fa6-d205-4969-b802-d9c569537906
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609866894 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.1609866894
Directory /workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.1411454199
Short name T233
Test name
Test status
Simulation time 77151634 ps
CPU time 3.64 seconds
Started Jul 29 05:51:16 PM PDT 24
Finished Jul 29 05:51:20 PM PDT 24
Peak memory 248704 kb
Host smart-5bf911b7-a46c-458a-9d10-79e947e9f19d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1411454199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.1411454199
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.3528514138
Short name T424
Test name
Test status
Simulation time 189292048 ps
CPU time 6.4 seconds
Started Jul 29 05:51:15 PM PDT 24
Finished Jul 29 05:51:21 PM PDT 24
Peak memory 248280 kb
Host smart-c396c650-3c13-47b1-97c3-c46f1bf1112f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3528514138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.3528514138
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.1524391298
Short name T673
Test name
Test status
Simulation time 2874103104 ps
CPU time 166.8 seconds
Started Jul 29 05:51:12 PM PDT 24
Finished Jul 29 05:53:59 PM PDT 24
Peak memory 256608 kb
Host smart-dcfed21b-ec9c-4805-b362-7afd9b61da7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15243
91298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.1524391298
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.3595958085
Short name T532
Test name
Test status
Simulation time 746060904 ps
CPU time 12.07 seconds
Started Jul 29 05:51:10 PM PDT 24
Finished Jul 29 05:51:22 PM PDT 24
Peak memory 248288 kb
Host smart-5db83ddc-4d88-46c0-87a7-4a1f82980525
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35959
58085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.3595958085
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.2297555748
Short name T321
Test name
Test status
Simulation time 142701067466 ps
CPU time 1979.08 seconds
Started Jul 29 05:51:15 PM PDT 24
Finished Jul 29 06:24:15 PM PDT 24
Peak memory 272696 kb
Host smart-aae6adce-730d-4dcb-99c7-ba7474c3d5d5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297555748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.2297555748
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.2220458379
Short name T649
Test name
Test status
Simulation time 36673608856 ps
CPU time 2241.74 seconds
Started Jul 29 05:51:16 PM PDT 24
Finished Jul 29 06:28:38 PM PDT 24
Peak memory 288232 kb
Host smart-9db22218-6da3-4a0b-808b-93c784adff54
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220458379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.2220458379
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.3667425692
Short name T600
Test name
Test status
Simulation time 7724202456 ps
CPU time 309.97 seconds
Started Jul 29 05:51:19 PM PDT 24
Finished Jul 29 05:56:29 PM PDT 24
Peak memory 248144 kb
Host smart-a353f33a-214e-47cb-8845-f7dbe87b249f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667425692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.3667425692
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.3798939543
Short name T548
Test name
Test status
Simulation time 574833616 ps
CPU time 40.86 seconds
Started Jul 29 05:51:10 PM PDT 24
Finished Jul 29 05:51:51 PM PDT 24
Peak memory 248372 kb
Host smart-3d60bd56-4722-4234-a9a3-c36655fa385a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37989
39543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.3798939543
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.2207922339
Short name T574
Test name
Test status
Simulation time 133783123 ps
CPU time 13.22 seconds
Started Jul 29 05:51:12 PM PDT 24
Finished Jul 29 05:51:26 PM PDT 24
Peak memory 256176 kb
Host smart-9c8c072e-382e-4d5a-9b61-e6cb9c24c744
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22079
22339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.2207922339
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.1232305326
Short name T629
Test name
Test status
Simulation time 186186930 ps
CPU time 6.27 seconds
Started Jul 29 05:51:15 PM PDT 24
Finished Jul 29 05:51:21 PM PDT 24
Peak memory 248228 kb
Host smart-7c1387ab-ecf1-437b-9b76-d08898e9d290
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12323
05326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.1232305326
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.2638371686
Short name T63
Test name
Test status
Simulation time 7420623227 ps
CPU time 36.86 seconds
Started Jul 29 05:51:11 PM PDT 24
Finished Jul 29 05:51:48 PM PDT 24
Peak memory 255532 kb
Host smart-f3914b2e-2e7d-4825-a97f-b484971d6b3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26383
71686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.2638371686
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.560941440
Short name T647
Test name
Test status
Simulation time 23498809381 ps
CPU time 327.86 seconds
Started Jul 29 05:51:15 PM PDT 24
Finished Jul 29 05:56:43 PM PDT 24
Peak memory 254532 kb
Host smart-0d37f9fa-4b16-40ad-be32-f070175e51c3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560941440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_hand
ler_stress_all.560941440
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.1289213725
Short name T701
Test name
Test status
Simulation time 15147045011 ps
CPU time 1575.27 seconds
Started Jul 29 05:51:15 PM PDT 24
Finished Jul 29 06:17:30 PM PDT 24
Peak memory 297276 kb
Host smart-03750d8c-f5d3-433a-8284-7aa80e60ff8e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289213725 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.1289213725
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.1756804666
Short name T229
Test name
Test status
Simulation time 76332381 ps
CPU time 3.54 seconds
Started Jul 29 05:51:14 PM PDT 24
Finished Jul 29 05:51:18 PM PDT 24
Peak memory 248656 kb
Host smart-86589629-8566-4902-95d0-a70956b6bd28
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1756804666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.1756804666
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.3296148177
Short name T616
Test name
Test status
Simulation time 21769777101 ps
CPU time 1441.6 seconds
Started Jul 29 05:51:15 PM PDT 24
Finished Jul 29 06:15:17 PM PDT 24
Peak memory 271900 kb
Host smart-f6aed4f9-3624-48ae-9690-0f0681a90b26
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296148177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.3296148177
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.2706631587
Short name T676
Test name
Test status
Simulation time 977518008 ps
CPU time 40.91 seconds
Started Jul 29 05:51:15 PM PDT 24
Finished Jul 29 05:51:56 PM PDT 24
Peak memory 248320 kb
Host smart-46e7634c-3c61-43a5-8c3b-7173c3fda93d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2706631587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.2706631587
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.2170450894
Short name T130
Test name
Test status
Simulation time 23884319707 ps
CPU time 294.73 seconds
Started Jul 29 05:51:16 PM PDT 24
Finished Jul 29 05:56:11 PM PDT 24
Peak memory 255816 kb
Host smart-2679832b-04fa-4a25-a7cb-c950d10babee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21704
50894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.2170450894
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.2835030240
Short name T133
Test name
Test status
Simulation time 1290006245 ps
CPU time 35.2 seconds
Started Jul 29 05:51:21 PM PDT 24
Finished Jul 29 05:51:56 PM PDT 24
Peak memory 256480 kb
Host smart-da64185c-6534-44f8-87ae-02a8515e2f4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28350
30240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.2835030240
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.3381412223
Short name T573
Test name
Test status
Simulation time 10320648719 ps
CPU time 835.54 seconds
Started Jul 29 05:51:14 PM PDT 24
Finished Jul 29 06:05:09 PM PDT 24
Peak memory 272964 kb
Host smart-cb6388a6-75bd-4f5c-9f93-27a992ffed99
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381412223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.3381412223
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.2383376915
Short name T64
Test name
Test status
Simulation time 18573491001 ps
CPU time 1305.66 seconds
Started Jul 29 05:51:18 PM PDT 24
Finished Jul 29 06:13:04 PM PDT 24
Peak memory 272924 kb
Host smart-ffa83687-ac9d-488e-b9dc-bc8daef75a8c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383376915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.2383376915
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.2109483515
Short name T697
Test name
Test status
Simulation time 5788820052 ps
CPU time 231.43 seconds
Started Jul 29 05:51:17 PM PDT 24
Finished Jul 29 05:55:08 PM PDT 24
Peak memory 248368 kb
Host smart-ab298023-4f12-4dcc-b0de-f0057a717ce5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109483515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.2109483515
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.3009142957
Short name T42
Test name
Test status
Simulation time 1650743599 ps
CPU time 29.2 seconds
Started Jul 29 05:51:18 PM PDT 24
Finished Jul 29 05:51:47 PM PDT 24
Peak memory 255800 kb
Host smart-1e7ef13f-b359-4aed-96dc-27eee2ea3d67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30091
42957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.3009142957
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.2569447220
Short name T53
Test name
Test status
Simulation time 1388225941 ps
CPU time 19.98 seconds
Started Jul 29 05:51:16 PM PDT 24
Finished Jul 29 05:51:36 PM PDT 24
Peak memory 247968 kb
Host smart-2f3fe03b-d376-47b4-8f0c-9a66c2eb664e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25694
47220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.2569447220
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.444341489
Short name T204
Test name
Test status
Simulation time 2259411505 ps
CPU time 34.9 seconds
Started Jul 29 05:51:15 PM PDT 24
Finished Jul 29 05:51:50 PM PDT 24
Peak memory 248308 kb
Host smart-e290dac4-3fce-449a-906b-0692cab4b193
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44434
1489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.444341489
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.3722948828
Short name T653
Test name
Test status
Simulation time 198786244 ps
CPU time 7.76 seconds
Started Jul 29 05:51:17 PM PDT 24
Finished Jul 29 05:51:25 PM PDT 24
Peak memory 252968 kb
Host smart-1956e9f1-f718-4114-ae9e-06c58a913d6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37229
48828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.3722948828
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.3714298562
Short name T44
Test name
Test status
Simulation time 226261657372 ps
CPU time 3496.86 seconds
Started Jul 29 05:51:16 PM PDT 24
Finished Jul 29 06:49:33 PM PDT 24
Peak memory 289028 kb
Host smart-9cad2b85-07b5-4b2e-8272-f8737df81c70
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714298562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.3714298562
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.4085801832
Short name T227
Test name
Test status
Simulation time 42256776 ps
CPU time 3.79 seconds
Started Jul 29 05:51:22 PM PDT 24
Finished Jul 29 05:51:26 PM PDT 24
Peak memory 248584 kb
Host smart-c9ef8b99-f909-4229-ad8a-23b09a1efed6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4085801832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.4085801832
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.1849241287
Short name T122
Test name
Test status
Simulation time 66724645461 ps
CPU time 1048.21 seconds
Started Jul 29 05:51:19 PM PDT 24
Finished Jul 29 06:08:48 PM PDT 24
Peak memory 264708 kb
Host smart-48603677-c117-45f1-9e31-29b5f2859d63
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849241287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.1849241287
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.3860873616
Short name T571
Test name
Test status
Simulation time 123865998 ps
CPU time 7.76 seconds
Started Jul 29 05:51:22 PM PDT 24
Finished Jul 29 05:51:30 PM PDT 24
Peak memory 248224 kb
Host smart-16a4979c-7d01-44c7-ba52-004131c0243f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3860873616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.3860873616
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.83070883
Short name T658
Test name
Test status
Simulation time 6899415864 ps
CPU time 53 seconds
Started Jul 29 05:51:19 PM PDT 24
Finished Jul 29 05:52:12 PM PDT 24
Peak memory 256080 kb
Host smart-c2aa92ee-f7ce-4d1c-9656-29877ae2b80d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83070
883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.83070883
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.4159415696
Short name T270
Test name
Test status
Simulation time 176266424 ps
CPU time 9.45 seconds
Started Jul 29 05:51:22 PM PDT 24
Finished Jul 29 05:51:31 PM PDT 24
Peak memory 252896 kb
Host smart-4c75b5a8-6d68-4a8c-b92f-399b0fccb5f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41594
15696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.4159415696
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.3414025221
Short name T105
Test name
Test status
Simulation time 6651329666 ps
CPU time 772.07 seconds
Started Jul 29 05:51:22 PM PDT 24
Finished Jul 29 06:04:14 PM PDT 24
Peak memory 272924 kb
Host smart-e242db42-1b0d-48b6-b57f-0c4b80da5dc8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414025221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.3414025221
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.2847195343
Short name T688
Test name
Test status
Simulation time 3976387658 ps
CPU time 157.1 seconds
Started Jul 29 05:51:20 PM PDT 24
Finished Jul 29 05:53:57 PM PDT 24
Peak memory 248216 kb
Host smart-fc202522-5566-494a-8f81-81c4d538aaa8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847195343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.2847195343
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.2121347440
Short name T613
Test name
Test status
Simulation time 1195835001 ps
CPU time 18.56 seconds
Started Jul 29 05:51:19 PM PDT 24
Finished Jul 29 05:51:38 PM PDT 24
Peak memory 248348 kb
Host smart-4a98bf76-583b-409d-854a-43a9080bf69a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21213
47440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.2121347440
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.922229724
Short name T440
Test name
Test status
Simulation time 1081663148 ps
CPU time 24.9 seconds
Started Jul 29 05:51:21 PM PDT 24
Finished Jul 29 05:51:46 PM PDT 24
Peak memory 256128 kb
Host smart-b9747512-863d-4ea4-849c-6ebf7a7c1c46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92222
9724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.922229724
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.1707420814
Short name T434
Test name
Test status
Simulation time 1609717395 ps
CPU time 28.59 seconds
Started Jul 29 05:51:22 PM PDT 24
Finished Jul 29 05:51:51 PM PDT 24
Peak memory 248288 kb
Host smart-506577cd-c7ac-443b-aa97-dcce247c6914
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17074
20814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.1707420814
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.335287860
Short name T500
Test name
Test status
Simulation time 788344013 ps
CPU time 23.46 seconds
Started Jul 29 05:51:15 PM PDT 24
Finished Jul 29 05:51:39 PM PDT 24
Peak memory 248272 kb
Host smart-4085d414-f916-4047-93a2-4156713c33e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33528
7860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.335287860
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.996650756
Short name T641
Test name
Test status
Simulation time 47864024463 ps
CPU time 2781.39 seconds
Started Jul 29 05:51:22 PM PDT 24
Finished Jul 29 06:37:44 PM PDT 24
Peak memory 288568 kb
Host smart-474eadbc-8260-4a99-8512-c7dff460ba33
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996650756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_hand
ler_stress_all.996650756
Directory /workspace/9.alert_handler_stress_all/latest
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