Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	86816	1			T1	2177		T7	2		T20	1
class_i[0x1]	49766	1			T1	2030		T4	140		T6	7
class_i[0x2]	54674	1			T1	838		T6	15		T7	4
class_i[0x3]	39499	1			T1	2124		T4	59		T7	5

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	59936	1			T1	1662		T4	50		T6	8
alert[0x1]	59938	1			T1	1494		T4	38		T6	14
alert[0x2]	54706	1			T1	1560		T4	42		T7	4
alert[0x3]	56175	1			T1	2453		T4	69		T7	3

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

230461

1

T1

7169

T4

199

T6

22

esc_ping_fail

294

1

T7

5

T16

5

T17

12

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	59849	1			T1	1662		T4	50		T6	8
esc_integrity_fail	alert[0x1]	59868	1			T1	1494		T4	38		T6	14
esc_integrity_fail	alert[0x2]	54632	1			T1	1560		T4	42		T7	2
esc_integrity_fail	alert[0x3]	56112	1			T1	2453		T4	69		T7	2
esc_ping_fail	alert[0x0]	87	1			T7	1		T16	1		T17	2
esc_ping_fail	alert[0x1]	70	1			T7	1		T16	2		T17	4
esc_ping_fail	alert[0x2]	74	1			T7	2		T16	2		T17	3
esc_ping_fail	alert[0x3]	63	1			T7	1		T17	3		T86	3

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	86720	1			T1	2177		T7	2		T20	1
esc_integrity_fail	class_i[0x1]	49691	1			T1	2030		T4	140		T6	7
esc_integrity_fail	class_i[0x2]	54617	1			T1	838		T6	15		T7	4
esc_integrity_fail	class_i[0x3]	39433	1			T1	2124		T4	59		T5	33
esc_ping_fail	class_i[0x0]	96	1			T16	5		T86	7		T135	7
esc_ping_fail	class_i[0x1]	75	1			T65	1		T303	1		T296	6
esc_ping_fail	class_i[0x2]	57	1			T17	12		T104	10		T229	5
esc_ping_fail	class_i[0x3]	66	1			T7	5		T65	5		T289	9