Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	724106490	0	0	623
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	724106490	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	724106490	723935699	0	0
tb.dut.CheckAccuCntDw	0	0	623	623	0	0
tb.dut.CheckEscCntDw	0	0	623	623	0	0
tb.dut.CheckNAlerts	0	0	623	623	0	0
tb.dut.CheckNClasses	0	0	623	623	0	0
tb.dut.CheckNEscSev	0	0	623	623	0	0
tb.dut.CrashdumpKnownO_A	0	0	724106490	723935699	0	0
tb.dut.EdnKnownO_A	0	0	724106490	723935699	0	0
tb.dut.EscPKnownO_A	0	0	724106490	723935699	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	724106490	80	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	724106490	80	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	724106490	80	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	724106490	80	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	724106490	80	0	0
tb.dut.IrqAKnownO_A	0	0	724106490	723935699	0	0
tb.dut.IrqBKnownO_A	0	0	724106490	723935699	0	0
tb.dut.IrqCKnownO_A	0	0	724106490	723935699	0	0
tb.dut.IrqDKnownO_A	0	0	724106490	723935699	0	0
tb.dut.TlAReadyKnownO_A	0	0	724106490	723935699	0	0
tb.dut.TlDValidKnownO_A	0	0	724106490	723935699	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	745658075	3494826	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	745658075	11527	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	745658075	9705	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	745658075	10107	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	745658075	10282	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	745658075	9702	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	745658075	9504	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	745658075	9911	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	745658075	9863	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	745658075	10722	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	745658075	10503	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	745658075	9497	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	745658075	10402	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	745658075	10664	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	745658075	10540	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	745658075	11693	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	745658075	11128	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	745658075	9780	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	745658075	11054	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	745658075	12195	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	745658075	11029	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	745658075	10822	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	745658075	9711	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	745658075	9656	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	745658075	9924	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	745658075	10846	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	745658075	11102	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	745658075	9719	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	745658075	10654	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	745658075	11371	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	745658075	9835	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	745658075	9817	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	745658075	10011	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	745658075	9874	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	745658075	11523	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	745658075	10013	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	745658075	9828	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	745658075	10030	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	745658075	11225	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	745658075	10753	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	745658075	9656	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	745658075	10390	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	745658075	9793	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	745658075	9881	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	745658075	9688	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	745658075	11203	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	745658075	10891	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	745658075	9362	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	745658075	9576	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	745658075	10043	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	745658075	10806	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	745658075	9491	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	745658075	9894	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	745658075	9907	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	745658075	10199	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	745658075	9949	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	745658075	10206	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	745658075	10383	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	745658075	9668	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	745658075	9745	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	745658075	9777	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	745658075	10785	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	745658075	10334	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	745658075	12224	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	745658075	10879	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	745658075	10808	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	745658075	9859	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	745658075	11011	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	745658075	9808	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	745658075	10895	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	745658075	18906	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	745658075	12406	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	745658075	11642	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	745658075	9751	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	745658075	9700	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	745658075	9743	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	745658075	9858	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	745658075	10012	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	745658075	10012	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	724106490	80	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	724106490	80	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	724106490	80	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	724106490	2572	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	724106490	227376	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	724106490	374250369	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	724106490	266	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	724106490	832	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	724106490	58	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	724106490	425	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	723908984	313477562	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	724106490	932	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	724106490	917	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	724106490	901	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	724106490	880	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	724106490	1090	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	724106490	124351	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	724106490	974	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	724106490	58	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	724106490	1216	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	724106490	976	0	0
tb.dut.gen_classes[0].u_esc_timer.EscStateOut_A	0	0	723907329	723837363	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	623	623	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	724106490	723935699	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	724106490	80	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	724106490	80	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	724106490	80	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	724106490	4764	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	724106490	194664	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	724106490	442747808	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	724106490	225	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	724106490	479	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	724106490	23	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	724106490	210	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	723908984	337039182	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	724106490	557	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	724106490	547	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	724106490	541	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	724106490	530	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	724106490	1268	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	724106490	150742	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	724106490	1181	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	724106490	64	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	724106490	1297	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	724106490	1057	0	0
tb.dut.gen_classes[1].u_esc_timer.EscStateOut_A	0	0	723907329	723837363	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	623	623	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	724106490	723935699	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	724106490	80	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	724106490	80	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	724106490	80	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	724106490	5010	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	724106490	194529	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	724106490	392979590	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	724106490	188	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	724106490	498	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	724106490	22	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	724106490	234	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	723908984	320587098	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	724106490	580	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	724106490	562	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	724106490	555	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	724106490	544	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	724106490	1623	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	724106490	142018	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	724106490	1530	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	724106490	70	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	724106490	1207	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	724106490	967	0	0
tb.dut.gen_classes[2].u_esc_timer.EscStateOut_A	0	0	723907329	723837363	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	623	623	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	724106490	723935699	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	724106490	80	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	724106490	80	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	724106490	80	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	724106490	3078	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	724106490	124345	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	724106490	458191701	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	724106490	216	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	724106490	459	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	724106490	10	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	724106490	210	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	723908984	330945952	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	724106490	533	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	724106490	523	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	724106490	508	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	724106490	503	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	724106490	1722	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	724106490	154816	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	724106490	1640	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	724106490	72	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	724106490	1350	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	724106490	1110	0	0
tb.dut.gen_classes[3].u_esc_timer.EscStateOut_A	0	0	723907329	723837363	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	623	623	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	724106490	723935699	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	745658075	138844376	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	745658075	744984415	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	745658075	744984415	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	745658075	204969204	0	0
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