Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	3	37	92.50

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	3	37	92.50	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	58	1			T4	1		T63	2		T71	1
class_index[0x1]	64	1			T63	1		T71	1		T49	1
class_index[0x2]	70	1			T1	1		T5	2		T46	1
class_index[0x3]	72	1			T1	1		T49	1		T75	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	97	1			T1	1		T4	1		T71	1
intr_timeout_cnt[1]	54	1			T5	2		T63	1		T71	1
intr_timeout_cnt[2]	35	1			T70	1		T24	1		T52	1
intr_timeout_cnt[3]	16	1			T70	1		T81	1		T57	1
intr_timeout_cnt[4]	12	1			T255	1		T256	1		T257	1
intr_timeout_cnt[5]	8	1			T50	1		T52	1		T55	1
intr_timeout_cnt[6]	16	1			T1	1		T63	2		T76	1
intr_timeout_cnt[7]	12	1			T49	2		T78	1		T57	1
intr_timeout_cnt[8]	7	1			T49	1		T26	1		T102	1
intr_timeout_cnt[9]	7	1			T46	1		T49	1		T76	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	3	37	92.50	3

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x1]]	[intr_timeout_cnt[7]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[5]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[9]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	20	1			T4	1		T79	1		T88	1
class_index[0x0]	intr_timeout_cnt[1]	8	1			T71	1		T24	1		T80	1
class_index[0x0]	intr_timeout_cnt[2]	12	1			T70	1		T129	1		T258	4
class_index[0x0]	intr_timeout_cnt[3]	6	1			T81	1		T259	1		T260	1
class_index[0x0]	intr_timeout_cnt[4]	2	1			T112	1		T261	1		-	-
class_index[0x0]	intr_timeout_cnt[5]	1	1			T55	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[6]	4	1			T63	2		T57	1		T109	1
class_index[0x0]	intr_timeout_cnt[7]	2	1			T49	1		T113	1		-	-
class_index[0x0]	intr_timeout_cnt[8]	1	1			T115	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[9]	2	1			T49	1		T101	1		-	-
class_index[0x1]	intr_timeout_cnt[0]	25	1			T71	1		T73	1		T75	1
class_index[0x1]	intr_timeout_cnt[1]	12	1			T63	1		T50	1		T26	1
class_index[0x1]	intr_timeout_cnt[2]	6	1			T80	1		T255	1		T262	1
class_index[0x1]	intr_timeout_cnt[3]	4	1			T40	1		T91	1		T263	1
class_index[0x1]	intr_timeout_cnt[4]	4	1			T255	1		T256	1		T23	1
class_index[0x1]	intr_timeout_cnt[5]	5	1			T52	1		T264	1		T265	1
class_index[0x1]	intr_timeout_cnt[6]	5	1			T101	2		T266	1		T267	1
class_index[0x1]	intr_timeout_cnt[8]	2	1			T49	1		T110	1		-	-
class_index[0x1]	intr_timeout_cnt[9]	1	1			T268	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[0]	25	1			T69	1		T70	1		T269	1
class_index[0x2]	intr_timeout_cnt[1]	16	1			T5	2		T62	1		T75	1
class_index[0x2]	intr_timeout_cnt[2]	9	1			T24	1		T57	2		T270	1
class_index[0x2]	intr_timeout_cnt[3]	2	1			T57	1		T258	1		-	-
class_index[0x2]	intr_timeout_cnt[4]	4	1			T257	1		T271	1		T268	2
class_index[0x2]	intr_timeout_cnt[5]	2	1			T50	1		T108	1		-	-
class_index[0x2]	intr_timeout_cnt[6]	4	1			T1	1		T52	1		T124	1
class_index[0x2]	intr_timeout_cnt[7]	2	1			T78	1		T91	1		-	-
class_index[0x2]	intr_timeout_cnt[8]	2	1			T26	1		T264	1		-	-
class_index[0x2]	intr_timeout_cnt[9]	4	1			T46	1		T76	1		T70	1
class_index[0x3]	intr_timeout_cnt[0]	27	1			T1	1		T75	1		T50	1
class_index[0x3]	intr_timeout_cnt[1]	18	1			T24	1		T51	1		T52	1
class_index[0x3]	intr_timeout_cnt[2]	8	1			T52	1		T255	1		T123	1
class_index[0x3]	intr_timeout_cnt[3]	4	1			T70	1		T272	1		T273	1
class_index[0x3]	intr_timeout_cnt[4]	2	1			T127	1		T274	1		-	-
class_index[0x3]	intr_timeout_cnt[6]	3	1			T76	1		T275	1		T267	1
class_index[0x3]	intr_timeout_cnt[7]	8	1			T49	1		T57	1		T255	3
class_index[0x3]	intr_timeout_cnt[8]	2	1			T102	1		T276	1		-	-