Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	356583	1			T1	4168		T2	37		T3	1565
all_values[1]	356583	1			T1	4168		T2	37		T3	1565
all_values[2]	356583	1			T1	4168		T2	37		T3	1565
all_values[3]	356583	1			T1	4168		T2	37		T3	1565

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

708978

1

T1

8388

T2

59

T3

3077

auto[1]

717354

1

T1

8284

T2

89

T3

3183

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

844969

1

T1

9752

T2

80

T3

4778

auto[1]

581363

1

T1

6920

T2

68

T3

1482

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	100975	1			T1	1064		T2	9		T3	757
all_values[0]	auto[0]	auto[1]	75689	1			T1	962		T2	9		T4	156
all_values[0]	auto[1]	auto[0]	103212	1			T1	1154		T2	10		T3	808
all_values[0]	auto[1]	auto[1]	76707	1			T1	988		T2	9		T11	2
all_values[1]	auto[0]	auto[0]	104938	1			T1	1315		T2	5		T3	441
all_values[1]	auto[0]	auto[1]	72298	1			T1	794		T2	5		T3	328
all_values[1]	auto[1]	auto[0]	106595	1			T1	1310		T2	15		T3	439
all_values[1]	auto[1]	auto[1]	72752	1			T1	749		T2	12		T3	357
all_values[2]	auto[0]	auto[0]	107055	1			T1	1223		T2	7		T3	592
all_values[2]	auto[0]	auto[1]	70937	1			T1	852		T2	5		T3	212
all_values[2]	auto[1]	auto[0]	107882	1			T1	1230		T2	14		T3	577
all_values[2]	auto[1]	auto[1]	70709	1			T1	863		T2	11		T3	184
all_values[3]	auto[0]	auto[0]	106174	1			T1	1279		T2	10		T3	549
all_values[3]	auto[0]	auto[1]	70912	1			T1	899		T2	9		T3	198
all_values[3]	auto[1]	auto[0]	108138	1			T1	1177		T2	10		T3	615
all_values[3]	auto[1]	auto[1]	71359	1			T1	813		T2	8		T3	203