Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	356583	1			T1	4168		T2	37		T3	1565
all_pins[1]	356583	1			T1	4168		T2	37		T3	1565
all_pins[2]	356583	1			T1	4168		T2	37		T3	1565
all_pins[3]	356583	1			T1	4168		T2	37		T3	1565

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1134805	1			T1	13259		T2	108		T3	5516
values[0x1]	291527	1			T1	3413		T2	40		T3	744
transitions[0x0=>0x1]	194092	1			T1	2344		T2	21		T3	616
transitions[0x1=>0x0]	194355	1			T1	2344		T2	21		T3	616

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	279876	1			T1	3180		T2	28		T3	1565
all_pins[0]	values[0x1]	76707	1			T1	988		T2	9		T11	2
all_pins[0]	transitions[0x0=>0x1]	76049	1			T1	980		T2	9		T11	1
all_pins[0]	transitions[0x1=>0x0]	70964	1			T1	805		T2	8		T3	203
all_pins[1]	values[0x0]	283831	1			T1	3419		T2	25		T3	1208
all_pins[1]	values[0x1]	72752	1			T1	749		T2	12		T3	357
all_pins[1]	transitions[0x0=>0x1]	40017	1			T1	393		T2	5		T3	357
all_pins[1]	transitions[0x1=>0x0]	43972	1			T1	632		T2	2		T11	1
all_pins[2]	values[0x0]	285874	1			T1	3305		T2	26		T3	1381
all_pins[2]	values[0x1]	70709	1			T1	863		T2	11		T3	184
all_pins[2]	transitions[0x0=>0x1]	38586	1			T1	531		T2	4		T3	95
all_pins[2]	transitions[0x1=>0x0]	40629	1			T1	417		T2	5		T3	268
all_pins[3]	values[0x0]	285224	1			T1	3355		T2	29		T3	1362
all_pins[3]	values[0x1]	71359	1			T1	813		T2	8		T3	203
all_pins[3]	transitions[0x0=>0x1]	39440	1			T1	440		T2	3		T3	164
all_pins[3]	transitions[0x1=>0x0]	38790	1			T1	490		T2	6		T3	145