Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	266	1			T172	4		T173	4		T248	7
all_values[1]	266	1			T172	4		T173	4		T248	7
all_values[2]	266	1			T172	4		T173	4		T248	7
all_values[3]	266	1			T172	4		T173	4		T248	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

552

1

T172

9

T173

6

T248

12

auto[1]

512

1

T172

7

T173

10

T248

16

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

402

1

T172

5

T173

10

T248

11

auto[1]

662

1

T172

11

T173

6

T248

17

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

630

1

T172

10

T173

11

T248

15

auto[1]

434

1

T172

6

T173

5

T248

13

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	24	0	24	100.00
Automatically Generated Cross Bins	24	0	24	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

51

1

T173

1

T326

2

T327

2

all_values[0]

auto[0]

auto[0]

auto[1]

30

1

T327

1

T328

2

T329

1

all_values[0]

auto[0]

auto[1]

auto[0]

46

1

T173

1

T248

1

T326

1

all_values[0]

auto[0]

auto[1]

auto[1]

29

1

T172

1

T248

1

T249

1

all_values[0]

auto[1]

auto[0]

auto[1]

57

1

T172

1

T173

2

T248

3

all_values[0]

auto[1]

auto[1]

auto[1]

53

1

T172

2

T248

2

T249

1

all_values[1]

auto[0]

auto[0]

auto[0]

48

1

T173

1

T248

3

T249

2

all_values[1]

auto[0]

auto[0]

auto[1]

30

1

T172

1

T330

2

T328

2

all_values[1]

auto[0]

auto[1]

auto[0]

59

1

T173

2

T248

2

T249

1

all_values[1]

auto[0]

auto[1]

auto[1]

20

1

T172

2

T326

1

T327

1

all_values[1]

auto[1]

auto[0]

auto[1]

53

1

T172

1

T249

1

T331

1

all_values[1]

auto[1]

auto[1]

auto[1]

56

1

T173

1

T248

2

T326

2

all_values[2]

auto[0]

auto[0]

auto[0]

40

1

T172

1

T249

1

T326

1

all_values[2]

auto[0]

auto[0]

auto[1]

47

1

T172

1

T248

1

T330

1

all_values[2]

auto[0]

auto[1]

auto[0]

44

1

T173

4

T248

2

T327

2

all_values[2]

auto[0]

auto[1]

auto[1]

22

1

T249

1

T326

1

T331

2

all_values[2]

auto[1]

auto[0]

auto[1]

63

1

T172

1

T248

2

T249

1

all_values[2]

auto[1]

auto[1]

auto[1]

50

1

T172

1

T248

2

T249

1

all_values[3]

auto[0]

auto[0]

auto[0]

62

1

T172

3

T248

3

T326

2

all_values[3]

auto[0]

auto[0]

auto[1]

22

1

T173

1

T249

1

T331

1

all_values[3]

auto[0]

auto[1]

auto[0]

52

1

T172

1

T173

1

T326

1

all_values[3]

auto[0]

auto[1]

auto[1]

28

1

T248

2

T249

2

T330

1

all_values[3]

auto[1]

auto[0]

auto[1]

49

1

T173

1

T249

1

T326

1

all_values[3]

auto[1]

auto[1]

auto[1]

53

1

T173

1

T248

2

T331

1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal