Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	89748	1			T1	843		T6	665		T13	910
accum_cnt_1000	220086	1			T1	1919		T3	863		T4	424
accum_cnt_100	25953	1			T1	240		T3	141		T4	89
accum_cnt_50	69920	1			T1	566		T2	30		T3	134
accum_cnt_10	182518	1			T1	2483		T2	13		T3	2360
accum_cnt_0	423015	1			T1	5805		T2	53		T3	1174

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	262771	1			T1	2977		T2	24		T3	1168
class_index[0x1]	262771	1			T1	2977		T2	24		T3	1168
class_index[0x2]	262771	1			T1	2977		T2	24		T3	1168
class_index[0x3]	262771	1			T1	2977		T2	24		T3	1168

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	25314	1			T1	378		T6	566		T134	430
class_index[0x0]	accum_cnt_1000	57912	1			T1	693		T4	231		T6	497
class_index[0x0]	accum_cnt_100	6687	1			T1	48		T4	29		T6	28
class_index[0x0]	accum_cnt_50	15852	1			T1	228		T2	18		T4	68
class_index[0x0]	accum_cnt_10	43496	1			T1	120		T2	6		T4	24
class_index[0x0]	accum_cnt_0	100022	1			T1	1458		T3	1168		T11	3
class_index[0x1]	accum_cnt_2000	20354	1			T13	283		T27	283		T62	140
class_index[0x1]	accum_cnt_1000	51634	1			T1	224		T4	24		T5	57
class_index[0x1]	accum_cnt_100	7461	1			T1	77		T4	10		T6	1363
class_index[0x1]	accum_cnt_50	16059	1			T1	55		T4	6		T6	2
class_index[0x1]	accum_cnt_10	49352	1			T1	818		T3	1166		T11	2
class_index[0x1]	accum_cnt_0	106686	1			T1	1803		T2	24		T3	2
class_index[0x2]	accum_cnt_2000	23880	1			T6	99		T13	627		T63	3
class_index[0x2]	accum_cnt_1000	58191	1			T1	273		T4	76		T6	85
class_index[0x2]	accum_cnt_100	6298	1			T1	67		T4	27		T6	4
class_index[0x2]	accum_cnt_50	16074	1			T1	47		T2	12		T4	25
class_index[0x2]	accum_cnt_10	40002	1			T1	633		T2	7		T3	1166
class_index[0x2]	accum_cnt_0	106839	1			T1	1957		T2	5		T3	2
class_index[0x3]	accum_cnt_2000	20200	1			T1	465		T19	155		T69	142
class_index[0x3]	accum_cnt_1000	52349	1			T1	729		T3	863		T4	93
class_index[0x3]	accum_cnt_100	5507	1			T1	48		T3	141		T4	23
class_index[0x3]	accum_cnt_50	21935	1			T1	236		T3	134		T4	50
class_index[0x3]	accum_cnt_10	49668	1			T1	912		T3	28		T11	3
class_index[0x3]	accum_cnt_0	109468	1			T1	587		T2	24		T3	2