Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	13455	1			T6	222		T15	54		T17	1
alert[0x1]	4226	1			T1	3		T6	449		T15	63
alert[0x2]	6255	1			T6	3450		T7	1		T15	97
alert[0x3]	12646	1			T1	11		T6	773		T63	1
alert[0x4]	3990	1			T1	7		T6	16		T82	1
alert[0x5]	1678	1			T7	1		T104	1		T106	55
alert[0x6]	2300	1			T68	90		T105	2		T50	789
alert[0x7]	7946	1			T6	44		T46	1		T86	1
alert[0x8]	3594	1			T15	224		T120	1		T65	1
alert[0x9]	3400	1			T4	21		T6	497		T15	112
alert[0xa]	4643	1			T5	6		T15	1590		T82	3
alert[0xb]	13440	1			T6	8		T7	1		T46	2
alert[0xc]	6249	1			T4	17		T63	4		T86	1
alert[0xd]	7276	1			T1	265		T4	51		T17	1
alert[0xe]	10774	1			T4	7		T6	105		T86	1
alert[0xf]	2008	1			T1	52		T7	1		T5	5
alert[0x10]	3419	1			T65	1		T134	38		T68	6
alert[0x11]	10595	1			T6	90		T86	1		T65	1
alert[0x12]	3466	1			T1	73		T6	615		T65	1
alert[0x13]	5641	1			T1	24		T15	27		T82	6
alert[0x14]	4304	1			T6	19		T15	4		T68	64
alert[0x15]	1754	1			T1	94		T3	1		T82	3
alert[0x16]	7255	1			T1	27		T6	33		T7	2
alert[0x17]	7408	1			T1	6		T6	121		T15	565
alert[0x18]	13028	1			T6	655		T15	29		T46	1
alert[0x19]	3849	1			T1	1299		T16	1		T17	1
alert[0x1a]	5285	1			T6	43		T15	42		T135	1
alert[0x1b]	3795	1			T6	89		T15	99		T120	1
alert[0x1c]	2010	1			T4	5		T16	1		T86	1
alert[0x1d]	2907	1			T1	3		T6	9		T7	1
alert[0x1e]	6481	1			T4	4		T6	3282		T15	48
alert[0x1f]	5192	1			T15	5		T46	1		T17	1
alert[0x20]	4179	1			T4	1		T16	1		T59	13
alert[0x21]	8344	1			T1	4		T4	1		T6	454
alert[0x22]	4877	1			T4	15		T6	188		T5	5
alert[0x23]	2409	1			T15	462		T86	1		T135	1
alert[0x24]	8069	1			T6	123		T7	1		T15	27
alert[0x25]	10948	1			T4	4		T68	320		T59	10
alert[0x26]	4591	1			T1	22		T4	20		T15	295
alert[0x27]	7547	1			T1	32		T4	8		T15	402
alert[0x28]	5840	1			T1	35		T15	332		T17	1
alert[0x29]	11805	1			T6	878		T15	9		T68	499
alert[0x2a]	4196	1			T1	8		T6	80		T15	32
alert[0x2b]	5986	1			T1	25		T4	4		T65	1
alert[0x2c]	9176	1			T1	6		T5	3		T15	5
alert[0x2d]	4477	1			T4	4		T15	454		T16	1
alert[0x2e]	3115	1			T6	83		T15	235		T13	1
alert[0x2f]	11028	1			T4	2		T7	1		T5	4
alert[0x30]	9462	1			T1	243		T6	4		T15	176
alert[0x31]	2722	1			T4	1		T17	1		T68	186
alert[0x32]	4785	1			T4	2		T46	1		T82	5
alert[0x33]	6683	1			T15	40		T16	1		T86	1
alert[0x34]	6693	1			T1	100		T4	31		T6	3
alert[0x35]	6275	1			T1	30		T4	19		T82	1
alert[0x36]	6337	1			T7	1		T17	1		T134	508
alert[0x37]	6870	1			T49	1		T59	1194		T62	102
alert[0x38]	5289	1			T15	152		T65	1		T59	831
alert[0x39]	7446	1			T4	1		T6	128		T15	28
alert[0x3a]	12410	1			T15	978		T46	1		T16	1
alert[0x3b]	11914	1			T4	2		T7	1		T15	61
alert[0x3c]	5142	1			T7	1		T15	1882		T82	5
alert[0x3d]	8234	1			T4	33		T6	646		T15	511
alert[0x3e]	5082	1			T4	5		T59	82		T62	1
alert[0x3f]	10288	1			T82	6		T17	1		T134	428
alert[0x40]	4602	1			T1	26		T15	16		T82	14

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	71901	1			T1	1255		T4	142		T7	1
class_i[0x1]	136107	1			T1	465		T3	1		T4	100
class_i[0x2]	112363	1			T1	86		T6	13005		T5	12
class_i[0x3]	96719	1			T1	589		T4	16		T6	12

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

416356

1

T1

2395

T4

258

T6

13107

alert_ping_fail

734

1

T3

1

T7

12

T13

1

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	13435	1			T6	222		T15	54		T134	107
alert_integrity_fail	alert[0x1]	4216	1			T1	3		T6	449		T15	63
alert_integrity_fail	alert[0x2]	6242	1			T6	3450		T15	97		T134	85
alert_integrity_fail	alert[0x3]	12641	1			T1	11		T6	773		T63	1
alert_integrity_fail	alert[0x4]	3975	1			T1	7		T6	16		T82	1
alert_integrity_fail	alert[0x5]	1671	1			T106	55		T70	279		T52	69
alert_integrity_fail	alert[0x6]	2289	1			T68	90		T105	2		T50	789
alert_integrity_fail	alert[0x7]	7931	1			T6	44		T46	1		T68	158
alert_integrity_fail	alert[0x8]	3581	1			T15	224		T134	123		T68	19
alert_integrity_fail	alert[0x9]	3387	1			T4	21		T6	497		T15	112
alert_integrity_fail	alert[0xa]	4627	1			T5	6		T15	1590		T82	3
alert_integrity_fail	alert[0xb]	13431	1			T6	8		T46	2		T82	1
alert_integrity_fail	alert[0xc]	6237	1			T4	17		T63	4		T59	15
alert_integrity_fail	alert[0xd]	7264	1			T1	265		T4	51		T134	1714
alert_integrity_fail	alert[0xe]	10767	1			T4	7		T6	105		T68	481
alert_integrity_fail	alert[0xf]	2000	1			T1	52		T5	5		T15	130
alert_integrity_fail	alert[0x10]	3403	1			T134	38		T68	6		T62	22
alert_integrity_fail	alert[0x11]	10587	1			T6	90		T134	31		T105	1
alert_integrity_fail	alert[0x12]	3457	1			T1	73		T6	615		T68	65
alert_integrity_fail	alert[0x13]	5622	1			T1	24		T15	27		T82	6
alert_integrity_fail	alert[0x14]	4289	1			T6	19		T15	4		T68	64
alert_integrity_fail	alert[0x15]	1734	1			T1	94		T82	3		T59	14
alert_integrity_fail	alert[0x16]	7245	1			T1	27		T6	33		T68	494
alert_integrity_fail	alert[0x17]	7394	1			T1	6		T6	121		T15	565
alert_integrity_fail	alert[0x18]	13019	1			T6	655		T15	29		T46	1
alert_integrity_fail	alert[0x19]	3835	1			T1	1299		T134	179		T62	34
alert_integrity_fail	alert[0x1a]	5279	1			T6	43		T15	42		T134	435
alert_integrity_fail	alert[0x1b]	3783	1			T6	89		T15	99		T134	401
alert_integrity_fail	alert[0x1c]	2000	1			T4	5		T134	11		T68	13
alert_integrity_fail	alert[0x1d]	2901	1			T1	3		T6	9		T68	172
alert_integrity_fail	alert[0x1e]	6469	1			T4	4		T6	3282		T15	48
alert_integrity_fail	alert[0x1f]	5173	1			T15	5		T46	1		T105	1
alert_integrity_fail	alert[0x20]	4161	1			T4	1		T59	13		T69	295
alert_integrity_fail	alert[0x21]	8328	1			T1	4		T4	1		T6	454
alert_integrity_fail	alert[0x22]	4861	1			T4	15		T6	188		T5	5
alert_integrity_fail	alert[0x23]	2398	1			T15	462		T134	15		T62	21
alert_integrity_fail	alert[0x24]	8059	1			T6	123		T15	27		T68	1172
alert_integrity_fail	alert[0x25]	10941	1			T4	4		T68	320		T59	10
alert_integrity_fail	alert[0x26]	4578	1			T1	22		T4	20		T15	295
alert_integrity_fail	alert[0x27]	7534	1			T1	32		T4	8		T15	402
alert_integrity_fail	alert[0x28]	5833	1			T1	35		T15	332		T134	13
alert_integrity_fail	alert[0x29]	11797	1			T6	878		T15	9		T68	499
alert_integrity_fail	alert[0x2a]	4178	1			T1	8		T6	80		T15	32
alert_integrity_fail	alert[0x2b]	5971	1			T1	25		T4	4		T49	1
alert_integrity_fail	alert[0x2c]	9165	1			T1	6		T5	3		T15	5
alert_integrity_fail	alert[0x2d]	4462	1			T4	4		T15	454		T62	204
alert_integrity_fail	alert[0x2e]	3099	1			T6	83		T15	235		T68	67
alert_integrity_fail	alert[0x2f]	11019	1			T4	2		T5	4		T82	2
alert_integrity_fail	alert[0x30]	9448	1			T1	243		T6	4		T15	176
alert_integrity_fail	alert[0x31]	2713	1			T4	1		T68	186		T49	2
alert_integrity_fail	alert[0x32]	4779	1			T4	2		T46	1		T82	5
alert_integrity_fail	alert[0x33]	6675	1			T15	40		T134	139		T68	28
alert_integrity_fail	alert[0x34]	6688	1			T1	100		T4	31		T6	3
alert_integrity_fail	alert[0x35]	6266	1			T1	30		T4	19		T82	1
alert_integrity_fail	alert[0x36]	6326	1			T134	508		T59	23		T62	9
alert_integrity_fail	alert[0x37]	6863	1			T49	1		T59	1194		T62	102
alert_integrity_fail	alert[0x38]	5280	1			T15	152		T59	831		T25	86
alert_integrity_fail	alert[0x39]	7433	1			T4	1		T6	128		T15	28
alert_integrity_fail	alert[0x3a]	12395	1			T15	978		T46	1		T134	71
alert_integrity_fail	alert[0x3b]	11906	1			T4	2		T15	61		T82	1
alert_integrity_fail	alert[0x3c]	5136	1			T15	1882		T82	5		T134	51
alert_integrity_fail	alert[0x3d]	8225	1			T4	33		T6	646		T15	511
alert_integrity_fail	alert[0x3e]	5075	1			T4	5		T59	82		T62	1
alert_integrity_fail	alert[0x3f]	10282	1			T82	6		T134	428		T105	15
alert_integrity_fail	alert[0x40]	4598	1			T1	26		T15	16		T82	14
alert_ping_fail	alert[0x0]	20	1			T17	1		T289	1		T229	1
alert_ping_fail	alert[0x1]	10	1			T86	2		T104	2		T290	1
alert_ping_fail	alert[0x2]	13	1			T7	1		T104	1		T244	1
alert_ping_fail	alert[0x3]	5	1			T291	1		T292	1		T293	1
alert_ping_fail	alert[0x4]	15	1			T65	1		T135	2		T289	1
alert_ping_fail	alert[0x5]	7	1			T7	1		T104	1		T244	1
alert_ping_fail	alert[0x6]	11	1			T294	2		T198	1		T295	1
alert_ping_fail	alert[0x7]	15	1			T86	1		T290	1		T234	2
alert_ping_fail	alert[0x8]	13	1			T120	1		T65	1		T135	1
alert_ping_fail	alert[0x9]	13	1			T17	1		T86	1		T135	1
alert_ping_fail	alert[0xa]	16	1			T86	1		T135	1		T290	1
alert_ping_fail	alert[0xb]	9	1			T7	1		T17	1		T104	1
alert_ping_fail	alert[0xc]	12	1			T86	1		T65	1		T135	3
alert_ping_fail	alert[0xd]	12	1			T17	1		T289	1		T290	1
alert_ping_fail	alert[0xe]	7	1			T86	1		T296	1		T297	1
alert_ping_fail	alert[0xf]	8	1			T7	1		T244	1		T298	2
alert_ping_fail	alert[0x10]	16	1			T65	1		T104	1		T290	1
alert_ping_fail	alert[0x11]	8	1			T86	1		T65	1		T244	1
alert_ping_fail	alert[0x12]	9	1			T65	1		T289	1		T298	1
alert_ping_fail	alert[0x13]	19	1			T289	1		T290	2		T299	1
alert_ping_fail	alert[0x14]	15	1			T107	1		T36	1		T298	1
alert_ping_fail	alert[0x15]	20	1			T3	1		T16	1		T299	1
alert_ping_fail	alert[0x16]	10	1			T7	2		T294	1		T198	2
alert_ping_fail	alert[0x17]	14	1			T16	1		T135	2		T244	1
alert_ping_fail	alert[0x18]	9	1			T294	1		T194	1		T298	1
alert_ping_fail	alert[0x19]	14	1			T16	1		T17	1		T104	2
alert_ping_fail	alert[0x1a]	6	1			T135	1		T295	1		T296	1
alert_ping_fail	alert[0x1b]	12	1			T120	1		T65	1		T36	1
alert_ping_fail	alert[0x1c]	10	1			T16	1		T86	1		T104	1
alert_ping_fail	alert[0x1d]	6	1			T7	1		T300	2		T301	1
alert_ping_fail	alert[0x1e]	12	1			T16	2		T135	1		T289	1
alert_ping_fail	alert[0x1f]	19	1			T17	1		T86	1		T120	1
alert_ping_fail	alert[0x20]	18	1			T16	1		T289	1		T287	2
alert_ping_fail	alert[0x21]	16	1			T120	1		T135	1		T229	1
alert_ping_fail	alert[0x22]	16	1			T120	1		T299	1		T244	1
alert_ping_fail	alert[0x23]	11	1			T86	1		T135	1		T104	1
alert_ping_fail	alert[0x24]	10	1			T7	1		T290	1		T195	1
alert_ping_fail	alert[0x25]	7	1			T36	1		T298	1		T302	1
alert_ping_fail	alert[0x26]	13	1			T16	1		T104	1		T244	1
alert_ping_fail	alert[0x27]	13	1			T86	1		T135	2		T289	1
alert_ping_fail	alert[0x28]	7	1			T17	1		T92	1		T237	1
alert_ping_fail	alert[0x29]	8	1			T229	1		T244	1		T296	1
alert_ping_fail	alert[0x2a]	18	1			T17	1		T65	1		T250	1
alert_ping_fail	alert[0x2b]	15	1			T65	1		T287	1		T299	1
alert_ping_fail	alert[0x2c]	11	1			T17	2		T66	2		T296	1
alert_ping_fail	alert[0x2d]	15	1			T16	1		T17	1		T104	1
alert_ping_fail	alert[0x2e]	16	1			T13	1		T16	1		T86	1
alert_ping_fail	alert[0x2f]	9	1			T7	1		T17	2		T135	2
alert_ping_fail	alert[0x30]	14	1			T16	1		T104	1		T290	1
alert_ping_fail	alert[0x31]	9	1			T17	1		T104	1		T194	1
alert_ping_fail	alert[0x32]	6	1			T289	1		T290	1		T36	1
alert_ping_fail	alert[0x33]	8	1			T16	1		T86	1		T303	1
alert_ping_fail	alert[0x34]	5	1			T17	1		T229	1		T301	1
alert_ping_fail	alert[0x35]	9	1			T17	1		T135	1		T229	1
alert_ping_fail	alert[0x36]	11	1			T7	1		T17	1		T289	1
alert_ping_fail	alert[0x37]	7	1			T303	1		T296	1		T304	1
alert_ping_fail	alert[0x38]	9	1			T65	1		T104	1		T289	1
alert_ping_fail	alert[0x39]	13	1			T65	1		T135	1		T290	1
alert_ping_fail	alert[0x3a]	15	1			T16	1		T86	1		T104	1
alert_ping_fail	alert[0x3b]	8	1			T7	1		T16	1		T135	1
alert_ping_fail	alert[0x3c]	6	1			T7	1		T290	1		T296	1
alert_ping_fail	alert[0x3d]	9	1			T303	1		T295	1		T296	1
alert_ping_fail	alert[0x3e]	7	1			T296	1		T297	1		T300	1
alert_ping_fail	alert[0x3f]	6	1			T17	1		T104	1		T295	1
alert_ping_fail	alert[0x40]	4	1			T289	1		T302	1		T305	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	71764	1			T1	1255		T4	142		T5	8
alert_integrity_fail	class_i[0x1]	135985	1			T1	465		T4	100		T6	90
alert_integrity_fail	class_i[0x2]	112114	1			T1	86		T6	13005		T5	12
alert_integrity_fail	class_i[0x3]	96493	1			T1	589		T4	16		T6	12
alert_ping_fail	class_i[0x0]	137	1			T7	1		T13	1		T65	1
alert_ping_fail	class_i[0x1]	122	1			T3	1		T86	1		T120	5
alert_ping_fail	class_i[0x2]	249	1			T17	18		T65	1		T66	4
alert_ping_fail	class_i[0x3]	226	1			T7	11		T16	14		T86	14