Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.64 99.99 98.66 92.86 100.00 100.00 99.38 99.56


Total test records in report: 828
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html
T772 /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.1243105548 Jul 30 05:21:01 PM PDT 24 Jul 30 05:21:05 PM PDT 24 19755445 ps
T186 /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.1226149873 Jul 30 05:21:09 PM PDT 24 Jul 30 05:22:01 PM PDT 24 363688134 ps
T773 /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.2143505718 Jul 30 05:20:50 PM PDT 24 Jul 30 05:21:00 PM PDT 24 124435830 ps
T774 /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.3067554422 Jul 30 05:20:32 PM PDT 24 Jul 30 05:20:35 PM PDT 24 66507702 ps
T775 /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.1007319719 Jul 30 05:20:59 PM PDT 24 Jul 30 05:21:01 PM PDT 24 7564239 ps
T776 /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.2790649722 Jul 30 05:20:33 PM PDT 24 Jul 30 05:21:17 PM PDT 24 2620713736 ps
T162 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.4285843784 Jul 30 05:20:41 PM PDT 24 Jul 30 05:24:57 PM PDT 24 38178697260 ps
T777 /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.3040800892 Jul 30 05:20:49 PM PDT 24 Jul 30 05:20:59 PM PDT 24 274192001 ps
T182 /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.1937306927 Jul 30 05:21:01 PM PDT 24 Jul 30 05:21:46 PM PDT 24 461652828 ps
T778 /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.3324356878 Jul 30 05:21:09 PM PDT 24 Jul 30 05:21:15 PM PDT 24 131348583 ps
T779 /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.2727041489 Jul 30 05:20:44 PM PDT 24 Jul 30 05:22:34 PM PDT 24 4806455983 ps
T780 /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.2690720041 Jul 30 05:21:05 PM PDT 24 Jul 30 05:21:07 PM PDT 24 6822702 ps
T188 /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.423799571 Jul 30 05:20:48 PM PDT 24 Jul 30 05:21:11 PM PDT 24 359854052 ps
T781 /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.2697796006 Jul 30 05:20:43 PM PDT 24 Jul 30 05:21:47 PM PDT 24 565632979 ps
T782 /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.1314511155 Jul 30 05:20:48 PM PDT 24 Jul 30 05:21:14 PM PDT 24 311473384 ps
T176 /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.766934476 Jul 30 05:21:13 PM PDT 24 Jul 30 05:21:16 PM PDT 24 60314586 ps
T783 /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.2108824839 Jul 30 05:21:10 PM PDT 24 Jul 30 05:21:22 PM PDT 24 110440152 ps
T784 /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.834384004 Jul 30 05:20:51 PM PDT 24 Jul 30 05:20:57 PM PDT 24 33391895 ps
T178 /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.638718665 Jul 30 05:20:35 PM PDT 24 Jul 30 05:20:39 PM PDT 24 261206284 ps
T189 /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.473928484 Jul 30 05:21:08 PM PDT 24 Jul 30 05:22:41 PM PDT 24 5175846348 ps
T785 /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.591165481 Jul 30 05:20:51 PM PDT 24 Jul 30 05:21:08 PM PDT 24 485243495 ps
T786 /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.779780039 Jul 30 05:21:37 PM PDT 24 Jul 30 05:21:38 PM PDT 24 13146536 ps
T155 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.3955598566 Jul 30 05:21:02 PM PDT 24 Jul 30 05:36:58 PM PDT 24 61641019499 ps
T787 /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.2023460603 Jul 30 05:20:52 PM PDT 24 Jul 30 05:21:08 PM PDT 24 876286863 ps
T788 /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.2983793085 Jul 30 05:20:48 PM PDT 24 Jul 30 05:21:12 PM PDT 24 1331080919 ps
T156 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.3271129909 Jul 30 05:21:05 PM PDT 24 Jul 30 05:23:35 PM PDT 24 8322521787 ps
T789 /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.3856259001 Jul 30 05:20:34 PM PDT 24 Jul 30 05:20:35 PM PDT 24 11055331 ps
T165 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.3149234732 Jul 30 05:20:47 PM PDT 24 Jul 30 05:33:37 PM PDT 24 18400969320 ps
T790 /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.1833308907 Jul 30 05:21:34 PM PDT 24 Jul 30 05:21:36 PM PDT 24 6572553 ps
T791 /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.1709954466 Jul 30 05:20:43 PM PDT 24 Jul 30 05:20:55 PM PDT 24 668238539 ps
T792 /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.3868447365 Jul 30 05:21:12 PM PDT 24 Jul 30 05:21:33 PM PDT 24 2942086145 ps
T793 /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.979407454 Jul 30 05:20:34 PM PDT 24 Jul 30 05:20:46 PM PDT 24 150423122 ps
T794 /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.4014182867 Jul 30 05:20:55 PM PDT 24 Jul 30 05:21:03 PM PDT 24 77685856 ps
T795 /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.2220507632 Jul 30 05:21:01 PM PDT 24 Jul 30 05:21:16 PM PDT 24 107589904 ps
T185 /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.2279190769 Jul 30 05:21:17 PM PDT 24 Jul 30 05:21:20 PM PDT 24 112518100 ps
T796 /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.2448806418 Jul 30 05:21:33 PM PDT 24 Jul 30 05:21:35 PM PDT 24 6633834 ps
T797 /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.1147012343 Jul 30 05:21:26 PM PDT 24 Jul 30 05:21:28 PM PDT 24 10082789 ps
T798 /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.2370742274 Jul 30 05:21:03 PM PDT 24 Jul 30 05:21:13 PM PDT 24 604240300 ps
T799 /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.1519267958 Jul 30 05:20:51 PM PDT 24 Jul 30 05:21:37 PM PDT 24 655951789 ps
T163 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.2845054304 Jul 30 05:21:12 PM PDT 24 Jul 30 05:22:31 PM PDT 24 2556273461 ps
T800 /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.616099405 Jul 30 05:21:26 PM PDT 24 Jul 30 05:21:28 PM PDT 24 13957163 ps
T801 /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.3714217603 Jul 30 05:21:30 PM PDT 24 Jul 30 05:21:31 PM PDT 24 12693812 ps
T802 /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.2352778708 Jul 30 05:20:57 PM PDT 24 Jul 30 05:21:06 PM PDT 24 408130000 ps
T803 /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.1096121379 Jul 30 05:20:34 PM PDT 24 Jul 30 05:20:38 PM PDT 24 192598761 ps
T804 /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.2846800160 Jul 30 05:20:31 PM PDT 24 Jul 30 05:20:46 PM PDT 24 91319363 ps
T805 /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.1344547549 Jul 30 05:21:33 PM PDT 24 Jul 30 05:21:35 PM PDT 24 9828280 ps
T161 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.810681267 Jul 30 05:21:15 PM PDT 24 Jul 30 05:24:13 PM PDT 24 5811612067 ps
T806 /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.3524963394 Jul 30 05:21:23 PM PDT 24 Jul 30 05:22:09 PM PDT 24 2248451709 ps
T807 /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.1064224467 Jul 30 05:21:13 PM PDT 24 Jul 30 05:21:27 PM PDT 24 352186093 ps
T808 /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.626437506 Jul 30 05:21:32 PM PDT 24 Jul 30 05:21:33 PM PDT 24 11020750 ps
T809 /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.1033161842 Jul 30 05:21:07 PM PDT 24 Jul 30 05:21:13 PM PDT 24 44373898 ps
T157 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.773823911 Jul 30 05:20:35 PM PDT 24 Jul 30 05:27:18 PM PDT 24 5445312506 ps
T810 /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.2195610405 Jul 30 05:20:46 PM PDT 24 Jul 30 05:20:48 PM PDT 24 14243822 ps
T164 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.2679586606 Jul 30 05:20:31 PM PDT 24 Jul 30 05:25:50 PM PDT 24 6165785354 ps
T811 /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.2963205242 Jul 30 05:20:26 PM PDT 24 Jul 30 05:20:35 PM PDT 24 719877755 ps
T812 /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.2559717209 Jul 30 05:20:46 PM PDT 24 Jul 30 05:20:51 PM PDT 24 65392781 ps
T813 /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.2951478570 Jul 30 05:21:33 PM PDT 24 Jul 30 05:21:34 PM PDT 24 14100591 ps
T333 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.1808346257 Jul 30 05:21:18 PM PDT 24 Jul 30 05:27:42 PM PDT 24 14830865792 ps
T814 /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.3750185364 Jul 30 05:20:30 PM PDT 24 Jul 30 05:20:41 PM PDT 24 229144026 ps
T815 /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.3106822056 Jul 30 05:20:39 PM PDT 24 Jul 30 05:27:12 PM PDT 24 5886444887 ps
T816 /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.1382774459 Jul 30 05:20:35 PM PDT 24 Jul 30 05:20:56 PM PDT 24 249150086 ps
T817 /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.2731475187 Jul 30 05:21:31 PM PDT 24 Jul 30 05:21:33 PM PDT 24 12043964 ps
T818 /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.3987791333 Jul 30 05:20:32 PM PDT 24 Jul 30 05:20:34 PM PDT 24 10897549 ps
T334 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.1650958610 Jul 30 05:20:51 PM PDT 24 Jul 30 05:28:57 PM PDT 24 40267472434 ps
T819 /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.3088539987 Jul 30 05:21:26 PM PDT 24 Jul 30 05:21:33 PM PDT 24 37354356 ps
T168 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.3308335035 Jul 30 05:21:04 PM PDT 24 Jul 30 05:31:37 PM PDT 24 32329995143 ps
T167 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.1507317475 Jul 30 05:20:49 PM PDT 24 Jul 30 05:25:47 PM PDT 24 14050759405 ps
T166 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.1738965429 Jul 30 05:20:57 PM PDT 24 Jul 30 05:31:36 PM PDT 24 9061802131 ps
T820 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.946683625 Jul 30 05:21:13 PM PDT 24 Jul 30 05:24:11 PM PDT 24 3300924821 ps
T821 /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.3103423454 Jul 30 05:21:00 PM PDT 24 Jul 30 05:21:15 PM PDT 24 715106106 ps
T335 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.4020034005 Jul 30 05:21:17 PM PDT 24 Jul 30 05:31:01 PM PDT 24 19060908086 ps
T822 /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.1459442166 Jul 30 05:21:12 PM PDT 24 Jul 30 05:21:14 PM PDT 24 9013226 ps
T823 /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.3424245858 Jul 30 05:20:36 PM PDT 24 Jul 30 05:20:42 PM PDT 24 70431300 ps
T824 /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.3907656273 Jul 30 05:21:07 PM PDT 24 Jul 30 05:21:52 PM PDT 24 2974151891 ps
T825 /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.744110710 Jul 30 05:21:12 PM PDT 24 Jul 30 05:21:41 PM PDT 24 1051910882 ps
T826 /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.1346646475 Jul 30 05:20:26 PM PDT 24 Jul 30 05:23:06 PM PDT 24 1154535878 ps
T827 /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.982891882 Jul 30 05:21:03 PM PDT 24 Jul 30 05:21:26 PM PDT 24 1460399404 ps
T828 /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.1585240802 Jul 30 05:20:33 PM PDT 24 Jul 30 05:20:42 PM PDT 24 96190997 ps

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.2638399373
Short name T1
Test name
Test status
Simulation time 47005598758 ps
CPU time 5124.02 seconds
Started Jul 30 05:32:06 PM PDT 24
Finished Jul 30 06:57:31 PM PDT 24
Peak memory 352248 kb
Host smart-c63cd807-d7aa-4589-b074-7c9c20fda3dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638399373 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.2638399373
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.1794488566
Short name T14
Test name
Test status
Simulation time 164550899 ps
CPU time 10.39 seconds
Started Jul 30 05:30:44 PM PDT 24
Finished Jul 30 05:30:54 PM PDT 24
Peak memory 248304 kb
Host smart-93837b5e-7210-45d9-ba7a-7b66eefea60a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1794488566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.1794488566
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.3697960301
Short name T201
Test name
Test status
Simulation time 8644141999 ps
CPU time 489.35 seconds
Started Jul 30 05:20:31 PM PDT 24
Finished Jul 30 05:28:41 PM PDT 24
Peak memory 240760 kb
Host smart-2481ac9e-773c-42cf-bb35-7e5d52ad849c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3697960301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.3697960301
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.2781094603
Short name T8
Test name
Test status
Simulation time 1725346212 ps
CPU time 24.22 seconds
Started Jul 30 05:29:43 PM PDT 24
Finished Jul 30 05:30:07 PM PDT 24
Peak memory 269800 kb
Host smart-b2105a9f-d490-494b-b7fe-9c6160213be7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2781094603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.2781094603
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.1541743499
Short name T62
Test name
Test status
Simulation time 234543662175 ps
CPU time 3717.26 seconds
Started Jul 30 05:35:52 PM PDT 24
Finished Jul 30 06:37:49 PM PDT 24
Peak memory 304404 kb
Host smart-8ecce9d1-1812-4e2a-ab96-a3bd0cd6cb6b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541743499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.1541743499
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.1275705994
Short name T87
Test name
Test status
Simulation time 29891777276 ps
CPU time 1332.16 seconds
Started Jul 30 05:34:09 PM PDT 24
Finished Jul 30 05:56:21 PM PDT 24
Peak memory 288596 kb
Host smart-e9766adb-31f6-4c6e-ad3f-0fbab9ec00aa
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275705994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.1275705994
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.1811581590
Short name T57
Test name
Test status
Simulation time 238285316533 ps
CPU time 1684.19 seconds
Started Jul 30 05:35:14 PM PDT 24
Finished Jul 30 06:03:18 PM PDT 24
Peak memory 289520 kb
Host smart-6763dc94-4fdd-4b4b-9fda-55a725db24bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811581590 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.1811581590
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.1634939213
Short name T139
Test name
Test status
Simulation time 4362898321 ps
CPU time 551.55 seconds
Started Jul 30 05:20:34 PM PDT 24
Finished Jul 30 05:29:46 PM PDT 24
Peak memory 265656 kb
Host smart-b710d7d6-8789-46fd-84f2-f071e3099387
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634939213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.1634939213
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.1473154769
Short name T25
Test name
Test status
Simulation time 26836124013 ps
CPU time 1898.21 seconds
Started Jul 30 05:31:44 PM PDT 24
Finished Jul 30 06:03:22 PM PDT 24
Peak memory 289092 kb
Host smart-47cc9412-a560-4f31-a975-c6c7b09ceaa1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473154769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.1473154769
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.1903890074
Short name T3
Test name
Test status
Simulation time 38403253162 ps
CPU time 2141.74 seconds
Started Jul 30 05:31:56 PM PDT 24
Finished Jul 30 06:07:38 PM PDT 24
Peak memory 289384 kb
Host smart-a7523603-6f81-4b5f-9921-9e9f39e4519d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903890074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.1903890074
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.1193956016
Short name T111
Test name
Test status
Simulation time 114633874890 ps
CPU time 1078.6 seconds
Started Jul 30 05:30:16 PM PDT 24
Finished Jul 30 05:48:15 PM PDT 24
Peak memory 282780 kb
Host smart-4b627025-3c9e-43dd-90f5-79b518eb83b9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193956016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.1193956016
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.2165165322
Short name T137
Test name
Test status
Simulation time 5420697746 ps
CPU time 367.19 seconds
Started Jul 30 05:20:49 PM PDT 24
Finished Jul 30 05:26:56 PM PDT 24
Peak memory 265632 kb
Host smart-1ec4380c-8887-4a03-9aed-97b9d3212aa1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2165165322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.2165165322
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.3238706283
Short name T115
Test name
Test status
Simulation time 13242528185 ps
CPU time 485 seconds
Started Jul 30 05:34:42 PM PDT 24
Finished Jul 30 05:42:47 PM PDT 24
Peak memory 271612 kb
Host smart-29faf9d2-9d1e-422f-b541-490ace82e8d3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238706283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.3238706283
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.2200238606
Short name T142
Test name
Test status
Simulation time 12819239453 ps
CPU time 952.05 seconds
Started Jul 30 05:20:58 PM PDT 24
Finished Jul 30 05:36:51 PM PDT 24
Peak memory 273188 kb
Host smart-ebf31458-6b6a-4428-99de-15a5313f1b7e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200238606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.2200238606
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.1963596629
Short name T177
Test name
Test status
Simulation time 922854809 ps
CPU time 76.4 seconds
Started Jul 30 05:20:56 PM PDT 24
Finished Jul 30 05:22:12 PM PDT 24
Peak memory 237784 kb
Host smart-deb800c0-cbde-4618-9204-db0be8698e21
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1963596629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.1963596629
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.2477927288
Short name T49
Test name
Test status
Simulation time 243329165223 ps
CPU time 3831.72 seconds
Started Jul 30 05:32:10 PM PDT 24
Finished Jul 30 06:36:03 PM PDT 24
Peak memory 296988 kb
Host smart-8353a199-9aef-403b-a54c-75f5bb379282
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477927288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.2477927288
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.2330785492
Short name T299
Test name
Test status
Simulation time 73294467065 ps
CPU time 3243.75 seconds
Started Jul 30 05:32:34 PM PDT 24
Finished Jul 30 06:26:38 PM PDT 24
Peak memory 289304 kb
Host smart-43ebbe0e-242f-4e88-8b41-84d3cbdffef9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330785492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.2330785492
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.773823911
Short name T157
Test name
Test status
Simulation time 5445312506 ps
CPU time 402.1 seconds
Started Jul 30 05:20:35 PM PDT 24
Finished Jul 30 05:27:18 PM PDT 24
Peak memory 266648 kb
Host smart-30282cc9-1460-4eb7-94fd-60fd9bb14a3c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=773823911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_error
s.773823911
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.768968263
Short name T327
Test name
Test status
Simulation time 12509611 ps
CPU time 1.7 seconds
Started Jul 30 05:20:57 PM PDT 24
Finished Jul 30 05:20:59 PM PDT 24
Peak memory 236632 kb
Host smart-73635e4a-1387-409a-be7c-d8d37d89c0d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=768968263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.768968263
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.3488457684
Short name T104
Test name
Test status
Simulation time 13310823723 ps
CPU time 530.96 seconds
Started Jul 30 05:31:16 PM PDT 24
Finished Jul 30 05:40:07 PM PDT 24
Peak memory 248316 kb
Host smart-a86cd15d-3e8f-4c78-ad6d-fff18325a00b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488457684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.3488457684
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.3870439662
Short name T4
Test name
Test status
Simulation time 24829260512 ps
CPU time 599.65 seconds
Started Jul 30 05:29:25 PM PDT 24
Finished Jul 30 05:39:25 PM PDT 24
Peak memory 264776 kb
Host smart-12463f88-f2c6-42f9-8442-12f54a3bb6ea
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870439662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.3870439662
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.574462354
Short name T160
Test name
Test status
Simulation time 18717520249 ps
CPU time 603.45 seconds
Started Jul 30 05:21:05 PM PDT 24
Finished Jul 30 05:31:08 PM PDT 24
Peak memory 273756 kb
Host smart-5f11e624-5533-4a59-bef7-a9a235cc40e8
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574462354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.574462354
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.4135525509
Short name T92
Test name
Test status
Simulation time 240089119019 ps
CPU time 3325.62 seconds
Started Jul 30 05:29:42 PM PDT 24
Finished Jul 30 06:25:08 PM PDT 24
Peak memory 288352 kb
Host smart-d694c039-1a9e-424b-b328-3ebc64714466
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135525509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.4135525509
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.4285843784
Short name T162
Test name
Test status
Simulation time 38178697260 ps
CPU time 256.17 seconds
Started Jul 30 05:20:41 PM PDT 24
Finished Jul 30 05:24:57 PM PDT 24
Peak memory 271296 kb
Host smart-d22db2c2-2352-43e2-851e-d71cb454c0cb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4285843784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.4285843784
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.1894185936
Short name T297
Test name
Test status
Simulation time 47211987294 ps
CPU time 485.99 seconds
Started Jul 30 05:29:46 PM PDT 24
Finished Jul 30 05:37:52 PM PDT 24
Peak memory 248224 kb
Host smart-9ffda3fa-5948-42ad-9b0a-60e91e44a1bb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894185936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.1894185936
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.22251663
Short name T131
Test name
Test status
Simulation time 2748510746 ps
CPU time 329.93 seconds
Started Jul 30 05:20:49 PM PDT 24
Finished Jul 30 05:26:19 PM PDT 24
Peak memory 270128 kb
Host smart-3abe66d5-09d2-474f-983c-c418c9811699
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22251663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.22251663
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.3606254026
Short name T124
Test name
Test status
Simulation time 450168563811 ps
CPU time 8504.72 seconds
Started Jul 30 05:29:53 PM PDT 24
Finished Jul 30 07:51:39 PM PDT 24
Peak memory 365232 kb
Host smart-1520a452-b0fb-41fc-aef0-e7c2ee3215eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606254026 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.3606254026
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.1376102526
Short name T26
Test name
Test status
Simulation time 477459219408 ps
CPU time 2270.16 seconds
Started Jul 30 05:29:26 PM PDT 24
Finished Jul 30 06:07:16 PM PDT 24
Peak memory 288764 kb
Host smart-28a6ffaa-7fe7-48bd-a105-41ada0f08fa1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376102526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.1376102526
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.970010800
Short name T120
Test name
Test status
Simulation time 28824684089 ps
CPU time 1698.79 seconds
Started Jul 30 05:29:16 PM PDT 24
Finished Jul 30 05:57:35 PM PDT 24
Peak memory 272892 kb
Host smart-6402690a-d15a-4435-b78e-027a4203f1a3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970010800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.970010800
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.2045134815
Short name T302
Test name
Test status
Simulation time 48919321591 ps
CPU time 472.76 seconds
Started Jul 30 05:34:07 PM PDT 24
Finished Jul 30 05:42:00 PM PDT 24
Peak memory 256060 kb
Host smart-9e2c3048-c86f-402c-bd86-69cd8c035ff6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045134815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.2045134815
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.3786686055
Short name T145
Test name
Test status
Simulation time 4204022160 ps
CPU time 332.87 seconds
Started Jul 30 05:21:23 PM PDT 24
Finished Jul 30 05:26:56 PM PDT 24
Peak memory 265636 kb
Host smart-3a4f9308-8e22-44e8-a178-290beb80cf84
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3786686055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.3786686055
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.1233529388
Short name T310
Test name
Test status
Simulation time 121580248636 ps
CPU time 2103.96 seconds
Started Jul 30 05:34:09 PM PDT 24
Finished Jul 30 06:09:14 PM PDT 24
Peak memory 288744 kb
Host smart-31f83c73-fc51-428e-a5cd-4c81b801d425
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233529388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.1233529388
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.2609558191
Short name T70
Test name
Test status
Simulation time 117859905866 ps
CPU time 5918.44 seconds
Started Jul 30 05:33:06 PM PDT 24
Finished Jul 30 07:11:45 PM PDT 24
Peak memory 348144 kb
Host smart-97126fac-0e8c-4ca3-b9f1-8c7c887243a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609558191 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.2609558191
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.3247432656
Short name T324
Test name
Test status
Simulation time 32682585015 ps
CPU time 2171.44 seconds
Started Jul 30 05:33:20 PM PDT 24
Finished Jul 30 06:09:31 PM PDT 24
Peak memory 284256 kb
Host smart-f968bdbd-b065-405b-9a42-ec4e897cb5f5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247432656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.3247432656
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.428001340
Short name T140
Test name
Test status
Simulation time 26711191883 ps
CPU time 147.48 seconds
Started Jul 30 05:20:27 PM PDT 24
Finished Jul 30 05:22:54 PM PDT 24
Peak memory 271976 kb
Host smart-f09a6f6c-5590-40a4-8cb1-45d1233ab40c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=428001340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_error
s.428001340
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.1917471793
Short name T65
Test name
Test status
Simulation time 15551098874 ps
CPU time 252.92 seconds
Started Jul 30 05:32:41 PM PDT 24
Finished Jul 30 05:36:54 PM PDT 24
Peak memory 255412 kb
Host smart-9e456337-7ada-4908-8937-99dbe852654a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917471793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.1917471793
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.1738965429
Short name T166
Test name
Test status
Simulation time 9061802131 ps
CPU time 639.23 seconds
Started Jul 30 05:20:57 PM PDT 24
Finished Jul 30 05:31:36 PM PDT 24
Peak memory 265608 kb
Host smart-776055d8-00ef-48e5-8c79-b2718a6f5fae
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738965429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.1738965429
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.3968124023
Short name T574
Test name
Test status
Simulation time 28157034797 ps
CPU time 3316.68 seconds
Started Jul 30 05:34:08 PM PDT 24
Finished Jul 30 06:29:25 PM PDT 24
Peak memory 322188 kb
Host smart-bb6930ec-0824-4577-9be0-b099660bd1e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968124023 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.3968124023
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.4191732295
Short name T52
Test name
Test status
Simulation time 366124526490 ps
CPU time 4027.23 seconds
Started Jul 30 05:33:11 PM PDT 24
Finished Jul 30 06:40:18 PM PDT 24
Peak memory 297580 kb
Host smart-39de0b4e-1304-4ec8-90e9-8893b48f2ff5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191732295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.4191732295
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.1229791632
Short name T91
Test name
Test status
Simulation time 75577378847 ps
CPU time 7585.96 seconds
Started Jul 30 05:29:24 PM PDT 24
Finished Jul 30 07:35:51 PM PDT 24
Peak memory 393948 kb
Host smart-edf6201c-399f-43b6-869c-2b680226192a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229791632 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.1229791632
Directory /workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.4020034005
Short name T335
Test name
Test status
Simulation time 19060908086 ps
CPU time 583.77 seconds
Started Jul 30 05:21:17 PM PDT 24
Finished Jul 30 05:31:01 PM PDT 24
Peak memory 265660 kb
Host smart-831a7255-349b-430a-95a7-aaacbc94630e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020034005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.4020034005
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.1559942477
Short name T329
Test name
Test status
Simulation time 9922445 ps
CPU time 1.75 seconds
Started Jul 30 05:21:26 PM PDT 24
Finished Jul 30 05:21:28 PM PDT 24
Peak memory 236764 kb
Host smart-acb7f2f4-ca0a-443e-a701-53f727963bc7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1559942477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.1559942477
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.616733315
Short name T300
Test name
Test status
Simulation time 46223603897 ps
CPU time 482.31 seconds
Started Jul 30 05:29:19 PM PDT 24
Finished Jul 30 05:37:21 PM PDT 24
Peak memory 256152 kb
Host smart-b7a8d832-777d-4123-8c1d-9d6d55a3be04
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616733315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.616733315
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.3586878000
Short name T292
Test name
Test status
Simulation time 47443057551 ps
CPU time 470.28 seconds
Started Jul 30 05:33:11 PM PDT 24
Finished Jul 30 05:41:01 PM PDT 24
Peak memory 248412 kb
Host smart-7f6d2589-1b77-42c1-978f-6057223f6c36
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586878000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.3586878000
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.2520256516
Short name T257
Test name
Test status
Simulation time 3610084007 ps
CPU time 39 seconds
Started Jul 30 05:34:23 PM PDT 24
Finished Jul 30 05:35:02 PM PDT 24
Peak memory 247524 kb
Host smart-7862b0cc-3158-4582-a74a-ffa86bc14508
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25202
56516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.2520256516
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.3222796697
Short name T107
Test name
Test status
Simulation time 148608527061 ps
CPU time 2301.96 seconds
Started Jul 30 05:30:43 PM PDT 24
Finished Jul 30 06:09:06 PM PDT 24
Peak memory 272256 kb
Host smart-84337965-b697-42cb-9e72-420028e3b9c7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222796697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.3222796697
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.1936465995
Short name T530
Test name
Test status
Simulation time 197454813678 ps
CPU time 4099.3 seconds
Started Jul 30 05:34:55 PM PDT 24
Finished Jul 30 06:43:15 PM PDT 24
Peak memory 305068 kb
Host smart-04a6cf58-bbff-4092-bb5e-335cae519635
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936465995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.1936465995
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.2353472569
Short name T50
Test name
Test status
Simulation time 51414572395 ps
CPU time 2820.1 seconds
Started Jul 30 05:31:48 PM PDT 24
Finished Jul 30 06:18:49 PM PDT 24
Peak memory 288992 kb
Host smart-2a381241-4e1c-4564-b162-9421ece42216
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353472569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.2353472569
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.2134207734
Short name T127
Test name
Test status
Simulation time 265424782213 ps
CPU time 5365.98 seconds
Started Jul 30 05:29:45 PM PDT 24
Finished Jul 30 06:59:12 PM PDT 24
Peak memory 330420 kb
Host smart-7462487c-fb16-4788-82b7-2e21e4e3b457
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134207734 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.2134207734
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.2132838944
Short name T169
Test name
Test status
Simulation time 213003204 ps
CPU time 4.18 seconds
Started Jul 30 05:20:26 PM PDT 24
Finished Jul 30 05:20:30 PM PDT 24
Peak memory 237816 kb
Host smart-5751a8d8-52a4-4669-b187-7c6bf03e4052
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2132838944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.2132838944
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.2591736571
Short name T226
Test name
Test status
Simulation time 43806467 ps
CPU time 3.6 seconds
Started Jul 30 05:29:18 PM PDT 24
Finished Jul 30 05:29:21 PM PDT 24
Peak memory 248572 kb
Host smart-b37ad929-bfbc-43da-a63f-b4423b7514a2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2591736571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.2591736571
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.2730774557
Short name T217
Test name
Test status
Simulation time 47969940 ps
CPU time 4.28 seconds
Started Jul 30 05:29:25 PM PDT 24
Finished Jul 30 05:29:30 PM PDT 24
Peak memory 248640 kb
Host smart-cf008486-5167-4c8d-af81-01bae0c1fc5f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2730774557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.2730774557
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.3896276115
Short name T215
Test name
Test status
Simulation time 177099250 ps
CPU time 4.02 seconds
Started Jul 30 05:30:36 PM PDT 24
Finished Jul 30 05:30:40 PM PDT 24
Peak memory 248652 kb
Host smart-1577107d-1055-49ce-b286-f3c45e928c9d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3896276115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.3896276115
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.2518001683
Short name T225
Test name
Test status
Simulation time 19782558 ps
CPU time 2.98 seconds
Started Jul 30 05:30:53 PM PDT 24
Finished Jul 30 05:30:56 PM PDT 24
Peak memory 248588 kb
Host smart-2c45a849-b2a3-48d5-bb15-7fc8b53011ec
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2518001683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.2518001683
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.463907100
Short name T690
Test name
Test status
Simulation time 1135525825127 ps
CPU time 8150.21 seconds
Started Jul 30 05:30:19 PM PDT 24
Finished Jul 30 07:46:10 PM PDT 24
Peak memory 369700 kb
Host smart-cfa58f17-6569-451e-9f20-5a21c2bdc213
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463907100 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.463907100
Directory /workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.1259616353
Short name T293
Test name
Test status
Simulation time 7880532873 ps
CPU time 310.33 seconds
Started Jul 30 05:30:28 PM PDT 24
Finished Jul 30 05:35:39 PM PDT 24
Peak memory 248224 kb
Host smart-053eb51d-21a2-454e-bc75-1426bd4ca99c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259616353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.1259616353
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.67250720
Short name T285
Test name
Test status
Simulation time 697678644 ps
CPU time 36.2 seconds
Started Jul 30 05:31:15 PM PDT 24
Finished Jul 30 05:31:52 PM PDT 24
Peak memory 255516 kb
Host smart-7df2f309-d27b-4960-a8d5-a8da4c7a5786
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67250
720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.67250720
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.183384949
Short name T279
Test name
Test status
Simulation time 22574565087 ps
CPU time 1450.64 seconds
Started Jul 30 05:29:54 PM PDT 24
Finished Jul 30 05:54:05 PM PDT 24
Peak memory 272992 kb
Host smart-b5261795-0c76-4de6-94ca-e8e2bdf124a9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183384949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.183384949
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.2843332751
Short name T46
Test name
Test status
Simulation time 960336871 ps
CPU time 60.05 seconds
Started Jul 30 05:29:43 PM PDT 24
Finished Jul 30 05:30:43 PM PDT 24
Peak memory 247800 kb
Host smart-b01a50db-0068-4e7d-86fa-2df7c9dca646
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28433
32751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.2843332751
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.3056699422
Short name T181
Test name
Test status
Simulation time 321316280 ps
CPU time 28.22 seconds
Started Jul 30 05:21:05 PM PDT 24
Finished Jul 30 05:21:33 PM PDT 24
Peak memory 237812 kb
Host smart-5430f8e1-4cb2-4f12-9ef2-d2dc3503431f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3056699422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.3056699422
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.1110998835
Short name T658
Test name
Test status
Simulation time 158140811835 ps
CPU time 5553.57 seconds
Started Jul 30 05:30:36 PM PDT 24
Finished Jul 30 07:03:10 PM PDT 24
Peak memory 321216 kb
Host smart-307cbe02-98f3-445b-8103-4277f52bfbe6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110998835 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.1110998835
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.1521221293
Short name T51
Test name
Test status
Simulation time 194483923237 ps
CPU time 2892.04 seconds
Started Jul 30 05:35:10 PM PDT 24
Finished Jul 30 06:23:23 PM PDT 24
Peak memory 289144 kb
Host smart-259cc95a-d732-45a4-8d69-e1eb5d4dc24e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521221293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.1521221293
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.867556371
Short name T136
Test name
Test status
Simulation time 24109344720 ps
CPU time 276.49 seconds
Started Jul 30 05:21:12 PM PDT 24
Finished Jul 30 05:25:48 PM PDT 24
Peak memory 265528 kb
Host smart-bc01410c-fb05-4606-bd0d-67c93f453a83
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=867556371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_erro
rs.867556371
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.3308335035
Short name T168
Test name
Test status
Simulation time 32329995143 ps
CPU time 632.85 seconds
Started Jul 30 05:21:04 PM PDT 24
Finished Jul 30 05:31:37 PM PDT 24
Peak memory 273744 kb
Host smart-fe50fd54-799b-4dad-b4a3-040bb7cb8785
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308335035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.3308335035
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.1282964185
Short name T745
Test name
Test status
Simulation time 8279017 ps
CPU time 1.58 seconds
Started Jul 30 05:21:08 PM PDT 24
Finished Jul 30 05:21:09 PM PDT 24
Peak memory 236816 kb
Host smart-840745f2-dac9-4b08-ae06-1346cb494953
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1282964185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.1282964185
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.600879986
Short name T112
Test name
Test status
Simulation time 171209920178 ps
CPU time 6656.46 seconds
Started Jul 30 05:29:25 PM PDT 24
Finished Jul 30 07:20:22 PM PDT 24
Peak memory 336964 kb
Host smart-1059fe74-a4a4-4055-a52f-ed9f5e6f155a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600879986 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.600879986
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.1160973961
Short name T55
Test name
Test status
Simulation time 602441838 ps
CPU time 42.8 seconds
Started Jul 30 05:30:12 PM PDT 24
Finished Jul 30 05:30:54 PM PDT 24
Peak memory 255836 kb
Host smart-59f4da3d-9f64-4581-8e03-f861aee2d17f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11609
73961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.1160973961
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.3838831921
Short name T262
Test name
Test status
Simulation time 898055522 ps
CPU time 53.51 seconds
Started Jul 30 05:30:19 PM PDT 24
Finished Jul 30 05:31:12 PM PDT 24
Peak memory 255776 kb
Host smart-7a0ad95c-566f-47e3-b28e-de8ea31330bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38388
31921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.3838831921
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.3210127361
Short name T282
Test name
Test status
Simulation time 33702240344 ps
CPU time 775.33 seconds
Started Jul 30 05:32:27 PM PDT 24
Finished Jul 30 05:45:23 PM PDT 24
Peak memory 272920 kb
Host smart-b30d8cb8-ab3f-44f3-ad10-145c421f2c01
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210127361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.3210127361
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.2917557906
Short name T17
Test name
Test status
Simulation time 13966668713 ps
CPU time 595.42 seconds
Started Jul 30 05:30:41 PM PDT 24
Finished Jul 30 05:40:36 PM PDT 24
Peak memory 248372 kb
Host smart-d2f165ff-1fe4-4b68-bd12-451ad3a80a30
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917557906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.2917557906
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.732476019
Short name T275
Test name
Test status
Simulation time 22025811409 ps
CPU time 2081.52 seconds
Started Jul 30 05:30:52 PM PDT 24
Finished Jul 30 06:05:34 PM PDT 24
Peak memory 288944 kb
Host smart-82d22be6-730f-4040-8859-f99aeceee3bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732476019 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.732476019
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.1519885207
Short name T321
Test name
Test status
Simulation time 171258653378 ps
CPU time 2280.7 seconds
Started Jul 30 05:31:03 PM PDT 24
Finished Jul 30 06:09:04 PM PDT 24
Peak memory 272952 kb
Host smart-483369c8-1f89-424f-9e91-b00187433a90
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519885207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.1519885207
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.3542076680
Short name T281
Test name
Test status
Simulation time 37130249420 ps
CPU time 360.96 seconds
Started Jul 30 05:31:28 PM PDT 24
Finished Jul 30 05:37:29 PM PDT 24
Peak memory 248428 kb
Host smart-19713bf6-6605-4073-baea-0549f3d8f094
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542076680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.3542076680
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.4050063026
Short name T81
Test name
Test status
Simulation time 227223164973 ps
CPU time 3479.44 seconds
Started Jul 30 05:32:10 PM PDT 24
Finished Jul 30 06:30:10 PM PDT 24
Peak memory 288796 kb
Host smart-4f525e9e-727e-4732-ad79-1eae0c5388c7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050063026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.4050063026
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.1558899906
Short name T13
Test name
Test status
Simulation time 76845263747 ps
CPU time 1671.15 seconds
Started Jul 30 05:32:13 PM PDT 24
Finished Jul 30 06:00:04 PM PDT 24
Peak memory 289392 kb
Host smart-1890ba91-66df-4624-9084-8c3e0f596b37
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558899906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.1558899906
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.24828088
Short name T268
Test name
Test status
Simulation time 479995291 ps
CPU time 24.44 seconds
Started Jul 30 05:32:34 PM PDT 24
Finished Jul 30 05:32:58 PM PDT 24
Peak memory 255852 kb
Host smart-5de5ce90-d29b-47b1-a537-bb1163990a85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24828
088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.24828088
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.1123588015
Short name T128
Test name
Test status
Simulation time 612410256449 ps
CPU time 5423.33 seconds
Started Jul 30 05:33:09 PM PDT 24
Finished Jul 30 07:03:33 PM PDT 24
Peak memory 352468 kb
Host smart-ef9dcded-01c3-40e5-bf38-fa95ebe41e0c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123588015 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.1123588015
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.2473126088
Short name T90
Test name
Test status
Simulation time 18401592534 ps
CPU time 809.85 seconds
Started Jul 30 05:34:17 PM PDT 24
Finished Jul 30 05:47:48 PM PDT 24
Peak memory 272424 kb
Host smart-82e6df05-29cb-42f3-b823-62574f5dce98
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473126088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.2473126088
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.3055788730
Short name T102
Test name
Test status
Simulation time 548195162 ps
CPU time 31.82 seconds
Started Jul 30 05:34:28 PM PDT 24
Finished Jul 30 05:35:00 PM PDT 24
Peak memory 248068 kb
Host smart-d21ee631-6d93-4464-b432-6721f361455e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30557
88730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.3055788730
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.3472570167
Short name T63
Test name
Test status
Simulation time 1274418417 ps
CPU time 84.37 seconds
Started Jul 30 05:35:07 PM PDT 24
Finished Jul 30 05:36:32 PM PDT 24
Peak memory 249256 kb
Host smart-a0f851ce-da87-48c4-896c-b7792233d1fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34725
70167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.3472570167
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.1229603457
Short name T277
Test name
Test status
Simulation time 1666896814 ps
CPU time 143.45 seconds
Started Jul 30 05:29:54 PM PDT 24
Finished Jul 30 05:32:17 PM PDT 24
Peak memory 255812 kb
Host smart-1a5e85b8-f5c3-4958-be6f-3d73f3ab6552
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12296
03457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.1229603457
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.2461592720
Short name T151
Test name
Test status
Simulation time 2168768604 ps
CPU time 351.54 seconds
Started Jul 30 05:21:13 PM PDT 24
Finished Jul 30 05:27:05 PM PDT 24
Peak memory 265496 kb
Host smart-fdc97a16-c938-4054-94e8-c19c7aa8a6d3
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461592720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.2461592720
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.638718665
Short name T178
Test name
Test status
Simulation time 261206284 ps
CPU time 4.02 seconds
Started Jul 30 05:20:35 PM PDT 24
Finished Jul 30 05:20:39 PM PDT 24
Peak memory 237656 kb
Host smart-d0ffec54-0262-4da6-b8d3-a2c82db44c88
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=638718665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.638718665
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.946683625
Short name T820
Test name
Test status
Simulation time 3300924821 ps
CPU time 177.53 seconds
Started Jul 30 05:21:13 PM PDT 24
Finished Jul 30 05:24:11 PM PDT 24
Peak memory 265456 kb
Host smart-bc656c2b-d8e7-4228-b26a-5ed0bb3fddce
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=946683625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_erro
rs.946683625
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.1937306927
Short name T182
Test name
Test status
Simulation time 461652828 ps
CPU time 45.66 seconds
Started Jul 30 05:21:01 PM PDT 24
Finished Jul 30 05:21:46 PM PDT 24
Peak memory 240604 kb
Host smart-5ab8ba91-1da6-4a83-bf21-d99694bee66d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1937306927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.1937306927
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.2279190769
Short name T185
Test name
Test status
Simulation time 112518100 ps
CPU time 3.03 seconds
Started Jul 30 05:21:17 PM PDT 24
Finished Jul 30 05:21:20 PM PDT 24
Peak memory 238716 kb
Host smart-f6cc8b6f-fbcd-4ff3-bdc2-85d19de46fdd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2279190769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.2279190769
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.3655350239
Short name T180
Test name
Test status
Simulation time 609626934 ps
CPU time 42.52 seconds
Started Jul 30 05:21:06 PM PDT 24
Finished Jul 30 05:21:49 PM PDT 24
Peak memory 240644 kb
Host smart-a92a11be-34f5-47af-8bbe-7f4ce4f2e676
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3655350239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.3655350239
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.2773996313
Short name T175
Test name
Test status
Simulation time 931918357 ps
CPU time 62 seconds
Started Jul 30 05:21:12 PM PDT 24
Finished Jul 30 05:22:14 PM PDT 24
Peak memory 237736 kb
Host smart-b3e57f0f-1d53-4935-9755-836aae912bd1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2773996313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.2773996313
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.473928484
Short name T189
Test name
Test status
Simulation time 5175846348 ps
CPU time 92.53 seconds
Started Jul 30 05:21:08 PM PDT 24
Finished Jul 30 05:22:41 PM PDT 24
Peak memory 240728 kb
Host smart-87be1e56-63df-418b-8860-6bc232826a9b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=473928484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.473928484
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.1226149873
Short name T186
Test name
Test status
Simulation time 363688134 ps
CPU time 51.4 seconds
Started Jul 30 05:21:09 PM PDT 24
Finished Jul 30 05:22:01 PM PDT 24
Peak memory 248800 kb
Host smart-8d26ca05-3f14-4a31-8c50-c1d9fa7d9af9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1226149873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.1226149873
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.766934476
Short name T176
Test name
Test status
Simulation time 60314586 ps
CPU time 2.37 seconds
Started Jul 30 05:21:13 PM PDT 24
Finished Jul 30 05:21:16 PM PDT 24
Peak memory 237672 kb
Host smart-3a00e992-d8bb-4cee-8b51-34ece99b679b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=766934476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.766934476
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.2457256808
Short name T152
Test name
Test status
Simulation time 3603667062 ps
CPU time 247.65 seconds
Started Jul 30 05:20:38 PM PDT 24
Finished Jul 30 05:24:45 PM PDT 24
Peak memory 266628 kb
Host smart-369679d3-fc87-42f2-8052-25794f1d2a25
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2457256808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.2457256808
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.383616038
Short name T183
Test name
Test status
Simulation time 50558698 ps
CPU time 2.9 seconds
Started Jul 30 05:20:41 PM PDT 24
Finished Jul 30 05:20:44 PM PDT 24
Peak memory 236804 kb
Host smart-a3ac4de9-bda9-4384-beee-03bbf586c8a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=383616038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.383616038
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.3015745243
Short name T153
Test name
Test status
Simulation time 17618662959 ps
CPU time 130.25 seconds
Started Jul 30 05:20:53 PM PDT 24
Finished Jul 30 05:23:03 PM PDT 24
Peak memory 257436 kb
Host smart-ea39081c-ca18-4ee7-9fb9-67dbea65f5e7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3015745243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.3015745243
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.1765147420
Short name T187
Test name
Test status
Simulation time 88930318 ps
CPU time 2.73 seconds
Started Jul 30 05:20:30 PM PDT 24
Finished Jul 30 05:20:33 PM PDT 24
Peak memory 238148 kb
Host smart-cc4c82dc-bdaf-4244-8656-70d92f46279b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1765147420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.1765147420
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.4166902136
Short name T171
Test name
Test status
Simulation time 56785309 ps
CPU time 2.92 seconds
Started Jul 30 05:21:17 PM PDT 24
Finished Jul 30 05:21:20 PM PDT 24
Peak memory 236776 kb
Host smart-d690e3c6-2fb2-4c80-bd69-e65f43104d7e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4166902136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.4166902136
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.423799571
Short name T188
Test name
Test status
Simulation time 359854052 ps
CPU time 22.52 seconds
Started Jul 30 05:20:48 PM PDT 24
Finished Jul 30 05:21:11 PM PDT 24
Peak memory 240620 kb
Host smart-c1aa874f-712b-4616-8645-a130a3f26f78
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=423799571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.423799571
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.3802449430
Short name T179
Test name
Test status
Simulation time 222749181 ps
CPU time 1.97 seconds
Started Jul 30 05:20:52 PM PDT 24
Finished Jul 30 05:20:54 PM PDT 24
Peak memory 236820 kb
Host smart-0bf42211-7a48-423e-9ede-efc341a4e895
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3802449430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.3802449430
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.2341242405
Short name T184
Test name
Test status
Simulation time 2598587870 ps
CPU time 48.42 seconds
Started Jul 30 05:20:58 PM PDT 24
Finished Jul 30 05:21:46 PM PDT 24
Peak memory 240684 kb
Host smart-d0bff7f8-be1e-4a17-bb1b-8617eb2031f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2341242405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.2341242405
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.3713397941
Short name T23
Test name
Test status
Simulation time 49862299782 ps
CPU time 1611.88 seconds
Started Jul 30 05:36:18 PM PDT 24
Finished Jul 30 06:03:10 PM PDT 24
Peak memory 305800 kb
Host smart-804f518c-db3e-4731-94da-2bea229767c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713397941 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.3713397941
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.1346646475
Short name T826
Test name
Test status
Simulation time 1154535878 ps
CPU time 159.78 seconds
Started Jul 30 05:20:26 PM PDT 24
Finished Jul 30 05:23:06 PM PDT 24
Peak memory 241052 kb
Host smart-eaa6aa7d-50bd-495c-acca-606d0226949d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1346646475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.1346646475
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.748003691
Short name T765
Test name
Test status
Simulation time 2948943478 ps
CPU time 237.14 seconds
Started Jul 30 05:20:27 PM PDT 24
Finished Jul 30 05:24:24 PM PDT 24
Peak memory 240676 kb
Host smart-7c39724c-3913-4042-a582-09389f6e02ae
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=748003691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.748003691
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.2963205242
Short name T811
Test name
Test status
Simulation time 719877755 ps
CPU time 8.34 seconds
Started Jul 30 05:20:26 PM PDT 24
Finished Jul 30 05:20:35 PM PDT 24
Peak memory 240644 kb
Host smart-71be9778-7941-495a-bedc-a6accf5c5ba8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2963205242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.2963205242
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.979407454
Short name T793
Test name
Test status
Simulation time 150423122 ps
CPU time 11.21 seconds
Started Jul 30 05:20:34 PM PDT 24
Finished Jul 30 05:20:46 PM PDT 24
Peak memory 240724 kb
Host smart-acf019cc-a122-49ec-868d-68eaed32babd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979407454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 0.alert_handler_csr_mem_rw_with_rand_reset.979407454
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.2060326226
Short name T209
Test name
Test status
Simulation time 19825111 ps
CPU time 3.27 seconds
Started Jul 30 05:20:25 PM PDT 24
Finished Jul 30 05:20:29 PM PDT 24
Peak memory 236752 kb
Host smart-90a40a46-2aee-467a-b59a-0153464cf546
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2060326226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.2060326226
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.3856259001
Short name T789
Test name
Test status
Simulation time 11055331 ps
CPU time 1.41 seconds
Started Jul 30 05:20:34 PM PDT 24
Finished Jul 30 05:20:35 PM PDT 24
Peak memory 235772 kb
Host smart-d96049a9-f883-41f5-81a2-327443a1e971
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3856259001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.3856259001
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.2846800160
Short name T804
Test name
Test status
Simulation time 91319363 ps
CPU time 14.24 seconds
Started Jul 30 05:20:31 PM PDT 24
Finished Jul 30 05:20:46 PM PDT 24
Peak memory 240620 kb
Host smart-802ea536-c6c2-4118-a7a0-522b122d144a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2846800160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.2846800160
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.1077092295
Short name T130
Test name
Test status
Simulation time 8825529423 ps
CPU time 387.23 seconds
Started Jul 30 05:20:21 PM PDT 24
Finished Jul 30 05:26:49 PM PDT 24
Peak memory 265616 kb
Host smart-8570b466-01dd-423f-8c3b-59b5753a0026
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077092295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.1077092295
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.1585240802
Short name T828
Test name
Test status
Simulation time 96190997 ps
CPU time 8.02 seconds
Started Jul 30 05:20:33 PM PDT 24
Finished Jul 30 05:20:42 PM PDT 24
Peak memory 252972 kb
Host smart-e5ec1985-3f75-4bbb-9e11-f2f1d19c2657
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1585240802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.1585240802
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.2106547558
Short name T207
Test name
Test status
Simulation time 20572332917 ps
CPU time 268.87 seconds
Started Jul 30 05:20:32 PM PDT 24
Finished Jul 30 05:25:01 PM PDT 24
Peak memory 240772 kb
Host smart-91a83f70-18e9-46af-a436-61bab55bba46
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2106547558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.2106547558
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.1096121379
Short name T803
Test name
Test status
Simulation time 192598761 ps
CPU time 3.87 seconds
Started Jul 30 05:20:34 PM PDT 24
Finished Jul 30 05:20:38 PM PDT 24
Peak memory 248852 kb
Host smart-21f1d36d-d759-4272-837f-9f3f82c6d18a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1096121379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.1096121379
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.3424245858
Short name T823
Test name
Test status
Simulation time 70431300 ps
CPU time 6.14 seconds
Started Jul 30 05:20:36 PM PDT 24
Finished Jul 30 05:20:42 PM PDT 24
Peak memory 248928 kb
Host smart-058df759-7083-4b52-8131-652d188a972f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424245858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.3424245858
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.3067554422
Short name T774
Test name
Test status
Simulation time 66507702 ps
CPU time 3.63 seconds
Started Jul 30 05:20:32 PM PDT 24
Finished Jul 30 05:20:35 PM PDT 24
Peak memory 237692 kb
Host smart-1be7b8c8-2b44-4bdc-82c3-d822ea9b67ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3067554422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.3067554422
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.3987791333
Short name T818
Test name
Test status
Simulation time 10897549 ps
CPU time 1.28 seconds
Started Jul 30 05:20:32 PM PDT 24
Finished Jul 30 05:20:34 PM PDT 24
Peak memory 237672 kb
Host smart-4d7ec065-6d64-4cc2-a208-8244e59c1fe6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3987791333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.3987791333
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.1976431604
Short name T725
Test name
Test status
Simulation time 92587212 ps
CPU time 12.64 seconds
Started Jul 30 05:20:35 PM PDT 24
Finished Jul 30 05:20:48 PM PDT 24
Peak memory 240644 kb
Host smart-d7a73ba6-66ee-4de9-9b42-5cbd352f3902
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1976431604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.1976431604
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.2679586606
Short name T164
Test name
Test status
Simulation time 6165785354 ps
CPU time 318.65 seconds
Started Jul 30 05:20:31 PM PDT 24
Finished Jul 30 05:25:50 PM PDT 24
Peak memory 271692 kb
Host smart-ba9d4fe0-52d2-45cb-9d9f-d003a781fa63
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2679586606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.2679586606
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.3750185364
Short name T814
Test name
Test status
Simulation time 229144026 ps
CPU time 10.44 seconds
Started Jul 30 05:20:30 PM PDT 24
Finished Jul 30 05:20:41 PM PDT 24
Peak memory 248384 kb
Host smart-6fec821b-2ec7-4d09-aaa5-62fb7b5f6264
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3750185364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.3750185364
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.3103423454
Short name T821
Test name
Test status
Simulation time 715106106 ps
CPU time 14.98 seconds
Started Jul 30 05:21:00 PM PDT 24
Finished Jul 30 05:21:15 PM PDT 24
Peak memory 251920 kb
Host smart-2e775da6-fce8-4305-988b-a2372e972e60
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103423454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.3103423454
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.3002883924
Short name T712
Test name
Test status
Simulation time 20049136 ps
CPU time 4.18 seconds
Started Jul 30 05:21:01 PM PDT 24
Finished Jul 30 05:21:05 PM PDT 24
Peak memory 237528 kb
Host smart-35fc3072-429e-4fa0-b33a-0f12a5ddc69f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3002883924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.3002883924
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.1459442166
Short name T822
Test name
Test status
Simulation time 9013226 ps
CPU time 1.27 seconds
Started Jul 30 05:21:12 PM PDT 24
Finished Jul 30 05:21:14 PM PDT 24
Peak memory 235564 kb
Host smart-4a372ac9-406d-4cfe-a8a8-86350240df63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1459442166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.1459442166
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.744110710
Short name T825
Test name
Test status
Simulation time 1051910882 ps
CPU time 28.84 seconds
Started Jul 30 05:21:12 PM PDT 24
Finished Jul 30 05:21:41 PM PDT 24
Peak memory 248700 kb
Host smart-b9891bad-75e4-4302-91a2-b31b3d1ccd0a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=744110710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_out
standing.744110710
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.2781154979
Short name T748
Test name
Test status
Simulation time 221861113 ps
CPU time 17.28 seconds
Started Jul 30 05:21:12 PM PDT 24
Finished Jul 30 05:21:29 PM PDT 24
Peak memory 248752 kb
Host smart-f34fcf4c-35ab-41f1-94c1-23b6364fb98b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2781154979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.2781154979
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.1952002361
Short name T336
Test name
Test status
Simulation time 43061979 ps
CPU time 7.83 seconds
Started Jul 30 05:21:01 PM PDT 24
Finished Jul 30 05:21:09 PM PDT 24
Peak memory 248880 kb
Host smart-81369ba0-0faf-478b-9160-727ce505cb5d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952002361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.1952002361
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.1243105548
Short name T772
Test name
Test status
Simulation time 19755445 ps
CPU time 4.32 seconds
Started Jul 30 05:21:01 PM PDT 24
Finished Jul 30 05:21:05 PM PDT 24
Peak memory 237660 kb
Host smart-77aab831-f63f-4330-bc25-c480688f7266
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1243105548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.1243105548
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.3854228610
Short name T760
Test name
Test status
Simulation time 7837838 ps
CPU time 1.48 seconds
Started Jul 30 05:21:03 PM PDT 24
Finished Jul 30 05:21:05 PM PDT 24
Peak memory 236720 kb
Host smart-4f50847b-ebbd-4b57-9d72-b83506b3d2ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3854228610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.3854228610
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.3187210056
Short name T741
Test name
Test status
Simulation time 95157718 ps
CPU time 12.77 seconds
Started Jul 30 05:21:00 PM PDT 24
Finished Jul 30 05:21:13 PM PDT 24
Peak memory 244996 kb
Host smart-a57aedfa-3dbb-415f-873b-f6c4402ca78a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3187210056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.3187210056
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.3955598566
Short name T155
Test name
Test status
Simulation time 61641019499 ps
CPU time 956.51 seconds
Started Jul 30 05:21:02 PM PDT 24
Finished Jul 30 05:36:58 PM PDT 24
Peak memory 265796 kb
Host smart-c67b28c2-ee24-4b8d-b6fd-e217b96c78da
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955598566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.3955598566
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.2220507632
Short name T795
Test name
Test status
Simulation time 107589904 ps
CPU time 15.01 seconds
Started Jul 30 05:21:01 PM PDT 24
Finished Jul 30 05:21:16 PM PDT 24
Peak memory 255504 kb
Host smart-1573ed18-09cf-415e-b73c-bc8b52e66b2b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2220507632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.2220507632
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.3319500742
Short name T707
Test name
Test status
Simulation time 81996798 ps
CPU time 2.44 seconds
Started Jul 30 05:21:01 PM PDT 24
Finished Jul 30 05:21:03 PM PDT 24
Peak memory 237720 kb
Host smart-9a8405b0-1f4c-4965-bb80-ccead4856b27
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3319500742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.3319500742
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.2370742274
Short name T798
Test name
Test status
Simulation time 604240300 ps
CPU time 9.79 seconds
Started Jul 30 05:21:03 PM PDT 24
Finished Jul 30 05:21:13 PM PDT 24
Peak memory 239436 kb
Host smart-dbe1e130-ae47-4d14-8d3a-2027666bea28
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370742274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.2370742274
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.573566628
Short name T722
Test name
Test status
Simulation time 34217049 ps
CPU time 6.28 seconds
Started Jul 30 05:21:07 PM PDT 24
Finished Jul 30 05:21:14 PM PDT 24
Peak memory 240668 kb
Host smart-7a1487f7-2684-4268-9b07-24c457dcfcf8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=573566628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.573566628
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.1007319719
Short name T775
Test name
Test status
Simulation time 7564239 ps
CPU time 1.49 seconds
Started Jul 30 05:20:59 PM PDT 24
Finished Jul 30 05:21:01 PM PDT 24
Peak memory 235756 kb
Host smart-da83c5ef-7381-4e9e-92c1-7d527a4bf319
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1007319719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.1007319719
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.982891882
Short name T827
Test name
Test status
Simulation time 1460399404 ps
CPU time 23.36 seconds
Started Jul 30 05:21:03 PM PDT 24
Finished Jul 30 05:21:26 PM PDT 24
Peak memory 245876 kb
Host smart-59244c80-b168-42bf-a619-e26b3a940951
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=982891882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_out
standing.982891882
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.22711424
Short name T143
Test name
Test status
Simulation time 1064918108 ps
CPU time 100.97 seconds
Started Jul 30 05:21:03 PM PDT 24
Finished Jul 30 05:22:44 PM PDT 24
Peak memory 265580 kb
Host smart-e6074462-a5e6-4975-a565-094cd087d0bf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=22711424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_error
s.22711424
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.239420688
Short name T731
Test name
Test status
Simulation time 44743206 ps
CPU time 5.86 seconds
Started Jul 30 05:21:00 PM PDT 24
Finished Jul 30 05:21:06 PM PDT 24
Peak memory 248744 kb
Host smart-ccfaf94d-b27d-4045-b350-a8ce6e8d4918
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=239420688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.239420688
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.2620681124
Short name T761
Test name
Test status
Simulation time 81654298 ps
CPU time 7.36 seconds
Started Jul 30 05:21:03 PM PDT 24
Finished Jul 30 05:21:11 PM PDT 24
Peak memory 248772 kb
Host smart-caaaeff7-748b-4cf8-89e7-d360998d5394
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620681124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.2620681124
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.28787211
Short name T204
Test name
Test status
Simulation time 66380418 ps
CPU time 4.09 seconds
Started Jul 30 05:21:04 PM PDT 24
Finished Jul 30 05:21:09 PM PDT 24
Peak memory 237668 kb
Host smart-2141ff76-44f3-43ab-9028-6fdcca9a7a66
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=28787211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.28787211
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.2690720041
Short name T780
Test name
Test status
Simulation time 6822702 ps
CPU time 1.5 seconds
Started Jul 30 05:21:05 PM PDT 24
Finished Jul 30 05:21:07 PM PDT 24
Peak memory 236736 kb
Host smart-149f27a8-6b92-4968-8bd0-8eb9a5635074
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2690720041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.2690720041
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.3907656273
Short name T824
Test name
Test status
Simulation time 2974151891 ps
CPU time 45.22 seconds
Started Jul 30 05:21:07 PM PDT 24
Finished Jul 30 05:21:52 PM PDT 24
Peak memory 245984 kb
Host smart-1bd38b4b-32ed-4540-94d7-b2ded05b3249
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3907656273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.3907656273
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.3271129909
Short name T156
Test name
Test status
Simulation time 8322521787 ps
CPU time 150.48 seconds
Started Jul 30 05:21:05 PM PDT 24
Finished Jul 30 05:23:35 PM PDT 24
Peak memory 268008 kb
Host smart-f6d53ed3-1c4c-46f3-8070-cea3abf14cfc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3271129909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.3271129909
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.4249051450
Short name T154
Test name
Test status
Simulation time 95857880427 ps
CPU time 1324.65 seconds
Started Jul 30 05:21:02 PM PDT 24
Finished Jul 30 05:43:07 PM PDT 24
Peak memory 265688 kb
Host smart-742f11f3-8de1-4a66-b770-861e5915dc90
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249051450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.4249051450
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.1033161842
Short name T809
Test name
Test status
Simulation time 44373898 ps
CPU time 6.05 seconds
Started Jul 30 05:21:07 PM PDT 24
Finished Jul 30 05:21:13 PM PDT 24
Peak memory 248980 kb
Host smart-9f2d45e2-e90b-4efb-a8cf-c0ea8c273d5b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1033161842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.1033161842
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.2369433133
Short name T254
Test name
Test status
Simulation time 187666627 ps
CPU time 13.78 seconds
Started Jul 30 05:21:09 PM PDT 24
Finished Jul 30 05:21:23 PM PDT 24
Peak memory 251992 kb
Host smart-2b61449b-56d9-43cd-8e88-d996fc9ae219
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369433133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.2369433133
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.3324356878
Short name T778
Test name
Test status
Simulation time 131348583 ps
CPU time 5.56 seconds
Started Jul 30 05:21:09 PM PDT 24
Finished Jul 30 05:21:15 PM PDT 24
Peak memory 237732 kb
Host smart-013ab79c-9a07-42bb-be63-737e3d2bcdce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3324356878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.3324356878
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.4142112135
Short name T752
Test name
Test status
Simulation time 12821107 ps
CPU time 1.71 seconds
Started Jul 30 05:21:12 PM PDT 24
Finished Jul 30 05:21:14 PM PDT 24
Peak memory 236744 kb
Host smart-6792b5d9-2ff8-43dd-81f3-7517b7a4527e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4142112135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.4142112135
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.4099067951
Short name T717
Test name
Test status
Simulation time 1607392427 ps
CPU time 22.69 seconds
Started Jul 30 05:21:13 PM PDT 24
Finished Jul 30 05:21:36 PM PDT 24
Peak memory 245756 kb
Host smart-7174a8bb-7712-4883-81a5-8494bdb47dc5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4099067951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.4099067951
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.2917793000
Short name T149
Test name
Test status
Simulation time 2600652980 ps
CPU time 237.36 seconds
Started Jul 30 05:21:05 PM PDT 24
Finished Jul 30 05:25:02 PM PDT 24
Peak memory 265580 kb
Host smart-df3abf08-89bb-44ff-b10b-27d3bd189da8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2917793000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.2917793000
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.3681548054
Short name T708
Test name
Test status
Simulation time 499517991 ps
CPU time 14.98 seconds
Started Jul 30 05:21:05 PM PDT 24
Finished Jul 30 05:21:20 PM PDT 24
Peak memory 248760 kb
Host smart-eb47b970-7a47-43f3-aa37-8802c7c2217e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3681548054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.3681548054
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.2584886173
Short name T754
Test name
Test status
Simulation time 150727075 ps
CPU time 11.48 seconds
Started Jul 30 05:21:08 PM PDT 24
Finished Jul 30 05:21:20 PM PDT 24
Peak memory 248836 kb
Host smart-c8885861-9713-4891-b6df-353fb12e5bab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584886173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.2584886173
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.769207434
Short name T738
Test name
Test status
Simulation time 19711898 ps
CPU time 4.09 seconds
Started Jul 30 05:21:10 PM PDT 24
Finished Jul 30 05:21:15 PM PDT 24
Peak memory 240636 kb
Host smart-17e67430-28cc-4e3d-835c-9d40e0444ed8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=769207434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.769207434
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.2108824839
Short name T783
Test name
Test status
Simulation time 110440152 ps
CPU time 11.64 seconds
Started Jul 30 05:21:10 PM PDT 24
Finished Jul 30 05:21:22 PM PDT 24
Peak memory 244992 kb
Host smart-9c79a961-54da-4d7a-94fc-1637b48a4cce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2108824839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.2108824839
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.792838751
Short name T144
Test name
Test status
Simulation time 2763530996 ps
CPU time 129.29 seconds
Started Jul 30 05:21:09 PM PDT 24
Finished Jul 30 05:23:19 PM PDT 24
Peak memory 257476 kb
Host smart-033399a5-ad59-4cc4-b40f-404e71c5af59
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=792838751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_erro
rs.792838751
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.1092008595
Short name T158
Test name
Test status
Simulation time 35035409455 ps
CPU time 513.87 seconds
Started Jul 30 05:21:10 PM PDT 24
Finished Jul 30 05:29:44 PM PDT 24
Peak memory 269184 kb
Host smart-ac76f54c-dcd7-4e9f-8d5c-05a1e2ddcbce
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092008595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.1092008595
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.2820270429
Short name T719
Test name
Test status
Simulation time 563749426 ps
CPU time 23.06 seconds
Started Jul 30 05:21:11 PM PDT 24
Finished Jul 30 05:21:35 PM PDT 24
Peak memory 248856 kb
Host smart-a667bebe-c466-4885-a8f2-416cf9c3866a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2820270429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.2820270429
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.4245586579
Short name T771
Test name
Test status
Simulation time 81273298 ps
CPU time 5.33 seconds
Started Jul 30 05:21:15 PM PDT 24
Finished Jul 30 05:21:20 PM PDT 24
Peak memory 240676 kb
Host smart-87229d8c-776e-4a8d-88fd-4d321fa926b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245586579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.4245586579
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.2626855013
Short name T755
Test name
Test status
Simulation time 123159796 ps
CPU time 9.47 seconds
Started Jul 30 05:21:13 PM PDT 24
Finished Jul 30 05:21:23 PM PDT 24
Peak memory 240648 kb
Host smart-c8f25f82-c0c5-4210-8b42-17db50f205a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2626855013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.2626855013
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.157860577
Short name T713
Test name
Test status
Simulation time 10147403 ps
CPU time 1.44 seconds
Started Jul 30 05:21:14 PM PDT 24
Finished Jul 30 05:21:15 PM PDT 24
Peak memory 237688 kb
Host smart-35c2dc49-3bba-428f-8a6e-74a25f97f735
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=157860577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.157860577
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.1064224467
Short name T807
Test name
Test status
Simulation time 352186093 ps
CPU time 13.23 seconds
Started Jul 30 05:21:13 PM PDT 24
Finished Jul 30 05:21:27 PM PDT 24
Peak memory 240616 kb
Host smart-91fce93b-b673-4097-baf8-aee6624739e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1064224467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.1064224467
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.810681267
Short name T161
Test name
Test status
Simulation time 5811612067 ps
CPU time 177.79 seconds
Started Jul 30 05:21:15 PM PDT 24
Finished Jul 30 05:24:13 PM PDT 24
Peak memory 265644 kb
Host smart-90354784-c58f-44b0-97cd-e438a1b2bee2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=810681267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_erro
rs.810681267
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.723510344
Short name T711
Test name
Test status
Simulation time 788923986 ps
CPU time 13.57 seconds
Started Jul 30 05:21:14 PM PDT 24
Finished Jul 30 05:21:27 PM PDT 24
Peak memory 253904 kb
Host smart-ffdad014-8e90-4e0b-b07d-5060e316f282
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=723510344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.723510344
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.788835601
Short name T756
Test name
Test status
Simulation time 57350766 ps
CPU time 9.1 seconds
Started Jul 30 05:21:20 PM PDT 24
Finished Jul 30 05:21:29 PM PDT 24
Peak memory 252184 kb
Host smart-ea6b85e3-97c0-45cc-9291-21f7dba8859e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788835601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 17.alert_handler_csr_mem_rw_with_rand_reset.788835601
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.600365250
Short name T208
Test name
Test status
Simulation time 35373876 ps
CPU time 6.83 seconds
Started Jul 30 05:21:24 PM PDT 24
Finished Jul 30 05:21:31 PM PDT 24
Peak memory 237724 kb
Host smart-d9d017ef-e522-4d7a-9a1c-85d5c8666c4f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=600365250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.600365250
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.1265677190
Short name T326
Test name
Test status
Simulation time 8015691 ps
CPU time 1.42 seconds
Started Jul 30 05:21:18 PM PDT 24
Finished Jul 30 05:21:19 PM PDT 24
Peak memory 237584 kb
Host smart-fabc3791-fd6d-4689-ad47-5f4f00ccbbd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1265677190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.1265677190
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.3524963394
Short name T806
Test name
Test status
Simulation time 2248451709 ps
CPU time 45 seconds
Started Jul 30 05:21:23 PM PDT 24
Finished Jul 30 05:22:09 PM PDT 24
Peak memory 245984 kb
Host smart-f6c992f5-6083-474c-a19a-1cb26d481d6e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3524963394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.3524963394
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.2845054304
Short name T163
Test name
Test status
Simulation time 2556273461 ps
CPU time 78.2 seconds
Started Jul 30 05:21:12 PM PDT 24
Finished Jul 30 05:22:31 PM PDT 24
Peak memory 265520 kb
Host smart-0638afae-c201-4402-b566-3fffec45fb58
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2845054304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.2845054304
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.2032988420
Short name T735
Test name
Test status
Simulation time 62678445 ps
CPU time 8.28 seconds
Started Jul 30 05:21:18 PM PDT 24
Finished Jul 30 05:21:26 PM PDT 24
Peak memory 252564 kb
Host smart-df20bce8-f2f2-4db8-81f0-bbff15dd64f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2032988420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.2032988420
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.873040636
Short name T764
Test name
Test status
Simulation time 258486116 ps
CPU time 9.6 seconds
Started Jul 30 05:21:22 PM PDT 24
Finished Jul 30 05:21:32 PM PDT 24
Peak memory 239732 kb
Host smart-a69a0ef5-f61a-4e4c-a865-461428a5e2a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873040636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 18.alert_handler_csr_mem_rw_with_rand_reset.873040636
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.3407415590
Short name T766
Test name
Test status
Simulation time 241806731 ps
CPU time 6 seconds
Started Jul 30 05:21:21 PM PDT 24
Finished Jul 30 05:21:27 PM PDT 24
Peak memory 237608 kb
Host smart-983d5596-4fb6-41bc-800e-cabaca42b841
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3407415590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.3407415590
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.1983922726
Short name T330
Test name
Test status
Simulation time 9972161 ps
CPU time 1.24 seconds
Started Jul 30 05:21:24 PM PDT 24
Finished Jul 30 05:21:25 PM PDT 24
Peak memory 237900 kb
Host smart-e1ea07e0-7e3f-4387-bbfb-1d5d8fc84bf8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1983922726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.1983922726
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.1579532287
Short name T767
Test name
Test status
Simulation time 369001815 ps
CPU time 22.22 seconds
Started Jul 30 05:21:21 PM PDT 24
Finished Jul 30 05:21:43 PM PDT 24
Peak memory 245816 kb
Host smart-14340353-225d-494a-9d5c-9681c9f42eed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1579532287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.1579532287
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.2297607309
Short name T138
Test name
Test status
Simulation time 9375837153 ps
CPU time 180.8 seconds
Started Jul 30 05:21:19 PM PDT 24
Finished Jul 30 05:24:20 PM PDT 24
Peak memory 265620 kb
Host smart-94d0451e-f713-4e88-a947-a954826d7bc7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2297607309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.2297607309
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.1808346257
Short name T333
Test name
Test status
Simulation time 14830865792 ps
CPU time 384 seconds
Started Jul 30 05:21:18 PM PDT 24
Finished Jul 30 05:27:42 PM PDT 24
Peak memory 265888 kb
Host smart-244efe92-5452-4a3a-a30c-09e9b0592550
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808346257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.1808346257
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.3158678959
Short name T740
Test name
Test status
Simulation time 431224369 ps
CPU time 9.04 seconds
Started Jul 30 05:21:20 PM PDT 24
Finished Jul 30 05:21:29 PM PDT 24
Peak memory 248872 kb
Host smart-95bd2606-bac4-4526-bb40-cc4a78d583f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3158678959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.3158678959
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.3454418759
Short name T763
Test name
Test status
Simulation time 121368742 ps
CPU time 5.86 seconds
Started Jul 30 05:21:27 PM PDT 24
Finished Jul 30 05:21:33 PM PDT 24
Peak memory 242720 kb
Host smart-ad5ea8a1-6c07-4a8d-bead-3dd36f93618d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454418759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.3454418759
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.3088539987
Short name T819
Test name
Test status
Simulation time 37354356 ps
CPU time 6.28 seconds
Started Jul 30 05:21:26 PM PDT 24
Finished Jul 30 05:21:33 PM PDT 24
Peak memory 237724 kb
Host smart-40d65010-f5dc-44ea-a299-d9b429869419
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3088539987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.3088539987
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.2416292740
Short name T730
Test name
Test status
Simulation time 9341793 ps
CPU time 1.35 seconds
Started Jul 30 05:21:23 PM PDT 24
Finished Jul 30 05:21:25 PM PDT 24
Peak memory 236800 kb
Host smart-8c162d35-757b-4b60-9128-8a9288ed16f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2416292740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.2416292740
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.2991015251
Short name T744
Test name
Test status
Simulation time 645025715 ps
CPU time 20.56 seconds
Started Jul 30 05:21:27 PM PDT 24
Finished Jul 30 05:21:47 PM PDT 24
Peak memory 248860 kb
Host smart-bca85b12-6444-46d7-a25c-5183e312ddfd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2991015251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.2991015251
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.2053539409
Short name T146
Test name
Test status
Simulation time 32282756161 ps
CPU time 570.7 seconds
Started Jul 30 05:21:24 PM PDT 24
Finished Jul 30 05:30:55 PM PDT 24
Peak memory 265888 kb
Host smart-e583e45b-b58f-497f-b871-d2b6f3af9ab6
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053539409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.2053539409
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.149546198
Short name T742
Test name
Test status
Simulation time 154759498 ps
CPU time 11.97 seconds
Started Jul 30 05:21:24 PM PDT 24
Finished Jul 30 05:21:36 PM PDT 24
Peak memory 248920 kb
Host smart-f7d81615-1000-4d75-af45-19883409f606
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=149546198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.149546198
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.3360579698
Short name T726
Test name
Test status
Simulation time 61528361 ps
CPU time 2.27 seconds
Started Jul 30 05:21:24 PM PDT 24
Finished Jul 30 05:21:27 PM PDT 24
Peak memory 238716 kb
Host smart-4675fb47-3fd3-4213-9c54-adde39a41273
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3360579698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.3360579698
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.1558801274
Short name T191
Test name
Test status
Simulation time 3183338056 ps
CPU time 143.62 seconds
Started Jul 30 05:20:36 PM PDT 24
Finished Jul 30 05:22:59 PM PDT 24
Peak memory 240680 kb
Host smart-12e5ecfe-478b-45da-a2e1-01f41ab44ffe
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1558801274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.1558801274
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.3501301315
Short name T202
Test name
Test status
Simulation time 1243429385 ps
CPU time 104.29 seconds
Started Jul 30 05:20:37 PM PDT 24
Finished Jul 30 05:22:22 PM PDT 24
Peak memory 237672 kb
Host smart-c6b40502-07c5-417d-8fa6-14dfe591d6cd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3501301315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.3501301315
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.3681176015
Short name T732
Test name
Test status
Simulation time 31483053 ps
CPU time 4.29 seconds
Started Jul 30 05:20:36 PM PDT 24
Finished Jul 30 05:20:40 PM PDT 24
Peak memory 248848 kb
Host smart-0bb04bc9-138c-4598-9f2d-f6dc72894c2c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3681176015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.3681176015
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.1468339547
Short name T332
Test name
Test status
Simulation time 64587753 ps
CPU time 9.65 seconds
Started Jul 30 05:20:39 PM PDT 24
Finished Jul 30 05:20:49 PM PDT 24
Peak memory 252104 kb
Host smart-6c079765-52e3-4fea-8cc2-63db61c14612
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468339547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.1468339547
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.538296236
Short name T203
Test name
Test status
Simulation time 362944001 ps
CPU time 9.96 seconds
Started Jul 30 05:20:36 PM PDT 24
Finished Jul 30 05:20:46 PM PDT 24
Peak memory 237672 kb
Host smart-638553b9-3912-4f4b-b1fb-212ce19c7d84
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=538296236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.538296236
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.3929361447
Short name T757
Test name
Test status
Simulation time 8412213 ps
CPU time 1.43 seconds
Started Jul 30 05:20:37 PM PDT 24
Finished Jul 30 05:20:38 PM PDT 24
Peak memory 236996 kb
Host smart-c75f3e34-e5b4-41e1-8ae2-c39497dec6f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3929361447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.3929361447
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.2790649722
Short name T776
Test name
Test status
Simulation time 2620713736 ps
CPU time 43.88 seconds
Started Jul 30 05:20:33 PM PDT 24
Finished Jul 30 05:21:17 PM PDT 24
Peak memory 245924 kb
Host smart-d3606a4c-b7af-4bda-8a83-0b8e059e42f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2790649722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.2790649722
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.888856888
Short name T159
Test name
Test status
Simulation time 23792920983 ps
CPU time 482.95 seconds
Started Jul 30 05:20:35 PM PDT 24
Finished Jul 30 05:28:38 PM PDT 24
Peak memory 269536 kb
Host smart-84510642-baa7-4471-aff0-486e89b97a29
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888856888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.888856888
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.1382774459
Short name T816
Test name
Test status
Simulation time 249150086 ps
CPU time 21.05 seconds
Started Jul 30 05:20:35 PM PDT 24
Finished Jul 30 05:20:56 PM PDT 24
Peak memory 254024 kb
Host smart-8824fad8-63a6-4c5b-b483-775597c78ff6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1382774459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.1382774459
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.616099405
Short name T800
Test name
Test status
Simulation time 13957163 ps
CPU time 1.42 seconds
Started Jul 30 05:21:26 PM PDT 24
Finished Jul 30 05:21:28 PM PDT 24
Peak memory 236800 kb
Host smart-f0f82039-3353-4a41-9af1-8c5ed657e5ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=616099405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.616099405
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.4140169703
Short name T718
Test name
Test status
Simulation time 28227828 ps
CPU time 1.33 seconds
Started Jul 30 05:21:27 PM PDT 24
Finished Jul 30 05:21:29 PM PDT 24
Peak memory 236588 kb
Host smart-eeb83325-3138-4a93-8611-3c846d202aa0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4140169703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.4140169703
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.1147012343
Short name T797
Test name
Test status
Simulation time 10082789 ps
CPU time 1.73 seconds
Started Jul 30 05:21:26 PM PDT 24
Finished Jul 30 05:21:28 PM PDT 24
Peak memory 236724 kb
Host smart-753759f9-2ed1-4858-898b-759b635d18fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1147012343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.1147012343
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.2285583508
Short name T739
Test name
Test status
Simulation time 6184721 ps
CPU time 1.41 seconds
Started Jul 30 05:21:28 PM PDT 24
Finished Jul 30 05:21:30 PM PDT 24
Peak memory 237604 kb
Host smart-fdbfbf41-84bd-4462-adac-280b04fd9ed0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2285583508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.2285583508
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.736342715
Short name T709
Test name
Test status
Simulation time 14493642 ps
CPU time 1.37 seconds
Started Jul 30 05:21:27 PM PDT 24
Finished Jul 30 05:21:29 PM PDT 24
Peak memory 237692 kb
Host smart-dd0cc9ab-1fe9-44cd-b8b3-c130d4c8c12d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=736342715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.736342715
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.334934531
Short name T723
Test name
Test status
Simulation time 11100465 ps
CPU time 1.26 seconds
Started Jul 30 05:21:26 PM PDT 24
Finished Jul 30 05:21:27 PM PDT 24
Peak memory 237628 kb
Host smart-4451c01b-615b-45f2-814e-d33345819bfc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=334934531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.334934531
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.2605557067
Short name T758
Test name
Test status
Simulation time 11591080 ps
CPU time 1.57 seconds
Started Jul 30 05:21:27 PM PDT 24
Finished Jul 30 05:21:29 PM PDT 24
Peak memory 236852 kb
Host smart-924ce352-92a6-475c-9bb1-306dfa22bdc5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2605557067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.2605557067
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.33228624
Short name T248
Test name
Test status
Simulation time 9201161 ps
CPU time 1.38 seconds
Started Jul 30 05:21:27 PM PDT 24
Finished Jul 30 05:21:28 PM PDT 24
Peak memory 236656 kb
Host smart-f10fe24d-3f9e-4096-b8fa-40805286c406
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=33228624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.33228624
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.3353451258
Short name T753
Test name
Test status
Simulation time 25761304 ps
CPU time 1.4 seconds
Started Jul 30 05:21:27 PM PDT 24
Finished Jul 30 05:21:29 PM PDT 24
Peak memory 237708 kb
Host smart-b415646f-4b78-449a-8b5c-3efcaff2b07a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3353451258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.3353451258
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.2697796006
Short name T781
Test name
Test status
Simulation time 565632979 ps
CPU time 64.02 seconds
Started Jul 30 05:20:43 PM PDT 24
Finished Jul 30 05:21:47 PM PDT 24
Peak memory 240636 kb
Host smart-9ddd6449-7911-460f-b51d-30bfcbcf0a51
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2697796006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.2697796006
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.3106822056
Short name T815
Test name
Test status
Simulation time 5886444887 ps
CPU time 392.72 seconds
Started Jul 30 05:20:39 PM PDT 24
Finished Jul 30 05:27:12 PM PDT 24
Peak memory 240716 kb
Host smart-3b175c15-387b-407e-af16-abc9ff9914cd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3106822056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.3106822056
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.3632634804
Short name T721
Test name
Test status
Simulation time 171995760 ps
CPU time 7.35 seconds
Started Jul 30 05:20:38 PM PDT 24
Finished Jul 30 05:20:45 PM PDT 24
Peak memory 249064 kb
Host smart-7a887053-25fc-41d4-8a96-05e2e740d432
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3632634804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.3632634804
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.1981995036
Short name T710
Test name
Test status
Simulation time 59573131 ps
CPU time 7.84 seconds
Started Jul 30 05:20:50 PM PDT 24
Finished Jul 30 05:20:57 PM PDT 24
Peak memory 255100 kb
Host smart-f343583f-3514-4b3f-8167-3ae66d4c9d47
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981995036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.1981995036
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.2559717209
Short name T812
Test name
Test status
Simulation time 65392781 ps
CPU time 5.33 seconds
Started Jul 30 05:20:46 PM PDT 24
Finished Jul 30 05:20:51 PM PDT 24
Peak memory 240448 kb
Host smart-8ec1b85f-4e3d-4eec-b0d9-2d436a521718
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2559717209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.2559717209
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.894536201
Short name T715
Test name
Test status
Simulation time 13777321 ps
CPU time 1.45 seconds
Started Jul 30 05:20:38 PM PDT 24
Finished Jul 30 05:20:39 PM PDT 24
Peak memory 236812 kb
Host smart-b5d06e45-3b9c-44f5-9e4c-bfd96b8cfc57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=894536201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.894536201
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.1547604605
Short name T759
Test name
Test status
Simulation time 5725939907 ps
CPU time 56.93 seconds
Started Jul 30 05:20:44 PM PDT 24
Finished Jul 30 05:21:41 PM PDT 24
Peak memory 246028 kb
Host smart-41ba0291-00ea-4b29-acaa-ed9e009a7122
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1547604605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.1547604605
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.4020965859
Short name T147
Test name
Test status
Simulation time 3717029143 ps
CPU time 408.2 seconds
Started Jul 30 05:20:39 PM PDT 24
Finished Jul 30 05:27:27 PM PDT 24
Peak memory 265576 kb
Host smart-78242eac-34a2-423b-acb5-950659b3cfa7
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020965859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.4020965859
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.2250511652
Short name T706
Test name
Test status
Simulation time 191659521 ps
CPU time 5.51 seconds
Started Jul 30 05:20:40 PM PDT 24
Finished Jul 30 05:20:45 PM PDT 24
Peak memory 248600 kb
Host smart-e205ef14-a313-4d56-837c-053b01a891bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2250511652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.2250511652
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.1763093956
Short name T173
Test name
Test status
Simulation time 18847034 ps
CPU time 1.43 seconds
Started Jul 30 05:21:27 PM PDT 24
Finished Jul 30 05:21:29 PM PDT 24
Peak memory 235688 kb
Host smart-66363bd1-ed91-4d8a-b78d-e4a0615a4a34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1763093956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.1763093956
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.3714217603
Short name T801
Test name
Test status
Simulation time 12693812 ps
CPU time 1.52 seconds
Started Jul 30 05:21:30 PM PDT 24
Finished Jul 30 05:21:31 PM PDT 24
Peak memory 237688 kb
Host smart-f28678f0-ff27-4e92-93a8-cb6edfe46999
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3714217603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.3714217603
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.924021479
Short name T249
Test name
Test status
Simulation time 19304071 ps
CPU time 1.49 seconds
Started Jul 30 05:21:27 PM PDT 24
Finished Jul 30 05:21:29 PM PDT 24
Peak memory 237732 kb
Host smart-e7bb996d-5dfb-4fc8-a628-b050b7c8a287
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=924021479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.924021479
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.3501281062
Short name T172
Test name
Test status
Simulation time 16054689 ps
CPU time 1.72 seconds
Started Jul 30 05:21:29 PM PDT 24
Finished Jul 30 05:21:31 PM PDT 24
Peak memory 236780 kb
Host smart-29bbb712-a2b4-46dd-ab09-5caeda6a0443
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3501281062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.3501281062
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.2731475187
Short name T817
Test name
Test status
Simulation time 12043964 ps
CPU time 1.66 seconds
Started Jul 30 05:21:31 PM PDT 24
Finished Jul 30 05:21:33 PM PDT 24
Peak memory 236816 kb
Host smart-ba73d7fc-d6fe-4800-95ae-0dde1f39c80a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2731475187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.2731475187
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.2849327423
Short name T728
Test name
Test status
Simulation time 11271614 ps
CPU time 1.47 seconds
Started Jul 30 05:21:32 PM PDT 24
Finished Jul 30 05:21:34 PM PDT 24
Peak memory 236792 kb
Host smart-8674f990-faca-45d3-8431-87f724d9078e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2849327423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.2849327423
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.1833308907
Short name T790
Test name
Test status
Simulation time 6572553 ps
CPU time 1.47 seconds
Started Jul 30 05:21:34 PM PDT 24
Finished Jul 30 05:21:36 PM PDT 24
Peak memory 236780 kb
Host smart-0362bd7b-77a3-4e16-a844-6a1f15737135
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1833308907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.1833308907
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.1479168423
Short name T733
Test name
Test status
Simulation time 25788319 ps
CPU time 1.43 seconds
Started Jul 30 05:21:30 PM PDT 24
Finished Jul 30 05:21:32 PM PDT 24
Peak memory 237756 kb
Host smart-3b76a45e-fb23-434c-9602-55d4eb469ace
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1479168423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.1479168423
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.2448806418
Short name T796
Test name
Test status
Simulation time 6633834 ps
CPU time 1.39 seconds
Started Jul 30 05:21:33 PM PDT 24
Finished Jul 30 05:21:35 PM PDT 24
Peak memory 237712 kb
Host smart-2f87dc8a-da07-45c3-80a0-df444f02fdcb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2448806418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.2448806418
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.375078391
Short name T331
Test name
Test status
Simulation time 20463742 ps
CPU time 1.34 seconds
Started Jul 30 05:21:30 PM PDT 24
Finished Jul 30 05:21:32 PM PDT 24
Peak memory 237568 kb
Host smart-a8ed5a85-d118-4d39-9821-8b4ca0e0037b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=375078391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.375078391
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.2593336681
Short name T190
Test name
Test status
Simulation time 8941158943 ps
CPU time 323.4 seconds
Started Jul 30 05:20:43 PM PDT 24
Finished Jul 30 05:26:06 PM PDT 24
Peak memory 241124 kb
Host smart-0fee7d0d-a2db-4b67-9e0c-05631e99a5fa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2593336681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.2593336681
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.2727041489
Short name T779
Test name
Test status
Simulation time 4806455983 ps
CPU time 109.62 seconds
Started Jul 30 05:20:44 PM PDT 24
Finished Jul 30 05:22:34 PM PDT 24
Peak memory 237764 kb
Host smart-dc6594fc-a94e-458a-a090-405e4f0bd9e7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2727041489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.2727041489
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.1283846744
Short name T174
Test name
Test status
Simulation time 362616958 ps
CPU time 8.52 seconds
Started Jul 30 05:20:45 PM PDT 24
Finished Jul 30 05:20:54 PM PDT 24
Peak memory 249208 kb
Host smart-6dd3f391-df86-44f4-beab-5ff91ae53e15
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1283846744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.1283846744
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.2143505718
Short name T773
Test name
Test status
Simulation time 124435830 ps
CPU time 10.74 seconds
Started Jul 30 05:20:50 PM PDT 24
Finished Jul 30 05:21:00 PM PDT 24
Peak memory 243768 kb
Host smart-b35fa1d6-088c-41d5-858c-24d4f5457639
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143505718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.2143505718
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.3417433454
Short name T206
Test name
Test status
Simulation time 32723559 ps
CPU time 6.14 seconds
Started Jul 30 05:20:44 PM PDT 24
Finished Jul 30 05:20:50 PM PDT 24
Peak memory 240608 kb
Host smart-bc056db8-7626-4321-ad3f-cce8605abf04
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3417433454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.3417433454
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.2195610405
Short name T810
Test name
Test status
Simulation time 14243822 ps
CPU time 1.48 seconds
Started Jul 30 05:20:46 PM PDT 24
Finished Jul 30 05:20:48 PM PDT 24
Peak memory 235784 kb
Host smart-c0e292eb-c9f3-4fff-8dc7-5cb174268e29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2195610405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.2195610405
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.929315289
Short name T205
Test name
Test status
Simulation time 753013848 ps
CPU time 47.72 seconds
Started Jul 30 05:20:50 PM PDT 24
Finished Jul 30 05:21:38 PM PDT 24
Peak memory 245712 kb
Host smart-682b0ccf-e54e-44e2-9104-35fa01d672a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=929315289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_outs
tanding.929315289
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.1507317475
Short name T167
Test name
Test status
Simulation time 14050759405 ps
CPU time 297.52 seconds
Started Jul 30 05:20:49 PM PDT 24
Finished Jul 30 05:25:47 PM PDT 24
Peak memory 265432 kb
Host smart-ddb880a6-f8d0-4f86-bd22-b1d180a1d4e4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507317475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.1507317475
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.1709954466
Short name T791
Test name
Test status
Simulation time 668238539 ps
CPU time 11.36 seconds
Started Jul 30 05:20:43 PM PDT 24
Finished Jul 30 05:20:55 PM PDT 24
Peak memory 253524 kb
Host smart-25140e7d-9a11-468e-b545-5590d48d5af1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1709954466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.1709954466
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.3730605391
Short name T170
Test name
Test status
Simulation time 59088442 ps
CPU time 2.47 seconds
Started Jul 30 05:20:50 PM PDT 24
Finished Jul 30 05:20:53 PM PDT 24
Peak memory 236620 kb
Host smart-2cb07656-6cf0-4a06-8442-a93a3b5c4626
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3730605391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.3730605391
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.2637422061
Short name T328
Test name
Test status
Simulation time 19303094 ps
CPU time 1.34 seconds
Started Jul 30 05:21:30 PM PDT 24
Finished Jul 30 05:21:31 PM PDT 24
Peak memory 237556 kb
Host smart-c03260b1-28bc-4c66-9e6a-5a8c0c93dc7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2637422061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.2637422061
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.2951478570
Short name T813
Test name
Test status
Simulation time 14100591 ps
CPU time 1.31 seconds
Started Jul 30 05:21:33 PM PDT 24
Finished Jul 30 05:21:34 PM PDT 24
Peak memory 235544 kb
Host smart-54427cee-2292-4142-86bf-8a439ddf5e60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2951478570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.2951478570
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.1145573818
Short name T768
Test name
Test status
Simulation time 13111289 ps
CPU time 1.6 seconds
Started Jul 30 05:21:31 PM PDT 24
Finished Jul 30 05:21:33 PM PDT 24
Peak memory 237900 kb
Host smart-2447cd62-4ff5-4507-a49a-4ac90369afd3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1145573818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.1145573818
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.2923030347
Short name T746
Test name
Test status
Simulation time 13817385 ps
CPU time 1.5 seconds
Started Jul 30 05:21:33 PM PDT 24
Finished Jul 30 05:21:35 PM PDT 24
Peak memory 236660 kb
Host smart-008fcc1b-3fde-4200-9b95-21e628f74ee1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2923030347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.2923030347
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.626437506
Short name T808
Test name
Test status
Simulation time 11020750 ps
CPU time 1.34 seconds
Started Jul 30 05:21:32 PM PDT 24
Finished Jul 30 05:21:33 PM PDT 24
Peak memory 236836 kb
Host smart-61c8c64b-31df-401f-8805-01548e009069
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=626437506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.626437506
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.2169786121
Short name T727
Test name
Test status
Simulation time 6197012 ps
CPU time 1.46 seconds
Started Jul 30 05:21:37 PM PDT 24
Finished Jul 30 05:21:38 PM PDT 24
Peak memory 237680 kb
Host smart-2bebf18b-4a4c-4474-9443-4431d9444518
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2169786121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.2169786121
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.779780039
Short name T786
Test name
Test status
Simulation time 13146536 ps
CPU time 1.23 seconds
Started Jul 30 05:21:37 PM PDT 24
Finished Jul 30 05:21:38 PM PDT 24
Peak memory 235752 kb
Host smart-dd60b93d-d663-4531-84ce-83964c7fc58a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=779780039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.779780039
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.1555999898
Short name T729
Test name
Test status
Simulation time 9263066 ps
CPU time 1.52 seconds
Started Jul 30 05:21:36 PM PDT 24
Finished Jul 30 05:21:37 PM PDT 24
Peak memory 236660 kb
Host smart-210b5792-9914-46ed-b993-387a3754c972
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1555999898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.1555999898
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.591465441
Short name T770
Test name
Test status
Simulation time 8193560 ps
CPU time 1.37 seconds
Started Jul 30 05:21:36 PM PDT 24
Finished Jul 30 05:21:37 PM PDT 24
Peak memory 237716 kb
Host smart-2bcc2f73-422c-4e5c-b60f-16cdd333da58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=591465441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.591465441
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.1344547549
Short name T805
Test name
Test status
Simulation time 9828280 ps
CPU time 1.27 seconds
Started Jul 30 05:21:33 PM PDT 24
Finished Jul 30 05:21:35 PM PDT 24
Peak memory 237668 kb
Host smart-0ac07249-4609-40cb-baaf-667e21547f16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1344547549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.1344547549
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.3040800892
Short name T777
Test name
Test status
Simulation time 274192001 ps
CPU time 10.08 seconds
Started Jul 30 05:20:49 PM PDT 24
Finished Jul 30 05:20:59 PM PDT 24
Peak memory 239040 kb
Host smart-e64387b7-e57a-4ae1-9ada-8b37bbda2f97
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040800892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.3040800892
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.1782169110
Short name T743
Test name
Test status
Simulation time 216472592 ps
CPU time 4.86 seconds
Started Jul 30 05:20:49 PM PDT 24
Finished Jul 30 05:20:54 PM PDT 24
Peak memory 236780 kb
Host smart-08495844-41ff-427a-9bfc-eff5a41dd98b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1782169110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.1782169110
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.2685440056
Short name T724
Test name
Test status
Simulation time 12620409 ps
CPU time 1.57 seconds
Started Jul 30 05:20:50 PM PDT 24
Finished Jul 30 05:20:51 PM PDT 24
Peak memory 237032 kb
Host smart-ebd8ea17-a6a6-49ca-8e3a-0844ad90795b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2685440056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.2685440056
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.1314511155
Short name T782
Test name
Test status
Simulation time 311473384 ps
CPU time 25.23 seconds
Started Jul 30 05:20:48 PM PDT 24
Finished Jul 30 05:21:14 PM PDT 24
Peak memory 248816 kb
Host smart-a170e63b-37f7-45d7-af87-9973537a08c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1314511155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.1314511155
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.3606530054
Short name T148
Test name
Test status
Simulation time 808540781 ps
CPU time 96.79 seconds
Started Jul 30 05:20:47 PM PDT 24
Finished Jul 30 05:22:24 PM PDT 24
Peak memory 266956 kb
Host smart-4f6e0c39-119b-4f7c-ab35-3983e5c872bf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3606530054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.3606530054
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.3149234732
Short name T165
Test name
Test status
Simulation time 18400969320 ps
CPU time 769.28 seconds
Started Jul 30 05:20:47 PM PDT 24
Finished Jul 30 05:33:37 PM PDT 24
Peak memory 265720 kb
Host smart-9d40100e-cbdc-482c-acd4-4e1e71c34875
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149234732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.3149234732
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.591165481
Short name T785
Test name
Test status
Simulation time 485243495 ps
CPU time 17.13 seconds
Started Jul 30 05:20:51 PM PDT 24
Finished Jul 30 05:21:08 PM PDT 24
Peak memory 248904 kb
Host smart-c2014d2e-6563-4f48-a018-b77a3bee8324
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=591165481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.591165481
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.3099089171
Short name T747
Test name
Test status
Simulation time 425416710 ps
CPU time 9.39 seconds
Started Jul 30 05:20:51 PM PDT 24
Finished Jul 30 05:21:01 PM PDT 24
Peak memory 252964 kb
Host smart-8f96c42d-1576-4d13-b244-3e488fdfd334
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099089171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.3099089171
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.4224827642
Short name T734
Test name
Test status
Simulation time 117165479 ps
CPU time 5.34 seconds
Started Jul 30 05:20:53 PM PDT 24
Finished Jul 30 05:20:58 PM PDT 24
Peak memory 236800 kb
Host smart-6f2d71c5-9c5f-4bf5-9f9e-c95a8b1538b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4224827642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.4224827642
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.3104055479
Short name T750
Test name
Test status
Simulation time 10543102 ps
CPU time 1.33 seconds
Started Jul 30 05:20:50 PM PDT 24
Finished Jul 30 05:20:51 PM PDT 24
Peak memory 237740 kb
Host smart-ea80600b-287a-4bd7-b7f6-32ba17deed01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3104055479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.3104055479
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.2023460603
Short name T787
Test name
Test status
Simulation time 876286863 ps
CPU time 15.5 seconds
Started Jul 30 05:20:52 PM PDT 24
Finished Jul 30 05:21:08 PM PDT 24
Peak memory 247024 kb
Host smart-7c063a2f-dfdc-4f3d-b9e6-47a601dcdefe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2023460603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.2023460603
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.2983793085
Short name T788
Test name
Test status
Simulation time 1331080919 ps
CPU time 23.94 seconds
Started Jul 30 05:20:48 PM PDT 24
Finished Jul 30 05:21:12 PM PDT 24
Peak memory 247924 kb
Host smart-cb50d694-2a83-44d5-bc8f-0333cf10180c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2983793085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.2983793085
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.3772455144
Short name T749
Test name
Test status
Simulation time 34650303 ps
CPU time 6.44 seconds
Started Jul 30 05:20:53 PM PDT 24
Finished Jul 30 05:21:00 PM PDT 24
Peak memory 256940 kb
Host smart-ba2564d5-4fa5-46f3-9f5a-9978f9440097
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772455144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.3772455144
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.834384004
Short name T784
Test name
Test status
Simulation time 33391895 ps
CPU time 5.51 seconds
Started Jul 30 05:20:51 PM PDT 24
Finished Jul 30 05:20:57 PM PDT 24
Peak memory 237728 kb
Host smart-5879f7aa-37f6-4c04-960b-72f5a67755c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=834384004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.834384004
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.3104985344
Short name T736
Test name
Test status
Simulation time 20126772 ps
CPU time 1.54 seconds
Started Jul 30 05:20:54 PM PDT 24
Finished Jul 30 05:20:55 PM PDT 24
Peak memory 237704 kb
Host smart-5f75f5c8-a990-4b84-8412-464058cf1b93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3104985344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.3104985344
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.1519267958
Short name T799
Test name
Test status
Simulation time 655951789 ps
CPU time 46.57 seconds
Started Jul 30 05:20:51 PM PDT 24
Finished Jul 30 05:21:37 PM PDT 24
Peak memory 248836 kb
Host smart-d112a776-cde5-4adf-becf-9166bb2943f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1519267958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.1519267958
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.3367510215
Short name T132
Test name
Test status
Simulation time 8810573639 ps
CPU time 318.57 seconds
Started Jul 30 05:20:51 PM PDT 24
Finished Jul 30 05:26:10 PM PDT 24
Peak memory 265584 kb
Host smart-3da444fb-67fd-4014-b0eb-7e91c70a562a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367510215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.3367510215
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.2832054268
Short name T737
Test name
Test status
Simulation time 311059405 ps
CPU time 24.44 seconds
Started Jul 30 05:20:56 PM PDT 24
Finished Jul 30 05:21:20 PM PDT 24
Peak memory 248592 kb
Host smart-da85eb42-64d4-48b5-a987-c2caf37c4bc7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2832054268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.2832054268
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.3282422665
Short name T720
Test name
Test status
Simulation time 53798928 ps
CPU time 10.13 seconds
Started Jul 30 05:21:12 PM PDT 24
Finished Jul 30 05:21:22 PM PDT 24
Peak memory 252500 kb
Host smart-6c7423ec-a79a-4a47-9dcb-00284a6b500b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282422665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.3282422665
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.1716748397
Short name T762
Test name
Test status
Simulation time 56560346 ps
CPU time 3.67 seconds
Started Jul 30 05:20:59 PM PDT 24
Finished Jul 30 05:21:03 PM PDT 24
Peak memory 240592 kb
Host smart-b59a1cac-ac5b-4fae-8ad2-a31bd783699b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1716748397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.1716748397
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.3214933195
Short name T751
Test name
Test status
Simulation time 6735257 ps
CPU time 1.58 seconds
Started Jul 30 05:20:58 PM PDT 24
Finished Jul 30 05:21:00 PM PDT 24
Peak memory 236864 kb
Host smart-3917c027-d425-47a2-a0ee-df3e60911be2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3214933195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.3214933195
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.3768561339
Short name T769
Test name
Test status
Simulation time 333065491 ps
CPU time 27.17 seconds
Started Jul 30 05:21:13 PM PDT 24
Finished Jul 30 05:21:41 PM PDT 24
Peak memory 245764 kb
Host smart-655c8729-9747-434c-b507-8a1e44d1fc7b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3768561339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.3768561339
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.3341941748
Short name T150
Test name
Test status
Simulation time 8750201395 ps
CPU time 281.26 seconds
Started Jul 30 05:20:58 PM PDT 24
Finished Jul 30 05:25:39 PM PDT 24
Peak memory 265660 kb
Host smart-4381ce73-a694-4a03-9677-2183804aa046
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3341941748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.3341941748
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.1650958610
Short name T334
Test name
Test status
Simulation time 40267472434 ps
CPU time 485.68 seconds
Started Jul 30 05:20:51 PM PDT 24
Finished Jul 30 05:28:57 PM PDT 24
Peak memory 265572 kb
Host smart-3232e09d-ddb0-44db-a4ee-10e8574881f4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650958610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.1650958610
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.2352778708
Short name T802
Test name
Test status
Simulation time 408130000 ps
CPU time 8.94 seconds
Started Jul 30 05:20:57 PM PDT 24
Finished Jul 30 05:21:06 PM PDT 24
Peak memory 248520 kb
Host smart-a9ac7357-d84d-47e7-a0f7-da9688e10609
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2352778708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.2352778708
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.1416244760
Short name T714
Test name
Test status
Simulation time 71825468 ps
CPU time 6.78 seconds
Started Jul 30 05:20:58 PM PDT 24
Finished Jul 30 05:21:05 PM PDT 24
Peak memory 256300 kb
Host smart-f7ba4a10-62c2-40a4-9022-d86b271a8a87
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416244760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.1416244760
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.3053364203
Short name T716
Test name
Test status
Simulation time 52561499 ps
CPU time 5.5 seconds
Started Jul 30 05:20:59 PM PDT 24
Finished Jul 30 05:21:04 PM PDT 24
Peak memory 240608 kb
Host smart-21a1b81d-9234-4496-9d01-6a340e21dd75
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3053364203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.3053364203
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.3868447365
Short name T792
Test name
Test status
Simulation time 2942086145 ps
CPU time 20.82 seconds
Started Jul 30 05:21:12 PM PDT 24
Finished Jul 30 05:21:33 PM PDT 24
Peak memory 240568 kb
Host smart-89aa6a47-db26-4876-9e65-82e6c2b1bcc0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3868447365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.3868447365
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.2823902252
Short name T141
Test name
Test status
Simulation time 18148479354 ps
CPU time 319.28 seconds
Started Jul 30 05:21:01 PM PDT 24
Finished Jul 30 05:26:20 PM PDT 24
Peak memory 265480 kb
Host smart-03e474ed-33eb-44af-9ee3-e969e87a96b4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2823902252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.2823902252
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.4014182867
Short name T794
Test name
Test status
Simulation time 77685856 ps
CPU time 7.17 seconds
Started Jul 30 05:20:55 PM PDT 24
Finished Jul 30 05:21:03 PM PDT 24
Peak memory 249008 kb
Host smart-064b78fe-0e74-4d90-8ba0-4b191d42d840
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4014182867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.4014182867
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.3500157015
Short name T439
Test name
Test status
Simulation time 12464546420 ps
CPU time 683.37 seconds
Started Jul 30 05:29:16 PM PDT 24
Finished Jul 30 05:40:40 PM PDT 24
Peak memory 264708 kb
Host smart-d9834c26-7eae-409c-b0f7-807e56e0a01d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500157015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.3500157015
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.2185283116
Short name T625
Test name
Test status
Simulation time 1662902311 ps
CPU time 20.6 seconds
Started Jul 30 05:29:19 PM PDT 24
Finished Jul 30 05:29:40 PM PDT 24
Peak memory 248384 kb
Host smart-fd5b7810-05a7-4587-a660-b681aba2d9dc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2185283116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.2185283116
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.2083969474
Short name T565
Test name
Test status
Simulation time 1327966300 ps
CPU time 83.54 seconds
Started Jul 30 05:29:15 PM PDT 24
Finished Jul 30 05:30:39 PM PDT 24
Peak memory 255612 kb
Host smart-8a555a93-3f2d-4cd7-a2d5-91d15a184022
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20839
69474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.2083969474
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.3274947341
Short name T99
Test name
Test status
Simulation time 703118961 ps
CPU time 17.54 seconds
Started Jul 30 05:29:16 PM PDT 24
Finished Jul 30 05:29:34 PM PDT 24
Peak memory 248388 kb
Host smart-9129e13e-323a-472a-8efe-4a1959c8a5d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32749
47341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.3274947341
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.4285088080
Short name T594
Test name
Test status
Simulation time 12688307106 ps
CPU time 1178.74 seconds
Started Jul 30 05:29:15 PM PDT 24
Finished Jul 30 05:48:54 PM PDT 24
Peak memory 286192 kb
Host smart-43394cf9-5e7f-49df-b5d9-f7cd2356a310
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285088080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.4285088080
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.284258066
Short name T194
Test name
Test status
Simulation time 111291265085 ps
CPU time 445.41 seconds
Started Jul 30 05:29:17 PM PDT 24
Finished Jul 30 05:36:42 PM PDT 24
Peak memory 248276 kb
Host smart-8b89370f-3493-4a34-98dd-0669f3d5e5c0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284258066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.284258066
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.1936601951
Short name T43
Test name
Test status
Simulation time 510215064 ps
CPU time 5.35 seconds
Started Jul 30 05:29:16 PM PDT 24
Finished Jul 30 05:29:21 PM PDT 24
Peak memory 248364 kb
Host smart-ab5416c0-faae-452f-abfb-56ae6f501ebe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19366
01951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.1936601951
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.799025007
Short name T53
Test name
Test status
Simulation time 352995553 ps
CPU time 15.58 seconds
Started Jul 30 05:29:17 PM PDT 24
Finished Jul 30 05:29:33 PM PDT 24
Peak memory 256548 kb
Host smart-8bdce0b0-2120-40a2-aafd-ff692f09a245
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79902
5007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.799025007
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.1111070093
Short name T34
Test name
Test status
Simulation time 605900681 ps
CPU time 28.82 seconds
Started Jul 30 05:29:18 PM PDT 24
Finished Jul 30 05:29:47 PM PDT 24
Peak memory 270928 kb
Host smart-c9fdc7f0-13db-4a7c-b7b5-fcef47872b24
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1111070093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.1111070093
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.2753329796
Short name T357
Test name
Test status
Simulation time 85150212 ps
CPU time 4.12 seconds
Started Jul 30 05:29:15 PM PDT 24
Finished Jul 30 05:29:19 PM PDT 24
Peak memory 240116 kb
Host smart-998daf17-2ff8-4251-821c-225d6ef796ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27533
29796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.2753329796
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.1883339697
Short name T500
Test name
Test status
Simulation time 1574119219 ps
CPU time 35 seconds
Started Jul 30 05:29:14 PM PDT 24
Finished Jul 30 05:29:49 PM PDT 24
Peak memory 256428 kb
Host smart-9ce1e441-e3d0-4013-a69a-38f09aba5567
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18833
39697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.1883339697
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.3575680566
Short name T356
Test name
Test status
Simulation time 148217461689 ps
CPU time 2066.37 seconds
Started Jul 30 05:29:18 PM PDT 24
Finished Jul 30 06:03:45 PM PDT 24
Peak memory 273076 kb
Host smart-a437a916-7da9-4e68-99de-4437bd8b8f9f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575680566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.3575680566
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.3514053791
Short name T133
Test name
Test status
Simulation time 6200817127 ps
CPU time 64.74 seconds
Started Jul 30 05:29:23 PM PDT 24
Finished Jul 30 05:30:27 PM PDT 24
Peak memory 248356 kb
Host smart-e35dab67-9951-4390-ad20-d1856f10f397
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3514053791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.3514053791
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.1679310620
Short name T361
Test name
Test status
Simulation time 5963961335 ps
CPU time 114.28 seconds
Started Jul 30 05:29:18 PM PDT 24
Finished Jul 30 05:31:12 PM PDT 24
Peak memory 255924 kb
Host smart-0f969e4c-d775-462e-ad59-fb7af3750ddc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16793
10620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.1679310620
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.986444229
Short name T522
Test name
Test status
Simulation time 2695057542 ps
CPU time 44.49 seconds
Started Jul 30 05:29:24 PM PDT 24
Finished Jul 30 05:30:09 PM PDT 24
Peak memory 248340 kb
Host smart-7585d171-13f9-436e-aad8-26e7091d55d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98644
4229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.986444229
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.660283608
Short name T308
Test name
Test status
Simulation time 27174065216 ps
CPU time 1570.19 seconds
Started Jul 30 05:29:24 PM PDT 24
Finished Jul 30 05:55:34 PM PDT 24
Peak memory 271984 kb
Host smart-bb03c5ab-bc0d-4717-88c3-cc0a03d1805d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660283608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.660283608
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.3454322612
Short name T540
Test name
Test status
Simulation time 42091026538 ps
CPU time 930.55 seconds
Started Jul 30 05:29:24 PM PDT 24
Finished Jul 30 05:44:54 PM PDT 24
Peak memory 268252 kb
Host smart-91873871-3095-4280-ada0-0b8953855cf8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454322612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.3454322612
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.2722278853
Short name T403
Test name
Test status
Simulation time 735851416 ps
CPU time 32.22 seconds
Started Jul 30 05:29:19 PM PDT 24
Finished Jul 30 05:29:52 PM PDT 24
Peak memory 249300 kb
Host smart-445942b0-9bca-4b6f-a1aa-2458ee7d53a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27222
78853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.2722278853
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.3181153442
Short name T608
Test name
Test status
Simulation time 310819883 ps
CPU time 11.26 seconds
Started Jul 30 05:29:19 PM PDT 24
Finished Jul 30 05:29:30 PM PDT 24
Peak memory 255836 kb
Host smart-5abffeb8-c83a-4fc8-a023-20472a7566ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31811
53442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.3181153442
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.4068576437
Short name T9
Test name
Test status
Simulation time 8606255674 ps
CPU time 26.96 seconds
Started Jul 30 05:29:25 PM PDT 24
Finished Jul 30 05:29:52 PM PDT 24
Peak memory 270152 kb
Host smart-ffea55c3-c9bc-4b89-a51c-8a65756cf6fd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4068576437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.4068576437
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.346759243
Short name T271
Test name
Test status
Simulation time 463224190 ps
CPU time 29.86 seconds
Started Jul 30 05:29:18 PM PDT 24
Finished Jul 30 05:29:48 PM PDT 24
Peak memory 247712 kb
Host smart-f811e012-a03c-4479-93a1-90f2b464c13f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34675
9243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.346759243
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.3279671498
Short name T359
Test name
Test status
Simulation time 4181705173 ps
CPU time 52.95 seconds
Started Jul 30 05:29:19 PM PDT 24
Finished Jul 30 05:30:12 PM PDT 24
Peak memory 256296 kb
Host smart-78ef1c13-284f-4c7e-88c0-055c3f2d8b1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32796
71498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.3279671498
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.1242426602
Short name T585
Test name
Test status
Simulation time 83277262835 ps
CPU time 2479.53 seconds
Started Jul 30 05:29:25 PM PDT 24
Finished Jul 30 06:10:45 PM PDT 24
Peak memory 289224 kb
Host smart-3015fc49-e2a8-45a1-9653-e3b2100c994c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242426602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.1242426602
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.233281614
Short name T212
Test name
Test status
Simulation time 384389622 ps
CPU time 3.93 seconds
Started Jul 30 05:30:20 PM PDT 24
Finished Jul 30 05:30:24 PM PDT 24
Peak memory 248608 kb
Host smart-df56d753-965d-4bdb-b1a2-bf8abb084469
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=233281614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.233281614
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.104515836
Short name T122
Test name
Test status
Simulation time 94035153929 ps
CPU time 1480.52 seconds
Started Jul 30 05:30:20 PM PDT 24
Finished Jul 30 05:55:00 PM PDT 24
Peak memory 288648 kb
Host smart-fe3724ba-5eb9-439b-bd5b-a66cddd4057e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104515836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.104515836
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.1744383762
Short name T423
Test name
Test status
Simulation time 822344053 ps
CPU time 12.42 seconds
Started Jul 30 05:30:15 PM PDT 24
Finished Jul 30 05:30:27 PM PDT 24
Peak memory 248288 kb
Host smart-84038cdd-8aa2-44e3-8faa-d63ae658a5c9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1744383762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.1744383762
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.2474138119
Short name T347
Test name
Test status
Simulation time 121310844 ps
CPU time 8.84 seconds
Started Jul 30 05:30:12 PM PDT 24
Finished Jul 30 05:30:20 PM PDT 24
Peak memory 250828 kb
Host smart-a10b43e9-016a-4a72-858c-a628d3a80b3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24741
38119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.2474138119
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.339833670
Short name T73
Test name
Test status
Simulation time 2480894250 ps
CPU time 39.78 seconds
Started Jul 30 05:30:13 PM PDT 24
Finished Jul 30 05:30:53 PM PDT 24
Peak memory 248412 kb
Host smart-4f1b90be-ce72-4602-a336-207e86276025
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33983
3670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.339833670
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.4031029464
Short name T309
Test name
Test status
Simulation time 73630831200 ps
CPU time 1881.84 seconds
Started Jul 30 05:30:17 PM PDT 24
Finished Jul 30 06:01:39 PM PDT 24
Peak memory 288492 kb
Host smart-eb58d564-865b-4edf-b1bb-e89c7c44da6d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031029464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.4031029464
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.3617191156
Short name T616
Test name
Test status
Simulation time 11397175128 ps
CPU time 127.15 seconds
Started Jul 30 05:30:16 PM PDT 24
Finished Jul 30 05:32:23 PM PDT 24
Peak memory 247512 kb
Host smart-8e905341-2be3-4cd8-a098-eecaca500689
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617191156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.3617191156
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.3000186816
Short name T45
Test name
Test status
Simulation time 267020230 ps
CPU time 19 seconds
Started Jul 30 05:30:08 PM PDT 24
Finished Jul 30 05:30:27 PM PDT 24
Peak memory 254468 kb
Host smart-6d224818-791b-4f5e-94cc-0f1c606f5b76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30001
86816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.3000186816
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.3030420453
Short name T693
Test name
Test status
Simulation time 779140109 ps
CPU time 37.46 seconds
Started Jul 30 05:30:07 PM PDT 24
Finished Jul 30 05:30:45 PM PDT 24
Peak memory 247880 kb
Host smart-f4207919-0291-4759-8ffe-7e89babe1000
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30304
20453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.3030420453
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.369421550
Short name T698
Test name
Test status
Simulation time 308228859 ps
CPU time 19.3 seconds
Started Jul 30 05:30:07 PM PDT 24
Finished Jul 30 05:30:26 PM PDT 24
Peak memory 248324 kb
Host smart-199855d3-1b60-4bc4-8a9f-6c1709c46acb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36942
1550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.369421550
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.1782841882
Short name T460
Test name
Test status
Simulation time 2342128736 ps
CPU time 182.22 seconds
Started Jul 30 05:30:16 PM PDT 24
Finished Jul 30 05:33:18 PM PDT 24
Peak memory 256552 kb
Host smart-1805b5d6-83bb-48db-ac04-eddd98e9dc99
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782841882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.1782841882
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.3756079034
Short name T221
Test name
Test status
Simulation time 49021375 ps
CPU time 4.15 seconds
Started Jul 30 05:30:26 PM PDT 24
Finished Jul 30 05:30:30 PM PDT 24
Peak memory 248660 kb
Host smart-8719a2ee-5a0a-4eac-92ce-7847f082321d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3756079034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.3756079034
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.4272632439
Short name T77
Test name
Test status
Simulation time 12129408360 ps
CPU time 975.44 seconds
Started Jul 30 05:30:17 PM PDT 24
Finished Jul 30 05:46:33 PM PDT 24
Peak memory 288312 kb
Host smart-fd2c3ce4-f0f3-45ea-b373-8c22ace2d3d3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272632439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.4272632439
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.3094414022
Short name T487
Test name
Test status
Simulation time 195548748 ps
CPU time 11.07 seconds
Started Jul 30 05:30:24 PM PDT 24
Finished Jul 30 05:30:35 PM PDT 24
Peak memory 248280 kb
Host smart-e6a25aba-d074-4de8-b6d8-7749d7ee51da
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3094414022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.3094414022
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.1862957516
Short name T246
Test name
Test status
Simulation time 3076275205 ps
CPU time 46.21 seconds
Started Jul 30 05:30:19 PM PDT 24
Finished Jul 30 05:31:05 PM PDT 24
Peak memory 256520 kb
Host smart-d61e63f3-d97c-4a50-8806-cf680d6f3c50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18629
57516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.1862957516
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.1997081097
Short name T315
Test name
Test status
Simulation time 16178271407 ps
CPU time 828.82 seconds
Started Jul 30 05:30:27 PM PDT 24
Finished Jul 30 05:44:16 PM PDT 24
Peak memory 272192 kb
Host smart-3723a22a-050d-4b38-bc17-4f1df4a0ba03
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997081097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.1997081097
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.2972617618
Short name T636
Test name
Test status
Simulation time 85915684099 ps
CPU time 2013.65 seconds
Started Jul 30 05:30:26 PM PDT 24
Finished Jul 30 06:04:00 PM PDT 24
Peak memory 288508 kb
Host smart-19df7907-a46c-4e5b-a0f4-544076b56db1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972617618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.2972617618
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.2793871718
Short name T536
Test name
Test status
Simulation time 22266281992 ps
CPU time 232.09 seconds
Started Jul 30 05:30:27 PM PDT 24
Finished Jul 30 05:34:19 PM PDT 24
Peak memory 248336 kb
Host smart-dfa4f0dd-d4fa-4f54-ab67-fc7c5672ab77
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793871718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.2793871718
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.407348930
Short name T663
Test name
Test status
Simulation time 123173977 ps
CPU time 6.14 seconds
Started Jul 30 05:30:21 PM PDT 24
Finished Jul 30 05:30:28 PM PDT 24
Peak memory 240080 kb
Host smart-48fcfc17-75e7-4c9a-8335-245eeb42b310
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40734
8930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.407348930
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.352668020
Short name T29
Test name
Test status
Simulation time 798855775 ps
CPU time 33.96 seconds
Started Jul 30 05:30:20 PM PDT 24
Finished Jul 30 05:30:54 PM PDT 24
Peak memory 256056 kb
Host smart-a138f6e1-7c8e-42e6-86a4-5dd8723a1f0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35266
8020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.352668020
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.3093953383
Short name T106
Test name
Test status
Simulation time 2744960065 ps
CPU time 25.53 seconds
Started Jul 30 05:30:19 PM PDT 24
Finished Jul 30 05:30:45 PM PDT 24
Peak memory 248332 kb
Host smart-6ffcd168-2862-4f48-a250-feded441036c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30939
53383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.3093953383
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.3294421661
Short name T435
Test name
Test status
Simulation time 658204226 ps
CPU time 25.57 seconds
Started Jul 30 05:30:21 PM PDT 24
Finished Jul 30 05:30:46 PM PDT 24
Peak memory 256420 kb
Host smart-2bb41979-7b74-473b-a034-4e004906bfab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32944
21661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.3294421661
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.3934132923
Short name T119
Test name
Test status
Simulation time 96224478647 ps
CPU time 3202 seconds
Started Jul 30 05:30:25 PM PDT 24
Finished Jul 30 06:23:47 PM PDT 24
Peak memory 298516 kb
Host smart-10170d28-bc69-49fb-8f2b-7d029ff21444
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934132923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.3934132923
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all_with_rand_reset.3043529868
Short name T32
Test name
Test status
Simulation time 151567512834 ps
CPU time 3394.41 seconds
Started Jul 30 05:30:23 PM PDT 24
Finished Jul 30 06:26:58 PM PDT 24
Peak memory 289248 kb
Host smart-1deea8a5-7a08-4aff-8133-51a194466ea2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043529868 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.alert_handler_stress_all_with_rand_reset.3043529868
Directory /workspace/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.275140832
Short name T227
Test name
Test status
Simulation time 88671948 ps
CPU time 3.24 seconds
Started Jul 30 05:30:45 PM PDT 24
Finished Jul 30 05:30:48 PM PDT 24
Peak memory 248552 kb
Host smart-7aea988e-9ad9-447d-aee7-8837927e4750
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=275140832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.275140832
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.535610114
Short name T61
Test name
Test status
Simulation time 1066727834 ps
CPU time 14.04 seconds
Started Jul 30 05:30:29 PM PDT 24
Finished Jul 30 05:30:43 PM PDT 24
Peak memory 248344 kb
Host smart-70c2b27b-de0b-4064-88d6-8d5e3ac6a916
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=535610114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.535610114
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.2589180600
Short name T684
Test name
Test status
Simulation time 5257261455 ps
CPU time 97.58 seconds
Started Jul 30 05:30:23 PM PDT 24
Finished Jul 30 05:32:01 PM PDT 24
Peak memory 256492 kb
Host smart-81f4724a-ef7c-4d18-988f-4ac286580da5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25891
80600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.2589180600
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.3513745208
Short name T364
Test name
Test status
Simulation time 148147265 ps
CPU time 12.26 seconds
Started Jul 30 05:30:25 PM PDT 24
Finished Jul 30 05:30:37 PM PDT 24
Peak memory 256264 kb
Host smart-139f9477-f3ee-42b3-bf10-7906cb11f32d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35137
45208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.3513745208
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.2941881701
Short name T412
Test name
Test status
Simulation time 11431879129 ps
CPU time 1066.51 seconds
Started Jul 30 05:30:29 PM PDT 24
Finished Jul 30 05:48:16 PM PDT 24
Peak memory 272880 kb
Host smart-9db4802b-8f6f-41ed-b1e8-1726c10c26d5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941881701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.2941881701
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.1966677900
Short name T432
Test name
Test status
Simulation time 41269361522 ps
CPU time 2560.36 seconds
Started Jul 30 05:30:29 PM PDT 24
Finished Jul 30 06:13:09 PM PDT 24
Peak memory 283740 kb
Host smart-571f1949-deb6-4ac3-9dbf-751f44934da0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966677900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.1966677900
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.150190791
Short name T419
Test name
Test status
Simulation time 187992672 ps
CPU time 19.19 seconds
Started Jul 30 05:30:28 PM PDT 24
Finished Jul 30 05:30:48 PM PDT 24
Peak memory 248368 kb
Host smart-e7b27ca7-14a3-4f55-9d81-50be31887914
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15019
0791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.150190791
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.3810402434
Short name T568
Test name
Test status
Simulation time 241202140 ps
CPU time 4.88 seconds
Started Jul 30 05:30:25 PM PDT 24
Finished Jul 30 05:30:30 PM PDT 24
Peak memory 239608 kb
Host smart-daf9f397-b2e0-477d-bb22-46b2000e30b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38104
02434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.3810402434
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.204486261
Short name T497
Test name
Test status
Simulation time 3115039127 ps
CPU time 54.53 seconds
Started Jul 30 05:30:27 PM PDT 24
Finished Jul 30 05:31:21 PM PDT 24
Peak memory 248320 kb
Host smart-3f5efae1-2fe2-4cc8-b66f-eb3f310f5432
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20448
6261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.204486261
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.2880364451
Short name T637
Test name
Test status
Simulation time 218098067 ps
CPU time 3.79 seconds
Started Jul 30 05:30:24 PM PDT 24
Finished Jul 30 05:30:27 PM PDT 24
Peak memory 249840 kb
Host smart-6da27407-186d-422d-bcfc-b31eec3b202e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28803
64451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.2880364451
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.887978805
Short name T31
Test name
Test status
Simulation time 14047630253 ps
CPU time 1304.45 seconds
Started Jul 30 05:30:28 PM PDT 24
Finished Jul 30 05:52:12 PM PDT 24
Peak memory 289024 kb
Host smart-a140fda9-9135-4203-9f46-0255eacb5693
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887978805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_han
dler_stress_all.887978805
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.482591879
Short name T596
Test name
Test status
Simulation time 15032789056 ps
CPU time 1258.36 seconds
Started Jul 30 05:33:10 PM PDT 24
Finished Jul 30 05:54:09 PM PDT 24
Peak memory 285496 kb
Host smart-ab300edb-7fd9-4a26-b7f3-c97953f86cfb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482591879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.482591879
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.2671567213
Short name T590
Test name
Test status
Simulation time 123254232 ps
CPU time 9.03 seconds
Started Jul 30 05:30:39 PM PDT 24
Finished Jul 30 05:30:48 PM PDT 24
Peak memory 248316 kb
Host smart-ced92355-b18f-4efc-976f-43f624ea627f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2671567213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.2671567213
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.4230742282
Short name T643
Test name
Test status
Simulation time 1448592654 ps
CPU time 102.21 seconds
Started Jul 30 05:30:33 PM PDT 24
Finished Jul 30 05:32:15 PM PDT 24
Peak memory 256576 kb
Host smart-53cddba8-c4c1-4384-ba74-7f0acde563f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42307
42282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.4230742282
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.654711115
Short name T464
Test name
Test status
Simulation time 652172887 ps
CPU time 42.02 seconds
Started Jul 30 05:30:32 PM PDT 24
Finished Jul 30 05:31:14 PM PDT 24
Peak memory 256384 kb
Host smart-e2ed10b7-2124-4d23-8354-48a73e9ba2ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65471
1115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.654711115
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.754323773
Short name T288
Test name
Test status
Simulation time 46256270491 ps
CPU time 1215.74 seconds
Started Jul 30 05:30:38 PM PDT 24
Finished Jul 30 05:50:54 PM PDT 24
Peak memory 284176 kb
Host smart-57397027-a5d6-43ec-8518-5c34e541c8a4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754323773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.754323773
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.3252225896
Short name T514
Test name
Test status
Simulation time 6306566498 ps
CPU time 547.64 seconds
Started Jul 30 05:30:36 PM PDT 24
Finished Jul 30 05:39:44 PM PDT 24
Peak memory 272288 kb
Host smart-be7b2c1d-edef-4aaf-9f61-c00fea3ccf91
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252225896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.3252225896
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.3217270763
Short name T198
Test name
Test status
Simulation time 24198494837 ps
CPU time 261.14 seconds
Started Jul 30 05:30:36 PM PDT 24
Finished Jul 30 05:34:58 PM PDT 24
Peak memory 255008 kb
Host smart-2aab5406-29b2-4f11-8ee3-5e8244ef227f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217270763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.3217270763
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.719883221
Short name T240
Test name
Test status
Simulation time 249442199 ps
CPU time 24.58 seconds
Started Jul 30 05:30:31 PM PDT 24
Finished Jul 30 05:30:56 PM PDT 24
Peak memory 255808 kb
Host smart-38169787-8e1a-4060-babd-db339c55e707
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71988
3221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.719883221
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.82957102
Short name T645
Test name
Test status
Simulation time 1019831870 ps
CPU time 31.14 seconds
Started Jul 30 05:30:32 PM PDT 24
Finished Jul 30 05:31:04 PM PDT 24
Peak memory 255836 kb
Host smart-3f0e24fa-52e5-4850-9c4b-70ca7b4d4bcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82957
102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.82957102
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.3621564486
Short name T78
Test name
Test status
Simulation time 806668447 ps
CPU time 51.91 seconds
Started Jul 30 05:30:35 PM PDT 24
Finished Jul 30 05:31:27 PM PDT 24
Peak memory 247876 kb
Host smart-7a4ead03-0907-4e4b-94c6-c8ed35ba6a76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36215
64486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.3621564486
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.4176361478
Short name T38
Test name
Test status
Simulation time 1210141630 ps
CPU time 32.58 seconds
Started Jul 30 05:30:33 PM PDT 24
Finished Jul 30 05:31:05 PM PDT 24
Peak memory 255812 kb
Host smart-a123bfbc-7bc2-448f-9269-e2375cf46fb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41763
61478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.4176361478
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.3787937358
Short name T263
Test name
Test status
Simulation time 14864771285 ps
CPU time 385.47 seconds
Started Jul 30 05:30:41 PM PDT 24
Finished Jul 30 05:37:07 PM PDT 24
Peak memory 264724 kb
Host smart-892db166-24e2-4942-b0b6-ca81a6b21280
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787937358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.3787937358
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.3968392080
Short name T224
Test name
Test status
Simulation time 64368467 ps
CPU time 3.8 seconds
Started Jul 30 05:30:46 PM PDT 24
Finished Jul 30 05:30:50 PM PDT 24
Peak memory 248684 kb
Host smart-7ffc51c7-bd78-4aee-b27a-b2fb3dc7500e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3968392080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.3968392080
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.422986321
Short name T105
Test name
Test status
Simulation time 128774056106 ps
CPU time 1893.1 seconds
Started Jul 30 05:30:39 PM PDT 24
Finished Jul 30 06:02:12 PM PDT 24
Peak memory 288560 kb
Host smart-481bbb39-e627-4c6f-9df9-86a5895c67ea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422986321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.422986321
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.3005034750
Short name T427
Test name
Test status
Simulation time 3986323810 ps
CPU time 286.07 seconds
Started Jul 30 05:30:40 PM PDT 24
Finished Jul 30 05:35:26 PM PDT 24
Peak memory 256556 kb
Host smart-16f20b30-bf64-4ec7-b84a-9efa9dde5898
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30050
34750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.3005034750
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.1692767168
Short name T662
Test name
Test status
Simulation time 336498802 ps
CPU time 8.09 seconds
Started Jul 30 05:30:42 PM PDT 24
Finished Jul 30 05:30:50 PM PDT 24
Peak memory 254032 kb
Host smart-e498d6ac-d88e-4773-9a79-09139331987b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16927
67168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.1692767168
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.1261890841
Short name T611
Test name
Test status
Simulation time 148601333118 ps
CPU time 1473.48 seconds
Started Jul 30 05:30:41 PM PDT 24
Finished Jul 30 05:55:15 PM PDT 24
Peak memory 272508 kb
Host smart-67bd4466-66f5-4646-bf39-9bbfacdfbb2e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261890841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.1261890841
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.2145137788
Short name T396
Test name
Test status
Simulation time 541951480 ps
CPU time 22.94 seconds
Started Jul 30 05:30:36 PM PDT 24
Finished Jul 30 05:30:59 PM PDT 24
Peak memory 256004 kb
Host smart-e9b94544-8c7c-4734-9e7b-0cd09cc5200e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21451
37788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.2145137788
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.1971404382
Short name T560
Test name
Test status
Simulation time 507405739 ps
CPU time 35.36 seconds
Started Jul 30 05:30:40 PM PDT 24
Finished Jul 30 05:31:16 PM PDT 24
Peak memory 248000 kb
Host smart-a74a9cbb-aab8-4241-bce1-125da49287af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19714
04382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.1971404382
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.2166255621
Short name T597
Test name
Test status
Simulation time 568160325 ps
CPU time 15.31 seconds
Started Jul 30 05:30:42 PM PDT 24
Finished Jul 30 05:30:58 PM PDT 24
Peak memory 255940 kb
Host smart-4b63b500-3775-44de-a356-823e376d5b95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21662
55621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.2166255621
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.2741574094
Short name T389
Test name
Test status
Simulation time 1190741986 ps
CPU time 35.39 seconds
Started Jul 30 05:30:37 PM PDT 24
Finished Jul 30 05:31:12 PM PDT 24
Peak memory 255576 kb
Host smart-a23d64ee-1d9a-4cb1-9c38-cf39628217a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27415
74094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.2741574094
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.1285115368
Short name T490
Test name
Test status
Simulation time 218696570096 ps
CPU time 2461.37 seconds
Started Jul 30 05:30:45 PM PDT 24
Finished Jul 30 06:11:47 PM PDT 24
Peak memory 289268 kb
Host smart-a89694cd-a6fa-4408-a8ce-969f9c833389
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285115368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.1285115368
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all_with_rand_reset.1346542606
Short name T192
Test name
Test status
Simulation time 61121023426 ps
CPU time 3284.38 seconds
Started Jul 30 05:30:49 PM PDT 24
Finished Jul 30 06:25:33 PM PDT 24
Peak memory 305452 kb
Host smart-7969a78b-0331-499c-bf38-766daf3bb87d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346542606 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.alert_handler_stress_all_with_rand_reset.1346542606
Directory /workspace/14.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.3025391528
Short name T59
Test name
Test status
Simulation time 73991831534 ps
CPU time 2035.39 seconds
Started Jul 30 05:30:48 PM PDT 24
Finished Jul 30 06:04:44 PM PDT 24
Peak memory 288388 kb
Host smart-855de13e-3856-4fdb-8099-e5c989e7ccba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025391528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.3025391528
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.354818599
Short name T440
Test name
Test status
Simulation time 9616650471 ps
CPU time 36.6 seconds
Started Jul 30 05:30:53 PM PDT 24
Finished Jul 30 05:31:30 PM PDT 24
Peak memory 248392 kb
Host smart-73a296e4-a930-4bb0-b4c5-db66b00cefd3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=354818599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.354818599
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.1034836477
Short name T483
Test name
Test status
Simulation time 21336067959 ps
CPU time 308.59 seconds
Started Jul 30 05:30:48 PM PDT 24
Finished Jul 30 05:35:57 PM PDT 24
Peak memory 256456 kb
Host smart-235c4e93-575e-4017-88b0-d8135c6e399c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10348
36477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.1034836477
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.2604446270
Short name T372
Test name
Test status
Simulation time 573176638 ps
CPU time 36.25 seconds
Started Jul 30 05:30:51 PM PDT 24
Finished Jul 30 05:31:27 PM PDT 24
Peak memory 248124 kb
Host smart-67f68a3b-334a-4aa1-a8fa-b37b643809bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26044
46270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.2604446270
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.488699690
Short name T237
Test name
Test status
Simulation time 160705275334 ps
CPU time 2549.95 seconds
Started Jul 30 05:30:49 PM PDT 24
Finished Jul 30 06:13:19 PM PDT 24
Peak memory 288404 kb
Host smart-c3dcd51f-068b-429d-8f6a-de4f2c2b755a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488699690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.488699690
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.623582819
Short name T474
Test name
Test status
Simulation time 79711549438 ps
CPU time 2392.56 seconds
Started Jul 30 05:30:51 PM PDT 24
Finished Jul 30 06:10:44 PM PDT 24
Peak memory 272948 kb
Host smart-87045d3b-75d7-4549-8cb2-5338fadfc24d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623582819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.623582819
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.747705237
Short name T545
Test name
Test status
Simulation time 34434643921 ps
CPU time 238.92 seconds
Started Jul 30 05:30:51 PM PDT 24
Finished Jul 30 05:34:50 PM PDT 24
Peak memory 248448 kb
Host smart-bfea404d-d681-4649-a3fc-3c1247efedb6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747705237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.747705237
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.2614826195
Short name T370
Test name
Test status
Simulation time 53231831 ps
CPU time 5.97 seconds
Started Jul 30 05:30:50 PM PDT 24
Finished Jul 30 05:30:56 PM PDT 24
Peak memory 248316 kb
Host smart-80f49247-b3a4-4eb4-9adf-cc314311dfc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26148
26195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.2614826195
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.266854737
Short name T614
Test name
Test status
Simulation time 410600422 ps
CPU time 28.89 seconds
Started Jul 30 05:30:49 PM PDT 24
Finished Jul 30 05:31:18 PM PDT 24
Peak memory 247772 kb
Host smart-5919b224-c7b2-4f5b-bbfc-ac5e9f8dab46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26685
4737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.266854737
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.162060345
Short name T256
Test name
Test status
Simulation time 169532779 ps
CPU time 18.33 seconds
Started Jul 30 05:30:48 PM PDT 24
Finished Jul 30 05:31:07 PM PDT 24
Peak memory 248352 kb
Host smart-554e2572-469b-42c9-a1d7-c36a96e4a326
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16206
0345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.162060345
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.241216021
Short name T344
Test name
Test status
Simulation time 17082438 ps
CPU time 2.91 seconds
Started Jul 30 05:30:51 PM PDT 24
Finished Jul 30 05:30:54 PM PDT 24
Peak memory 248308 kb
Host smart-274756de-4f7f-4e2f-bbe7-87234ff51622
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24121
6021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.241216021
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.900409476
Short name T114
Test name
Test status
Simulation time 170370117454 ps
CPU time 2108.87 seconds
Started Jul 30 05:30:53 PM PDT 24
Finished Jul 30 06:06:02 PM PDT 24
Peak memory 272992 kb
Host smart-8870bbdd-15aa-4cf1-b1b4-c0067950d658
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900409476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_han
dler_stress_all.900409476
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.891973503
Short name T228
Test name
Test status
Simulation time 111779835 ps
CPU time 3.25 seconds
Started Jul 30 05:30:56 PM PDT 24
Finished Jul 30 05:31:00 PM PDT 24
Peak memory 248640 kb
Host smart-6ece1908-6b49-49d2-acbb-42353de5ce18
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=891973503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.891973503
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.2786182029
Short name T680
Test name
Test status
Simulation time 128726117096 ps
CPU time 2141.94 seconds
Started Jul 30 05:30:53 PM PDT 24
Finished Jul 30 06:06:35 PM PDT 24
Peak memory 287200 kb
Host smart-023daa04-dece-4586-b7d0-9048ce82fde4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786182029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.2786182029
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.3176063624
Short name T513
Test name
Test status
Simulation time 588961904 ps
CPU time 8.7 seconds
Started Jul 30 05:30:53 PM PDT 24
Finished Jul 30 05:31:02 PM PDT 24
Peak memory 248260 kb
Host smart-8ab32c5c-cbba-4dbd-b185-b623c8769387
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3176063624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.3176063624
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.3956647525
Short name T387
Test name
Test status
Simulation time 3358879937 ps
CPU time 183.32 seconds
Started Jul 30 05:30:51 PM PDT 24
Finished Jul 30 05:33:55 PM PDT 24
Peak memory 255952 kb
Host smart-43d9ae4e-4f7f-4a82-9959-b63ceb76206f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39566
47525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.3956647525
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.1794951093
Short name T502
Test name
Test status
Simulation time 618159251 ps
CPU time 25.58 seconds
Started Jul 30 05:30:54 PM PDT 24
Finished Jul 30 05:31:20 PM PDT 24
Peak memory 248276 kb
Host smart-56cbc085-2a56-4912-a189-b73234fb7646
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17949
51093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.1794951093
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.1211886316
Short name T314
Test name
Test status
Simulation time 21595169256 ps
CPU time 858.95 seconds
Started Jul 30 05:30:50 PM PDT 24
Finished Jul 30 05:45:09 PM PDT 24
Peak memory 272048 kb
Host smart-9371558b-6539-4251-bc58-a0b8da62ffb4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211886316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.1211886316
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.3496361767
Short name T27
Test name
Test status
Simulation time 30245016406 ps
CPU time 673.25 seconds
Started Jul 30 05:30:53 PM PDT 24
Finished Jul 30 05:42:07 PM PDT 24
Peak memory 268924 kb
Host smart-319ff814-6727-46e0-bcc7-3ebd8cac33ed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496361767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.3496361767
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.4263400573
Short name T289
Test name
Test status
Simulation time 38876684097 ps
CPU time 438.93 seconds
Started Jul 30 05:30:53 PM PDT 24
Finished Jul 30 05:38:12 PM PDT 24
Peak memory 255044 kb
Host smart-73f787d0-4dd7-46aa-ab84-a1e7cac056ba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263400573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.4263400573
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.2501919606
Short name T642
Test name
Test status
Simulation time 4412019920 ps
CPU time 51.41 seconds
Started Jul 30 05:30:54 PM PDT 24
Finished Jul 30 05:31:46 PM PDT 24
Peak memory 255620 kb
Host smart-93e4f45c-92d0-4a87-a1a6-14dc485dd2ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25019
19606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.2501919606
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.3551452910
Short name T67
Test name
Test status
Simulation time 2135867032 ps
CPU time 30.75 seconds
Started Jul 30 05:30:52 PM PDT 24
Finished Jul 30 05:31:23 PM PDT 24
Peak memory 255856 kb
Host smart-e308f6c8-1279-49aa-9fc4-ee4f7df85710
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35514
52910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.3551452910
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.780865297
Short name T453
Test name
Test status
Simulation time 870766789 ps
CPU time 25.66 seconds
Started Jul 30 05:30:52 PM PDT 24
Finished Jul 30 05:31:18 PM PDT 24
Peak memory 248920 kb
Host smart-f4f33165-a3bf-4497-a9cd-3e4b234f5990
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78086
5297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.780865297
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.3573712590
Short name T339
Test name
Test status
Simulation time 39502719 ps
CPU time 4.45 seconds
Started Jul 30 05:30:52 PM PDT 24
Finished Jul 30 05:30:57 PM PDT 24
Peak memory 248320 kb
Host smart-62c6a9f0-16b0-4a12-b580-85f223a25a4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35737
12590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.3573712590
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.933520278
Short name T676
Test name
Test status
Simulation time 31963392836 ps
CPU time 1920.46 seconds
Started Jul 30 05:30:57 PM PDT 24
Finished Jul 30 06:02:58 PM PDT 24
Peak memory 288652 kb
Host smart-872d0c05-b8d5-4fb7-aa23-adba0b209e3c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933520278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_han
dler_stress_all.933520278
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.675456244
Short name T193
Test name
Test status
Simulation time 53352870247 ps
CPU time 1973.04 seconds
Started Jul 30 05:30:58 PM PDT 24
Finished Jul 30 06:03:51 PM PDT 24
Peak memory 282272 kb
Host smart-6b5a408e-bb2e-44e0-a3c9-83cfa2cd5812
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675456244 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.675456244
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.2260018136
Short name T210
Test name
Test status
Simulation time 33226252 ps
CPU time 3.6 seconds
Started Jul 30 05:31:04 PM PDT 24
Finished Jul 30 05:31:08 PM PDT 24
Peak memory 248632 kb
Host smart-d2df1fa3-60cf-4909-a7a9-c9b0e58c1c66
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2260018136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.2260018136
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.1894213309
Short name T415
Test name
Test status
Simulation time 8873639552 ps
CPU time 679.24 seconds
Started Jul 30 05:31:00 PM PDT 24
Finished Jul 30 05:42:20 PM PDT 24
Peak memory 272592 kb
Host smart-3647fa10-f94a-43da-968f-9c70b97054e3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894213309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.1894213309
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.3997935821
Short name T238
Test name
Test status
Simulation time 234649657 ps
CPU time 11.44 seconds
Started Jul 30 05:31:00 PM PDT 24
Finished Jul 30 05:31:11 PM PDT 24
Peak memory 248204 kb
Host smart-3b6cec54-079b-4dbb-92bf-4715ebea5aa5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3997935821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.3997935821
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.2002799609
Short name T245
Test name
Test status
Simulation time 2602314233 ps
CPU time 87.1 seconds
Started Jul 30 05:31:02 PM PDT 24
Finished Jul 30 05:32:30 PM PDT 24
Peak memory 256076 kb
Host smart-f4ef4cb1-51c6-4eb8-b4ce-ede69088e114
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20027
99609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.2002799609
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.3780218185
Short name T494
Test name
Test status
Simulation time 1866518186 ps
CPU time 62.03 seconds
Started Jul 30 05:30:57 PM PDT 24
Finished Jul 30 05:31:59 PM PDT 24
Peak memory 255960 kb
Host smart-4e3ce097-13a3-4dec-b53a-56793116b7ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37802
18185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.3780218185
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.71406623
Short name T686
Test name
Test status
Simulation time 52500160479 ps
CPU time 2216.21 seconds
Started Jul 30 05:31:00 PM PDT 24
Finished Jul 30 06:07:57 PM PDT 24
Peak memory 272840 kb
Host smart-78805406-9c2a-4825-8b43-fd59757e03bf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71406623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.71406623
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.993426217
Short name T86
Test name
Test status
Simulation time 117236574875 ps
CPU time 403.31 seconds
Started Jul 30 05:30:59 PM PDT 24
Finished Jul 30 05:37:43 PM PDT 24
Peak memory 247964 kb
Host smart-dc151ac4-e3ea-40af-880e-d38c1b140d09
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993426217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.993426217
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.2135760501
Short name T472
Test name
Test status
Simulation time 607153568 ps
CPU time 12.32 seconds
Started Jul 30 05:30:55 PM PDT 24
Finished Jul 30 05:31:07 PM PDT 24
Peak memory 248392 kb
Host smart-7fe4c7fa-573f-47d5-97be-b8d218316614
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21357
60501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.2135760501
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.3553920643
Short name T417
Test name
Test status
Simulation time 1862394546 ps
CPU time 32.94 seconds
Started Jul 30 05:30:58 PM PDT 24
Finished Jul 30 05:31:31 PM PDT 24
Peak memory 247660 kb
Host smart-1d2939ba-1ac1-4f90-bf75-c50b5f43edfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35539
20643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.3553920643
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.1784653373
Short name T567
Test name
Test status
Simulation time 989717219 ps
CPU time 28.65 seconds
Started Jul 30 05:31:01 PM PDT 24
Finished Jul 30 05:31:30 PM PDT 24
Peak memory 248352 kb
Host smart-5aaeb9fb-0507-4637-ad0c-47e6947c4e9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17846
53373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.1784653373
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.1193207680
Short name T589
Test name
Test status
Simulation time 948303495 ps
CPU time 18.32 seconds
Started Jul 30 05:30:57 PM PDT 24
Finished Jul 30 05:31:16 PM PDT 24
Peak memory 256592 kb
Host smart-35c45aee-f07f-4a1f-985a-900f9cc8adb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11932
07680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.1193207680
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.2065957981
Short name T98
Test name
Test status
Simulation time 15427229338 ps
CPU time 366.63 seconds
Started Jul 30 05:31:13 PM PDT 24
Finished Jul 30 05:37:19 PM PDT 24
Peak memory 264984 kb
Host smart-29a0047b-7d33-47c1-bbb4-4065273ef50c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065957981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.2065957981
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.4055465519
Short name T219
Test name
Test status
Simulation time 62424665 ps
CPU time 4.5 seconds
Started Jul 30 05:31:08 PM PDT 24
Finished Jul 30 05:31:13 PM PDT 24
Peak memory 248608 kb
Host smart-489cbadd-82b1-4950-b3e3-69e0838f0316
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4055465519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.4055465519
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.3930024402
Short name T94
Test name
Test status
Simulation time 39156654019 ps
CPU time 2412 seconds
Started Jul 30 05:31:04 PM PDT 24
Finished Jul 30 06:11:16 PM PDT 24
Peak memory 289168 kb
Host smart-a9a816ed-6e5f-452e-9be6-1e92ec81c2ef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930024402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.3930024402
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.354335838
Short name T610
Test name
Test status
Simulation time 1923774522 ps
CPU time 22.95 seconds
Started Jul 30 05:31:16 PM PDT 24
Finished Jul 30 05:31:39 PM PDT 24
Peak memory 248264 kb
Host smart-9c99342e-5c20-48fa-898d-91e7937112bf
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=354335838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.354335838
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.1031181824
Short name T355
Test name
Test status
Simulation time 1692204505 ps
CPU time 100.09 seconds
Started Jul 30 05:31:05 PM PDT 24
Finished Jul 30 05:32:45 PM PDT 24
Peak memory 256100 kb
Host smart-4352ce2b-4b46-4880-991c-065766a6385d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10311
81824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.1031181824
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.4054218280
Short name T562
Test name
Test status
Simulation time 320054202 ps
CPU time 21.01 seconds
Started Jul 30 05:31:02 PM PDT 24
Finished Jul 30 05:31:24 PM PDT 24
Peak memory 248276 kb
Host smart-67c49323-3d7f-4e98-89b4-2fe640ccdbc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40542
18280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.4054218280
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.3678353847
Short name T312
Test name
Test status
Simulation time 40431766303 ps
CPU time 2223.31 seconds
Started Jul 30 05:31:10 PM PDT 24
Finished Jul 30 06:08:14 PM PDT 24
Peak memory 272904 kb
Host smart-0637dd3e-75d7-4d0c-8d9b-ba7558556462
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678353847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.3678353847
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.482036114
Short name T400
Test name
Test status
Simulation time 10750588648 ps
CPU time 1486.43 seconds
Started Jul 30 05:31:16 PM PDT 24
Finished Jul 30 05:56:02 PM PDT 24
Peak memory 288636 kb
Host smart-86c55157-5c3a-4d3f-8663-e48b4e1faad4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482036114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.482036114
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.3219641091
Short name T649
Test name
Test status
Simulation time 191075950625 ps
CPU time 490.72 seconds
Started Jul 30 05:31:08 PM PDT 24
Finished Jul 30 05:39:19 PM PDT 24
Peak memory 248376 kb
Host smart-c5735c7c-ba3d-4cf0-9246-1f612481998c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219641091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.3219641091
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.1914209501
Short name T236
Test name
Test status
Simulation time 489867394 ps
CPU time 10.14 seconds
Started Jul 30 05:31:02 PM PDT 24
Finished Jul 30 05:31:12 PM PDT 24
Peak memory 248308 kb
Host smart-17a4df3b-4d00-45dc-b799-1402b2edd7f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19142
09501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.1914209501
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.3676510043
Short name T410
Test name
Test status
Simulation time 878340582 ps
CPU time 58.6 seconds
Started Jul 30 05:30:58 PM PDT 24
Finished Jul 30 05:31:58 PM PDT 24
Peak memory 248288 kb
Host smart-0bbb3491-de37-4e5a-b899-73f24c6ab32d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36765
10043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.3676510043
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.2651374622
Short name T259
Test name
Test status
Simulation time 194659777 ps
CPU time 21 seconds
Started Jul 30 05:31:05 PM PDT 24
Finished Jul 30 05:31:26 PM PDT 24
Peak memory 247480 kb
Host smart-d3d300f5-ecd3-476f-a4e8-c4a3834f4742
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26513
74622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.2651374622
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.3322745427
Short name T655
Test name
Test status
Simulation time 3317259901 ps
CPU time 28.18 seconds
Started Jul 30 05:31:01 PM PDT 24
Finished Jul 30 05:31:29 PM PDT 24
Peak memory 248392 kb
Host smart-341e081b-55ad-458f-b6e1-3207236a09b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33227
45427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.3322745427
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.2882733821
Short name T496
Test name
Test status
Simulation time 47392067015 ps
CPU time 414.11 seconds
Started Jul 30 05:31:09 PM PDT 24
Finished Jul 30 05:38:03 PM PDT 24
Peak memory 254240 kb
Host smart-6d62cb12-edb4-4bf6-9eff-60499ef9834f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882733821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.2882733821
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.2575104554
Short name T116
Test name
Test status
Simulation time 64141394548 ps
CPU time 4382.12 seconds
Started Jul 30 05:31:15 PM PDT 24
Finished Jul 30 06:44:18 PM PDT 24
Peak memory 320572 kb
Host smart-464efe6b-2568-439d-8125-b4bde2bb0405
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575104554 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.2575104554
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.42741069
Short name T223
Test name
Test status
Simulation time 89068055 ps
CPU time 3.78 seconds
Started Jul 30 05:31:16 PM PDT 24
Finished Jul 30 05:31:20 PM PDT 24
Peak memory 248652 kb
Host smart-e806636b-9b38-4c7d-9d5d-e71a1654efda
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=42741069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.42741069
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.4112195183
Short name T578
Test name
Test status
Simulation time 25512033525 ps
CPU time 755.17 seconds
Started Jul 30 05:31:13 PM PDT 24
Finished Jul 30 05:43:48 PM PDT 24
Peak memory 272880 kb
Host smart-acb2289a-2d28-4b5c-ba53-7ec46a8527ac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112195183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.4112195183
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.241300314
Short name T626
Test name
Test status
Simulation time 411783374 ps
CPU time 7.27 seconds
Started Jul 30 05:31:18 PM PDT 24
Finished Jul 30 05:31:26 PM PDT 24
Peak memory 248324 kb
Host smart-672ac8e0-cd15-4319-befa-eacd4c21d66b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=241300314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.241300314
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.866717807
Short name T546
Test name
Test status
Simulation time 247838432 ps
CPU time 26.3 seconds
Started Jul 30 05:31:13 PM PDT 24
Finished Jul 30 05:31:40 PM PDT 24
Peak memory 255884 kb
Host smart-25c7a158-41e6-4acf-81e3-aa719ba7d5b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86671
7807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.866717807
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.3719368825
Short name T517
Test name
Test status
Simulation time 68638063 ps
CPU time 7.47 seconds
Started Jul 30 05:31:16 PM PDT 24
Finished Jul 30 05:31:24 PM PDT 24
Peak memory 247932 kb
Host smart-6b30a8ae-8d6c-4116-b8b8-fc269dcf9c58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37193
68825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.3719368825
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.2659199395
Short name T537
Test name
Test status
Simulation time 199502767093 ps
CPU time 2780.2 seconds
Started Jul 30 05:31:14 PM PDT 24
Finished Jul 30 06:17:34 PM PDT 24
Peak memory 285700 kb
Host smart-ca922001-5838-4581-9cff-9d9ca2d60bfe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659199395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.2659199395
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.166876389
Short name T538
Test name
Test status
Simulation time 83381923466 ps
CPU time 2541.72 seconds
Started Jul 30 05:31:13 PM PDT 24
Finished Jul 30 06:13:35 PM PDT 24
Peak memory 283892 kb
Host smart-95367b85-a85f-4905-8aab-ad0bbfd17b4b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166876389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.166876389
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.857018986
Short name T280
Test name
Test status
Simulation time 740427416 ps
CPU time 23.33 seconds
Started Jul 30 05:31:13 PM PDT 24
Finished Jul 30 05:31:37 PM PDT 24
Peak memory 255768 kb
Host smart-bd2dd5d8-2095-4053-a4f1-1e8c44219f3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85701
8986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.857018986
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.3668529790
Short name T30
Test name
Test status
Simulation time 241959975 ps
CPU time 24.53 seconds
Started Jul 30 05:31:11 PM PDT 24
Finished Jul 30 05:31:35 PM PDT 24
Peak memory 255788 kb
Host smart-bc9772f4-5e46-48a5-94bc-bc24acac4ad1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36685
29790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.3668529790
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.3980282879
Short name T570
Test name
Test status
Simulation time 3082285366 ps
CPU time 74.74 seconds
Started Jul 30 05:31:09 PM PDT 24
Finished Jul 30 05:32:24 PM PDT 24
Peak memory 256588 kb
Host smart-8c7ce2a2-823d-4f42-b6eb-21127c02f316
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39802
82879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.3980282879
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.2863029806
Short name T612
Test name
Test status
Simulation time 45588335195 ps
CPU time 2587.22 seconds
Started Jul 30 05:31:18 PM PDT 24
Finished Jul 30 06:14:26 PM PDT 24
Peak memory 289344 kb
Host smart-9f477f4c-ec26-431d-981d-c517ee2b3a04
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863029806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.2863029806
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.4145458854
Short name T216
Test name
Test status
Simulation time 333778024 ps
CPU time 3.48 seconds
Started Jul 30 05:29:28 PM PDT 24
Finished Jul 30 05:29:31 PM PDT 24
Peak memory 248584 kb
Host smart-6bd6214f-d34f-4cc4-84e9-b26e777ed976
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4145458854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.4145458854
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.4230171173
Short name T524
Test name
Test status
Simulation time 158521228662 ps
CPU time 1729.83 seconds
Started Jul 30 05:29:24 PM PDT 24
Finished Jul 30 05:58:14 PM PDT 24
Peak memory 284048 kb
Host smart-525995ad-da63-4795-9fc1-80a8a2cea29d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230171173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.4230171173
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.1986347510
Short name T525
Test name
Test status
Simulation time 717072223 ps
CPU time 11.48 seconds
Started Jul 30 05:29:26 PM PDT 24
Finished Jul 30 05:29:38 PM PDT 24
Peak memory 248300 kb
Host smart-5363ac49-857a-42c3-b5f7-f89c5e52d8ff
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1986347510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.1986347510
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.3100077938
Short name T416
Test name
Test status
Simulation time 2180465912 ps
CPU time 56.97 seconds
Started Jul 30 05:29:24 PM PDT 24
Finished Jul 30 05:30:21 PM PDT 24
Peak memory 255912 kb
Host smart-6ca38bf6-d332-4c9b-9e93-ef6309907734
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31000
77938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.3100077938
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.3617563900
Short name T598
Test name
Test status
Simulation time 1171115281 ps
CPU time 31.83 seconds
Started Jul 30 05:29:25 PM PDT 24
Finished Jul 30 05:29:57 PM PDT 24
Peak memory 248348 kb
Host smart-418427e0-7f60-4e53-9d5c-1fa7f4552477
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36175
63900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.3617563900
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.2636723645
Short name T325
Test name
Test status
Simulation time 18604123432 ps
CPU time 1430.11 seconds
Started Jul 30 05:29:25 PM PDT 24
Finished Jul 30 05:53:15 PM PDT 24
Peak memory 289340 kb
Host smart-3f6bfefd-469e-4f01-b8da-0960b2340352
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636723645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.2636723645
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.697774489
Short name T671
Test name
Test status
Simulation time 50950488882 ps
CPU time 1591.81 seconds
Started Jul 30 05:29:26 PM PDT 24
Finished Jul 30 05:55:58 PM PDT 24
Peak memory 272748 kb
Host smart-ddfa6c3e-29f6-48b8-8a99-687818bdd6b6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697774489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.697774489
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.154068618
Short name T583
Test name
Test status
Simulation time 4659479778 ps
CPU time 192.81 seconds
Started Jul 30 05:29:24 PM PDT 24
Finished Jul 30 05:32:37 PM PDT 24
Peak memory 248376 kb
Host smart-b2b11e96-d67c-46ef-83fa-fe10a2ccf6bf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154068618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.154068618
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.2989046176
Short name T600
Test name
Test status
Simulation time 78868173 ps
CPU time 5.82 seconds
Started Jul 30 05:29:23 PM PDT 24
Finished Jul 30 05:29:29 PM PDT 24
Peak memory 248328 kb
Host smart-39d08bc4-5bf4-43dc-9c5b-02f1c9b3d5db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29890
46176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.2989046176
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.2548441760
Short name T629
Test name
Test status
Simulation time 129459725 ps
CPU time 9.25 seconds
Started Jul 30 05:29:22 PM PDT 24
Finished Jul 30 05:29:31 PM PDT 24
Peak memory 252720 kb
Host smart-0ef56cfd-a81e-4b0c-8479-14f43d97bcd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25484
41760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.2548441760
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.3491704022
Short name T10
Test name
Test status
Simulation time 210433772 ps
CPU time 13.32 seconds
Started Jul 30 05:29:29 PM PDT 24
Finished Jul 30 05:29:42 PM PDT 24
Peak memory 270752 kb
Host smart-113166ff-2bf4-403c-9d7e-809d5c3f5385
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3491704022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.3491704022
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.1847698579
Short name T267
Test name
Test status
Simulation time 403659009 ps
CPU time 27.46 seconds
Started Jul 30 05:29:23 PM PDT 24
Finished Jul 30 05:29:51 PM PDT 24
Peak memory 247864 kb
Host smart-d8a290cb-a283-4f8f-bc08-ad85be435952
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18476
98579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.1847698579
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.4176502504
Short name T231
Test name
Test status
Simulation time 1639700387 ps
CPU time 45.84 seconds
Started Jul 30 05:29:23 PM PDT 24
Finished Jul 30 05:30:09 PM PDT 24
Peak memory 256488 kb
Host smart-69a78b17-e63b-4a42-ab07-cb3b354b91fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41765
02504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.4176502504
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.1855790435
Short name T76
Test name
Test status
Simulation time 58294617328 ps
CPU time 3588.21 seconds
Started Jul 30 05:29:28 PM PDT 24
Finished Jul 30 06:29:17 PM PDT 24
Peak memory 289500 kb
Host smart-ceaad0a6-b9fe-427b-9af6-dac5772619dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855790435 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.1855790435
Directory /workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.2474121634
Short name T519
Test name
Test status
Simulation time 133526054714 ps
CPU time 2375.23 seconds
Started Jul 30 05:31:19 PM PDT 24
Finished Jul 30 06:10:54 PM PDT 24
Peak memory 287164 kb
Host smart-2859b4e3-97d4-446c-966f-636e6644f284
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474121634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.2474121634
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.1229015375
Short name T41
Test name
Test status
Simulation time 3414801152 ps
CPU time 81.43 seconds
Started Jul 30 05:31:20 PM PDT 24
Finished Jul 30 05:32:41 PM PDT 24
Peak memory 255988 kb
Host smart-a16bc8fb-b019-4e10-a258-52f5f9bec381
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12290
15375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.1229015375
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.1801832020
Short name T458
Test name
Test status
Simulation time 3687233591 ps
CPU time 43.99 seconds
Started Jul 30 05:31:20 PM PDT 24
Finished Jul 30 05:32:04 PM PDT 24
Peak memory 248176 kb
Host smart-83863c54-1877-48c4-984f-926a7a780fc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18018
32020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.1801832020
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.2992481650
Short name T323
Test name
Test status
Simulation time 24207193252 ps
CPU time 1085.89 seconds
Started Jul 30 05:31:21 PM PDT 24
Finished Jul 30 05:49:28 PM PDT 24
Peak memory 272272 kb
Host smart-de98ff6a-a1fa-42cb-aa1e-6b270ab0cb11
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992481650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.2992481650
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.2635995248
Short name T554
Test name
Test status
Simulation time 25390715085 ps
CPU time 1598.95 seconds
Started Jul 30 05:31:25 PM PDT 24
Finished Jul 30 05:58:04 PM PDT 24
Peak memory 272464 kb
Host smart-b6a6e3e5-10d6-41f8-86b1-59d30a5c602f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635995248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.2635995248
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.4285979850
Short name T659
Test name
Test status
Simulation time 18937925239 ps
CPU time 432.72 seconds
Started Jul 30 05:31:23 PM PDT 24
Finished Jul 30 05:38:36 PM PDT 24
Peak memory 248376 kb
Host smart-2fb418ff-5181-401c-92db-6faa631de146
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285979850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.4285979850
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.1529667760
Short name T418
Test name
Test status
Simulation time 541312988 ps
CPU time 13.9 seconds
Started Jul 30 05:31:17 PM PDT 24
Finished Jul 30 05:31:31 PM PDT 24
Peak memory 255488 kb
Host smart-b40ac452-bee0-4cc0-8421-7a7cc9c4e280
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15296
67760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.1529667760
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.1666282875
Short name T83
Test name
Test status
Simulation time 206315962 ps
CPU time 5.24 seconds
Started Jul 30 05:31:17 PM PDT 24
Finished Jul 30 05:31:23 PM PDT 24
Peak memory 251996 kb
Host smart-ca89a6e9-4445-4021-9238-d0ed227b8860
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16662
82875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.1666282875
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.177410326
Short name T40
Test name
Test status
Simulation time 256443048 ps
CPU time 19.38 seconds
Started Jul 30 05:31:19 PM PDT 24
Finished Jul 30 05:31:38 PM PDT 24
Peak memory 248288 kb
Host smart-f4bffed2-a555-443b-aac1-d6d40ae269ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17741
0326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.177410326
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.583859387
Short name T535
Test name
Test status
Simulation time 1137260681 ps
CPU time 46.22 seconds
Started Jul 30 05:31:18 PM PDT 24
Finished Jul 30 05:32:04 PM PDT 24
Peak memory 248264 kb
Host smart-f2ff8cbf-4af2-4053-9122-7102f1f2b41c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58385
9387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.583859387
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.2999151582
Short name T101
Test name
Test status
Simulation time 46233416150 ps
CPU time 2780.9 seconds
Started Jul 30 05:31:20 PM PDT 24
Finished Jul 30 06:17:41 PM PDT 24
Peak memory 289300 kb
Host smart-1511d8c1-f64e-49a4-9baf-091b870458ff
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999151582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.2999151582
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all_with_rand_reset.721785936
Short name T434
Test name
Test status
Simulation time 41433187365 ps
CPU time 4232.38 seconds
Started Jul 30 05:31:23 PM PDT 24
Finished Jul 30 06:41:55 PM PDT 24
Peak memory 321332 kb
Host smart-7f788a5e-ca55-4534-af7f-fdab7ef09321
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721785936 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 20.alert_handler_stress_all_with_rand_reset.721785936
Directory /workspace/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.3510063461
Short name T411
Test name
Test status
Simulation time 10025702668 ps
CPU time 1218.71 seconds
Started Jul 30 05:31:27 PM PDT 24
Finished Jul 30 05:51:46 PM PDT 24
Peak memory 288416 kb
Host smart-0fb4d5b9-daec-4560-8b40-ee48cfa40ed3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510063461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.3510063461
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.3671310521
Short name T409
Test name
Test status
Simulation time 28714105288 ps
CPU time 124.63 seconds
Started Jul 30 05:31:30 PM PDT 24
Finished Jul 30 05:33:35 PM PDT 24
Peak memory 255752 kb
Host smart-97b5edda-ac21-4043-8a7d-824a057c347c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36713
10521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.3671310521
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.3947977298
Short name T118
Test name
Test status
Simulation time 467763381 ps
CPU time 22.68 seconds
Started Jul 30 05:31:26 PM PDT 24
Finished Jul 30 05:31:49 PM PDT 24
Peak memory 256524 kb
Host smart-b5a1bce2-c17a-42cc-8e1a-a45129cc94b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39479
77298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.3947977298
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.1884610837
Short name T291
Test name
Test status
Simulation time 89723032740 ps
CPU time 1502.62 seconds
Started Jul 30 05:31:27 PM PDT 24
Finished Jul 30 05:56:29 PM PDT 24
Peak memory 272316 kb
Host smart-8ffec4ae-6108-484e-9e4a-d9e7d7e65afc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884610837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.1884610837
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.1444148191
Short name T652
Test name
Test status
Simulation time 18434920993 ps
CPU time 1149.62 seconds
Started Jul 30 05:31:29 PM PDT 24
Finished Jul 30 05:50:39 PM PDT 24
Peak memory 264716 kb
Host smart-bfa7ddbe-4806-476d-9c1d-e29f64a8a2b2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444148191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.1444148191
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.3182010630
Short name T456
Test name
Test status
Simulation time 1746058774 ps
CPU time 25.25 seconds
Started Jul 30 05:31:22 PM PDT 24
Finished Jul 30 05:31:47 PM PDT 24
Peak memory 255752 kb
Host smart-c85246db-44f4-4e71-8f96-493b032df165
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31820
10630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.3182010630
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.1099431727
Short name T28
Test name
Test status
Simulation time 919855122 ps
CPU time 28.31 seconds
Started Jul 30 05:31:39 PM PDT 24
Finished Jul 30 05:32:07 PM PDT 24
Peak memory 247848 kb
Host smart-8deb01dd-437d-4ba1-8f5e-c30d4ddded7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10994
31727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.1099431727
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.2273655667
Short name T632
Test name
Test status
Simulation time 1279404750 ps
CPU time 37.95 seconds
Started Jul 30 05:31:26 PM PDT 24
Finished Jul 30 05:32:04 PM PDT 24
Peak memory 255908 kb
Host smart-506eea2b-bdb3-47ed-9993-7f922436b2bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22736
55667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.2273655667
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.1155831626
Short name T352
Test name
Test status
Simulation time 1566653498 ps
CPU time 37.86 seconds
Started Jul 30 05:31:21 PM PDT 24
Finished Jul 30 05:31:58 PM PDT 24
Peak memory 256456 kb
Host smart-45cb5d7e-3835-4d9e-a9b9-8498abf96fe7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11558
31626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.1155831626
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.526025986
Short name T261
Test name
Test status
Simulation time 49778431965 ps
CPU time 750.9 seconds
Started Jul 30 05:31:31 PM PDT 24
Finished Jul 30 05:44:02 PM PDT 24
Peak memory 264780 kb
Host smart-872fcd09-611d-40a7-9581-4df058aa4b0e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526025986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_han
dler_stress_all.526025986
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.2388986924
Short name T640
Test name
Test status
Simulation time 30909851385 ps
CPU time 1851.6 seconds
Started Jul 30 05:31:32 PM PDT 24
Finished Jul 30 06:02:24 PM PDT 24
Peak memory 289452 kb
Host smart-54160d2f-48de-49a6-8366-ae319b366e4d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388986924 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.2388986924
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.3616824303
Short name T407
Test name
Test status
Simulation time 63546020970 ps
CPU time 2021.48 seconds
Started Jul 30 05:31:29 PM PDT 24
Finished Jul 30 06:05:11 PM PDT 24
Peak memory 272600 kb
Host smart-9ae2876b-0981-4240-ba4a-1b40c55e53da
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616824303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.3616824303
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.4033836459
Short name T657
Test name
Test status
Simulation time 10466033457 ps
CPU time 149.03 seconds
Started Jul 30 05:31:29 PM PDT 24
Finished Jul 30 05:33:59 PM PDT 24
Peak memory 250388 kb
Host smart-1c70bbe0-c530-4da4-af7f-7fa83af8c71a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40338
36459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.4033836459
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.4167376935
Short name T426
Test name
Test status
Simulation time 159063218 ps
CPU time 11.05 seconds
Started Jul 30 05:31:31 PM PDT 24
Finished Jul 30 05:31:42 PM PDT 24
Peak memory 247728 kb
Host smart-7617bc3d-a2f1-414a-bdbe-5488e4b74254
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41673
76935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.4167376935
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.4152936609
Short name T253
Test name
Test status
Simulation time 10502400375 ps
CPU time 897.53 seconds
Started Jul 30 05:31:32 PM PDT 24
Finished Jul 30 05:46:30 PM PDT 24
Peak memory 272824 kb
Host smart-c7b070b3-b737-4d7f-a3c5-3395180a0f4c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152936609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.4152936609
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.277808690
Short name T380
Test name
Test status
Simulation time 45301006795 ps
CPU time 1447.92 seconds
Started Jul 30 05:31:32 PM PDT 24
Finished Jul 30 05:55:40 PM PDT 24
Peak memory 268856 kb
Host smart-e9620f6a-b971-44ab-9661-414cca80cb0d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277808690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.277808690
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.4015063590
Short name T294
Test name
Test status
Simulation time 40996559307 ps
CPU time 430.06 seconds
Started Jul 30 05:31:29 PM PDT 24
Finished Jul 30 05:38:40 PM PDT 24
Peak memory 248100 kb
Host smart-9b7df2e3-42ae-482d-8522-17dcfe766c26
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015063590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.4015063590
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.1235801914
Short name T39
Test name
Test status
Simulation time 951027616 ps
CPU time 25.99 seconds
Started Jul 30 05:31:32 PM PDT 24
Finished Jul 30 05:31:58 PM PDT 24
Peak memory 255744 kb
Host smart-713a386c-3ca6-4776-9128-3e4137af4cda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12358
01914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.1235801914
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.3353964714
Short name T47
Test name
Test status
Simulation time 863508266 ps
CPU time 53.4 seconds
Started Jul 30 05:31:31 PM PDT 24
Finished Jul 30 05:32:25 PM PDT 24
Peak memory 247864 kb
Host smart-59a74db1-bcd3-444d-89eb-f49354fc3afc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33539
64714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.3353964714
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.990662525
Short name T688
Test name
Test status
Simulation time 219048182 ps
CPU time 17.18 seconds
Started Jul 30 05:31:31 PM PDT 24
Finished Jul 30 05:31:48 PM PDT 24
Peak memory 254916 kb
Host smart-37c8d047-9585-4e18-a673-e21296bc1483
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99066
2525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.990662525
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.4160992679
Short name T442
Test name
Test status
Simulation time 962125472 ps
CPU time 15.62 seconds
Started Jul 30 05:31:32 PM PDT 24
Finished Jul 30 05:31:48 PM PDT 24
Peak memory 255020 kb
Host smart-6cc88276-c21a-45e2-bcb8-35fcbcf409c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41609
92679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.4160992679
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.2463953737
Short name T69
Test name
Test status
Simulation time 83457445777 ps
CPU time 1260.05 seconds
Started Jul 30 05:31:33 PM PDT 24
Finished Jul 30 05:52:33 PM PDT 24
Peak memory 288688 kb
Host smart-ff3ec6db-5104-47bd-b866-f06b58cfd72f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463953737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.2463953737
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.161273752
Short name T134
Test name
Test status
Simulation time 55248438621 ps
CPU time 1108.04 seconds
Started Jul 30 05:31:41 PM PDT 24
Finished Jul 30 05:50:09 PM PDT 24
Peak memory 284904 kb
Host smart-bc1006a8-8889-4a55-ab03-30b4644dc950
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161273752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.161273752
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.528666729
Short name T337
Test name
Test status
Simulation time 312698411 ps
CPU time 4.48 seconds
Started Jul 30 05:31:36 PM PDT 24
Finished Jul 30 05:31:40 PM PDT 24
Peak memory 239100 kb
Host smart-f781f7d2-16f0-48a8-9cc1-ba0fc10c676e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52866
6729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.528666729
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.2379530335
Short name T547
Test name
Test status
Simulation time 4781425388 ps
CPU time 50 seconds
Started Jul 30 05:31:34 PM PDT 24
Finished Jul 30 05:32:24 PM PDT 24
Peak memory 256040 kb
Host smart-a7e22eef-c509-4208-8be8-9c4130b15b6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23795
30335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.2379530335
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.53876416
Short name T521
Test name
Test status
Simulation time 151519947242 ps
CPU time 1552.43 seconds
Started Jul 30 05:31:40 PM PDT 24
Finished Jul 30 05:57:33 PM PDT 24
Peak memory 272240 kb
Host smart-cb8360fd-bcbb-44a8-9fc7-402cc410804c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53876416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.53876416
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.4196724099
Short name T475
Test name
Test status
Simulation time 21647546013 ps
CPU time 1304.94 seconds
Started Jul 30 05:31:39 PM PDT 24
Finished Jul 30 05:53:25 PM PDT 24
Peak memory 264832 kb
Host smart-06f5036e-7821-4fc9-ad91-a059d3059aa8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196724099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.4196724099
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.3975248737
Short name T229
Test name
Test status
Simulation time 25382132712 ps
CPU time 482.99 seconds
Started Jul 30 05:31:41 PM PDT 24
Finished Jul 30 05:39:44 PM PDT 24
Peak memory 248264 kb
Host smart-cb6a3b61-b4d5-4387-8d26-814d18e8fd88
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975248737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.3975248737
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.2677517027
Short name T365
Test name
Test status
Simulation time 513978922 ps
CPU time 29.38 seconds
Started Jul 30 05:31:33 PM PDT 24
Finished Jul 30 05:32:03 PM PDT 24
Peak memory 255748 kb
Host smart-e53d02f7-3e24-4ab4-9617-504d92c14dc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26775
17027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.2677517027
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.1721751094
Short name T443
Test name
Test status
Simulation time 1719410179 ps
CPU time 38.7 seconds
Started Jul 30 05:31:35 PM PDT 24
Finished Jul 30 05:32:13 PM PDT 24
Peak memory 248376 kb
Host smart-5b2a2dda-922a-484d-a0f9-6847c003e420
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17217
51094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.1721751094
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.2277769332
Short name T272
Test name
Test status
Simulation time 1122160274 ps
CPU time 34.9 seconds
Started Jul 30 05:31:37 PM PDT 24
Finished Jul 30 05:32:12 PM PDT 24
Peak memory 256472 kb
Host smart-5fdd06bf-3759-417c-a680-a77c852ca3f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22777
69332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.2277769332
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.1335558101
Short name T601
Test name
Test status
Simulation time 6059626388 ps
CPU time 55.27 seconds
Started Jul 30 05:31:35 PM PDT 24
Finished Jul 30 05:32:30 PM PDT 24
Peak memory 255944 kb
Host smart-cc6dd617-233c-45d4-986b-43ec963660df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13355
58101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.1335558101
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.219829967
Short name T75
Test name
Test status
Simulation time 49305714168 ps
CPU time 3008.41 seconds
Started Jul 30 05:31:40 PM PDT 24
Finished Jul 30 06:21:48 PM PDT 24
Peak memory 288624 kb
Host smart-10a52ece-cdef-49cd-aa9a-a02bd782b2ea
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219829967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_han
dler_stress_all.219829967
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.1080130722
Short name T80
Test name
Test status
Simulation time 309325491641 ps
CPU time 1027.05 seconds
Started Jul 30 05:31:41 PM PDT 24
Finished Jul 30 05:48:48 PM PDT 24
Peak memory 284356 kb
Host smart-c21d0fe6-63c9-4cb1-9cc6-1b69f4ac7854
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080130722 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.1080130722
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.1071204937
Short name T660
Test name
Test status
Simulation time 2983774967 ps
CPU time 49.19 seconds
Started Jul 30 05:31:42 PM PDT 24
Finished Jul 30 05:32:31 PM PDT 24
Peak memory 256132 kb
Host smart-c5a49e76-b8f1-4ffe-a21a-a90952c9e96c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10712
04937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.1071204937
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.1385400772
Short name T270
Test name
Test status
Simulation time 1991432067 ps
CPU time 30.65 seconds
Started Jul 30 05:31:43 PM PDT 24
Finished Jul 30 05:32:13 PM PDT 24
Peak memory 247876 kb
Host smart-d08a386d-17e6-45b7-a453-79be3c11499d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13854
00772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.1385400772
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.1345839538
Short name T66
Test name
Test status
Simulation time 60025458565 ps
CPU time 2410.39 seconds
Started Jul 30 05:31:45 PM PDT 24
Finished Jul 30 06:11:56 PM PDT 24
Peak memory 289204 kb
Host smart-44dee2b6-b633-4066-bb11-60626bb647bb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345839538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.1345839538
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.1483721457
Short name T381
Test name
Test status
Simulation time 84967936303 ps
CPU time 3307.09 seconds
Started Jul 30 05:31:44 PM PDT 24
Finished Jul 30 06:26:52 PM PDT 24
Peak memory 289100 kb
Host smart-248e3967-cf45-49a0-aa3f-7dd20d26405e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483721457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.1483721457
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.2836039959
Short name T630
Test name
Test status
Simulation time 7180944654 ps
CPU time 155.74 seconds
Started Jul 30 05:31:44 PM PDT 24
Finished Jul 30 05:34:20 PM PDT 24
Peak memory 248352 kb
Host smart-b75649bb-167a-4541-bcc2-cb233f122b5a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836039959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.2836039959
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.3052611387
Short name T84
Test name
Test status
Simulation time 800105834 ps
CPU time 49.15 seconds
Started Jul 30 05:31:41 PM PDT 24
Finished Jul 30 05:32:30 PM PDT 24
Peak memory 248328 kb
Host smart-d280829a-6efa-4766-89cb-1b75cdc9559c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30526
11387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.3052611387
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.289401883
Short name T397
Test name
Test status
Simulation time 1529873457 ps
CPU time 22 seconds
Started Jul 30 05:31:42 PM PDT 24
Finished Jul 30 05:32:04 PM PDT 24
Peak memory 248296 kb
Host smart-37ca952e-a7d9-47a6-879a-9dc86dbacc9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28940
1883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.289401883
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.3801178066
Short name T445
Test name
Test status
Simulation time 113654494 ps
CPU time 4.66 seconds
Started Jul 30 05:31:45 PM PDT 24
Finished Jul 30 05:31:50 PM PDT 24
Peak memory 247784 kb
Host smart-2fd96042-c631-4a1a-9594-cfc47e797919
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38011
78066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.3801178066
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.3047523992
Short name T534
Test name
Test status
Simulation time 2470782461 ps
CPU time 36.16 seconds
Started Jul 30 05:31:41 PM PDT 24
Finished Jul 30 05:32:17 PM PDT 24
Peak memory 255612 kb
Host smart-bcd145d0-75a2-48d1-9244-ec478aa1dec7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30475
23992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.3047523992
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.755260750
Short name T95
Test name
Test status
Simulation time 45799177899 ps
CPU time 1591.08 seconds
Started Jul 30 05:31:50 PM PDT 24
Finished Jul 30 05:58:21 PM PDT 24
Peak memory 272912 kb
Host smart-f2266403-1b45-4731-94c4-ff0715a68c2f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755260750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.755260750
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.1288441955
Short name T606
Test name
Test status
Simulation time 7434428538 ps
CPU time 164.39 seconds
Started Jul 30 05:31:51 PM PDT 24
Finished Jul 30 05:34:36 PM PDT 24
Peak memory 256600 kb
Host smart-354edcc1-a787-4040-9c53-05c3c3712376
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12884
41955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.1288441955
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.3591358769
Short name T391
Test name
Test status
Simulation time 395177792 ps
CPU time 17.48 seconds
Started Jul 30 05:31:49 PM PDT 24
Finished Jul 30 05:32:06 PM PDT 24
Peak memory 247748 kb
Host smart-456a5492-c2e9-4fed-9574-083f39f9f74e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35913
58769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.3591358769
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.3305072305
Short name T702
Test name
Test status
Simulation time 63024442845 ps
CPU time 1476.46 seconds
Started Jul 30 05:31:52 PM PDT 24
Finished Jul 30 05:56:28 PM PDT 24
Peak memory 288456 kb
Host smart-f74a85ce-410c-457d-8cd1-19bc885f4e74
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305072305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.3305072305
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.17080211
Short name T548
Test name
Test status
Simulation time 2507230409 ps
CPU time 94.83 seconds
Started Jul 30 05:31:52 PM PDT 24
Finished Jul 30 05:33:26 PM PDT 24
Peak memory 248272 kb
Host smart-f4fd2b39-e216-45ea-b87b-f3fd4f0204e7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17080211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.17080211
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.2887017243
Short name T588
Test name
Test status
Simulation time 197636211 ps
CPU time 25.93 seconds
Started Jul 30 05:31:49 PM PDT 24
Finished Jul 30 05:32:15 PM PDT 24
Peak memory 248272 kb
Host smart-aa5b9b18-d8cd-410c-83b2-041b27594ee0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28870
17243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.2887017243
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.1620640984
Short name T386
Test name
Test status
Simulation time 357588585 ps
CPU time 32.96 seconds
Started Jul 30 05:31:51 PM PDT 24
Finished Jul 30 05:32:24 PM PDT 24
Peak memory 256556 kb
Host smart-45d0eb61-0033-4dfa-90eb-aebc1536a291
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16206
40984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.1620640984
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.635279001
Short name T20
Test name
Test status
Simulation time 1378778994 ps
CPU time 20.99 seconds
Started Jul 30 05:31:50 PM PDT 24
Finished Jul 30 05:32:11 PM PDT 24
Peak memory 247840 kb
Host smart-dda235ed-d180-434d-ab62-23867985ca99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63527
9001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.635279001
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.1255445787
Short name T399
Test name
Test status
Simulation time 3158339381 ps
CPU time 49.05 seconds
Started Jul 30 05:31:50 PM PDT 24
Finished Jul 30 05:32:39 PM PDT 24
Peak memory 255568 kb
Host smart-e8a30f88-0a89-4742-b8ad-155cacc5f0ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12554
45787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.1255445787
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.3902428382
Short name T283
Test name
Test status
Simulation time 1811278906 ps
CPU time 161.93 seconds
Started Jul 30 05:31:52 PM PDT 24
Finished Jul 30 05:34:34 PM PDT 24
Peak memory 256400 kb
Host smart-037b7e27-fb7e-494c-8ec1-21fcae661692
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902428382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.3902428382
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.3939059066
Short name T454
Test name
Test status
Simulation time 36041019901 ps
CPU time 2151.59 seconds
Started Jul 30 05:31:59 PM PDT 24
Finished Jul 30 06:07:51 PM PDT 24
Peak memory 289308 kb
Host smart-ab6e37f7-1f5e-456b-a55b-5fe583cb3b1c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939059066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.3939059066
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.1207145404
Short name T463
Test name
Test status
Simulation time 919277355 ps
CPU time 67.82 seconds
Started Jul 30 05:31:59 PM PDT 24
Finished Jul 30 05:33:07 PM PDT 24
Peak memory 255744 kb
Host smart-f12606df-95ec-4498-8c8a-dc92b0e3468d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12071
45404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.1207145404
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.3485183881
Short name T700
Test name
Test status
Simulation time 492937855 ps
CPU time 20.3 seconds
Started Jul 30 05:31:56 PM PDT 24
Finished Jul 30 05:32:16 PM PDT 24
Peak memory 255828 kb
Host smart-6b002260-a8bf-4a52-8b3c-06e54110bdcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34851
83881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.3485183881
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.1481058748
Short name T648
Test name
Test status
Simulation time 9806808676 ps
CPU time 1207.97 seconds
Started Jul 30 05:32:05 PM PDT 24
Finished Jul 30 05:52:14 PM PDT 24
Peak memory 272892 kb
Host smart-337be421-3d68-4116-ae31-2f46e2592f5e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481058748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.1481058748
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.4258318155
Short name T16
Test name
Test status
Simulation time 19510079393 ps
CPU time 386.59 seconds
Started Jul 30 05:32:00 PM PDT 24
Finished Jul 30 05:38:27 PM PDT 24
Peak memory 248268 kb
Host smart-cec7d7b4-6ff0-4fb8-8f99-a23c4448a790
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258318155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.4258318155
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.2644136739
Short name T54
Test name
Test status
Simulation time 401727512 ps
CPU time 10.98 seconds
Started Jul 30 05:31:56 PM PDT 24
Finished Jul 30 05:32:07 PM PDT 24
Peak memory 248364 kb
Host smart-9f3033c9-2361-4dcc-b11b-184535061a7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26441
36739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.2644136739
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.165976032
Short name T576
Test name
Test status
Simulation time 537702947 ps
CPU time 16.89 seconds
Started Jul 30 05:31:57 PM PDT 24
Finished Jul 30 05:32:14 PM PDT 24
Peak memory 247660 kb
Host smart-d0e0cb80-e4de-455b-945f-d1bcd35e220b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16597
6032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.165976032
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.3683291683
Short name T350
Test name
Test status
Simulation time 248807268 ps
CPU time 27.98 seconds
Started Jul 30 05:31:58 PM PDT 24
Finished Jul 30 05:32:26 PM PDT 24
Peak memory 248344 kb
Host smart-027e4a82-a2dc-4c79-9d17-ca6d8c18ff3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36832
91683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.3683291683
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.1763619412
Short name T12
Test name
Test status
Simulation time 2704543515 ps
CPU time 41.6 seconds
Started Jul 30 05:31:58 PM PDT 24
Finished Jul 30 05:32:40 PM PDT 24
Peak memory 248772 kb
Host smart-71ce4ade-e064-4618-97fa-bdde58962c43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17636
19412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.1763619412
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.3967647606
Short name T68
Test name
Test status
Simulation time 59744031425 ps
CPU time 3468.23 seconds
Started Jul 30 05:32:03 PM PDT 24
Finished Jul 30 06:29:51 PM PDT 24
Peak memory 289408 kb
Host smart-43145b99-2043-4302-b5f0-03ab6f7b5db0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967647606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.3967647606
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.2061934803
Short name T694
Test name
Test status
Simulation time 29191708859 ps
CPU time 711.11 seconds
Started Jul 30 05:32:04 PM PDT 24
Finished Jul 30 05:43:55 PM PDT 24
Peak memory 272316 kb
Host smart-a5d1d0d2-584f-41da-bf7b-7e6be9f2bb4f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061934803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.2061934803
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.3310007060
Short name T368
Test name
Test status
Simulation time 6360773654 ps
CPU time 46.92 seconds
Started Jul 30 05:32:04 PM PDT 24
Finished Jul 30 05:32:51 PM PDT 24
Peak memory 255592 kb
Host smart-d4ae00c7-7e4e-4422-b4c4-aa6c7a812d4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33100
07060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.3310007060
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.2110335819
Short name T628
Test name
Test status
Simulation time 376073954 ps
CPU time 23.84 seconds
Started Jul 30 05:32:03 PM PDT 24
Finished Jul 30 05:32:27 PM PDT 24
Peak memory 247984 kb
Host smart-32382153-28ba-456b-9274-8cde1439f695
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21103
35819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.2110335819
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.52877451
Short name T679
Test name
Test status
Simulation time 860759464262 ps
CPU time 3547.29 seconds
Started Jul 30 05:32:09 PM PDT 24
Finished Jul 30 06:31:17 PM PDT 24
Peak memory 288532 kb
Host smart-f641b013-d591-4a38-9479-e0a65f0e559c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52877451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.52877451
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.733377637
Short name T481
Test name
Test status
Simulation time 110251204190 ps
CPU time 1740.88 seconds
Started Jul 30 05:32:10 PM PDT 24
Finished Jul 30 06:01:11 PM PDT 24
Peak memory 272956 kb
Host smart-7013c4b3-6b05-4cdf-b19d-afa66b8e5dea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733377637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.733377637
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.534515214
Short name T580
Test name
Test status
Simulation time 4637977895 ps
CPU time 195.49 seconds
Started Jul 30 05:32:08 PM PDT 24
Finished Jul 30 05:35:23 PM PDT 24
Peak memory 248244 kb
Host smart-ab694d1a-9aa1-45cb-8414-2e3e3e604b59
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534515214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.534515214
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.3485605228
Short name T646
Test name
Test status
Simulation time 371489152 ps
CPU time 7.31 seconds
Started Jul 30 05:32:02 PM PDT 24
Finished Jul 30 05:32:10 PM PDT 24
Peak memory 248320 kb
Host smart-af7f6350-1c07-4606-a219-655fe2c76d9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34856
05228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.3485605228
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.2351226016
Short name T518
Test name
Test status
Simulation time 1792667425 ps
CPU time 28.7 seconds
Started Jul 30 05:32:02 PM PDT 24
Finished Jul 30 05:32:31 PM PDT 24
Peak memory 247656 kb
Host smart-878bd009-0c2f-42c2-8b6f-ca02680d6eb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23512
26016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.2351226016
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.3918137862
Short name T512
Test name
Test status
Simulation time 360130014 ps
CPU time 19.42 seconds
Started Jul 30 05:32:01 PM PDT 24
Finished Jul 30 05:32:20 PM PDT 24
Peak memory 247708 kb
Host smart-78ededa3-7185-4825-a1da-ae2eb8ed63c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39181
37862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.3918137862
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.698449356
Short name T622
Test name
Test status
Simulation time 3498395849 ps
CPU time 28.33 seconds
Started Jul 30 05:32:35 PM PDT 24
Finished Jul 30 05:33:03 PM PDT 24
Peak memory 248600 kb
Host smart-cbafd86c-dc09-4a64-a25c-3cc7e814a727
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69844
9356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.698449356
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.1020680533
Short name T15
Test name
Test status
Simulation time 143517074976 ps
CPU time 2186.25 seconds
Started Jul 30 05:32:13 PM PDT 24
Finished Jul 30 06:08:39 PM PDT 24
Peak memory 288700 kb
Host smart-4f32dfdf-6868-479e-9526-6a39ac5f1709
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020680533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.1020680533
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.194589591
Short name T451
Test name
Test status
Simulation time 15213952081 ps
CPU time 268.56 seconds
Started Jul 30 05:32:09 PM PDT 24
Finished Jul 30 05:36:38 PM PDT 24
Peak memory 256632 kb
Host smart-367a0ae5-b5b9-410c-b2fb-bd8bb473a3b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19458
9591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.194589591
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.463943933
Short name T703
Test name
Test status
Simulation time 1692634444 ps
CPU time 22.12 seconds
Started Jul 30 05:32:08 PM PDT 24
Finished Jul 30 05:32:30 PM PDT 24
Peak memory 254556 kb
Host smart-c5713af1-6bd7-4dcc-963c-093402733a46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46394
3933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.463943933
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.1922493630
Short name T527
Test name
Test status
Simulation time 127793592599 ps
CPU time 1445.87 seconds
Started Jul 30 05:32:11 PM PDT 24
Finished Jul 30 05:56:17 PM PDT 24
Peak memory 272772 kb
Host smart-34695a78-c2c4-4fdc-9896-5869fd7b2c80
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922493630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.1922493630
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.1575704505
Short name T404
Test name
Test status
Simulation time 36351534874 ps
CPU time 413.37 seconds
Started Jul 30 05:32:12 PM PDT 24
Finished Jul 30 05:39:06 PM PDT 24
Peak memory 248352 kb
Host smart-591e88e3-519e-417e-8bff-fc36c9cfac0e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575704505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.1575704505
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.37556372
Short name T549
Test name
Test status
Simulation time 5503020547 ps
CPU time 54.75 seconds
Started Jul 30 05:32:07 PM PDT 24
Finished Jul 30 05:33:02 PM PDT 24
Peak memory 256536 kb
Host smart-4e0744c7-d965-49d8-967f-a059777eb671
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37556
372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.37556372
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.1951328729
Short name T56
Test name
Test status
Simulation time 209174392 ps
CPU time 22.88 seconds
Started Jul 30 05:32:11 PM PDT 24
Finished Jul 30 05:32:34 PM PDT 24
Peak memory 247936 kb
Host smart-37aba02a-cebb-4e1c-8b2b-6d76f3fa7ec0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19513
28729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.1951328729
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.3860287245
Short name T258
Test name
Test status
Simulation time 736410982 ps
CPU time 24.16 seconds
Started Jul 30 05:32:12 PM PDT 24
Finished Jul 30 05:32:36 PM PDT 24
Peak memory 255608 kb
Host smart-71c85af1-9d83-43c5-ab1a-ff33912810f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38602
87245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.3860287245
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.2028529453
Short name T473
Test name
Test status
Simulation time 183044073 ps
CPU time 8.45 seconds
Started Jul 30 05:32:07 PM PDT 24
Finished Jul 30 05:32:15 PM PDT 24
Peak memory 254464 kb
Host smart-23137604-ac29-4f93-8fb0-d8bc56b57ca7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20285
29453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.2028529453
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.2865877919
Short name T639
Test name
Test status
Simulation time 46583827867 ps
CPU time 4120.83 seconds
Started Jul 30 05:32:18 PM PDT 24
Finished Jul 30 06:40:59 PM PDT 24
Peak memory 346432 kb
Host smart-0e9a37ff-431f-44cb-9909-c35deb967e77
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865877919 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.2865877919
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.1832819224
Short name T89
Test name
Test status
Simulation time 38430097755 ps
CPU time 1337.59 seconds
Started Jul 30 05:32:23 PM PDT 24
Finished Jul 30 05:54:41 PM PDT 24
Peak memory 272900 kb
Host smart-f0f007be-ba9b-4bfe-9966-4c35f36e2210
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832819224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.1832819224
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.2109502821
Short name T385
Test name
Test status
Simulation time 3236981084 ps
CPU time 199.99 seconds
Started Jul 30 05:32:23 PM PDT 24
Finished Jul 30 05:35:43 PM PDT 24
Peak memory 256596 kb
Host smart-445a7589-3909-46f9-9ca8-b6c0e94e8faa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21095
02821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.2109502821
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.3315409875
Short name T635
Test name
Test status
Simulation time 2625706374 ps
CPU time 40.9 seconds
Started Jul 30 05:32:21 PM PDT 24
Finished Jul 30 05:33:02 PM PDT 24
Peak memory 256268 kb
Host smart-4b287cba-053c-49db-86b1-5e5ef83297aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33154
09875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.3315409875
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.1211010602
Short name T653
Test name
Test status
Simulation time 19711291842 ps
CPU time 1090.75 seconds
Started Jul 30 05:32:22 PM PDT 24
Finished Jul 30 05:50:33 PM PDT 24
Peak memory 272792 kb
Host smart-30d17acc-499c-43d9-b17f-d2a10c5fdb6f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211010602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.1211010602
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.423817624
Short name T705
Test name
Test status
Simulation time 35508408717 ps
CPU time 1973.75 seconds
Started Jul 30 05:32:23 PM PDT 24
Finished Jul 30 06:05:17 PM PDT 24
Peak memory 272696 kb
Host smart-14e10ca3-eef4-4ba5-a7d0-453be42542be
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423817624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.423817624
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.2184411261
Short name T298
Test name
Test status
Simulation time 56355993095 ps
CPU time 597.16 seconds
Started Jul 30 05:32:23 PM PDT 24
Finished Jul 30 05:42:20 PM PDT 24
Peak memory 248332 kb
Host smart-68822c8b-933f-4b1e-a89e-1974816550d9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184411261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.2184411261
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.4163479279
Short name T510
Test name
Test status
Simulation time 1005209511 ps
CPU time 57.66 seconds
Started Jul 30 05:32:15 PM PDT 24
Finished Jul 30 05:33:12 PM PDT 24
Peak memory 248276 kb
Host smart-20d65c18-3e54-4bcc-8201-4a96523d484c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41634
79279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.4163479279
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.271786124
Short name T103
Test name
Test status
Simulation time 697573576 ps
CPU time 48.18 seconds
Started Jul 30 05:32:21 PM PDT 24
Finished Jul 30 05:33:09 PM PDT 24
Peak memory 255772 kb
Host smart-4e180045-9876-4224-8860-f53e08e13257
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27178
6124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.271786124
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.2837543076
Short name T266
Test name
Test status
Simulation time 810775448 ps
CPU time 24.23 seconds
Started Jul 30 05:32:21 PM PDT 24
Finished Jul 30 05:32:45 PM PDT 24
Peak memory 247916 kb
Host smart-750a4fa8-189a-4a90-bf56-383cc3eefd3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28375
43076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.2837543076
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.4022714115
Short name T592
Test name
Test status
Simulation time 1105646530 ps
CPU time 17.46 seconds
Started Jul 30 05:32:16 PM PDT 24
Finished Jul 30 05:32:34 PM PDT 24
Peak memory 255612 kb
Host smart-7dac3952-9ab7-4900-b334-22bfa3498899
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40227
14115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.4022714115
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.317927779
Short name T264
Test name
Test status
Simulation time 337874309393 ps
CPU time 1627.24 seconds
Started Jul 30 05:32:21 PM PDT 24
Finished Jul 30 05:59:29 PM PDT 24
Peak memory 272976 kb
Host smart-521bd8f5-b0ab-4f6a-a9eb-7fb22809ae8e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317927779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_han
dler_stress_all.317927779
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.1838672768
Short name T44
Test name
Test status
Simulation time 26334784 ps
CPU time 2.62 seconds
Started Jul 30 05:29:31 PM PDT 24
Finished Jul 30 05:29:34 PM PDT 24
Peak memory 248604 kb
Host smart-9c6ec4f2-5734-49fa-b58c-a917ae89d380
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1838672768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.1838672768
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.1210335306
Short name T651
Test name
Test status
Simulation time 189128792472 ps
CPU time 2889.13 seconds
Started Jul 30 05:29:32 PM PDT 24
Finished Jul 30 06:17:42 PM PDT 24
Peak memory 288768 kb
Host smart-974915ba-7e04-4738-a976-cc11ab875ed4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210335306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.1210335306
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.421847084
Short name T674
Test name
Test status
Simulation time 471850187 ps
CPU time 7.89 seconds
Started Jul 30 05:29:33 PM PDT 24
Finished Jul 30 05:29:41 PM PDT 24
Peak memory 248320 kb
Host smart-121ba1dd-d78c-426a-9a0b-48cb9feee9bc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=421847084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.421847084
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.4160395466
Short name T239
Test name
Test status
Simulation time 80084227874 ps
CPU time 264.51 seconds
Started Jul 30 05:29:27 PM PDT 24
Finished Jul 30 05:33:52 PM PDT 24
Peak memory 256556 kb
Host smart-a086605c-4326-4341-b45c-cd06d1d5d3b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41603
95466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.4160395466
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.170883715
Short name T369
Test name
Test status
Simulation time 301858149 ps
CPU time 27.69 seconds
Started Jul 30 05:29:27 PM PDT 24
Finished Jul 30 05:29:55 PM PDT 24
Peak memory 255768 kb
Host smart-882fe1ef-0df8-4843-85ae-9b24804076ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17088
3715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.170883715
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.2570691756
Short name T695
Test name
Test status
Simulation time 327281110902 ps
CPU time 2102.05 seconds
Started Jul 30 05:29:31 PM PDT 24
Finished Jul 30 06:04:34 PM PDT 24
Peak memory 288672 kb
Host smart-60b1e79b-8a54-4e6c-b811-8cd9ba9e2e92
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570691756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.2570691756
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.995649930
Short name T436
Test name
Test status
Simulation time 44095964951 ps
CPU time 1047.81 seconds
Started Jul 30 05:29:32 PM PDT 24
Finished Jul 30 05:47:00 PM PDT 24
Peak memory 281628 kb
Host smart-e38ffa7e-d700-4787-9da0-683e1ce674b2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995649930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.995649930
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.4107406081
Short name T296
Test name
Test status
Simulation time 11567330135 ps
CPU time 397.4 seconds
Started Jul 30 05:29:32 PM PDT 24
Finished Jul 30 05:36:09 PM PDT 24
Peak memory 248192 kb
Host smart-60c8c3e3-0d1e-4ca3-808f-a7adb373157f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107406081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.4107406081
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.4025184357
Short name T603
Test name
Test status
Simulation time 1324782654 ps
CPU time 32.51 seconds
Started Jul 30 05:29:27 PM PDT 24
Finished Jul 30 05:30:00 PM PDT 24
Peak memory 248340 kb
Host smart-06f7605a-f3e2-4006-85d9-4f1aa90128a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40251
84357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.4025184357
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.2887497429
Short name T428
Test name
Test status
Simulation time 946045616 ps
CPU time 35.64 seconds
Started Jul 30 05:29:27 PM PDT 24
Finished Jul 30 05:30:03 PM PDT 24
Peak memory 256084 kb
Host smart-1b716b88-aabd-47ad-a0fc-b83d2ed19d0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28874
97429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.2887497429
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.3788891484
Short name T33
Test name
Test status
Simulation time 354545433 ps
CPU time 21.52 seconds
Started Jul 30 05:29:31 PM PDT 24
Finished Jul 30 05:29:53 PM PDT 24
Peak memory 275776 kb
Host smart-03e6aa8f-20fc-4e06-9fa3-892846e19ba7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3788891484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.3788891484
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.1743917502
Short name T82
Test name
Test status
Simulation time 3079784904 ps
CPU time 50.36 seconds
Started Jul 30 05:29:27 PM PDT 24
Finished Jul 30 05:30:17 PM PDT 24
Peak memory 249476 kb
Host smart-70703025-0d7d-4431-9b3e-1841894b73ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17439
17502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.1743917502
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.2090468017
Short name T531
Test name
Test status
Simulation time 521204510 ps
CPU time 35.92 seconds
Started Jul 30 05:29:30 PM PDT 24
Finished Jul 30 05:30:06 PM PDT 24
Peak memory 256552 kb
Host smart-338b2c01-f1bb-46d9-9c7b-c3f27cfd2309
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20904
68017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.2090468017
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.3420331431
Short name T109
Test name
Test status
Simulation time 352002666065 ps
CPU time 3983.03 seconds
Started Jul 30 05:29:33 PM PDT 24
Finished Jul 30 06:35:56 PM PDT 24
Peak memory 297384 kb
Host smart-00a31417-2db3-4eed-b0e9-c350147b4a64
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420331431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.3420331431
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.1125051640
Short name T93
Test name
Test status
Simulation time 162046579047 ps
CPU time 1519.88 seconds
Started Jul 30 05:32:34 PM PDT 24
Finished Jul 30 05:57:55 PM PDT 24
Peak memory 267780 kb
Host smart-40e0594d-c501-43b1-b9d3-bbc1240a717f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125051640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.1125051640
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.3438359378
Short name T573
Test name
Test status
Simulation time 5032922509 ps
CPU time 319.7 seconds
Started Jul 30 05:32:32 PM PDT 24
Finished Jul 30 05:37:52 PM PDT 24
Peak memory 256544 kb
Host smart-ef3d0afe-67d3-4cb6-b378-6e6ad94ca94e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34383
59378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.3438359378
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.2577182254
Short name T607
Test name
Test status
Simulation time 1131180986 ps
CPU time 62.19 seconds
Started Jul 30 05:32:31 PM PDT 24
Finished Jul 30 05:33:34 PM PDT 24
Peak memory 248084 kb
Host smart-e7c3a638-6461-4fd1-b1ab-93334e0b47af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25771
82254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.2577182254
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.3161933894
Short name T408
Test name
Test status
Simulation time 315232123324 ps
CPU time 3257.18 seconds
Started Jul 30 05:32:37 PM PDT 24
Finished Jul 30 06:26:54 PM PDT 24
Peak memory 289152 kb
Host smart-5a226f39-144a-4bc7-bdd7-6c6f0c1da811
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161933894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.3161933894
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.541106823
Short name T304
Test name
Test status
Simulation time 56638381825 ps
CPU time 608.1 seconds
Started Jul 30 05:32:35 PM PDT 24
Finished Jul 30 05:42:43 PM PDT 24
Peak memory 248328 kb
Host smart-352ee9a7-63f4-48e6-a515-d4d7aa1499ce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541106823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.541106823
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.2126775987
Short name T200
Test name
Test status
Simulation time 317765888 ps
CPU time 36.36 seconds
Started Jul 30 05:32:32 PM PDT 24
Finished Jul 30 05:33:09 PM PDT 24
Peak memory 248344 kb
Host smart-d2800390-234e-4f0f-966d-e818fcadf432
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21267
75987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.2126775987
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.683013789
Short name T664
Test name
Test status
Simulation time 118506441 ps
CPU time 14.89 seconds
Started Jul 30 05:32:30 PM PDT 24
Finished Jul 30 05:32:46 PM PDT 24
Peak memory 247796 kb
Host smart-29f418a2-184b-41ce-bf8d-9597ff03cf72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68301
3789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.683013789
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.3413201496
Short name T480
Test name
Test status
Simulation time 3175091951 ps
CPU time 53.47 seconds
Started Jul 30 05:32:30 PM PDT 24
Finished Jul 30 05:33:24 PM PDT 24
Peak memory 256556 kb
Host smart-932b338c-cac2-4b71-b26c-60107270e73d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34132
01496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.3413201496
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.1038069074
Short name T697
Test name
Test status
Simulation time 107199633262 ps
CPU time 2494.28 seconds
Started Jul 30 05:32:35 PM PDT 24
Finished Jul 30 06:14:09 PM PDT 24
Peak memory 288804 kb
Host smart-95a76d55-ce69-4d85-8d72-185aa3861721
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038069074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.1038069074
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.2454254402
Short name T58
Test name
Test status
Simulation time 76849078659 ps
CPU time 3685.14 seconds
Started Jul 30 05:32:34 PM PDT 24
Finished Jul 30 06:34:00 PM PDT 24
Peak memory 287292 kb
Host smart-84f1ca07-2f7f-4621-8ee5-f8211227673b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454254402 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.2454254402
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.2043692539
Short name T488
Test name
Test status
Simulation time 72020798644 ps
CPU time 1127.97 seconds
Started Jul 30 05:32:39 PM PDT 24
Finished Jul 30 05:51:27 PM PDT 24
Peak memory 264728 kb
Host smart-2327638e-f7a7-4523-af80-a55d8e27be18
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043692539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.2043692539
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.3522293486
Short name T609
Test name
Test status
Simulation time 1398332081 ps
CPU time 91.69 seconds
Started Jul 30 05:32:40 PM PDT 24
Finished Jul 30 05:34:12 PM PDT 24
Peak memory 256316 kb
Host smart-5ad4606a-f4f8-4838-9af6-564b93c89e74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35222
93486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.3522293486
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.2209163824
Short name T72
Test name
Test status
Simulation time 690554421 ps
CPU time 17.32 seconds
Started Jul 30 05:32:40 PM PDT 24
Finished Jul 30 05:32:58 PM PDT 24
Peak memory 256480 kb
Host smart-f06b51fa-1110-447b-be0c-6bf8b64ff710
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22091
63824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.2209163824
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.1868423076
Short name T319
Test name
Test status
Simulation time 48651917482 ps
CPU time 1472.55 seconds
Started Jul 30 05:32:39 PM PDT 24
Finished Jul 30 05:57:12 PM PDT 24
Peak memory 272132 kb
Host smart-b32de541-088c-4432-abf5-652ebaf168ef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868423076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.1868423076
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.1184011736
Short name T681
Test name
Test status
Simulation time 34632595927 ps
CPU time 2139.06 seconds
Started Jul 30 05:32:39 PM PDT 24
Finished Jul 30 06:08:18 PM PDT 24
Peak memory 281092 kb
Host smart-f50a32f2-4f09-4815-aab1-6fb01e29d0d7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184011736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.1184011736
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.2573319319
Short name T492
Test name
Test status
Simulation time 234004612 ps
CPU time 24.5 seconds
Started Jul 30 05:32:35 PM PDT 24
Finished Jul 30 05:32:59 PM PDT 24
Peak memory 248344 kb
Host smart-699e8f85-dc99-4d84-903b-866b1de4592a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25733
19319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.2573319319
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.3506571103
Short name T48
Test name
Test status
Simulation time 1770779048 ps
CPU time 28.88 seconds
Started Jul 30 05:32:36 PM PDT 24
Finished Jul 30 05:33:05 PM PDT 24
Peak memory 255556 kb
Host smart-e12d96ed-3ae0-4093-beda-a3136388c312
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35065
71103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.3506571103
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.276848150
Short name T384
Test name
Test status
Simulation time 143414967 ps
CPU time 6.79 seconds
Started Jul 30 05:32:41 PM PDT 24
Finished Jul 30 05:32:48 PM PDT 24
Peak memory 248936 kb
Host smart-2c35cc22-4917-4887-8a3e-996f5423cbfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27684
8150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.276848150
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.88941655
Short name T243
Test name
Test status
Simulation time 222635225 ps
CPU time 10.21 seconds
Started Jul 30 05:32:34 PM PDT 24
Finished Jul 30 05:32:44 PM PDT 24
Peak memory 248328 kb
Host smart-83cc1588-af98-4e08-b0cc-e5d4eb9d0469
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88941
655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.88941655
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.2381993484
Short name T108
Test name
Test status
Simulation time 332927855441 ps
CPU time 3076.75 seconds
Started Jul 30 05:32:41 PM PDT 24
Finished Jul 30 06:23:58 PM PDT 24
Peak memory 289256 kb
Host smart-a3b286b1-fc57-40fe-b8e1-5bf67350afb6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381993484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.2381993484
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.530988363
Short name T392
Test name
Test status
Simulation time 102369437706 ps
CPU time 8984.41 seconds
Started Jul 30 05:32:39 PM PDT 24
Finished Jul 30 08:02:24 PM PDT 24
Peak memory 394244 kb
Host smart-c6f5f4b7-9be3-44a8-93e9-ba8c2fd5b4ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530988363 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.530988363
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.3183794740
Short name T6
Test name
Test status
Simulation time 103866444777 ps
CPU time 1443.07 seconds
Started Jul 30 05:32:51 PM PDT 24
Finished Jul 30 05:56:54 PM PDT 24
Peak memory 288468 kb
Host smart-e13c1b9e-5e40-4280-8930-4d6806533728
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183794740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.3183794740
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.403701995
Short name T343
Test name
Test status
Simulation time 208924320 ps
CPU time 16.33 seconds
Started Jul 30 05:32:45 PM PDT 24
Finished Jul 30 05:33:01 PM PDT 24
Peak memory 256084 kb
Host smart-c382f8a9-3a77-41c2-8787-6157de9c0aab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40370
1995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.403701995
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.4230153571
Short name T701
Test name
Test status
Simulation time 2849106038 ps
CPU time 69.48 seconds
Started Jul 30 05:32:45 PM PDT 24
Finished Jul 30 05:33:55 PM PDT 24
Peak memory 256548 kb
Host smart-4e81ab04-81ac-43fd-b259-6536e3cc89e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42301
53571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.4230153571
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.681029521
Short name T311
Test name
Test status
Simulation time 228828734631 ps
CPU time 2696.3 seconds
Started Jul 30 05:32:51 PM PDT 24
Finished Jul 30 06:17:47 PM PDT 24
Peak memory 288544 kb
Host smart-08048e42-4c73-4e0d-baae-cac20e6684f4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681029521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.681029521
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.601005058
Short name T520
Test name
Test status
Simulation time 22636926303 ps
CPU time 1201.84 seconds
Started Jul 30 05:32:50 PM PDT 24
Finished Jul 30 05:52:52 PM PDT 24
Peak memory 282756 kb
Host smart-5ffcb226-38a4-480e-9417-2917848167c4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601005058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.601005058
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.3917575757
Short name T7
Test name
Test status
Simulation time 28795051094 ps
CPU time 322.4 seconds
Started Jul 30 05:32:47 PM PDT 24
Finished Jul 30 05:38:10 PM PDT 24
Peak memory 248336 kb
Host smart-cd119921-8412-46b1-a8e6-73d7c73daa19
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917575757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.3917575757
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.1911646173
Short name T495
Test name
Test status
Simulation time 1088252425 ps
CPU time 50.4 seconds
Started Jul 30 05:32:44 PM PDT 24
Finished Jul 30 05:33:35 PM PDT 24
Peak memory 255916 kb
Host smart-31b86015-d38d-49e0-bce6-f8d7c88b8db6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19116
46173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.1911646173
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.3494133772
Short name T340
Test name
Test status
Simulation time 216238986 ps
CPU time 6.02 seconds
Started Jul 30 05:32:43 PM PDT 24
Finished Jul 30 05:32:49 PM PDT 24
Peak memory 239656 kb
Host smart-5b1a7e07-9b85-4f4e-8500-c0af52eaf7c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34941
33772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.3494133772
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.1643351100
Short name T501
Test name
Test status
Simulation time 1046953639 ps
CPU time 52.43 seconds
Started Jul 30 05:32:44 PM PDT 24
Finished Jul 30 05:33:37 PM PDT 24
Peak memory 256108 kb
Host smart-e3e03738-0eec-46a6-a4bb-e09f5df97ac7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16433
51100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.1643351100
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.3752554716
Short name T623
Test name
Test status
Simulation time 3647184707 ps
CPU time 15.42 seconds
Started Jul 30 05:32:44 PM PDT 24
Finished Jul 30 05:33:00 PM PDT 24
Peak memory 248888 kb
Host smart-449e7eac-4025-426f-9430-e16c0634cc68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37525
54716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.3752554716
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.3660121838
Short name T123
Test name
Test status
Simulation time 141185080257 ps
CPU time 4249.79 seconds
Started Jul 30 05:32:47 PM PDT 24
Finished Jul 30 06:43:37 PM PDT 24
Peak memory 297580 kb
Host smart-a8ab8371-d01c-44db-9db2-ba5cc007bb52
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660121838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.3660121838
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.3268991021
Short name T110
Test name
Test status
Simulation time 59065502627 ps
CPU time 3701.88 seconds
Started Jul 30 05:32:50 PM PDT 24
Finished Jul 30 06:34:32 PM PDT 24
Peak memory 281312 kb
Host smart-43e25690-b978-4ea8-9abd-1eafc4a73c69
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268991021 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.3268991021
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.810006275
Short name T656
Test name
Test status
Simulation time 25276326604 ps
CPU time 614.95 seconds
Started Jul 30 05:32:57 PM PDT 24
Finished Jul 30 05:43:12 PM PDT 24
Peak memory 272412 kb
Host smart-3deae36b-d12e-4792-b1c4-52d368893c7c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810006275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.810006275
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.2150945176
Short name T354
Test name
Test status
Simulation time 10244232585 ps
CPU time 145.37 seconds
Started Jul 30 05:32:50 PM PDT 24
Finished Jul 30 05:35:16 PM PDT 24
Peak memory 255904 kb
Host smart-f675912b-55c2-4df3-a56c-98c1cb482f87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21509
45176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.2150945176
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.2351770939
Short name T566
Test name
Test status
Simulation time 179216944 ps
CPU time 18.63 seconds
Started Jul 30 05:32:49 PM PDT 24
Finished Jul 30 05:33:08 PM PDT 24
Peak memory 247916 kb
Host smart-edab4919-dfc7-4b1a-8db7-46219110fc2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23517
70939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.2351770939
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.3717934696
Short name T320
Test name
Test status
Simulation time 49403978804 ps
CPU time 1208.32 seconds
Started Jul 30 05:32:58 PM PDT 24
Finished Jul 30 05:53:07 PM PDT 24
Peak memory 272852 kb
Host smart-d76c4284-735c-4161-8369-af3df27c2c89
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717934696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.3717934696
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.4270365762
Short name T486
Test name
Test status
Simulation time 12897285952 ps
CPU time 986.72 seconds
Started Jul 30 05:32:57 PM PDT 24
Finished Jul 30 05:49:24 PM PDT 24
Peak memory 282684 kb
Host smart-69194ec8-2de9-4f38-99a3-6eaeed630d6e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270365762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.4270365762
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.1481278371
Short name T647
Test name
Test status
Simulation time 18218590564 ps
CPU time 179.5 seconds
Started Jul 30 05:32:58 PM PDT 24
Finished Jul 30 05:35:57 PM PDT 24
Peak memory 248372 kb
Host smart-43ef072e-0dfa-40ec-a72f-e4a0846cf788
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481278371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.1481278371
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.1484691109
Short name T420
Test name
Test status
Simulation time 168288517 ps
CPU time 9.55 seconds
Started Jul 30 05:32:51 PM PDT 24
Finished Jul 30 05:33:00 PM PDT 24
Peak memory 248316 kb
Host smart-1f4e4ab8-c0e2-4842-beb3-4b2ca420ecc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14846
91109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.1484691109
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.1351034826
Short name T79
Test name
Test status
Simulation time 212860066 ps
CPU time 13.1 seconds
Started Jul 30 05:32:48 PM PDT 24
Finished Jul 30 05:33:02 PM PDT 24
Peak memory 247916 kb
Host smart-e3548a31-c937-4935-9820-4a165e442bdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13510
34826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.1351034826
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.3942003916
Short name T489
Test name
Test status
Simulation time 3048665778 ps
CPU time 49.06 seconds
Started Jul 30 05:32:56 PM PDT 24
Finished Jul 30 05:33:45 PM PDT 24
Peak memory 255784 kb
Host smart-027d5a74-4d0f-4ae6-aa8f-d03cb55a3d7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39420
03916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.3942003916
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.1681910711
Short name T476
Test name
Test status
Simulation time 280923454 ps
CPU time 28.44 seconds
Started Jul 30 05:32:47 PM PDT 24
Finished Jul 30 05:33:16 PM PDT 24
Peak memory 255600 kb
Host smart-2d497e2b-c1cb-42f5-806e-d1ed3876f333
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16819
10711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.1681910711
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.3445285455
Short name T422
Test name
Test status
Simulation time 47759035240 ps
CPU time 269.82 seconds
Started Jul 30 05:32:58 PM PDT 24
Finished Jul 30 05:37:28 PM PDT 24
Peak memory 256604 kb
Host smart-1b75e2d6-db8d-4ab8-af7e-19d78e0e5651
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445285455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.3445285455
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.778085392
Short name T97
Test name
Test status
Simulation time 172150788261 ps
CPU time 2477.43 seconds
Started Jul 30 05:33:03 PM PDT 24
Finished Jul 30 06:14:20 PM PDT 24
Peak memory 289048 kb
Host smart-98718b13-4974-4207-8bc3-d7bc6a2acd13
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778085392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.778085392
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.1361295136
Short name T363
Test name
Test status
Simulation time 4540421923 ps
CPU time 85.51 seconds
Started Jul 30 05:33:00 PM PDT 24
Finished Jul 30 05:34:25 PM PDT 24
Peak memory 256536 kb
Host smart-4913fcc3-312e-497c-8687-24f11b1b7d07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13612
95136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.1361295136
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.3160357421
Short name T634
Test name
Test status
Simulation time 686416897 ps
CPU time 18.14 seconds
Started Jul 30 05:33:01 PM PDT 24
Finished Jul 30 05:33:19 PM PDT 24
Peak memory 248248 kb
Host smart-1c3c7821-b44a-4e55-8ffc-8c660eec56bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31603
57421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.3160357421
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.503862532
Short name T307
Test name
Test status
Simulation time 17093672489 ps
CPU time 1265.97 seconds
Started Jul 30 05:33:02 PM PDT 24
Finished Jul 30 05:54:09 PM PDT 24
Peak memory 287280 kb
Host smart-accca66c-3e6c-4613-abcc-14a1fb3d5d43
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503862532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.503862532
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.1575255856
Short name T60
Test name
Test status
Simulation time 94841646462 ps
CPU time 1974.03 seconds
Started Jul 30 05:33:01 PM PDT 24
Finished Jul 30 06:05:56 PM PDT 24
Peak memory 282288 kb
Host smart-6a2506c1-c7fc-48f3-9805-fdff641d7f7e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575255856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.1575255856
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.230919538
Short name T244
Test name
Test status
Simulation time 57245990192 ps
CPU time 381.57 seconds
Started Jul 30 05:33:01 PM PDT 24
Finished Jul 30 05:39:23 PM PDT 24
Peak memory 248200 kb
Host smart-cea167e2-d0e5-463a-924a-2a642cd48cbe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230919538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.230919538
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.3680045859
Short name T467
Test name
Test status
Simulation time 5142701476 ps
CPU time 46.3 seconds
Started Jul 30 05:32:57 PM PDT 24
Finished Jul 30 05:33:44 PM PDT 24
Peak memory 256588 kb
Host smart-ecd991ce-c3fb-461e-917e-c80b9141edb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36800
45859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.3680045859
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.1795980540
Short name T377
Test name
Test status
Simulation time 1555725583 ps
CPU time 26.45 seconds
Started Jul 30 05:32:58 PM PDT 24
Finished Jul 30 05:33:25 PM PDT 24
Peak memory 247800 kb
Host smart-757e7984-a28f-4586-9395-6b5b091c8bf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17959
80540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.1795980540
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.320541931
Short name T470
Test name
Test status
Simulation time 63268824 ps
CPU time 5.12 seconds
Started Jul 30 05:33:02 PM PDT 24
Finished Jul 30 05:33:07 PM PDT 24
Peak memory 239684 kb
Host smart-822b55ec-d5c0-4d82-9bd7-701870175a07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32054
1931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.320541931
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.1483648544
Short name T542
Test name
Test status
Simulation time 402402575 ps
CPU time 23.79 seconds
Started Jul 30 05:32:57 PM PDT 24
Finished Jul 30 05:33:21 PM PDT 24
Peak memory 248780 kb
Host smart-f8f82a6a-9bae-4857-bbc4-fe116dd3fed0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14836
48544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.1483648544
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.3362241402
Short name T5
Test name
Test status
Simulation time 50301220068 ps
CPU time 441.65 seconds
Started Jul 30 05:33:02 PM PDT 24
Finished Jul 30 05:40:24 PM PDT 24
Peak memory 255168 kb
Host smart-cbbeb0df-ab86-4368-8061-11b56237ceee
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362241402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.3362241402
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.2622490678
Short name T96
Test name
Test status
Simulation time 35635497267 ps
CPU time 861.28 seconds
Started Jul 30 05:33:05 PM PDT 24
Finished Jul 30 05:47:27 PM PDT 24
Peak memory 272976 kb
Host smart-ded790db-ea77-43dd-9539-b0151be2134b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622490678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.2622490678
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.3527690911
Short name T619
Test name
Test status
Simulation time 1275167024 ps
CPU time 122.16 seconds
Started Jul 30 05:33:06 PM PDT 24
Finished Jul 30 05:35:08 PM PDT 24
Peak memory 256100 kb
Host smart-b82d736a-d405-4ff8-b3ad-1076ba449b95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35276
90911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.3527690911
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.1484659177
Short name T382
Test name
Test status
Simulation time 2849500538 ps
CPU time 26.61 seconds
Started Jul 30 05:33:06 PM PDT 24
Finished Jul 30 05:33:32 PM PDT 24
Peak memory 247984 kb
Host smart-6a6ab263-6e6b-48be-84af-23316d5b8192
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14846
59177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.1484659177
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.1443903311
Short name T665
Test name
Test status
Simulation time 10266784286 ps
CPU time 919.29 seconds
Started Jul 30 05:33:10 PM PDT 24
Finished Jul 30 05:48:29 PM PDT 24
Peak memory 272248 kb
Host smart-a7816d9c-082e-45d4-b0aa-6ffb8a9a1f9e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443903311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.1443903311
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.1063032123
Short name T242
Test name
Test status
Simulation time 46504663572 ps
CPU time 1012.99 seconds
Started Jul 30 05:33:09 PM PDT 24
Finished Jul 30 05:50:03 PM PDT 24
Peak memory 272360 kb
Host smart-52074995-7e76-4a85-83a5-79f55df6a774
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063032123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.1063032123
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.3271651811
Short name T477
Test name
Test status
Simulation time 390080662 ps
CPU time 15.32 seconds
Started Jul 30 05:33:06 PM PDT 24
Finished Jul 30 05:33:21 PM PDT 24
Peak memory 254524 kb
Host smart-a5d57181-15c0-4cb7-a3a6-4968fb8657e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32716
51811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.3271651811
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.4016732178
Short name T100
Test name
Test status
Simulation time 168335906 ps
CPU time 18.39 seconds
Started Jul 30 05:33:07 PM PDT 24
Finished Jul 30 05:33:26 PM PDT 24
Peak memory 248360 kb
Host smart-635cf046-ea44-4f4f-b321-4e10bf4c3a1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40167
32178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.4016732178
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.1884540681
Short name T618
Test name
Test status
Simulation time 1252532037 ps
CPU time 44.11 seconds
Started Jul 30 05:33:07 PM PDT 24
Finished Jul 30 05:33:51 PM PDT 24
Peak memory 256076 kb
Host smart-0a1cdab9-6a2f-492f-990f-d3a3cd755013
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18845
40681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.1884540681
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.4275538024
Short name T529
Test name
Test status
Simulation time 536710573 ps
CPU time 18.79 seconds
Started Jul 30 05:33:05 PM PDT 24
Finished Jul 30 05:33:24 PM PDT 24
Peak memory 248288 kb
Host smart-060940a0-793e-4aec-a618-7661850dd7aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42755
38024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.4275538024
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.86647856
Short name T551
Test name
Test status
Simulation time 70455754871 ps
CPU time 1698.5 seconds
Started Jul 30 05:33:21 PM PDT 24
Finished Jul 30 06:01:40 PM PDT 24
Peak memory 288564 kb
Host smart-d7fdc566-25d7-4fbb-b06f-ef659c105eda
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86647856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.86647856
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.555700240
Short name T394
Test name
Test status
Simulation time 3608291550 ps
CPU time 230.78 seconds
Started Jul 30 05:33:21 PM PDT 24
Finished Jul 30 05:37:12 PM PDT 24
Peak memory 251468 kb
Host smart-7672eab0-e19c-492b-928e-4ce5aa08f263
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55570
0240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.555700240
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.1616703283
Short name T455
Test name
Test status
Simulation time 1990445912 ps
CPU time 42.98 seconds
Started Jul 30 05:33:21 PM PDT 24
Finished Jul 30 05:34:04 PM PDT 24
Peak memory 248328 kb
Host smart-6308904c-3538-4cb1-a4c0-cd8ac94c87d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16167
03283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.1616703283
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.3478630892
Short name T284
Test name
Test status
Simulation time 83942667651 ps
CPU time 2443.85 seconds
Started Jul 30 05:33:19 PM PDT 24
Finished Jul 30 06:14:03 PM PDT 24
Peak memory 281164 kb
Host smart-7481b3bf-a69b-486e-94e1-f74fab43c779
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478630892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.3478630892
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.3959204106
Short name T644
Test name
Test status
Simulation time 13641989104 ps
CPU time 275.64 seconds
Started Jul 30 05:33:21 PM PDT 24
Finished Jul 30 05:37:57 PM PDT 24
Peak memory 248380 kb
Host smart-f83da8d1-f5f5-41c2-9fb0-bde8852149f7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959204106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.3959204106
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.3909604862
Short name T485
Test name
Test status
Simulation time 101055175 ps
CPU time 4.89 seconds
Started Jul 30 05:33:13 PM PDT 24
Finished Jul 30 05:33:18 PM PDT 24
Peak memory 248320 kb
Host smart-25d1d30e-b7bc-405d-88ba-f61507ecb5f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39096
04862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.3909604862
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.2489076833
Short name T11
Test name
Test status
Simulation time 140642388 ps
CPU time 5.82 seconds
Started Jul 30 05:33:16 PM PDT 24
Finished Jul 30 05:33:22 PM PDT 24
Peak memory 247916 kb
Host smart-1d94e35f-cb87-453e-bd2f-422442484e04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24890
76833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.2489076833
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.2828535166
Short name T511
Test name
Test status
Simulation time 3577474989 ps
CPU time 57.12 seconds
Started Jul 30 05:33:21 PM PDT 24
Finished Jul 30 05:34:18 PM PDT 24
Peak memory 248032 kb
Host smart-ac60b04e-da4c-4728-9314-6ad4cc0b0f33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28285
35166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.2828535166
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.1691958383
Short name T493
Test name
Test status
Simulation time 4395832204 ps
CPU time 76.88 seconds
Started Jul 30 05:33:16 PM PDT 24
Finished Jul 30 05:34:33 PM PDT 24
Peak memory 256556 kb
Host smart-da8837dc-5995-47f1-b344-781539f58bf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16919
58383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.1691958383
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.4232050948
Short name T255
Test name
Test status
Simulation time 53529406851 ps
CPU time 3109.51 seconds
Started Jul 30 05:33:24 PM PDT 24
Finished Jul 30 06:25:14 PM PDT 24
Peak memory 288928 kb
Host smart-9c1ee2e7-3e45-4466-9db9-58e71a8e86e3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232050948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.4232050948
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.4255885008
Short name T351
Test name
Test status
Simulation time 90984974751 ps
CPU time 1295.52 seconds
Started Jul 30 05:33:35 PM PDT 24
Finished Jul 30 05:55:10 PM PDT 24
Peak memory 266724 kb
Host smart-2634a585-c884-46a4-8241-a747cc87e0fb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255885008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.4255885008
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.2941936655
Short name T704
Test name
Test status
Simulation time 6975979992 ps
CPU time 215.8 seconds
Started Jul 30 05:33:28 PM PDT 24
Finished Jul 30 05:37:04 PM PDT 24
Peak memory 250496 kb
Host smart-b3d35215-a88f-4e36-900f-0e1c7d226248
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29419
36655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.2941936655
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.3361089812
Short name T506
Test name
Test status
Simulation time 1197543454 ps
CPU time 37.81 seconds
Started Jul 30 05:33:23 PM PDT 24
Finished Jul 30 05:34:01 PM PDT 24
Peak memory 248320 kb
Host smart-8b29ebda-aa07-4ffd-a5ac-36e3a41f3ac6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33610
89812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.3361089812
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.369206747
Short name T250
Test name
Test status
Simulation time 25962825982 ps
CPU time 1339.65 seconds
Started Jul 30 05:33:33 PM PDT 24
Finished Jul 30 05:55:53 PM PDT 24
Peak memory 284648 kb
Host smart-6dec0795-d76c-4940-845d-af504d4d2f34
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369206747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.369206747
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.3501461625
Short name T19
Test name
Test status
Simulation time 78298030410 ps
CPU time 1452.77 seconds
Started Jul 30 05:33:34 PM PDT 24
Finished Jul 30 05:57:47 PM PDT 24
Peak memory 271664 kb
Host smart-80bd216c-2531-4ef7-805b-2b03b20725df
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501461625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.3501461625
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.4098108997
Short name T303
Test name
Test status
Simulation time 14185648017 ps
CPU time 148.26 seconds
Started Jul 30 05:33:32 PM PDT 24
Finished Jul 30 05:36:01 PM PDT 24
Peak memory 248412 kb
Host smart-0f87ae3e-4a3b-47bf-970d-5e5780b3e2b9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098108997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.4098108997
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.3993565520
Short name T373
Test name
Test status
Simulation time 241445912 ps
CPU time 17.92 seconds
Started Jul 30 05:33:23 PM PDT 24
Finished Jul 30 05:33:41 PM PDT 24
Peak memory 256248 kb
Host smart-1cbab219-aa7f-47cd-a2a7-b8e300f0c3fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39935
65520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.3993565520
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.14890046
Short name T22
Test name
Test status
Simulation time 570455095 ps
CPU time 18.62 seconds
Started Jul 30 05:33:23 PM PDT 24
Finished Jul 30 05:33:42 PM PDT 24
Peak memory 248328 kb
Host smart-99410e0e-1826-4d67-9cc4-a5b88181e320
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14890
046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.14890046
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.1006868607
Short name T532
Test name
Test status
Simulation time 37027464 ps
CPU time 3.74 seconds
Started Jul 30 05:33:34 PM PDT 24
Finished Jul 30 05:33:37 PM PDT 24
Peak memory 239452 kb
Host smart-9409d441-222c-44e3-8a96-de30d3acb760
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10068
68607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.1006868607
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.1402931655
Short name T398
Test name
Test status
Simulation time 2285124566 ps
CPU time 38.56 seconds
Started Jul 30 05:33:22 PM PDT 24
Finished Jul 30 05:34:00 PM PDT 24
Peak memory 255880 kb
Host smart-5ead0663-5d40-4f95-b4c1-8d27fa097c26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14029
31655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.1402931655
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.2311934590
Short name T523
Test name
Test status
Simulation time 7876218335 ps
CPU time 982.24 seconds
Started Jul 30 05:33:32 PM PDT 24
Finished Jul 30 05:49:55 PM PDT 24
Peak memory 283152 kb
Host smart-ae703c60-f3f3-42cd-b1a8-af5c81d262ac
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311934590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.2311934590
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all_with_rand_reset.73800442
Short name T252
Test name
Test status
Simulation time 177220238135 ps
CPU time 2584.68 seconds
Started Jul 30 05:33:36 PM PDT 24
Finished Jul 30 06:16:41 PM PDT 24
Peak memory 285692 kb
Host smart-09a2328d-344e-403e-bd16-1a2bc7345034
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73800442 -assert nopostproc +UVM_TESTNAME=alert_
handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 37.alert_handler_stress_all_with_rand_reset.73800442
Directory /workspace/37.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.2783504803
Short name T349
Test name
Test status
Simulation time 30891798799 ps
CPU time 1464.78 seconds
Started Jul 30 05:33:38 PM PDT 24
Finished Jul 30 05:58:03 PM PDT 24
Peak memory 288428 kb
Host smart-1c30b7d6-d201-4104-84cb-f67c867eb244
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783504803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.2783504803
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.1815622708
Short name T371
Test name
Test status
Simulation time 1224422638 ps
CPU time 72.97 seconds
Started Jul 30 05:33:36 PM PDT 24
Finished Jul 30 05:34:49 PM PDT 24
Peak memory 248364 kb
Host smart-6d2c354f-3bad-458a-9a7a-dc69a4ef1b35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18156
22708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.1815622708
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.2374484801
Short name T24
Test name
Test status
Simulation time 1326311806 ps
CPU time 40.97 seconds
Started Jul 30 05:33:35 PM PDT 24
Finished Jul 30 05:34:16 PM PDT 24
Peak memory 248144 kb
Host smart-741c0ed0-4b86-4caf-981f-24b3a8261ccc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23744
84801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.2374484801
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.3364171333
Short name T286
Test name
Test status
Simulation time 20385584080 ps
CPU time 1320.73 seconds
Started Jul 30 05:33:44 PM PDT 24
Finished Jul 30 05:55:45 PM PDT 24
Peak memory 272784 kb
Host smart-17a363c4-71d9-4691-9e56-214ed4a77855
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364171333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.3364171333
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.1606662603
Short name T375
Test name
Test status
Simulation time 172972052983 ps
CPU time 1777.96 seconds
Started Jul 30 05:33:42 PM PDT 24
Finished Jul 30 06:03:21 PM PDT 24
Peak memory 272916 kb
Host smart-595e0803-a554-41a3-ad9f-b9ad852d10e8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606662603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.1606662603
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.234408037
Short name T290
Test name
Test status
Simulation time 13511637828 ps
CPU time 534.13 seconds
Started Jul 30 05:33:41 PM PDT 24
Finished Jul 30 05:42:35 PM PDT 24
Peak memory 247296 kb
Host smart-ad51dcfb-5852-426e-93d9-2ba2638cb675
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234408037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.234408037
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.851449004
Short name T526
Test name
Test status
Simulation time 180044825 ps
CPU time 11.68 seconds
Started Jul 30 05:33:37 PM PDT 24
Finished Jul 30 05:33:49 PM PDT 24
Peak memory 255916 kb
Host smart-0c677fac-8e6f-4d31-a719-c2656183aa41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85144
9004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.851449004
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.2298520684
Short name T457
Test name
Test status
Simulation time 157512674 ps
CPU time 13.89 seconds
Started Jul 30 05:33:38 PM PDT 24
Finished Jul 30 05:33:52 PM PDT 24
Peak memory 248372 kb
Host smart-13b7e888-6c92-453c-b565-8ea9da17841a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22985
20684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.2298520684
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.2852410381
Short name T85
Test name
Test status
Simulation time 257401181 ps
CPU time 19.22 seconds
Started Jul 30 05:33:37 PM PDT 24
Finished Jul 30 05:33:56 PM PDT 24
Peak memory 255884 kb
Host smart-f365aec6-7b26-41bd-9510-101e2b9b682b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28524
10381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.2852410381
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.914364359
Short name T556
Test name
Test status
Simulation time 2734314639 ps
CPU time 43.88 seconds
Started Jul 30 05:33:37 PM PDT 24
Finished Jul 30 05:34:21 PM PDT 24
Peak memory 255676 kb
Host smart-bb7aa5ff-3918-4284-84ab-0f73cbbc40b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91436
4359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.914364359
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.3666120827
Short name T692
Test name
Test status
Simulation time 10676717695 ps
CPU time 1087.88 seconds
Started Jul 30 05:33:41 PM PDT 24
Finished Jul 30 05:51:49 PM PDT 24
Peak memory 283168 kb
Host smart-1ec8fc78-9c0d-4369-97c8-65a1c6fa1a72
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666120827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.3666120827
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.113727661
Short name T37
Test name
Test status
Simulation time 55324340038 ps
CPU time 3060.21 seconds
Started Jul 30 05:33:41 PM PDT 24
Finished Jul 30 06:24:42 PM PDT 24
Peak memory 338356 kb
Host smart-4bf97f02-dd28-4d6f-8416-6765401f0fd9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113727661 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.113727661
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.1744543992
Short name T18
Test name
Test status
Simulation time 8441687057 ps
CPU time 695.43 seconds
Started Jul 30 05:33:54 PM PDT 24
Finished Jul 30 05:45:30 PM PDT 24
Peak memory 272152 kb
Host smart-0b034905-f56c-401f-ba15-219c23f01b33
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744543992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.1744543992
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.388815901
Short name T459
Test name
Test status
Simulation time 235464239 ps
CPU time 18.53 seconds
Started Jul 30 05:33:51 PM PDT 24
Finished Jul 30 05:34:09 PM PDT 24
Peak memory 256084 kb
Host smart-0ff294a6-1424-4185-9cb6-255d290e11bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38881
5901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.388815901
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.3577886327
Short name T413
Test name
Test status
Simulation time 2698385146 ps
CPU time 23.45 seconds
Started Jul 30 05:33:46 PM PDT 24
Finished Jul 30 05:34:09 PM PDT 24
Peak memory 255868 kb
Host smart-67c003a2-e553-4d0f-8d10-9aea6d3df912
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35778
86327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.3577886327
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.1521505346
Short name T322
Test name
Test status
Simulation time 206008157434 ps
CPU time 3263.07 seconds
Started Jul 30 05:33:55 PM PDT 24
Finished Jul 30 06:28:19 PM PDT 24
Peak memory 280936 kb
Host smart-e562bf27-b63b-421f-bbfc-b7917bc056d9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521505346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.1521505346
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.3101631651
Short name T627
Test name
Test status
Simulation time 117979488052 ps
CPU time 1428.03 seconds
Started Jul 30 05:33:56 PM PDT 24
Finished Jul 30 05:57:44 PM PDT 24
Peak memory 272884 kb
Host smart-cf63767b-1802-45ec-ad14-34882baef334
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101631651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.3101631651
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.3329615677
Short name T466
Test name
Test status
Simulation time 9906530803 ps
CPU time 205.59 seconds
Started Jul 30 05:33:55 PM PDT 24
Finished Jul 30 05:37:21 PM PDT 24
Peak memory 255672 kb
Host smart-0f1d207a-6102-4fd6-81bd-94a63c560544
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329615677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.3329615677
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.2682086468
Short name T383
Test name
Test status
Simulation time 734181934 ps
CPU time 8.47 seconds
Started Jul 30 05:33:43 PM PDT 24
Finished Jul 30 05:33:53 PM PDT 24
Peak memory 253900 kb
Host smart-5f54fb2b-e4ec-459d-a7a5-a72e8621cd33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26820
86468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.2682086468
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.878887745
Short name T498
Test name
Test status
Simulation time 1450062676 ps
CPU time 13.22 seconds
Started Jul 30 05:33:47 PM PDT 24
Finished Jul 30 05:34:00 PM PDT 24
Peak memory 255580 kb
Host smart-3a15b447-0983-4704-81f4-be9e844b58ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87888
7745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.878887745
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.3371414368
Short name T505
Test name
Test status
Simulation time 3605436021 ps
CPU time 32.22 seconds
Started Jul 30 05:33:52 PM PDT 24
Finished Jul 30 05:34:24 PM PDT 24
Peak memory 248040 kb
Host smart-f07e6812-a3fa-4ce0-94f2-ca461ea04f72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33714
14368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.3371414368
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.3156636115
Short name T641
Test name
Test status
Simulation time 7200533084 ps
CPU time 55.04 seconds
Started Jul 30 05:33:40 PM PDT 24
Finished Jul 30 05:34:35 PM PDT 24
Peak memory 255716 kb
Host smart-c5fd27c8-7d9b-4b6a-8667-dfe47d3ed7b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31566
36115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.3156636115
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.2846755458
Short name T269
Test name
Test status
Simulation time 98855406110 ps
CPU time 629.99 seconds
Started Jul 30 05:33:54 PM PDT 24
Finished Jul 30 05:44:24 PM PDT 24
Peak memory 256580 kb
Host smart-823bf8f4-457e-4acc-813a-4d0fa6202c45
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846755458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.2846755458
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.1698566997
Short name T222
Test name
Test status
Simulation time 82071278 ps
CPU time 3.9 seconds
Started Jul 30 05:29:39 PM PDT 24
Finished Jul 30 05:29:43 PM PDT 24
Peak memory 248608 kb
Host smart-62e92d14-a7ad-44ed-aec0-ae16b22823f0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1698566997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.1698566997
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.2396994857
Short name T699
Test name
Test status
Simulation time 5542529006 ps
CPU time 645.52 seconds
Started Jul 30 05:29:40 PM PDT 24
Finished Jul 30 05:40:26 PM PDT 24
Peak memory 272380 kb
Host smart-dc6c459a-0fba-45b6-ac54-beb36411490c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396994857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.2396994857
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.2188868330
Short name T661
Test name
Test status
Simulation time 224934637 ps
CPU time 13.57 seconds
Started Jul 30 05:29:41 PM PDT 24
Finished Jul 30 05:29:55 PM PDT 24
Peak memory 248296 kb
Host smart-3ac6c24f-e0e0-4470-beec-9f13b4af04c4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2188868330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.2188868330
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.2190036837
Short name T507
Test name
Test status
Simulation time 1708924521 ps
CPU time 54.03 seconds
Started Jul 30 05:29:34 PM PDT 24
Finished Jul 30 05:30:28 PM PDT 24
Peak memory 256536 kb
Host smart-e05d23e1-122d-45b5-a49f-c74946e5850f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21900
36837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.2190036837
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.862513786
Short name T260
Test name
Test status
Simulation time 2207464975 ps
CPU time 39.47 seconds
Started Jul 30 05:29:36 PM PDT 24
Finished Jul 30 05:30:15 PM PDT 24
Peak memory 248428 kb
Host smart-1dc107c7-8208-47fb-9b4f-fb8068bc51a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86251
3786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.862513786
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.2588866063
Short name T379
Test name
Test status
Simulation time 22728846420 ps
CPU time 1253.19 seconds
Started Jul 30 05:29:39 PM PDT 24
Finished Jul 30 05:50:33 PM PDT 24
Peak memory 289176 kb
Host smart-f04fe27b-0790-428c-9864-56d5645445a9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588866063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.2588866063
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.197988134
Short name T552
Test name
Test status
Simulation time 36952345792 ps
CPU time 190.63 seconds
Started Jul 30 05:29:39 PM PDT 24
Finished Jul 30 05:32:50 PM PDT 24
Peak memory 248360 kb
Host smart-63997596-0da2-4b2e-8970-9c8240ecf54a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197988134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.197988134
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.3378695314
Short name T232
Test name
Test status
Simulation time 36684400 ps
CPU time 4.98 seconds
Started Jul 30 05:29:37 PM PDT 24
Finished Jul 30 05:29:42 PM PDT 24
Peak memory 251008 kb
Host smart-8541fd1d-4e5a-4038-ad5f-9aeacafaccff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33786
95314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.3378695314
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.4233537391
Short name T559
Test name
Test status
Simulation time 886715799 ps
CPU time 46.73 seconds
Started Jul 30 05:29:36 PM PDT 24
Finished Jul 30 05:30:23 PM PDT 24
Peak memory 247764 kb
Host smart-7456601d-fe72-40ec-8a37-d9d672fad3f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42335
37391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.4233537391
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.3979386688
Short name T353
Test name
Test status
Simulation time 6628908620 ps
CPU time 39.23 seconds
Started Jul 30 05:29:31 PM PDT 24
Finished Jul 30 05:30:10 PM PDT 24
Peak memory 255536 kb
Host smart-78b5ee49-c075-4abf-b780-e56096a0d70c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39793
86688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.3979386688
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.776846255
Short name T564
Test name
Test status
Simulation time 17126533870 ps
CPU time 1700.45 seconds
Started Jul 30 05:29:43 PM PDT 24
Finished Jul 30 05:58:04 PM PDT 24
Peak memory 289324 kb
Host smart-2b327de7-ba77-4e80-81a8-3bd8a7865eb7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776846255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_hand
ler_stress_all.776846255
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.2172887940
Short name T117
Test name
Test status
Simulation time 69549364120 ps
CPU time 1580.92 seconds
Started Jul 30 05:34:03 PM PDT 24
Finished Jul 30 06:00:24 PM PDT 24
Peak memory 288704 kb
Host smart-32dae0fa-630d-45e3-ab1d-8b9cb574bb19
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172887940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.2172887940
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.2542188767
Short name T196
Test name
Test status
Simulation time 2400085523 ps
CPU time 133.72 seconds
Started Jul 30 05:34:01 PM PDT 24
Finished Jul 30 05:36:15 PM PDT 24
Peak memory 255856 kb
Host smart-fcdd5f6c-9485-4d13-be2a-099eda0fab9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25421
88767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.2542188767
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.1635851582
Short name T672
Test name
Test status
Simulation time 832128179 ps
CPU time 37.49 seconds
Started Jul 30 05:34:01 PM PDT 24
Finished Jul 30 05:34:38 PM PDT 24
Peak memory 248336 kb
Host smart-db7b4590-99c0-4c75-b5ca-fda09d93db68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16358
51582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.1635851582
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.331825041
Short name T247
Test name
Test status
Simulation time 68997082515 ps
CPU time 1980.76 seconds
Started Jul 30 05:34:09 PM PDT 24
Finished Jul 30 06:07:10 PM PDT 24
Peak memory 285092 kb
Host smart-db4d402b-8cb4-4cd3-b639-c7de73d45bba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331825041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.331825041
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.666831169
Short name T584
Test name
Test status
Simulation time 137025753 ps
CPU time 15.23 seconds
Started Jul 30 05:34:00 PM PDT 24
Finished Jul 30 05:34:15 PM PDT 24
Peak memory 256472 kb
Host smart-36526f2f-2078-4e60-bcca-9583c0dd1ec6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66683
1169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.666831169
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.1158770394
Short name T64
Test name
Test status
Simulation time 424031036 ps
CPU time 24.56 seconds
Started Jul 30 05:33:58 PM PDT 24
Finished Jul 30 05:34:23 PM PDT 24
Peak memory 255248 kb
Host smart-21063e48-ec5b-4e82-81ca-fe3fd17592d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11587
70394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.1158770394
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.2354818582
Short name T613
Test name
Test status
Simulation time 65137669 ps
CPU time 5.46 seconds
Started Jul 30 05:34:03 PM PDT 24
Finished Jul 30 05:34:09 PM PDT 24
Peak memory 240188 kb
Host smart-29ee8809-931d-4046-b486-d47e557a1335
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23548
18582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.2354818582
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.3930961940
Short name T587
Test name
Test status
Simulation time 896119207 ps
CPU time 37.89 seconds
Started Jul 30 05:33:58 PM PDT 24
Finished Jul 30 05:34:36 PM PDT 24
Peak memory 256704 kb
Host smart-a7dc5cb0-101f-439f-8c7b-80d86d9868bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39309
61940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.3930961940
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.3270309312
Short name T88
Test name
Test status
Simulation time 110999770244 ps
CPU time 1195.78 seconds
Started Jul 30 05:34:21 PM PDT 24
Finished Jul 30 05:54:17 PM PDT 24
Peak memory 272960 kb
Host smart-78d3b440-c478-45c4-b6fe-d4fb4626e505
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270309312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.3270309312
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.1411021856
Short name T358
Test name
Test status
Simulation time 10009647765 ps
CPU time 159.01 seconds
Started Jul 30 05:34:18 PM PDT 24
Finished Jul 30 05:36:57 PM PDT 24
Peak memory 256524 kb
Host smart-d9e732b4-e241-4033-8400-e3fd8e2d05f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14110
21856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.1411021856
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.1105909567
Short name T446
Test name
Test status
Simulation time 211609546 ps
CPU time 24.02 seconds
Started Jul 30 05:34:14 PM PDT 24
Finished Jul 30 05:34:38 PM PDT 24
Peak memory 248296 kb
Host smart-f6f5752b-2d97-4611-9cb0-6d6b13569992
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11059
09567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.1105909567
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.1883632836
Short name T287
Test name
Test status
Simulation time 508028143124 ps
CPU time 2604.87 seconds
Started Jul 30 05:34:18 PM PDT 24
Finished Jul 30 06:17:43 PM PDT 24
Peak memory 284648 kb
Host smart-2641bdb2-4246-44a7-9943-677ba38aa647
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883632836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.1883632836
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.647945931
Short name T654
Test name
Test status
Simulation time 8418519349 ps
CPU time 96.53 seconds
Started Jul 30 05:34:18 PM PDT 24
Finished Jul 30 05:35:54 PM PDT 24
Peak memory 248396 kb
Host smart-d4a385a4-9937-44f6-8983-7e2740876385
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647945931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.647945931
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.1698376037
Short name T341
Test name
Test status
Simulation time 547508845 ps
CPU time 3.86 seconds
Started Jul 30 05:34:08 PM PDT 24
Finished Jul 30 05:34:12 PM PDT 24
Peak memory 240128 kb
Host smart-7019c53d-b261-412c-8602-d08ce89d68f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16983
76037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.1698376037
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.1519713012
Short name T469
Test name
Test status
Simulation time 1159665699 ps
CPU time 37.66 seconds
Started Jul 30 05:34:18 PM PDT 24
Finished Jul 30 05:34:55 PM PDT 24
Peak memory 248228 kb
Host smart-963c2f98-a8b9-4e2b-9b4e-a54a80a5483a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15197
13012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.1519713012
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.180658967
Short name T577
Test name
Test status
Simulation time 127714469 ps
CPU time 10.7 seconds
Started Jul 30 05:34:10 PM PDT 24
Finished Jul 30 05:34:21 PM PDT 24
Peak memory 256156 kb
Host smart-43cf55ff-573c-425e-89c3-72b0db587e09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18065
8967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.180658967
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.2493841385
Short name T621
Test name
Test status
Simulation time 47822159865 ps
CPU time 2756.11 seconds
Started Jul 30 05:34:19 PM PDT 24
Finished Jul 30 06:20:16 PM PDT 24
Peak memory 289372 kb
Host smart-d0208baf-e246-4a0e-ad5b-33676de69c6e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493841385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.2493841385
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all_with_rand_reset.1145118688
Short name T251
Test name
Test status
Simulation time 163355931940 ps
CPU time 1733.56 seconds
Started Jul 30 05:34:18 PM PDT 24
Finished Jul 30 06:03:11 PM PDT 24
Peak memory 289428 kb
Host smart-e387aa63-1a5d-4e13-9e52-b0b965e19796
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145118688 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.alert_handler_stress_all_with_rand_reset.1145118688
Directory /workspace/41.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.2898807084
Short name T624
Test name
Test status
Simulation time 112887614484 ps
CPU time 1868.02 seconds
Started Jul 30 05:34:27 PM PDT 24
Finished Jul 30 06:05:36 PM PDT 24
Peak memory 283052 kb
Host smart-8a2ed47b-4088-4f14-a176-71f9c2f67773
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898807084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.2898807084
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.1489283090
Short name T429
Test name
Test status
Simulation time 23252440690 ps
CPU time 160.93 seconds
Started Jul 30 05:34:30 PM PDT 24
Finished Jul 30 05:37:12 PM PDT 24
Peak memory 255976 kb
Host smart-08af9078-fff8-4e07-ba73-532bc90dfd51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14892
83090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.1489283090
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.2398299004
Short name T572
Test name
Test status
Simulation time 829768863 ps
CPU time 49.64 seconds
Started Jul 30 05:34:28 PM PDT 24
Finished Jul 30 05:35:18 PM PDT 24
Peak memory 247804 kb
Host smart-11eccecc-55ba-4426-bb73-82e26d870aca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23982
99004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.2398299004
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.503641991
Short name T121
Test name
Test status
Simulation time 58523935285 ps
CPU time 1582.48 seconds
Started Jul 30 05:34:31 PM PDT 24
Finished Jul 30 06:00:54 PM PDT 24
Peak memory 272872 kb
Host smart-0ad298bf-9534-4c4d-a9c1-39df7edcd6cd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503641991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.503641991
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.4110386573
Short name T586
Test name
Test status
Simulation time 68225265069 ps
CPU time 2430.19 seconds
Started Jul 30 05:34:28 PM PDT 24
Finished Jul 30 06:14:58 PM PDT 24
Peak memory 289296 kb
Host smart-82e43493-bf51-416a-9406-881090d58e43
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110386573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.4110386573
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.3763022457
Short name T301
Test name
Test status
Simulation time 33020534458 ps
CPU time 661.68 seconds
Started Jul 30 05:34:28 PM PDT 24
Finished Jul 30 05:45:30 PM PDT 24
Peak memory 247296 kb
Host smart-ce1da2be-cd7f-4e73-889a-af73ccbd1919
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763022457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.3763022457
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.1126809069
Short name T346
Test name
Test status
Simulation time 939120578 ps
CPU time 17.35 seconds
Started Jul 30 05:34:18 PM PDT 24
Finished Jul 30 05:34:35 PM PDT 24
Peak memory 255844 kb
Host smart-ad98d818-77c2-4ac3-a8e8-d351ffce72de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11268
09069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.1126809069
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.259691505
Short name T615
Test name
Test status
Simulation time 3430664536 ps
CPU time 43.73 seconds
Started Jul 30 05:34:23 PM PDT 24
Finished Jul 30 05:35:06 PM PDT 24
Peak memory 255892 kb
Host smart-200af545-af97-44ce-abe6-e89f78a56448
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25969
1505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.259691505
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.1967307817
Short name T599
Test name
Test status
Simulation time 2604496584 ps
CPU time 20.87 seconds
Started Jul 30 05:34:19 PM PDT 24
Finished Jul 30 05:34:40 PM PDT 24
Peak memory 255608 kb
Host smart-9322dffb-035a-4c7b-81f0-629c926f1296
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19673
07817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.1967307817
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.635792491
Short name T691
Test name
Test status
Simulation time 12791613656 ps
CPU time 681.27 seconds
Started Jul 30 05:34:28 PM PDT 24
Finished Jul 30 05:45:50 PM PDT 24
Peak memory 272852 kb
Host smart-805a236e-2ef7-484d-b565-1670ec33507a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635792491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_han
dler_stress_all.635792491
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all_with_rand_reset.3996789765
Short name T414
Test name
Test status
Simulation time 23476515222 ps
CPU time 1249.07 seconds
Started Jul 30 05:34:30 PM PDT 24
Finished Jul 30 05:55:20 PM PDT 24
Peak memory 281328 kb
Host smart-9a7c3351-1559-4f67-a082-832bba36d179
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996789765 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.alert_handler_stress_all_with_rand_reset.3996789765
Directory /workspace/42.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.2498685280
Short name T504
Test name
Test status
Simulation time 350467712128 ps
CPU time 2570.42 seconds
Started Jul 30 05:34:34 PM PDT 24
Finished Jul 30 06:17:25 PM PDT 24
Peak memory 283264 kb
Host smart-a13e56b1-0467-4ddd-9503-923afa4e002d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498685280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.2498685280
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.1316762866
Short name T390
Test name
Test status
Simulation time 977459352 ps
CPU time 43.5 seconds
Started Jul 30 05:34:37 PM PDT 24
Finished Jul 30 05:35:21 PM PDT 24
Peak memory 255812 kb
Host smart-7e4e5467-2b38-41e2-9c79-3caf399923a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13167
62866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.1316762866
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.3532088956
Short name T235
Test name
Test status
Simulation time 576433030 ps
CPU time 37.39 seconds
Started Jul 30 05:34:36 PM PDT 24
Finished Jul 30 05:35:14 PM PDT 24
Peak memory 248372 kb
Host smart-1de992b0-66a6-4637-814f-4b848e2cef8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35320
88956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.3532088956
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.385441440
Short name T650
Test name
Test status
Simulation time 39365059266 ps
CPU time 1388.5 seconds
Started Jul 30 05:34:42 PM PDT 24
Finished Jul 30 05:57:50 PM PDT 24
Peak memory 272616 kb
Host smart-86ab75a6-cbdc-4301-aa6b-ab389bd5e7b6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385441440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.385441440
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.2055729070
Short name T581
Test name
Test status
Simulation time 73586222855 ps
CPU time 1370.62 seconds
Started Jul 30 05:34:41 PM PDT 24
Finished Jul 30 05:57:31 PM PDT 24
Peak memory 287888 kb
Host smart-d2450179-27f1-4233-8a98-422ced9704e0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055729070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.2055729070
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.1583849701
Short name T295
Test name
Test status
Simulation time 7904195435 ps
CPU time 331.82 seconds
Started Jul 30 05:34:37 PM PDT 24
Finished Jul 30 05:40:09 PM PDT 24
Peak memory 248156 kb
Host smart-f6d72d3c-efa0-437a-9490-22c2656e3b98
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583849701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.1583849701
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.975888515
Short name T405
Test name
Test status
Simulation time 533504028 ps
CPU time 21.13 seconds
Started Jul 30 05:34:33 PM PDT 24
Finished Jul 30 05:34:54 PM PDT 24
Peak memory 255884 kb
Host smart-1756aa0a-83eb-48db-a543-c172607cfe28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97588
8515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.975888515
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.2511430708
Short name T673
Test name
Test status
Simulation time 216253867 ps
CPU time 17.45 seconds
Started Jul 30 05:34:37 PM PDT 24
Finished Jul 30 05:34:54 PM PDT 24
Peak memory 254760 kb
Host smart-0bc67837-440d-4816-acd3-fb6333dd3d1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25114
30708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.2511430708
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.1061979442
Short name T265
Test name
Test status
Simulation time 773468392 ps
CPU time 54.04 seconds
Started Jul 30 05:34:37 PM PDT 24
Finished Jul 30 05:35:31 PM PDT 24
Peak memory 248440 kb
Host smart-d8ac1b59-b4ee-47b2-ad94-1076de71d58d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10619
79442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.1061979442
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.2756309675
Short name T433
Test name
Test status
Simulation time 5122945295 ps
CPU time 18.26 seconds
Started Jul 30 05:34:35 PM PDT 24
Finished Jul 30 05:34:53 PM PDT 24
Peak memory 248384 kb
Host smart-da79786c-ac3d-41c8-aa98-0e7dc04ad202
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27563
09675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.2756309675
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.3130042463
Short name T430
Test name
Test status
Simulation time 34163295355 ps
CPU time 2382.45 seconds
Started Jul 30 05:34:57 PM PDT 24
Finished Jul 30 06:14:40 PM PDT 24
Peak memory 286184 kb
Host smart-b2cfa93d-d3bc-4610-a750-4793c86d081f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130042463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.3130042463
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.855581194
Short name T338
Test name
Test status
Simulation time 14695863518 ps
CPU time 112.13 seconds
Started Jul 30 05:34:49 PM PDT 24
Finished Jul 30 05:36:41 PM PDT 24
Peak memory 255992 kb
Host smart-8d3da1d8-d0b2-44ee-87e0-a954d4456c3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85558
1194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.855581194
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.269692842
Short name T638
Test name
Test status
Simulation time 142947039 ps
CPU time 17.74 seconds
Started Jul 30 05:34:49 PM PDT 24
Finished Jul 30 05:35:07 PM PDT 24
Peak memory 248172 kb
Host smart-301f65ae-2c65-407c-b0da-6570fec99b8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26969
2842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.269692842
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.4006828371
Short name T313
Test name
Test status
Simulation time 36519896384 ps
CPU time 1572.03 seconds
Started Jul 30 05:34:55 PM PDT 24
Finished Jul 30 06:01:07 PM PDT 24
Peak memory 289140 kb
Host smart-61039271-ca95-40bd-a40e-35fb21182b22
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006828371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.4006828371
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.1923150604
Short name T342
Test name
Test status
Simulation time 228635337400 ps
CPU time 3554.99 seconds
Started Jul 30 05:34:54 PM PDT 24
Finished Jul 30 06:34:10 PM PDT 24
Peak memory 288736 kb
Host smart-44b87807-801b-450d-9ec2-d05b0ae1c3d6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923150604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.1923150604
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.935839825
Short name T499
Test name
Test status
Simulation time 4626778965 ps
CPU time 78.07 seconds
Started Jul 30 05:34:52 PM PDT 24
Finished Jul 30 05:36:11 PM PDT 24
Peak memory 248212 kb
Host smart-c112de69-ab42-4ecf-a9ad-d47673ee9df7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935839825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.935839825
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.1302877185
Short name T388
Test name
Test status
Simulation time 1107243127 ps
CPU time 26.84 seconds
Started Jul 30 05:34:46 PM PDT 24
Finished Jul 30 05:35:13 PM PDT 24
Peak memory 255988 kb
Host smart-165b0698-a144-4521-9f37-f9390d861e15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13028
77185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.1302877185
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.2646381191
Short name T544
Test name
Test status
Simulation time 2207162966 ps
CPU time 30.51 seconds
Started Jul 30 05:34:42 PM PDT 24
Finished Jul 30 05:35:13 PM PDT 24
Peak memory 248280 kb
Host smart-6a390a88-6306-48f2-8e62-bca3ed5dbc9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26463
81191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.2646381191
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.3848180624
Short name T437
Test name
Test status
Simulation time 939889323 ps
CPU time 14.6 seconds
Started Jul 30 05:34:55 PM PDT 24
Finished Jul 30 05:35:10 PM PDT 24
Peak memory 255972 kb
Host smart-0cbb0a83-eeb5-41bc-8bc0-dff7a994dd77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38481
80624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.3848180624
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.4141550666
Short name T591
Test name
Test status
Simulation time 295320981 ps
CPU time 29.44 seconds
Started Jul 30 05:34:46 PM PDT 24
Finished Jul 30 05:35:16 PM PDT 24
Peak memory 256408 kb
Host smart-73fa5d2a-7094-46d9-8ff0-e2bfd05d7f87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41415
50666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.4141550666
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.523625697
Short name T668
Test name
Test status
Simulation time 39380721632 ps
CPU time 2256.39 seconds
Started Jul 30 05:35:12 PM PDT 24
Finished Jul 30 06:12:49 PM PDT 24
Peak memory 288996 kb
Host smart-5c244edd-f9a8-48a6-8071-6fb2723b43b9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523625697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.523625697
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.2912801026
Short name T395
Test name
Test status
Simulation time 4791776140 ps
CPU time 151.83 seconds
Started Jul 30 05:35:06 PM PDT 24
Finished Jul 30 05:37:38 PM PDT 24
Peak memory 256180 kb
Host smart-e1b5fdcb-c2de-4a41-8a03-a30ffd3c4851
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29128
01026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.2912801026
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.531002515
Short name T447
Test name
Test status
Simulation time 468145365 ps
CPU time 32.53 seconds
Started Jul 30 05:35:07 PM PDT 24
Finished Jul 30 05:35:39 PM PDT 24
Peak memory 256472 kb
Host smart-fe9afdf3-cb6d-49db-b884-61590ef1baa8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53100
2515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.531002515
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.3381988788
Short name T563
Test name
Test status
Simulation time 31826833838 ps
CPU time 1657 seconds
Started Jul 30 05:35:12 PM PDT 24
Finished Jul 30 06:02:50 PM PDT 24
Peak memory 272972 kb
Host smart-f0bc6813-fb42-4345-aab5-66302a452e43
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381988788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.3381988788
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.3010519054
Short name T602
Test name
Test status
Simulation time 55665829426 ps
CPU time 3221.17 seconds
Started Jul 30 05:35:15 PM PDT 24
Finished Jul 30 06:28:56 PM PDT 24
Peak memory 289140 kb
Host smart-1b8cc3e3-9077-45c5-9707-2f6774fd30ee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010519054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.3010519054
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.3722407367
Short name T687
Test name
Test status
Simulation time 24472060013 ps
CPU time 391.54 seconds
Started Jul 30 05:35:12 PM PDT 24
Finished Jul 30 05:41:44 PM PDT 24
Peak memory 247240 kb
Host smart-5bb0f19a-b418-42dc-979d-a9ae447b6cce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722407367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.3722407367
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.3682086062
Short name T461
Test name
Test status
Simulation time 7335720632 ps
CPU time 50.5 seconds
Started Jul 30 05:34:59 PM PDT 24
Finished Jul 30 05:35:49 PM PDT 24
Peak memory 256388 kb
Host smart-8b7ffd3d-d65d-4804-b187-8e9433a1c911
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36820
86062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.3682086062
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.1117379234
Short name T515
Test name
Test status
Simulation time 649572385 ps
CPU time 53.81 seconds
Started Jul 30 05:35:08 PM PDT 24
Finished Jul 30 05:36:02 PM PDT 24
Peak memory 256216 kb
Host smart-45106f5c-8d1a-4b72-8a01-6b1619a88750
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11173
79234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.1117379234
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.253257649
Short name T21
Test name
Test status
Simulation time 128660534 ps
CPU time 13.19 seconds
Started Jul 30 05:34:58 PM PDT 24
Finished Jul 30 05:35:11 PM PDT 24
Peak memory 256036 kb
Host smart-2fc4e9fd-d30d-4770-a5a4-5ab645a8b46e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25325
7649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.253257649
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.1930621163
Short name T484
Test name
Test status
Simulation time 5248267027 ps
CPU time 581.13 seconds
Started Jul 30 05:35:31 PM PDT 24
Finished Jul 30 05:45:12 PM PDT 24
Peak memory 271276 kb
Host smart-be9107eb-e9d3-4647-bfcf-f5c2c5e993a0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930621163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.1930621163
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.4043465001
Short name T126
Test name
Test status
Simulation time 6667338614 ps
CPU time 133.45 seconds
Started Jul 30 05:35:26 PM PDT 24
Finished Jul 30 05:37:40 PM PDT 24
Peak memory 255960 kb
Host smart-e59346ba-a68b-4644-9415-e22f212dc247
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40434
65001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.4043465001
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.154445618
Short name T508
Test name
Test status
Simulation time 119247170 ps
CPU time 10.57 seconds
Started Jul 30 05:35:27 PM PDT 24
Finished Jul 30 05:35:37 PM PDT 24
Peak memory 247892 kb
Host smart-8e8df5af-0763-4593-9e5a-6c1ac4b34f63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15444
5618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.154445618
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.1320047606
Short name T509
Test name
Test status
Simulation time 47318177135 ps
CPU time 998.37 seconds
Started Jul 30 05:35:32 PM PDT 24
Finished Jul 30 05:52:11 PM PDT 24
Peak memory 272392 kb
Host smart-a96fdbe9-8dbe-4d9d-9611-eeb2ebe3bb67
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320047606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.1320047606
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.1456612835
Short name T516
Test name
Test status
Simulation time 12735674164 ps
CPU time 1179.38 seconds
Started Jul 30 05:35:33 PM PDT 24
Finished Jul 30 05:55:12 PM PDT 24
Peak memory 282368 kb
Host smart-f3fb702d-ecb5-430f-9c64-e5e574281f1c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456612835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.1456612835
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.3685573098
Short name T571
Test name
Test status
Simulation time 26530456243 ps
CPU time 286.69 seconds
Started Jul 30 05:35:31 PM PDT 24
Finished Jul 30 05:40:18 PM PDT 24
Peak memory 248376 kb
Host smart-874fee78-7370-41ca-8751-4bf8cd447608
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685573098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.3685573098
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.1303177956
Short name T677
Test name
Test status
Simulation time 417212746 ps
CPU time 23.07 seconds
Started Jul 30 05:35:14 PM PDT 24
Finished Jul 30 05:35:37 PM PDT 24
Peak memory 255940 kb
Host smart-dd6001b1-6928-4c48-9057-f4ef37749883
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13031
77956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.1303177956
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.4197427308
Short name T539
Test name
Test status
Simulation time 426989119 ps
CPU time 22.42 seconds
Started Jul 30 05:35:25 PM PDT 24
Finished Jul 30 05:35:47 PM PDT 24
Peak memory 247936 kb
Host smart-d09fab58-d6af-4954-9977-f16ad7a8b657
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41974
27308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.4197427308
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.2195068423
Short name T558
Test name
Test status
Simulation time 1788581407 ps
CPU time 18.08 seconds
Started Jul 30 05:35:33 PM PDT 24
Finished Jul 30 05:35:51 PM PDT 24
Peak memory 248352 kb
Host smart-876181c7-ac3e-43c4-8458-28dbd68c65e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21950
68423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.2195068423
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.741105218
Short name T345
Test name
Test status
Simulation time 538516585 ps
CPU time 14.19 seconds
Started Jul 30 05:35:11 PM PDT 24
Finished Jul 30 05:35:26 PM PDT 24
Peak memory 256436 kb
Host smart-557b442e-5e08-4974-b8c8-42841e56cfbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74110
5218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.741105218
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.4020142704
Short name T633
Test name
Test status
Simulation time 15576992534 ps
CPU time 341.78 seconds
Started Jul 30 05:35:36 PM PDT 24
Finished Jul 30 05:41:18 PM PDT 24
Peak memory 256552 kb
Host smart-03d78a40-9d31-4b2a-af99-b515d8cef4f8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020142704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.4020142704
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.1760505268
Short name T278
Test name
Test status
Simulation time 152722655629 ps
CPU time 2243.39 seconds
Started Jul 30 05:35:50 PM PDT 24
Finished Jul 30 06:13:14 PM PDT 24
Peak memory 285876 kb
Host smart-40eda11d-c9db-4a42-b45e-f74ae617e868
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760505268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.1760505268
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.416512368
Short name T468
Test name
Test status
Simulation time 941848678 ps
CPU time 56.85 seconds
Started Jul 30 05:35:51 PM PDT 24
Finished Jul 30 05:36:48 PM PDT 24
Peak memory 255636 kb
Host smart-2c2b1cce-a0aa-4e9f-8d34-3ffd1c450dc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41651
2368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.416512368
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.3911113194
Short name T528
Test name
Test status
Simulation time 162025693 ps
CPU time 14.42 seconds
Started Jul 30 05:35:42 PM PDT 24
Finished Jul 30 05:35:57 PM PDT 24
Peak memory 256120 kb
Host smart-0b1e1640-4a18-4379-a07d-a4f26b0040ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39111
13194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.3911113194
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.3967539286
Short name T306
Test name
Test status
Simulation time 95715178463 ps
CPU time 2635.66 seconds
Started Jul 30 05:35:46 PM PDT 24
Finished Jul 30 06:19:42 PM PDT 24
Peak memory 284292 kb
Host smart-c796a9ba-61a3-4bc1-9b8d-bada2180bac9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967539286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.3967539286
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.1893038209
Short name T401
Test name
Test status
Simulation time 49004012395 ps
CPU time 2638.04 seconds
Started Jul 30 05:35:52 PM PDT 24
Finished Jul 30 06:19:50 PM PDT 24
Peak memory 288816 kb
Host smart-2a25a0e8-171f-43da-afdd-5cd495dbe1b0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893038209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.1893038209
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.1251119304
Short name T135
Test name
Test status
Simulation time 45409581734 ps
CPU time 471.49 seconds
Started Jul 30 05:35:51 PM PDT 24
Finished Jul 30 05:43:42 PM PDT 24
Peak memory 248248 kb
Host smart-a7a62383-768d-4c7b-9eae-c66078ff3d37
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251119304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.1251119304
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.25183627
Short name T241
Test name
Test status
Simulation time 341289768 ps
CPU time 16.29 seconds
Started Jul 30 05:35:32 PM PDT 24
Finished Jul 30 05:35:48 PM PDT 24
Peak memory 248320 kb
Host smart-e3759335-b273-4b06-ae1c-5037e9e75354
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25183
627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.25183627
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.1757969866
Short name T362
Test name
Test status
Simulation time 180438415 ps
CPU time 4.5 seconds
Started Jul 30 05:35:39 PM PDT 24
Finished Jul 30 05:35:44 PM PDT 24
Peak memory 239592 kb
Host smart-c0b8fe79-0ff9-4400-acf9-fcde1f9b82bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17579
69866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.1757969866
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.4168655539
Short name T35
Test name
Test status
Simulation time 195267119 ps
CPU time 10.04 seconds
Started Jul 30 05:35:35 PM PDT 24
Finished Jul 30 05:35:45 PM PDT 24
Peak memory 254912 kb
Host smart-76e56746-2527-484b-beca-4cfc0329b600
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41686
55539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.4168655539
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.3073658200
Short name T631
Test name
Test status
Simulation time 147671303683 ps
CPU time 3885.88 seconds
Started Jul 30 05:35:51 PM PDT 24
Finished Jul 30 06:40:37 PM PDT 24
Peak memory 337924 kb
Host smart-36120ef1-e2cf-42fc-8530-863c830f7cb6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073658200 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.3073658200
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.3822338088
Short name T367
Test name
Test status
Simulation time 94578990863 ps
CPU time 1597.11 seconds
Started Jul 30 05:36:00 PM PDT 24
Finished Jul 30 06:02:37 PM PDT 24
Peak memory 272728 kb
Host smart-785274a7-6182-4c46-afd8-73d3c82c2911
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822338088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.3822338088
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.1541576882
Short name T421
Test name
Test status
Simulation time 1250155524 ps
CPU time 92 seconds
Started Jul 30 05:35:58 PM PDT 24
Finished Jul 30 05:37:30 PM PDT 24
Peak memory 256092 kb
Host smart-698d1f84-f555-4881-8ab4-19e8cf7c38a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15415
76882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.1541576882
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.2744109537
Short name T465
Test name
Test status
Simulation time 377199307 ps
CPU time 22.18 seconds
Started Jul 30 05:35:53 PM PDT 24
Finished Jul 30 05:36:16 PM PDT 24
Peak memory 248320 kb
Host smart-8e25c7ad-5555-49f4-9219-3c8f5e163ac9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27441
09537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.2744109537
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.1301130212
Short name T550
Test name
Test status
Simulation time 38968954182 ps
CPU time 2122.41 seconds
Started Jul 30 05:35:53 PM PDT 24
Finished Jul 30 06:11:16 PM PDT 24
Peak memory 272964 kb
Host smart-858c27c1-719d-49ac-be30-1ea45bb11e52
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301130212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.1301130212
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.366597644
Short name T424
Test name
Test status
Simulation time 50778485477 ps
CPU time 1454.71 seconds
Started Jul 30 05:36:01 PM PDT 24
Finished Jul 30 06:00:16 PM PDT 24
Peak memory 272960 kb
Host smart-919ccba8-8a69-4f56-b35c-957c47919511
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366597644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.366597644
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.192022903
Short name T604
Test name
Test status
Simulation time 13170583201 ps
CPU time 271.58 seconds
Started Jul 30 05:35:54 PM PDT 24
Finished Jul 30 05:40:26 PM PDT 24
Peak memory 247300 kb
Host smart-a9c67c4b-d5af-4c29-a497-3af07919467a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192022903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.192022903
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.3885137619
Short name T230
Test name
Test status
Simulation time 1192466865 ps
CPU time 27.6 seconds
Started Jul 30 05:35:53 PM PDT 24
Finished Jul 30 05:36:21 PM PDT 24
Peak memory 255472 kb
Host smart-770ed5eb-2ffa-4c09-ad94-13959fa210e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38851
37619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.3885137619
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.1612180299
Short name T561
Test name
Test status
Simulation time 1387357429 ps
CPU time 53.18 seconds
Started Jul 30 05:35:50 PM PDT 24
Finished Jul 30 05:36:44 PM PDT 24
Peak memory 255900 kb
Host smart-c765bef7-34e2-4fd3-a4b2-93cfa77c2a4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16121
80299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.1612180299
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.4210626960
Short name T273
Test name
Test status
Simulation time 519343301 ps
CPU time 17.99 seconds
Started Jul 30 05:35:52 PM PDT 24
Finished Jul 30 05:36:10 PM PDT 24
Peak memory 255804 kb
Host smart-2a4b60b1-4fc6-4f40-b73f-8433eba33129
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42106
26960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.4210626960
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.644259724
Short name T669
Test name
Test status
Simulation time 1661491795 ps
CPU time 29.5 seconds
Started Jul 30 05:35:51 PM PDT 24
Finished Jul 30 05:36:20 PM PDT 24
Peak memory 256268 kb
Host smart-7a7b56ab-2fbc-4b8d-ac3c-b77c2640862f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64425
9724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.644259724
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.795424273
Short name T113
Test name
Test status
Simulation time 52227753782 ps
CPU time 1288.35 seconds
Started Jul 30 05:36:00 PM PDT 24
Finished Jul 30 05:57:29 PM PDT 24
Peak memory 288784 kb
Host smart-d15330d9-9592-4515-809e-bb4da7a70e5b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795424273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_han
dler_stress_all.795424273
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.3658357644
Short name T678
Test name
Test status
Simulation time 92027599604 ps
CPU time 1639.66 seconds
Started Jul 30 05:36:15 PM PDT 24
Finished Jul 30 06:03:35 PM PDT 24
Peak memory 272940 kb
Host smart-4bf76afa-e63e-47e1-bc4a-298a1ff34f4e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658357644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.3658357644
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.2855450137
Short name T125
Test name
Test status
Simulation time 157259992 ps
CPU time 18.35 seconds
Started Jul 30 05:36:14 PM PDT 24
Finished Jul 30 05:36:33 PM PDT 24
Peak memory 255852 kb
Host smart-8d20d428-13c0-4bac-8ef0-d05ecd448119
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28554
50137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.2855450137
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.2183751451
Short name T452
Test name
Test status
Simulation time 1601277361 ps
CPU time 26.53 seconds
Started Jul 30 05:36:09 PM PDT 24
Finished Jul 30 05:36:36 PM PDT 24
Peak memory 247784 kb
Host smart-710c139a-04fd-41dd-8b97-c787c4151a11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21837
51451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.2183751451
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.230282086
Short name T617
Test name
Test status
Simulation time 115491214370 ps
CPU time 2544.02 seconds
Started Jul 30 05:36:13 PM PDT 24
Finished Jul 30 06:18:38 PM PDT 24
Peak memory 288496 kb
Host smart-e25a4edb-314d-4fac-a906-223b5e262a83
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230282086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.230282086
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.489782895
Short name T478
Test name
Test status
Simulation time 36129726256 ps
CPU time 2002.18 seconds
Started Jul 30 05:36:13 PM PDT 24
Finished Jul 30 06:09:36 PM PDT 24
Peak memory 284224 kb
Host smart-639fc3d9-f752-4aac-a11c-9cd1a9f1360d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489782895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.489782895
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.1540752585
Short name T582
Test name
Test status
Simulation time 45416337514 ps
CPU time 358.19 seconds
Started Jul 30 05:36:13 PM PDT 24
Finished Jul 30 05:42:11 PM PDT 24
Peak memory 248340 kb
Host smart-512f4b68-a6ec-464a-8652-ae0e33e8cb91
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540752585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.1540752585
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.1660769058
Short name T593
Test name
Test status
Simulation time 72321049 ps
CPU time 8.76 seconds
Started Jul 30 05:36:05 PM PDT 24
Finished Jul 30 05:36:14 PM PDT 24
Peak memory 248240 kb
Host smart-54cc4eab-bd76-4589-bdc7-a0bb6cd0d5b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16607
69058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.1660769058
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.1174460453
Short name T666
Test name
Test status
Simulation time 825106610 ps
CPU time 12.86 seconds
Started Jul 30 05:36:08 PM PDT 24
Finished Jul 30 05:36:21 PM PDT 24
Peak memory 254872 kb
Host smart-a56c7ee1-3a6a-4d58-adbc-45becdcb64ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11744
60453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.1174460453
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.2283067500
Short name T129
Test name
Test status
Simulation time 1028655159 ps
CPU time 17.38 seconds
Started Jul 30 05:36:13 PM PDT 24
Finished Jul 30 05:36:30 PM PDT 24
Peak memory 254620 kb
Host smart-816682ec-8135-49cf-8c28-adb4a7bf54c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22830
67500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.2283067500
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.2327303106
Short name T605
Test name
Test status
Simulation time 341461078 ps
CPU time 11.94 seconds
Started Jul 30 05:36:05 PM PDT 24
Finished Jul 30 05:36:17 PM PDT 24
Peak memory 248268 kb
Host smart-1b9db0cd-1119-430d-9fed-cab91a381abe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23273
03106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.2327303106
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.184839516
Short name T199
Test name
Test status
Simulation time 2791518437 ps
CPU time 54.64 seconds
Started Jul 30 05:36:13 PM PDT 24
Finished Jul 30 05:37:08 PM PDT 24
Peak memory 256500 kb
Host smart-87f10543-771f-4d7c-b62f-34dbeeaac1a0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184839516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_han
dler_stress_all.184839516
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.2150653164
Short name T220
Test name
Test status
Simulation time 16648817 ps
CPU time 3.07 seconds
Started Jul 30 05:29:45 PM PDT 24
Finished Jul 30 05:29:48 PM PDT 24
Peak memory 248684 kb
Host smart-b01d58d4-3abc-4f6b-ac80-03c24b28bfc5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2150653164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.2150653164
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.3832941641
Short name T197
Test name
Test status
Simulation time 343679570465 ps
CPU time 3325.85 seconds
Started Jul 30 05:29:44 PM PDT 24
Finished Jul 30 06:25:11 PM PDT 24
Peak memory 289124 kb
Host smart-3eef864e-f1ca-4117-98b7-7ec5c73c1471
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832941641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.3832941641
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.2666476289
Short name T366
Test name
Test status
Simulation time 240162207 ps
CPU time 13.86 seconds
Started Jul 30 05:29:45 PM PDT 24
Finished Jul 30 05:29:59 PM PDT 24
Peak memory 248336 kb
Host smart-f405721b-a4bf-4cb3-9aaa-59c63cd98119
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2666476289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.2666476289
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.1264348318
Short name T533
Test name
Test status
Simulation time 3318770042 ps
CPU time 93.16 seconds
Started Jul 30 05:29:39 PM PDT 24
Finished Jul 30 05:31:12 PM PDT 24
Peak memory 256052 kb
Host smart-9dfd1129-785c-4910-b9cd-5ef0e98c87f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12643
48318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.1264348318
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.753761357
Short name T74
Test name
Test status
Simulation time 144390440 ps
CPU time 9.83 seconds
Started Jul 30 05:29:43 PM PDT 24
Finished Jul 30 05:29:53 PM PDT 24
Peak memory 248236 kb
Host smart-afd4b937-ae74-48a2-855f-e159d1d1bbe4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75376
1357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.753761357
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.723802651
Short name T316
Test name
Test status
Simulation time 96135742247 ps
CPU time 2929.44 seconds
Started Jul 30 05:29:44 PM PDT 24
Finished Jul 30 06:18:33 PM PDT 24
Peak memory 285788 kb
Host smart-4300f827-7bc1-4c14-aa50-9ccb16be878e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723802651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.723802651
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.2092217572
Short name T569
Test name
Test status
Simulation time 34824512315 ps
CPU time 622.58 seconds
Started Jul 30 05:29:44 PM PDT 24
Finished Jul 30 05:40:07 PM PDT 24
Peak memory 265836 kb
Host smart-d3cf52b1-9446-4752-bf3c-32e8dae35216
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092217572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.2092217572
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.2910614916
Short name T376
Test name
Test status
Simulation time 812134412 ps
CPU time 22.34 seconds
Started Jul 30 05:29:41 PM PDT 24
Finished Jul 30 05:30:03 PM PDT 24
Peak memory 248272 kb
Host smart-716376b2-5253-4987-a79c-b446d32fa6e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29106
14916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.2910614916
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.3643999453
Short name T438
Test name
Test status
Simulation time 130064979 ps
CPU time 6.55 seconds
Started Jul 30 05:29:39 PM PDT 24
Finished Jul 30 05:29:46 PM PDT 24
Peak memory 254720 kb
Host smart-55e5cdd4-e954-4c9c-8c58-c9dfdf65e65e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36439
99453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.3643999453
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.3575084507
Short name T579
Test name
Test status
Simulation time 1776486741 ps
CPU time 32.17 seconds
Started Jul 30 05:29:44 PM PDT 24
Finished Jul 30 05:30:16 PM PDT 24
Peak memory 255880 kb
Host smart-de604d8f-e62f-4b0b-8cea-6a3636ff7391
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35750
84507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.3575084507
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.4035923251
Short name T553
Test name
Test status
Simulation time 2513484107 ps
CPU time 43.01 seconds
Started Jul 30 05:29:38 PM PDT 24
Finished Jul 30 05:30:21 PM PDT 24
Peak memory 255908 kb
Host smart-7f21eef3-554a-4b7e-9779-84f888a02679
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40359
23251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.4035923251
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.2900147458
Short name T448
Test name
Test status
Simulation time 123472670042 ps
CPU time 3609.5 seconds
Started Jul 30 05:29:45 PM PDT 24
Finished Jul 30 06:29:55 PM PDT 24
Peak memory 297496 kb
Host smart-f4f2795e-e23e-478a-bd22-1b83ef3b6d9d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900147458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.2900147458
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.3590147953
Short name T218
Test name
Test status
Simulation time 15073581 ps
CPU time 2.42 seconds
Started Jul 30 05:29:48 PM PDT 24
Finished Jul 30 05:29:50 PM PDT 24
Peak memory 248572 kb
Host smart-1fd15e56-c51b-4323-9a30-19d850c73d4f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3590147953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.3590147953
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.1231843649
Short name T503
Test name
Test status
Simulation time 78097539782 ps
CPU time 1439.85 seconds
Started Jul 30 05:29:50 PM PDT 24
Finished Jul 30 05:53:51 PM PDT 24
Peak memory 272068 kb
Host smart-25f56d0b-cc8b-4da9-b725-a0ac6e81c743
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231843649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.1231843649
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.3163036078
Short name T667
Test name
Test status
Simulation time 305120500 ps
CPU time 9.02 seconds
Started Jul 30 05:29:49 PM PDT 24
Finished Jul 30 05:29:58 PM PDT 24
Peak memory 248332 kb
Host smart-8bedd16f-ccc6-4da3-ae47-dccd78d76319
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3163036078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.3163036078
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.882586383
Short name T689
Test name
Test status
Simulation time 5053558942 ps
CPU time 106.7 seconds
Started Jul 30 05:29:47 PM PDT 24
Finished Jul 30 05:31:34 PM PDT 24
Peak memory 256112 kb
Host smart-c3d6402e-5bc6-4821-9ab5-297c774b2f6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88258
6383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.882586383
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.1513173198
Short name T491
Test name
Test status
Simulation time 2458139106 ps
CPU time 32.45 seconds
Started Jul 30 05:29:48 PM PDT 24
Finished Jul 30 05:30:21 PM PDT 24
Peak memory 256064 kb
Host smart-a67fb603-0981-4538-b314-f52533e5cbdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15131
73198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.1513173198
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.2851601432
Short name T317
Test name
Test status
Simulation time 21811343148 ps
CPU time 979.6 seconds
Started Jul 30 05:29:47 PM PDT 24
Finished Jul 30 05:46:07 PM PDT 24
Peak memory 272548 kb
Host smart-f595e80b-61ee-47e5-a041-94344c3d0d5a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851601432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.2851601432
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.970780906
Short name T425
Test name
Test status
Simulation time 34345656187 ps
CPU time 1656.61 seconds
Started Jul 30 05:29:47 PM PDT 24
Finished Jul 30 05:57:24 PM PDT 24
Peak memory 288788 kb
Host smart-d557f143-8e98-4969-90b6-72fb38f47260
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970780906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.970780906
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.1233828750
Short name T431
Test name
Test status
Simulation time 8044209937 ps
CPU time 284.25 seconds
Started Jul 30 05:29:48 PM PDT 24
Finished Jul 30 05:34:33 PM PDT 24
Peak memory 248220 kb
Host smart-aabfc939-e9be-43ff-9c8a-626c6196eb96
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233828750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.1233828750
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.1104444933
Short name T402
Test name
Test status
Simulation time 2183929652 ps
CPU time 30.54 seconds
Started Jul 30 05:29:46 PM PDT 24
Finished Jul 30 05:30:16 PM PDT 24
Peak memory 255656 kb
Host smart-fcf4e0a8-e813-452c-8f7d-fd1c6bc490a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11044
44933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.1104444933
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.1844110392
Short name T696
Test name
Test status
Simulation time 4911026490 ps
CPU time 46.66 seconds
Started Jul 30 05:29:43 PM PDT 24
Finished Jul 30 05:30:30 PM PDT 24
Peak memory 256156 kb
Host smart-4dc3c64a-a7a9-4951-89f5-f006609fa871
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18441
10392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.1844110392
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.3386850253
Short name T575
Test name
Test status
Simulation time 120323042 ps
CPU time 4.6 seconds
Started Jul 30 05:29:47 PM PDT 24
Finished Jul 30 05:29:52 PM PDT 24
Peak memory 240080 kb
Host smart-4c32e198-c7f8-4b07-9e40-88979ae4f355
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33868
50253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.3386850253
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.1653726693
Short name T675
Test name
Test status
Simulation time 562886112 ps
CPU time 29.32 seconds
Started Jul 30 05:29:43 PM PDT 24
Finished Jul 30 05:30:13 PM PDT 24
Peak memory 255652 kb
Host smart-7eead2b2-0863-45b4-90cb-4523e78f9528
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16537
26693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.1653726693
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.1265847248
Short name T276
Test name
Test status
Simulation time 128986604596 ps
CPU time 3425.05 seconds
Started Jul 30 05:29:49 PM PDT 24
Finished Jul 30 06:26:54 PM PDT 24
Peak memory 289056 kb
Host smart-9b50a802-3ac0-4017-9c5f-7628b2c04f9d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265847248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.1265847248
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.145665135
Short name T213
Test name
Test status
Simulation time 38026238 ps
CPU time 2.25 seconds
Started Jul 30 05:29:53 PM PDT 24
Finished Jul 30 05:29:55 PM PDT 24
Peak memory 248644 kb
Host smart-cd6b556f-d76d-4624-ba79-40528d32b843
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=145665135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.145665135
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.2564759676
Short name T555
Test name
Test status
Simulation time 86606856598 ps
CPU time 1345.14 seconds
Started Jul 30 05:29:53 PM PDT 24
Finished Jul 30 05:52:18 PM PDT 24
Peak memory 272160 kb
Host smart-bb1f9003-5354-427f-8a0a-b24988b48f30
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564759676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.2564759676
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.3644549461
Short name T682
Test name
Test status
Simulation time 465530926 ps
CPU time 13.83 seconds
Started Jul 30 05:29:51 PM PDT 24
Finished Jul 30 05:30:05 PM PDT 24
Peak memory 248216 kb
Host smart-ea94535e-6ff0-4ce8-aa0b-0383b22c8498
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3644549461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.3644549461
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.3900624309
Short name T71
Test name
Test status
Simulation time 1290308659 ps
CPU time 21.7 seconds
Started Jul 30 05:29:55 PM PDT 24
Finished Jul 30 05:30:17 PM PDT 24
Peak memory 255372 kb
Host smart-36a73599-1c50-47a0-bc11-82256a5c5b48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39006
24309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.3900624309
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.330580558
Short name T378
Test name
Test status
Simulation time 24623560457 ps
CPU time 707.04 seconds
Started Jul 30 05:29:52 PM PDT 24
Finished Jul 30 05:41:39 PM PDT 24
Peak memory 272320 kb
Host smart-47584c7c-1807-4455-81e3-f6f3be18adf6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330580558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.330580558
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.2192710189
Short name T36
Test name
Test status
Simulation time 15523697943 ps
CPU time 170.83 seconds
Started Jul 30 05:29:55 PM PDT 24
Finished Jul 30 05:32:46 PM PDT 24
Peak memory 248312 kb
Host smart-4ceee440-93af-4554-bae1-56b4429c8695
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192710189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.2192710189
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.1778566642
Short name T557
Test name
Test status
Simulation time 4382988376 ps
CPU time 67.59 seconds
Started Jul 30 05:29:57 PM PDT 24
Finished Jul 30 05:31:05 PM PDT 24
Peak memory 255596 kb
Host smart-a7caa0d4-c322-42ef-b6ef-3753bc26e900
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17785
66642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.1778566642
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.3127618153
Short name T462
Test name
Test status
Simulation time 281930186 ps
CPU time 9.91 seconds
Started Jul 30 05:29:54 PM PDT 24
Finished Jul 30 05:30:04 PM PDT 24
Peak memory 247904 kb
Host smart-530dc0f0-d8e6-44f3-badc-178e0fe489c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31276
18153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.3127618153
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.878643287
Short name T393
Test name
Test status
Simulation time 157778143 ps
CPU time 4.45 seconds
Started Jul 30 05:29:50 PM PDT 24
Finished Jul 30 05:29:54 PM PDT 24
Peak memory 239672 kb
Host smart-978b55f1-9269-40e2-ba25-95b0f7b5d825
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87864
3287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.878643287
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.2009145543
Short name T449
Test name
Test status
Simulation time 2359504390 ps
CPU time 34.17 seconds
Started Jul 30 05:29:47 PM PDT 24
Finished Jul 30 05:30:21 PM PDT 24
Peak memory 255648 kb
Host smart-2dbe05d6-59b1-4caf-a89a-e848e2f09abb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20091
45543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.2009145543
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.1104091538
Short name T444
Test name
Test status
Simulation time 650285253 ps
CPU time 62.18 seconds
Started Jul 30 05:29:57 PM PDT 24
Finished Jul 30 05:30:59 PM PDT 24
Peak memory 256504 kb
Host smart-9578ad3c-e896-4476-a6ed-e9c94b374f65
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104091538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.1104091538
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.1238246515
Short name T42
Test name
Test status
Simulation time 59064311590 ps
CPU time 5635.62 seconds
Started Jul 30 05:29:58 PM PDT 24
Finished Jul 30 07:03:54 PM PDT 24
Peak memory 336908 kb
Host smart-b226e047-3f5a-424c-afd4-587704b7a827
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238246515 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.1238246515
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.2889418715
Short name T214
Test name
Test status
Simulation time 26437532 ps
CPU time 2.37 seconds
Started Jul 30 05:29:56 PM PDT 24
Finished Jul 30 05:29:59 PM PDT 24
Peak memory 248660 kb
Host smart-fa14b1cb-475b-4b97-a0e8-a06c87c12fee
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2889418715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.2889418715
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.2969563953
Short name T683
Test name
Test status
Simulation time 13585818454 ps
CPU time 1031.29 seconds
Started Jul 30 05:29:57 PM PDT 24
Finished Jul 30 05:47:09 PM PDT 24
Peak memory 281164 kb
Host smart-2426c73f-469e-4fb8-adad-4f773498b0b3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969563953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.2969563953
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.3770006005
Short name T541
Test name
Test status
Simulation time 1962250621 ps
CPU time 42.58 seconds
Started Jul 30 05:29:56 PM PDT 24
Finished Jul 30 05:30:39 PM PDT 24
Peak memory 248268 kb
Host smart-f7019390-81f7-4a26-81fe-75120771e0fb
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3770006005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.3770006005
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.3080197174
Short name T543
Test name
Test status
Simulation time 5411965706 ps
CPU time 168.31 seconds
Started Jul 30 05:29:57 PM PDT 24
Finished Jul 30 05:32:45 PM PDT 24
Peak memory 256404 kb
Host smart-9ad9ed1c-0254-4fcf-9072-6da6bb86e4b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30801
97174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.3080197174
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.2637897917
Short name T479
Test name
Test status
Simulation time 258478301 ps
CPU time 25.21 seconds
Started Jul 30 05:29:54 PM PDT 24
Finished Jul 30 05:30:20 PM PDT 24
Peak memory 248352 kb
Host smart-1516ed3c-ef92-40cf-aacb-10779b1986fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26378
97917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.2637897917
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.1575640887
Short name T318
Test name
Test status
Simulation time 90567446533 ps
CPU time 2438.03 seconds
Started Jul 30 05:29:57 PM PDT 24
Finished Jul 30 06:10:36 PM PDT 24
Peak memory 282656 kb
Host smart-c2107437-5248-47fa-9c86-24c9fa5e6e62
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575640887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.1575640887
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.3871484724
Short name T441
Test name
Test status
Simulation time 122801799082 ps
CPU time 1926.63 seconds
Started Jul 30 05:29:56 PM PDT 24
Finished Jul 30 06:02:03 PM PDT 24
Peak memory 288772 kb
Host smart-08a84ebc-b6e0-4a37-b18e-8169912bb8de
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871484724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.3871484724
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.1135203823
Short name T195
Test name
Test status
Simulation time 39596402905 ps
CPU time 341.57 seconds
Started Jul 30 05:29:55 PM PDT 24
Finished Jul 30 05:35:37 PM PDT 24
Peak memory 248276 kb
Host smart-71178b7e-5011-43d0-aff7-f498c738088f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135203823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.1135203823
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.4258124031
Short name T471
Test name
Test status
Simulation time 787799783 ps
CPU time 43.22 seconds
Started Jul 30 05:29:51 PM PDT 24
Finished Jul 30 05:30:34 PM PDT 24
Peak memory 255680 kb
Host smart-c86a1b2e-c0f2-4881-835c-dde8e1c7c0ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42581
24031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.4258124031
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.1895319239
Short name T482
Test name
Test status
Simulation time 4811433391 ps
CPU time 66.59 seconds
Started Jul 30 05:29:52 PM PDT 24
Finished Jul 30 05:30:58 PM PDT 24
Peak memory 248248 kb
Host smart-732c1dee-974d-45f0-8d0e-65c4412db69a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18953
19239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.1895319239
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.3990925527
Short name T233
Test name
Test status
Simulation time 532643055 ps
CPU time 29.57 seconds
Started Jul 30 05:29:56 PM PDT 24
Finished Jul 30 05:30:26 PM PDT 24
Peak memory 247480 kb
Host smart-130be96c-e0cf-4c05-9dd9-c5caaeaddbc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39909
25527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.3990925527
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.2051987172
Short name T620
Test name
Test status
Simulation time 1692627520 ps
CPU time 23.73 seconds
Started Jul 30 05:29:57 PM PDT 24
Finished Jul 30 05:30:20 PM PDT 24
Peak memory 256500 kb
Host smart-65bba31e-4f32-4d54-a4bb-27617df56d1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20519
87172 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.2051987172
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.1382707501
Short name T374
Test name
Test status
Simulation time 3138114319 ps
CPU time 33.87 seconds
Started Jul 30 05:29:56 PM PDT 24
Finished Jul 30 05:30:30 PM PDT 24
Peak memory 249380 kb
Host smart-cdaed1bf-30ee-4c21-842d-e7cb2a637ec5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382707501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.1382707501
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.4058724309
Short name T211
Test name
Test status
Simulation time 96441685 ps
CPU time 2.89 seconds
Started Jul 30 05:30:06 PM PDT 24
Finished Jul 30 05:30:09 PM PDT 24
Peak memory 248688 kb
Host smart-f26eb9c6-c543-418c-8ab0-a7500d771117
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4058724309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.4058724309
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.21018886
Short name T685
Test name
Test status
Simulation time 1169471531 ps
CPU time 14.03 seconds
Started Jul 30 05:30:04 PM PDT 24
Finished Jul 30 05:30:18 PM PDT 24
Peak memory 248436 kb
Host smart-8e420392-37b3-413d-94a5-a35692864b67
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=21018886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.21018886
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.163604722
Short name T360
Test name
Test status
Simulation time 295801162 ps
CPU time 15.25 seconds
Started Jul 30 05:30:03 PM PDT 24
Finished Jul 30 05:30:18 PM PDT 24
Peak memory 247944 kb
Host smart-57a88b71-b603-4925-8f25-700af854d9bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16360
4722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.163604722
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.760278505
Short name T406
Test name
Test status
Simulation time 93076477 ps
CPU time 4.85 seconds
Started Jul 30 05:30:00 PM PDT 24
Finished Jul 30 05:30:05 PM PDT 24
Peak memory 247900 kb
Host smart-a88db4cd-6c60-41b4-aff1-5074288be88a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76027
8505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.760278505
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.1203585866
Short name T234
Test name
Test status
Simulation time 138389225820 ps
CPU time 2083.95 seconds
Started Jul 30 05:30:03 PM PDT 24
Finished Jul 30 06:04:48 PM PDT 24
Peak memory 283624 kb
Host smart-c6f24384-b8d7-465e-883e-878b69886486
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203585866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.1203585866
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.1132860644
Short name T595
Test name
Test status
Simulation time 76894056350 ps
CPU time 1328.19 seconds
Started Jul 30 05:30:03 PM PDT 24
Finished Jul 30 05:52:12 PM PDT 24
Peak memory 272764 kb
Host smart-0a34dd1f-afac-40cf-9828-54ad1983a59a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132860644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.1132860644
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.682674695
Short name T305
Test name
Test status
Simulation time 31487513065 ps
CPU time 322.16 seconds
Started Jul 30 05:30:06 PM PDT 24
Finished Jul 30 05:35:28 PM PDT 24
Peak memory 247248 kb
Host smart-e84aa48d-df90-4a3c-99f4-c167279d6c08
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682674695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.682674695
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.1685405923
Short name T670
Test name
Test status
Simulation time 76069392 ps
CPU time 11.27 seconds
Started Jul 30 05:30:01 PM PDT 24
Finished Jul 30 05:30:13 PM PDT 24
Peak memory 248332 kb
Host smart-42cebcd2-7f85-408d-8ff7-a0ba0f83cd26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16854
05923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.1685405923
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.3883042785
Short name T2
Test name
Test status
Simulation time 4730550802 ps
CPU time 35.55 seconds
Started Jul 30 05:30:01 PM PDT 24
Finished Jul 30 05:30:37 PM PDT 24
Peak memory 255840 kb
Host smart-005b6122-f9c8-465f-bce1-db495e90f862
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38830
42785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.3883042785
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.900513137
Short name T348
Test name
Test status
Simulation time 108467629 ps
CPU time 7.46 seconds
Started Jul 30 05:30:05 PM PDT 24
Finished Jul 30 05:30:13 PM PDT 24
Peak memory 247876 kb
Host smart-802f95a5-4466-4951-abab-073bc6ad8223
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90051
3137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.900513137
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.3199911144
Short name T450
Test name
Test status
Simulation time 4526434386 ps
CPU time 27.68 seconds
Started Jul 30 05:30:01 PM PDT 24
Finished Jul 30 05:30:28 PM PDT 24
Peak memory 255640 kb
Host smart-7c2b32fa-8cac-4c0f-be4d-0ba83a8b0bf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31999
11144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.3199911144
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.2985882126
Short name T274
Test name
Test status
Simulation time 16168070653 ps
CPU time 1736.25 seconds
Started Jul 30 05:30:06 PM PDT 24
Finished Jul 30 05:59:02 PM PDT 24
Peak memory 300952 kb
Host smart-e4ad6f9e-f5ad-4904-9337-d7593e2e6805
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985882126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.2985882126
Directory /workspace/9.alert_handler_stress_all/latest
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