Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	65612	1			T19	15		T59	293		T41	4199
class_i[0x1]	66807	1			T18	6		T19	5		T26	51
class_i[0x2]	60551	1			T3	10		T21	5		T18	10
class_i[0x3]	76584	1			T41	116		T62	1		T29	3169

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	65107	1			T3	2		T18	9		T24	24
alert[0x1]	66242	1			T3	3		T18	5		T24	1
alert[0x2]	68104	1			T3	3		T21	4		T24	2
alert[0x3]	70101	1			T3	2		T21	1		T18	2

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

269290

1

T21

5

T18

10

T24

30

esc_ping_fail

264

1

T3

10

T18

6

T19

8

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	65029	1			T18	6		T24	24		T28	10
esc_integrity_fail	alert[0x1]	66167	1			T18	3		T24	1		T28	15
esc_integrity_fail	alert[0x2]	68046	1			T21	4		T24	2		T28	26
esc_integrity_fail	alert[0x3]	70048	1			T21	1		T18	1		T24	3
esc_ping_fail	alert[0x0]	78	1			T3	2		T18	3		T19	3
esc_ping_fail	alert[0x1]	75	1			T3	3		T18	2		T19	1
esc_ping_fail	alert[0x2]	58	1			T3	3		T19	3		T64	1
esc_ping_fail	alert[0x3]	53	1			T3	2		T18	1		T19	1

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	65555	1			T19	12		T59	293		T41	4199
esc_integrity_fail	class_i[0x1]	66729	1			T26	51		T41	104		T30	4688
esc_integrity_fail	class_i[0x2]	60480	1			T21	5		T18	10		T24	30
esc_integrity_fail	class_i[0x3]	76526	1			T41	116		T29	3169		T64	13
esc_ping_fail	class_i[0x0]	57	1			T19	3		T62	4		T299	2
esc_ping_fail	class_i[0x1]	78	1			T18	6		T19	5		T217	1
esc_ping_fail	class_i[0x2]	71	1			T3	10		T64	7		T217	1
esc_ping_fail	class_i[0x3]	58	1			T62	1		T217	1		T300	1