Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	707762413	0	0	623
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	707762413	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	707762413	707605749	0	0
tb.dut.CheckAccuCntDw	0	0	623	623	0	0
tb.dut.CheckEscCntDw	0	0	623	623	0	0
tb.dut.CheckNAlerts	0	0	623	623	0	0
tb.dut.CheckNClasses	0	0	623	623	0	0
tb.dut.CheckNEscSev	0	0	623	623	0	0
tb.dut.CrashdumpKnownO_A	0	0	707762413	707605749	0	0
tb.dut.EdnKnownO_A	0	0	707762413	707605749	0	0
tb.dut.EscPKnownO_A	0	0	707762413	707605749	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	707762413	70	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	707762413	70	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	707762413	70	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	707762413	70	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	707762413	70	0	0
tb.dut.IrqAKnownO_A	0	0	707762413	707605749	0	0
tb.dut.IrqBKnownO_A	0	0	707762413	707605749	0	0
tb.dut.IrqCKnownO_A	0	0	707762413	707605749	0	0
tb.dut.IrqDKnownO_A	0	0	707762413	707605749	0	0
tb.dut.TlAReadyKnownO_A	0	0	707762413	707605749	0	0
tb.dut.TlDValidKnownO_A	0	0	707762413	707605749	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	733314859	3386445	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	733314859	20622	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	733314859	20285	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	733314859	20279	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	733314859	20374	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	733314859	19904	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	733314859	20444	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	733314859	20356	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	733314859	20413	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	733314859	20375	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	733314859	20521	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	733314859	20498	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	733314859	20146	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	733314859	20392	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	733314859	20432	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	733314859	20385	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	733314859	20380	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	733314859	20088	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	733314859	20175	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	733314859	20269	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	733314859	20165	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	733314859	20606	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	733314859	20215	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	733314859	20194	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	733314859	20322	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	733314859	20563	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	733314859	20578	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	733314859	20285	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	733314859	20985	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	733314859	20235	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	733314859	20448	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	733314859	20415	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	733314859	20489	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	733314859	20328	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	733314859	20510	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	733314859	20349	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	733314859	20747	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	733314859	20670	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	733314859	20512	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	733314859	20423	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	733314859	20037	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	733314859	20131	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	733314859	20421	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	733314859	20705	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	733314859	20018	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	733314859	20295	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	733314859	20365	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	733314859	19969	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	733314859	20439	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	733314859	20255	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	733314859	20686	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	733314859	20125	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	733314859	20288	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	733314859	20444	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	733314859	20225	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	733314859	19891	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	733314859	20472	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	733314859	20731	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	733314859	20441	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	733314859	20080	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	733314859	19951	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	733314859	20509	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	733314859	20608	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	733314859	20963	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	733314859	20141	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	733314859	20031	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	733314859	20560	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	733314859	20480	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	733314859	20583	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	733314859	20219	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	733314859	41377	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	733314859	20532	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	733314859	20395	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	733314859	20481	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	733314859	20286	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	733314859	20605	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	733314859	19952	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	733314859	20458	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	733314859	20026	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	707762413	70	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	707762413	70	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	707762413	70	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	707762413	3315	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	707762413	218260	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	707762413	332007861	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	707762413	210	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	707762413	872	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	707762413	38	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	707762413	437	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	707636586	251040390	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	707762413	957	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	707762413	941	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	707762413	918	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	707762413	898	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	707762413	752	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	707762413	95152	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	707762413	643	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	707762413	69	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	707762413	1216	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	707762413	1006	0	0
tb.dut.gen_classes[0].u_esc_timer.EscStateOut_A	0	0	707635597	707567937	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	623	623	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	707762413	707605749	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	707762413	70	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	707762413	70	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	707762413	70	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	707762413	4007	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	707762413	233122	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	707762413	377867673	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	707762413	217	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	707762413	496	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	707762413	27	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	707762413	239	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	707636586	303479615	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	707762413	571	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	707762413	559	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	707762413	548	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	707762413	542	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	707762413	1318	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	707762413	163150	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	707762413	1227	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	707762413	63	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	707762413	1155	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	707762413	945	0	0
tb.dut.gen_classes[1].u_esc_timer.EscStateOut_A	0	0	707635597	707567937	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	623	623	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	707762413	707605749	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	707762413	70	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	707762413	70	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	707762413	70	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	707762413	3901	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	707762413	180047	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	707762413	438638954	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	707762413	169	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	707762413	491	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	707762413	28	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	707762413	227	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	707636586	353537474	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	707762413	564	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	707762413	555	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	707762413	550	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	707762413	534	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	707762413	1299	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	707762413	146704	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	707762413	1213	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	707762413	58	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	707762413	1102	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	707762413	892	0	0
tb.dut.gen_classes[2].u_esc_timer.EscStateOut_A	0	0	707635597	707567937	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	623	623	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	707762413	707605749	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	707762413	70	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	707762413	70	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	707762413	70	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	707762413	2272	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	707762413	222961	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	707762413	410542496	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	707762413	212	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	707762413	508	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	707762413	18	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	707762413	221	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	707636586	324251969	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	707762413	579	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	707762413	561	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	707762413	553	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	707762413	543	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	707762413	809	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	707762413	122268	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	707762413	725	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	707762413	65	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	707762413	1099	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	707762413	889	0	0
tb.dut.gen_classes[3].u_esc_timer.EscStateOut_A	0	0	707635597	707567937	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	623	623	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	707762413	707605749	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	733314859	142908896	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	733314859	732656369	0	0
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