Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.31	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	44	1	43	97.73

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_sig_index_cp	4	0	4	100.00	100	1	1	0
esc_sig_len_cp	11	0	11	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
len_per_esc_sig	44	1	43	97.73	100	1	1	0

Summary for Variable esc_sig_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_sig_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	174	1			T7	1		T16	1		T5	1
index[0x1]	183	1			T11	1		T17	1		T26	2
index[0x2]	176	1			T15	1		T8	1		T26	7
index[0x3]	165	1			T8	4		T26	5		T58	1

---

Summary for Variable esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for esc_sig_len_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lens_less_than_1000[0]	231	1			T11	1		T7	1		T26	6
lens_less_than_1000[1]	124	1			T16	1		T26	3		T59	1
lens_less_than_1000[2]	106	1			T15	1		T17	1		T26	3
lens_less_than_1000[3]	74	1			T8	4		T41	1		T61	1
lens_less_than_1000[4]	52	1			T8	1		T26	3		T59	1
lens_less_than_1000[5]	36	1			T269	1		T74	1		T48	4
lens_less_than_1000[6]	27	1			T59	1		T66	1		T47	1
lens_less_than_1000[7]	20	1			T26	1		T114	2		T74	1
lens_less_than_1000[8]	11	1			T5	1		T269	1		T234	1
lens_less_than_1000[9]	6	1			T270	1		T258	1		T271	1
len_2	11	1			T29	1		T44	1		T272	1

---

Summary for Cross len_per_esc_sig

Samples crossed: esc_sig_index_cp esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	44	1	43	97.73	1

Automatically Generated Cross Bins for len_per_esc_sig

Uncovered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	NUMBER	STATUS
[index[0x3]]	[lens_less_than_1000[8]]	0	1	1

Covered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	lens_less_than_1000[0]	62	1			T7	1		T26	1		T29	1
index[0x0]	lens_less_than_1000[1]	31	1			T16	1		T26	1		T31	1
index[0x0]	lens_less_than_1000[2]	31	1			T229	1		T47	1		T48	1
index[0x0]	lens_less_than_1000[3]	14	1			T273	1		T33	2		T86	1
index[0x0]	lens_less_than_1000[4]	12	1			T65	1		T104	1		T33	1
index[0x0]	lens_less_than_1000[5]	8	1			T48	4		T274	2		T275	1
index[0x0]	lens_less_than_1000[6]	2	1			T66	1		T81	1		-	-
index[0x0]	lens_less_than_1000[7]	4	1			T74	1		T276	1		T277	2
index[0x0]	lens_less_than_1000[8]	6	1			T5	1		T234	1		T278	1
index[0x0]	lens_less_than_1000[9]	2	1			T270	1		T271	1		-	-
index[0x0]	len_2	2	1			T279	1		T226	1		-	-
index[0x1]	lens_less_than_1000[0]	61	1			T11	1		T26	1		T29	2
index[0x1]	lens_less_than_1000[1]	41	1			T59	1		T44	1		T52	1
index[0x1]	lens_less_than_1000[2]	19	1			T17	1		T26	1		T47	1
index[0x1]	lens_less_than_1000[3]	17	1			T44	1		T74	1		T272	1
index[0x1]	lens_less_than_1000[4]	9	1			T59	1		T76	1		T280	1
index[0x1]	lens_less_than_1000[5]	11	1			T269	1		T74	1		T281	1
index[0x1]	lens_less_than_1000[6]	13	1			T55	5		T106	1		T175	1
index[0x1]	lens_less_than_1000[7]	5	1			T114	1		T45	1		T282	1
index[0x1]	lens_less_than_1000[8]	3	1			T74	1		T272	1		T283	1
index[0x1]	lens_less_than_1000[9]	1	1			T258	1		-	-		-	-
index[0x1]	len_2	3	1			T272	1		T78	1		T284	1
index[0x2]	lens_less_than_1000[0]	48	1			T26	3		T41	2		T29	1
index[0x2]	lens_less_than_1000[1]	31	1			T26	2		T79	1		T273	1
index[0x2]	lens_less_than_1000[2]	31	1			T15	1		T26	1		T59	1
index[0x2]	lens_less_than_1000[3]	23	1			T41	1		T61	1		T30	1
index[0x2]	lens_less_than_1000[4]	11	1			T8	1		T31	1		T285	1
index[0x2]	lens_less_than_1000[5]	9	1			T52	1		T286	1		T256	2
index[0x2]	lens_less_than_1000[6]	9	1			T59	1		T78	1		T94	1
index[0x2]	lens_less_than_1000[7]	6	1			T26	1		T114	1		T287	1
index[0x2]	lens_less_than_1000[8]	2	1			T269	1		T288	1		-	-
index[0x2]	lens_less_than_1000[9]	2	1			T289	1		T290	1		-	-
index[0x2]	len_2	4	1			T29	1		T44	1		T291	1
index[0x3]	lens_less_than_1000[0]	60	1			T26	1		T58	1		T99	1
index[0x3]	lens_less_than_1000[1]	21	1			T41	1		T243	1		T77	5
index[0x3]	lens_less_than_1000[2]	25	1			T26	1		T65	1		T68	1
index[0x3]	lens_less_than_1000[3]	20	1			T8	4		T74	1		T105	1
index[0x3]	lens_less_than_1000[4]	20	1			T26	3		T104	1		T113	1
index[0x3]	lens_less_than_1000[5]	8	1			T77	1		T292	1		T92	1
index[0x3]	lens_less_than_1000[6]	3	1			T47	1		T175	1		T293	1
index[0x3]	lens_less_than_1000[7]	5	1			T294	3		T295	1		T296	1
index[0x3]	lens_less_than_1000[9]	1	1			T289	1		-	-		-	-
index[0x3]	len_2	2	1			T266	1		T297	1		-	-