Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	2	38	95.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	2	38	95.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	69	1			T25	1		T26	3		T29	1
class_index[0x1]	63	1			T24	1		T26	1		T59	1
class_index[0x2]	58	1			T26	4		T59	1		T41	1
class_index[0x3]	65	1			T11	2		T5	1		T26	2

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	103	1			T11	1		T25	1		T5	1
intr_timeout_cnt[1]	44	1			T11	1		T26	3		T59	1
intr_timeout_cnt[2]	26	1			T26	2		T59	1		T74	1
intr_timeout_cnt[3]	15	1			T59	1		T49	1		T254	1
intr_timeout_cnt[4]	21	1			T65	2		T74	2		T46	1
intr_timeout_cnt[5]	7	1			T47	3		T78	1		T108	1
intr_timeout_cnt[6]	10	1			T41	1		T74	2		T255	2
intr_timeout_cnt[7]	14	1			T24	1		T66	2		T46	1
intr_timeout_cnt[8]	7	1			T66	1		T78	2		T106	1
intr_timeout_cnt[9]	8	1			T49	1		T77	1		T175	3

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	2	38	95.00	2

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[6]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[5]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	30	1			T25	1		T26	1		T31	1
class_index[0x0]	intr_timeout_cnt[1]	18	1			T29	1		T66	4		T32	1
class_index[0x0]	intr_timeout_cnt[2]	7	1			T26	2		T74	1		T49	1
class_index[0x0]	intr_timeout_cnt[3]	3	1			T49	1		T256	2		-	-
class_index[0x0]	intr_timeout_cnt[4]	6	1			T55	1		T257	1		T258	1
class_index[0x0]	intr_timeout_cnt[5]	1	1			T108	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[7]	1	1			T259	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[8]	1	1			T78	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[9]	2	1			T260	1		T261	1		-	-
class_index[0x1]	intr_timeout_cnt[0]	17	1			T41	1		T44	1		T53	1
class_index[0x1]	intr_timeout_cnt[1]	9	1			T26	1		T76	1		T74	1
class_index[0x1]	intr_timeout_cnt[2]	6	1			T59	1		T78	1		T92	1
class_index[0x1]	intr_timeout_cnt[3]	2	1			T254	1		T52	1		-	-
class_index[0x1]	intr_timeout_cnt[4]	9	1			T65	1		T74	1		T46	1
class_index[0x1]	intr_timeout_cnt[5]	4	1			T47	3		T78	1		-	-
class_index[0x1]	intr_timeout_cnt[6]	5	1			T74	2		T255	1		T262	1
class_index[0x1]	intr_timeout_cnt[7]	6	1			T24	1		T66	2		T187	1
class_index[0x1]	intr_timeout_cnt[8]	1	1			T106	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[9]	4	1			T77	1		T175	3		-	-
class_index[0x2]	intr_timeout_cnt[0]	27	1			T26	4		T41	1		T67	1
class_index[0x2]	intr_timeout_cnt[1]	7	1			T59	1		T49	1		T103	1
class_index[0x2]	intr_timeout_cnt[2]	9	1			T49	1		T263	1		T52	1
class_index[0x2]	intr_timeout_cnt[3]	2	1			T255	1		T239	1		-	-
class_index[0x2]	intr_timeout_cnt[4]	4	1			T65	1		T103	1		T264	1
class_index[0x2]	intr_timeout_cnt[5]	2	1			T188	1		T265	1		-	-
class_index[0x2]	intr_timeout_cnt[6]	1	1			T55	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[7]	2	1			T46	1		T266	1		-	-
class_index[0x2]	intr_timeout_cnt[8]	3	1			T66	1		T78	1		T185	1
class_index[0x2]	intr_timeout_cnt[9]	1	1			T49	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[0]	29	1			T11	1		T5	1		T29	1
class_index[0x3]	intr_timeout_cnt[1]	10	1			T11	1		T26	2		T73	1
class_index[0x3]	intr_timeout_cnt[2]	4	1			T93	1		T267	1		T239	1
class_index[0x3]	intr_timeout_cnt[3]	8	1			T59	1		T255	1		T268	1
class_index[0x3]	intr_timeout_cnt[4]	2	1			T74	1		T49	1		-	-
class_index[0x3]	intr_timeout_cnt[6]	4	1			T41	1		T255	1		T252	1
class_index[0x3]	intr_timeout_cnt[7]	5	1			T52	1		T264	1		T238	1
class_index[0x3]	intr_timeout_cnt[8]	2	1			T239	1		T187	1		-	-
class_index[0x3]	intr_timeout_cnt[9]	1	1			T262	1		-	-		-	-