Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	364958	1			T1	55		T2	91		T3	53
all_values[1]	364958	1			T1	55		T2	91		T3	53
all_values[2]	364958	1			T1	55		T2	91		T3	53
all_values[3]	364958	1			T1	55		T2	91		T3	53

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

726867

1

T1

120

T2

177

T11

42

auto[1]

732965

1

T1

100

T2

187

T3

212

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

862750

1

T1

113

T2

189

T3

186

auto[1]

597082

1

T1

107

T2

175

T3

26

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	103201	1			T1	14		T2	22		T11	2
all_values[0]	auto[0]	auto[1]	78568	1			T1	14		T2	21		T11	2
all_values[0]	auto[1]	auto[0]	104447	1			T1	14		T2	27		T3	53
all_values[0]	auto[1]	auto[1]	78742	1			T1	13		T2	21		T11	9
all_values[1]	auto[0]	auto[0]	109278	1			T1	16		T2	21		T11	6
all_values[1]	auto[0]	auto[1]	72595	1			T1	13		T2	21		T11	5
all_values[1]	auto[1]	auto[0]	110537	1			T1	13		T2	25		T3	53
all_values[1]	auto[1]	auto[1]	72548	1			T1	13		T2	24		T11	6
all_values[2]	auto[0]	auto[0]	107695	1			T1	16		T2	25		T11	6
all_values[2]	auto[0]	auto[1]	74135	1			T1	16		T2	23		T11	5
all_values[2]	auto[1]	auto[0]	109292	1			T1	12		T2	22		T3	27
all_values[2]	auto[1]	auto[1]	73836	1			T1	11		T2	21		T3	26
all_values[3]	auto[0]	auto[0]	108277	1			T1	16		T2	23		T11	8
all_values[3]	auto[0]	auto[1]	73118	1			T1	15		T2	21		T11	8
all_values[3]	auto[1]	auto[0]	110023	1			T1	12		T2	24		T3	53
all_values[3]	auto[1]	auto[1]	73540	1			T1	12		T2	23		T11	3