Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	364958	1			T1	55		T2	91		T3	53
all_pins[1]	364958	1			T1	55		T2	91		T3	53
all_pins[2]	364958	1			T1	55		T2	91		T3	53
all_pins[3]	364958	1			T1	55		T2	91		T3	53

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1161166	1			T1	171		T2	275		T3	186
values[0x1]	298666	1			T1	49		T2	89		T3	26
transitions[0x0=>0x1]	198129	1			T1	31		T2	51		T3	26
transitions[0x1=>0x0]	198373	1			T1	32		T2	51		T3	26

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	286216	1			T1	42		T2	70		T3	53
all_pins[0]	values[0x1]	78742	1			T1	13		T2	21		T11	9
all_pins[0]	transitions[0x0=>0x1]	78037	1			T1	12		T2	21		T11	9
all_pins[0]	transitions[0x1=>0x0]	73079	1			T1	12		T2	23		T11	3
all_pins[1]	values[0x0]	292410	1			T1	42		T2	67		T3	53
all_pins[1]	values[0x1]	72548	1			T1	13		T2	24		T11	6
all_pins[1]	transitions[0x0=>0x1]	39325	1			T1	6		T2	11		T11	1
all_pins[1]	transitions[0x1=>0x0]	45519	1			T1	6		T2	8		T11	4
all_pins[2]	values[0x0]	291122	1			T1	44		T2	70		T3	27
all_pins[2]	values[0x1]	73836	1			T1	11		T2	21		T3	26
all_pins[2]	transitions[0x0=>0x1]	40768	1			T1	6		T2	10		T3	26
all_pins[2]	transitions[0x1=>0x0]	39480	1			T1	8		T2	13		T11	2
all_pins[3]	values[0x0]	291418	1			T1	43		T2	68		T3	53
all_pins[3]	values[0x1]	73540	1			T1	12		T2	23		T11	3
all_pins[3]	transitions[0x0=>0x1]	39999	1			T1	7		T2	9		T11	1
all_pins[3]	transitions[0x1=>0x0]	40295	1			T1	6		T2	7		T3	26