Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	85555	1			T7	404		T8	1000		T21	230
accum_cnt_1000	245982	1			T7	740		T15	47		T8	1111
accum_cnt_100	27364	1			T2	15		T7	36		T12	15
accum_cnt_50	73410	1			T2	21		T11	12		T7	32
accum_cnt_10	172638	1			T1	54		T2	9		T11	43
accum_cnt_0	419499	1			T1	54		T2	135		T3	156

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	268852	1			T1	27		T2	45		T3	39
class_index[0x1]	268852	1			T1	27		T2	45		T3	39
class_index[0x2]	268852	1			T1	27		T2	45		T3	39
class_index[0x3]	268852	1			T1	27		T2	45		T3	39

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	24309	1			T7	404		T8	575		T21	230
class_index[0x0]	accum_cnt_1000	71042	1			T7	740		T8	730		T17	565
class_index[0x0]	accum_cnt_100	9649	1			T2	15		T7	36		T12	15
class_index[0x0]	accum_cnt_50	21392	1			T2	21		T7	32		T12	17
class_index[0x0]	accum_cnt_10	41549	1			T1	1		T2	8		T7	13
class_index[0x0]	accum_cnt_0	90278	1			T1	26		T2	1		T3	39
class_index[0x1]	accum_cnt_2000	22892	1			T8	425		T22	674		T6	142
class_index[0x1]	accum_cnt_1000	61541	1			T8	381		T16	8		T22	596
class_index[0x1]	accum_cnt_100	6378	1			T8	19		T16	19		T22	32
class_index[0x1]	accum_cnt_50	14962	1			T11	2		T8	16		T16	13
class_index[0x1]	accum_cnt_10	43709	1			T2	1		T11	17		T7	1229
class_index[0x1]	accum_cnt_0	102589	1			T1	27		T2	44		T3	39
class_index[0x2]	accum_cnt_2000	17681	1			T29	53		T65	527		T68	316
class_index[0x2]	accum_cnt_1000	57700	1			T15	47		T26	598		T59	104
class_index[0x2]	accum_cnt_100	5965	1			T15	16		T6	43		T26	66
class_index[0x2]	accum_cnt_50	18881	1			T15	14		T5	2		T6	22
class_index[0x2]	accum_cnt_10	37162	1			T1	27		T11	17		T7	2
class_index[0x2]	accum_cnt_0	121463	1			T2	45		T3	39		T11	5
class_index[0x3]	accum_cnt_2000	20673	1			T22	438		T29	235		T30	422
class_index[0x3]	accum_cnt_1000	55699	1			T17	460		T22	414		T5	3
class_index[0x3]	accum_cnt_100	5372	1			T16	17		T17	136		T22	24
class_index[0x3]	accum_cnt_50	18175	1			T11	10		T14	1		T16	22
class_index[0x3]	accum_cnt_10	50218	1			T1	26		T11	9		T14	5
class_index[0x3]	accum_cnt_0	105169	1			T1	1		T2	45		T3	39