Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	4728	1			T21	15		T6	338		T64	1
alert[0x1]	4759	1			T21	30		T18	1		T19	1
alert[0x2]	6388	1			T6	3136		T59	3		T62	2
alert[0x3]	13039	1			T19	1		T62	1		T299	1
alert[0x4]	4743	1			T3	1		T18	1		T28	2
alert[0x5]	2735	1			T59	13		T29	27		T44	6
alert[0x6]	4259	1			T21	86		T18	1		T19	1
alert[0x7]	6483	1			T21	43		T26	1		T62	1
alert[0x8]	7777	1			T3	1		T21	90		T6	99
alert[0x9]	5001	1			T21	3		T19	1		T6	667
alert[0xa]	7072	1			T3	1		T21	878		T231	1
alert[0xb]	8442	1			T28	21		T6	111		T59	2
alert[0xc]	6124	1			T3	1		T6	157		T59	1
alert[0xd]	12407	1			T21	216		T19	1		T6	63
alert[0xe]	7108	1			T6	974		T26	5		T29	2
alert[0xf]	8856	1			T21	132		T6	363		T29	48
alert[0x10]	10589	1			T21	32		T28	1		T19	2
alert[0x11]	6924	1			T101	5		T300	1		T44	23
alert[0x12]	7515	1			T21	3		T19	1		T26	1
alert[0x13]	7519	1			T19	1		T59	4		T29	7
alert[0x14]	7151	1			T3	1		T21	76		T29	6
alert[0x15]	10256	1			T21	237		T70	7		T101	6
alert[0x16]	3863	1			T6	117		T26	88		T231	1
alert[0x17]	8682	1			T3	1		T41	1		T44	5
alert[0x18]	4384	1			T21	45		T19	1		T6	226
alert[0x19]	7993	1			T21	72		T18	1		T59	15
alert[0x1a]	7090	1			T21	224		T26	7		T41	2
alert[0x1b]	3077	1			T3	1		T21	95		T6	250
alert[0x1c]	8377	1			T29	4		T44	11		T113	1
alert[0x1d]	6165	1			T21	10		T18	1		T26	7
alert[0x1e]	4168	1			T63	2		T65	12		T113	2
alert[0x1f]	4577	1			T28	1		T6	72		T58	1
alert[0x20]	9041	1			T3	1		T21	30		T6	288
alert[0x21]	10147	1			T3	1		T18	2		T29	30
alert[0x22]	6603	1			T6	240		T59	4		T70	44
alert[0x23]	7333	1			T21	20		T26	3		T59	2
alert[0x24]	5418	1			T3	1		T18	1		T59	10
alert[0x25]	3547	1			T21	19		T26	1		T44	4
alert[0x26]	7078	1			T21	45		T18	1		T6	335
alert[0x27]	5840	1			T59	15		T29	78		T64	1
alert[0x28]	8651	1			T17	1		T21	9		T104	1
alert[0x29]	9544	1			T21	15		T28	1		T6	357
alert[0x2a]	10926	1			T21	243		T19	1		T6	516
alert[0x2b]	8113	1			T21	93		T59	21		T29	493
alert[0x2c]	10799	1			T3	1		T21	73		T28	1
alert[0x2d]	18470	1			T3	2		T26	29		T70	6
alert[0x2e]	2330	1			T21	55		T19	1		T6	37
alert[0x2f]	5934	1			T28	25		T26	321		T59	2
alert[0x30]	1923	1			T18	2		T19	1		T59	14
alert[0x31]	16288	1			T21	49		T26	17		T41	16
alert[0x32]	5564	1			T21	23		T18	1		T6	231
alert[0x33]	7329	1			T41	1		T29	28		T64	1
alert[0x34]	2099	1			T28	24		T6	286		T29	22
alert[0x35]	4822	1			T19	1		T66	1		T76	5
alert[0x36]	8739	1			T21	191		T6	1		T26	1
alert[0x37]	3110	1			T19	2		T6	32		T26	1
alert[0x38]	9101	1			T6	2869		T59	4		T41	7
alert[0x39]	4839	1			T21	15		T6	320		T62	1
alert[0x3a]	4352	1			T3	2		T6	236		T41	21
alert[0x3b]	4005	1			T21	109		T65	3		T113	1
alert[0x3c]	4551	1			T21	5		T6	3		T29	98
alert[0x3d]	7122	1			T18	1		T28	13		T29	4
alert[0x3e]	4874	1			T3	1		T6	27		T29	23
alert[0x3f]	9266	1			T18	1		T6	121		T29	7
alert[0x40]	4220	1			T21	22		T28	3		T41	1

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	79210	1			T21	3289		T19	2		T6	70
class_i[0x1]	129422	1			T19	2		T6	12787		T26	406
class_i[0x2]	139038	1			T3	16		T21	14		T19	1
class_i[0x3]	102559	1			T17	1		T18	14		T28	92

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

449602

1

T21

3303

T28

92

T6

12890

alert_ping_fail

627

1

T3

16

T17

1

T18

14

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	4719	1			T21	15		T6	338		T74	13
alert_integrity_fail	alert[0x1]	4750	1			T21	30		T6	173		T66	2
alert_integrity_fail	alert[0x2]	6380	1			T6	3136		T59	3		T66	2
alert_integrity_fail	alert[0x3]	13027	1			T32	4		T74	2		T33	455
alert_integrity_fail	alert[0x4]	4735	1			T28	2		T6	6		T59	19
alert_integrity_fail	alert[0x5]	2729	1			T59	13		T29	27		T44	6
alert_integrity_fail	alert[0x6]	4249	1			T21	86		T6	239		T26	9
alert_integrity_fail	alert[0x7]	6477	1			T21	43		T26	1		T29	12
alert_integrity_fail	alert[0x8]	7769	1			T21	90		T6	99		T59	1
alert_integrity_fail	alert[0x9]	4992	1			T21	3		T6	667		T59	1
alert_integrity_fail	alert[0xa]	7062	1			T21	878		T33	95		T301	415
alert_integrity_fail	alert[0xb]	8431	1			T28	21		T6	111		T59	2
alert_integrity_fail	alert[0xc]	6116	1			T6	157		T59	1		T29	10
alert_integrity_fail	alert[0xd]	12397	1			T21	216		T6	63		T29	135
alert_integrity_fail	alert[0xe]	7092	1			T6	974		T26	5		T29	2
alert_integrity_fail	alert[0xf]	8849	1			T21	132		T6	363		T29	48
alert_integrity_fail	alert[0x10]	10579	1			T21	32		T28	1		T29	57
alert_integrity_fail	alert[0x11]	6916	1			T101	5		T44	23		T32	11
alert_integrity_fail	alert[0x12]	7500	1			T21	3		T26	1		T41	11
alert_integrity_fail	alert[0x13]	7510	1			T59	4		T29	7		T65	1
alert_integrity_fail	alert[0x14]	7141	1			T21	76		T29	6		T70	11
alert_integrity_fail	alert[0x15]	10245	1			T21	237		T70	7		T101	6
alert_integrity_fail	alert[0x16]	3856	1			T6	117		T26	88		T44	30
alert_integrity_fail	alert[0x17]	8676	1			T41	1		T44	5		T73	3
alert_integrity_fail	alert[0x18]	4375	1			T21	45		T6	226		T26	3
alert_integrity_fail	alert[0x19]	7986	1			T21	72		T59	15		T29	16
alert_integrity_fail	alert[0x1a]	7079	1			T21	224		T26	7		T41	2
alert_integrity_fail	alert[0x1b]	3068	1			T21	95		T6	250		T41	3
alert_integrity_fail	alert[0x1c]	8369	1			T29	4		T44	11		T33	163
alert_integrity_fail	alert[0x1d]	6155	1			T21	10		T26	7		T29	20
alert_integrity_fail	alert[0x1e]	4163	1			T63	2		T65	12		T32	82
alert_integrity_fail	alert[0x1f]	4559	1			T28	1		T6	72		T41	1
alert_integrity_fail	alert[0x20]	9032	1			T21	30		T6	288		T29	1
alert_integrity_fail	alert[0x21]	10133	1			T29	30		T66	1		T70	125
alert_integrity_fail	alert[0x22]	6594	1			T6	240		T59	4		T70	44
alert_integrity_fail	alert[0x23]	7325	1			T21	20		T26	3		T59	2
alert_integrity_fail	alert[0x24]	5408	1			T59	10		T70	78		T101	1
alert_integrity_fail	alert[0x25]	3541	1			T21	19		T26	1		T44	4
alert_integrity_fail	alert[0x26]	7063	1			T21	45		T6	335		T26	3
alert_integrity_fail	alert[0x27]	5833	1			T59	15		T29	78		T70	16
alert_integrity_fail	alert[0x28]	8638	1			T21	9		T73	419		T32	4
alert_integrity_fail	alert[0x29]	9536	1			T21	15		T28	1		T6	357
alert_integrity_fail	alert[0x2a]	10902	1			T21	243		T6	516		T29	20
alert_integrity_fail	alert[0x2b]	8102	1			T21	93		T59	21		T29	493
alert_integrity_fail	alert[0x2c]	10784	1			T21	73		T28	1		T29	4
alert_integrity_fail	alert[0x2d]	18463	1			T26	29		T70	6		T73	136
alert_integrity_fail	alert[0x2e]	2313	1			T21	55		T6	37		T63	2
alert_integrity_fail	alert[0x2f]	5920	1			T28	25		T26	321		T59	2
alert_integrity_fail	alert[0x30]	1913	1			T59	14		T29	10		T44	124
alert_integrity_fail	alert[0x31]	16279	1			T21	49		T26	17		T41	16
alert_integrity_fail	alert[0x32]	5554	1			T21	23		T6	231		T29	10
alert_integrity_fail	alert[0x33]	7323	1			T41	1		T29	28		T66	4
alert_integrity_fail	alert[0x34]	2091	1			T28	24		T6	286		T29	22
alert_integrity_fail	alert[0x35]	4815	1			T66	1		T76	5		T44	20
alert_integrity_fail	alert[0x36]	8728	1			T21	191		T6	1		T26	1
alert_integrity_fail	alert[0x37]	3102	1			T6	32		T26	1		T101	9
alert_integrity_fail	alert[0x38]	9090	1			T6	2869		T59	4		T41	7
alert_integrity_fail	alert[0x39]	4828	1			T21	15		T6	320		T44	240
alert_integrity_fail	alert[0x3a]	4346	1			T6	236		T41	21		T70	37
alert_integrity_fail	alert[0x3b]	3996	1			T21	109		T65	3		T230	1
alert_integrity_fail	alert[0x3c]	4541	1			T21	5		T6	3		T29	98
alert_integrity_fail	alert[0x3d]	7113	1			T28	13		T29	4		T70	35
alert_integrity_fail	alert[0x3e]	4865	1			T6	27		T29	23		T65	1
alert_integrity_fail	alert[0x3f]	9263	1			T6	121		T29	7		T33	1132
alert_integrity_fail	alert[0x40]	4217	1			T21	22		T28	3		T41	1
alert_ping_fail	alert[0x0]	9	1			T64	1		T217	1		T302	1
alert_ping_fail	alert[0x1]	9	1			T18	1		T19	1		T302	1
alert_ping_fail	alert[0x2]	8	1			T62	2		T303	1		T304	1
alert_ping_fail	alert[0x3]	12	1			T19	1		T62	1		T299	1
alert_ping_fail	alert[0x4]	8	1			T3	1		T18	1		T305	1
alert_ping_fail	alert[0x5]	6	1			T113	1		T306	1		T305	2
alert_ping_fail	alert[0x6]	10	1			T18	1		T19	1		T231	1
alert_ping_fail	alert[0x7]	6	1			T62	1		T307	1		T308	1
alert_ping_fail	alert[0x8]	8	1			T3	1		T299	1		T224	1
alert_ping_fail	alert[0x9]	9	1			T19	1		T62	1		T305	1
alert_ping_fail	alert[0xa]	10	1			T3	1		T231	1		T309	1
alert_ping_fail	alert[0xb]	11	1			T64	1		T300	1		T310	1
alert_ping_fail	alert[0xc]	8	1			T3	1		T64	2		T311	1
alert_ping_fail	alert[0xd]	10	1			T19	1		T64	2		T302	1
alert_ping_fail	alert[0xe]	16	1			T300	1		T113	1		T236	1
alert_ping_fail	alert[0xf]	7	1			T113	1		T312	1		T311	1
alert_ping_fail	alert[0x10]	10	1			T19	2		T310	2		T313	1
alert_ping_fail	alert[0x11]	8	1			T300	1		T303	1		T304	2
alert_ping_fail	alert[0x12]	15	1			T19	1		T62	1		T64	1
alert_ping_fail	alert[0x13]	9	1			T19	1		T104	1		T113	1
alert_ping_fail	alert[0x14]	10	1			T3	1		T298	1		T80	1
alert_ping_fail	alert[0x15]	11	1			T113	1		T236	1		T314	1
alert_ping_fail	alert[0x16]	7	1			T231	1		T303	1		T312	1
alert_ping_fail	alert[0x17]	6	1			T3	1		T113	1		T218	1
alert_ping_fail	alert[0x18]	9	1			T19	1		T62	1		T307	1
alert_ping_fail	alert[0x19]	7	1			T18	1		T310	1		T304	1
alert_ping_fail	alert[0x1a]	11	1			T64	1		T113	1		T302	1
alert_ping_fail	alert[0x1b]	9	1			T3	1		T104	1		T113	1
alert_ping_fail	alert[0x1c]	8	1			T113	1		T305	1		T303	1
alert_ping_fail	alert[0x1d]	10	1			T18	1		T64	1		T306	1
alert_ping_fail	alert[0x1e]	5	1			T113	2		T303	1		T315	1
alert_ping_fail	alert[0x1f]	18	1			T58	1		T233	2		T304	1
alert_ping_fail	alert[0x20]	9	1			T3	1		T113	1		T309	1
alert_ping_fail	alert[0x21]	14	1			T3	1		T18	2		T104	1
alert_ping_fail	alert[0x22]	9	1			T231	1		T316	1		T310	1
alert_ping_fail	alert[0x23]	8	1			T62	1		T310	1		T303	1
alert_ping_fail	alert[0x24]	10	1			T3	1		T18	1		T299	1
alert_ping_fail	alert[0x25]	6	1			T315	1		T317	1		T318	1
alert_ping_fail	alert[0x26]	15	1			T18	1		T217	1		T299	1
alert_ping_fail	alert[0x27]	7	1			T64	1		T310	1		T312	1
alert_ping_fail	alert[0x28]	13	1			T17	1		T104	1		T305	1
alert_ping_fail	alert[0x29]	8	1			T217	1		T299	1		T303	2
alert_ping_fail	alert[0x2a]	24	1			T19	1		T99	3		T217	2
alert_ping_fail	alert[0x2b]	11	1			T310	1		T303	1		T307	2
alert_ping_fail	alert[0x2c]	15	1			T3	1		T19	1		T319	1
alert_ping_fail	alert[0x2d]	7	1			T3	2		T233	1		T304	1
alert_ping_fail	alert[0x2e]	17	1			T19	1		T64	1		T233	2
alert_ping_fail	alert[0x2f]	14	1			T64	1		T236	1		T315	1
alert_ping_fail	alert[0x30]	10	1			T18	2		T19	1		T64	1
alert_ping_fail	alert[0x31]	9	1			T217	1		T305	1		T218	1
alert_ping_fail	alert[0x32]	10	1			T18	1		T299	1		T113	1
alert_ping_fail	alert[0x33]	6	1			T64	1		T317	1		T318	1
alert_ping_fail	alert[0x34]	8	1			T64	1		T303	1		T218	1
alert_ping_fail	alert[0x35]	7	1			T19	1		T113	2		T320	1
alert_ping_fail	alert[0x36]	11	1			T62	1		T113	1		T315	1
alert_ping_fail	alert[0x37]	8	1			T19	2		T64	1		T310	1
alert_ping_fail	alert[0x38]	11	1			T300	2		T304	3		T320	2
alert_ping_fail	alert[0x39]	11	1			T62	1		T113	2		T315	1
alert_ping_fail	alert[0x3a]	6	1			T3	2		T321	1		T322	1
alert_ping_fail	alert[0x3b]	9	1			T113	1		T236	1		T305	1
alert_ping_fail	alert[0x3c]	10	1			T303	1		T223	1		T312	1
alert_ping_fail	alert[0x3d]	9	1			T18	1		T303	1		T307	1
alert_ping_fail	alert[0x3e]	9	1			T3	1		T64	1		T302	1
alert_ping_fail	alert[0x3f]	3	1			T18	1		T318	1		T323	1
alert_ping_fail	alert[0x40]	3	1			T236	1		T305	1		T324	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	79092	1			T21	3289		T6	70		T59	66
alert_integrity_fail	class_i[0x1]	129215	1			T6	12787		T26	406		T41	76
alert_integrity_fail	class_i[0x2]	138910	1			T21	14		T26	84		T59	249
alert_integrity_fail	class_i[0x3]	102385	1			T28	92		T6	33		T26	7
alert_ping_fail	class_i[0x0]	118	1			T19	2		T62	10		T217	1
alert_ping_fail	class_i[0x1]	207	1			T19	2		T64	2		T99	3
alert_ping_fail	class_i[0x2]	128	1			T3	16		T19	1		T64	13
alert_ping_fail	class_i[0x3]	174	1			T17	1		T18	14		T19	12