Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.26	99.99	98.69	97.09	100.00	100.00	99.38	99.68

Total test records in report: 828

T772	/workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.122301754	Jul 31 05:20:50 PM PDT 24	Jul 31 05:21:08 PM PDT 24	1353473359 ps
T773	/workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.3366185473	Jul 31 05:20:41 PM PDT 24	Jul 31 05:20:53 PM PDT 24	327541057 ps
T130	/workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.2606425262	Jul 31 05:20:43 PM PDT 24	Jul 31 05:39:37 PM PDT 24	30640712084 ps
T774	/workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.594195889	Jul 31 05:20:46 PM PDT 24	Jul 31 05:20:51 PM PDT 24	120445997 ps
T775	/workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.2715201698	Jul 31 05:20:47 PM PDT 24	Jul 31 05:20:57 PM PDT 24	307395293 ps
T776	/workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.4053635019	Jul 31 05:21:25 PM PDT 24	Jul 31 05:21:30 PM PDT 24	29817168 ps
T777	/workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.422776727	Jul 31 05:20:48 PM PDT 24	Jul 31 05:20:53 PM PDT 24	40438624 ps
T778	/workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.1214451147	Jul 31 05:20:46 PM PDT 24	Jul 31 05:21:09 PM PDT 24	173769276 ps
T779	/workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.1185333784	Jul 31 05:20:50 PM PDT 24	Jul 31 05:20:54 PM PDT 24	29967286 ps
T780	/workspace/coverage/cover_reg_top/18.alert_handler_intr_test.2230300949	Jul 31 05:21:14 PM PDT 24	Jul 31 05:21:17 PM PDT 24	23187886 ps
T781	/workspace/coverage/cover_reg_top/44.alert_handler_intr_test.242012431	Jul 31 05:21:02 PM PDT 24	Jul 31 05:21:04 PM PDT 24	8241015 ps
T136	/workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.4273795939	Jul 31 05:20:46 PM PDT 24	Jul 31 05:30:40 PM PDT 24	27846437098 ps
T145	/workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.1443858427	Jul 31 05:21:06 PM PDT 24	Jul 31 05:23:41 PM PDT 24	18203021994 ps
T147	/workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.2391732510	Jul 31 05:20:51 PM PDT 24	Jul 31 05:24:07 PM PDT 24	8968385053 ps
T127	/workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.779904251	Jul 31 05:21:01 PM PDT 24	Jul 31 05:41:08 PM PDT 24	16458031275 ps
T782	/workspace/coverage/cover_reg_top/1.alert_handler_intr_test.1338321325	Jul 31 05:21:09 PM PDT 24	Jul 31 05:21:11 PM PDT 24	9368932 ps
T783	/workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.1521074194	Jul 31 05:21:14 PM PDT 24	Jul 31 05:25:12 PM PDT 24	14860837284 ps
T784	/workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.3729536045	Jul 31 05:20:40 PM PDT 24	Jul 31 05:24:33 PM PDT 24	3883956318 ps
T785	/workspace/coverage/cover_reg_top/32.alert_handler_intr_test.1405675701	Jul 31 05:20:47 PM PDT 24	Jul 31 05:20:48 PM PDT 24	11503275 ps
T786	/workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.3366432130	Jul 31 05:20:39 PM PDT 24	Jul 31 05:26:45 PM PDT 24	22786792624 ps
T787	/workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.3708764621	Jul 31 05:20:36 PM PDT 24	Jul 31 05:20:45 PM PDT 24	298600983 ps
T788	/workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.1164587942	Jul 31 05:21:06 PM PDT 24	Jul 31 05:21:11 PM PDT 24	285121294 ps
T148	/workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.1159801848	Jul 31 05:20:44 PM PDT 24	Jul 31 05:32:27 PM PDT 24	20666047667 ps
T150	/workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.1947326569	Jul 31 05:21:03 PM PDT 24	Jul 31 05:32:12 PM PDT 24	4460858102 ps
T789	/workspace/coverage/cover_reg_top/25.alert_handler_intr_test.1607126637	Jul 31 05:21:18 PM PDT 24	Jul 31 05:21:20 PM PDT 24	12525722 ps
T790	/workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.3797481060	Jul 31 05:20:40 PM PDT 24	Jul 31 05:22:27 PM PDT 24	857855194 ps
T146	/workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.1080526712	Jul 31 05:20:51 PM PDT 24	Jul 31 05:22:45 PM PDT 24	3224942820 ps
T791	/workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.1227506287	Jul 31 05:20:55 PM PDT 24	Jul 31 05:21:03 PM PDT 24	54206037 ps
T122	/workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.2433155500	Jul 31 05:20:38 PM PDT 24	Jul 31 05:22:08 PM PDT 24	827751155 ps
T792	/workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.2914435435	Jul 31 05:21:09 PM PDT 24	Jul 31 05:21:23 PM PDT 24	689725059 ps
T793	/workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.635994711	Jul 31 05:20:45 PM PDT 24	Jul 31 05:20:58 PM PDT 24	156192771 ps
T142	/workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.211829099	Jul 31 05:20:52 PM PDT 24	Jul 31 05:31:49 PM PDT 24	8341092598 ps
T794	/workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.3717593656	Jul 31 05:21:12 PM PDT 24	Jul 31 05:21:24 PM PDT 24	608314674 ps
T795	/workspace/coverage/cover_reg_top/13.alert_handler_intr_test.3377474905	Jul 31 05:20:52 PM PDT 24	Jul 31 05:20:53 PM PDT 24	25804346 ps
T796	/workspace/coverage/cover_reg_top/17.alert_handler_intr_test.21413113	Jul 31 05:21:03 PM PDT 24	Jul 31 05:21:05 PM PDT 24	11944261 ps
T797	/workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.3857714376	Jul 31 05:20:38 PM PDT 24	Jul 31 05:20:47 PM PDT 24	118503075 ps
T798	/workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.1330962123	Jul 31 05:20:52 PM PDT 24	Jul 31 05:20:56 PM PDT 24	46657174 ps
T799	/workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.2188793719	Jul 31 05:20:51 PM PDT 24	Jul 31 05:20:55 PM PDT 24	90788273 ps
T143	/workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.1805363069	Jul 31 05:20:48 PM PDT 24	Jul 31 05:22:33 PM PDT 24	1465832605 ps
T800	/workspace/coverage/cover_reg_top/16.alert_handler_intr_test.1083370386	Jul 31 05:20:56 PM PDT 24	Jul 31 05:20:58 PM PDT 24	8077062 ps
T801	/workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.1850383011	Jul 31 05:20:53 PM PDT 24	Jul 31 05:21:03 PM PDT 24	537662530 ps
T802	/workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.3478656236	Jul 31 05:20:47 PM PDT 24	Jul 31 05:21:39 PM PDT 24	715120723 ps
T803	/workspace/coverage/cover_reg_top/46.alert_handler_intr_test.3052619059	Jul 31 05:20:51 PM PDT 24	Jul 31 05:20:52 PM PDT 24	7863364 ps
T159	/workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.2254383747	Jul 31 05:20:38 PM PDT 24	Jul 31 05:20:42 PM PDT 24	625740721 ps
T804	/workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.3773062426	Jul 31 05:20:50 PM PDT 24	Jul 31 05:21:15 PM PDT 24	180567186 ps
T149	/workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.3044959675	Jul 31 05:20:57 PM PDT 24	Jul 31 05:23:12 PM PDT 24	1840693089 ps
T137	/workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.2715370078	Jul 31 05:20:51 PM PDT 24	Jul 31 05:41:09 PM PDT 24	136739317774 ps
T805	/workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.2274766433	Jul 31 05:20:41 PM PDT 24	Jul 31 05:21:08 PM PDT 24	765559343 ps
T173	/workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.2434650283	Jul 31 05:20:47 PM PDT 24	Jul 31 05:20:50 PM PDT 24	91489900 ps
T806	/workspace/coverage/cover_reg_top/4.alert_handler_intr_test.1578836689	Jul 31 05:20:43 PM PDT 24	Jul 31 05:20:44 PM PDT 24	10669241 ps
T807	/workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.108805063	Jul 31 05:20:39 PM PDT 24	Jul 31 05:20:45 PM PDT 24	406742236 ps
T131	/workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.1746262829	Jul 31 05:20:44 PM PDT 24	Jul 31 05:27:31 PM PDT 24	23480243214 ps
T808	/workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.769770884	Jul 31 05:21:00 PM PDT 24	Jul 31 05:21:06 PM PDT 24	75823808 ps
T152	/workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.2425985680	Jul 31 05:21:00 PM PDT 24	Jul 31 05:23:59 PM PDT 24	9665536749 ps
T809	/workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.3491229673	Jul 31 05:20:39 PM PDT 24	Jul 31 05:20:56 PM PDT 24	302270672 ps
T123	/workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.668930059	Jul 31 05:20:38 PM PDT 24	Jul 31 05:31:56 PM PDT 24	4495000952 ps
T810	/workspace/coverage/cover_reg_top/47.alert_handler_intr_test.1565979184	Jul 31 05:21:07 PM PDT 24	Jul 31 05:21:09 PM PDT 24	10193061 ps
T811	/workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.1976311970	Jul 31 05:21:06 PM PDT 24	Jul 31 05:21:13 PM PDT 24	53840273 ps
T812	/workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.3801712727	Jul 31 05:20:59 PM PDT 24	Jul 31 05:21:16 PM PDT 24	3451384476 ps
T144	/workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.2258449403	Jul 31 05:21:03 PM PDT 24	Jul 31 05:26:58 PM PDT 24	4796706649 ps
T813	/workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.2036867437	Jul 31 05:21:04 PM PDT 24	Jul 31 05:21:08 PM PDT 24	103158912 ps
T814	/workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.3484663555	Jul 31 05:20:42 PM PDT 24	Jul 31 05:39:48 PM PDT 24	62678563419 ps
T815	/workspace/coverage/cover_reg_top/8.alert_handler_intr_test.1713787615	Jul 31 05:20:46 PM PDT 24	Jul 31 05:20:47 PM PDT 24	11793680 ps
T816	/workspace/coverage/cover_reg_top/21.alert_handler_intr_test.1156923494	Jul 31 05:20:50 PM PDT 24	Jul 31 05:20:52 PM PDT 24	12299542 ps
T817	/workspace/coverage/cover_reg_top/19.alert_handler_intr_test.3651009378	Jul 31 05:21:00 PM PDT 24	Jul 31 05:21:02 PM PDT 24	12139096 ps
T818	/workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.3762576430	Jul 31 05:20:47 PM PDT 24	Jul 31 05:20:54 PM PDT 24	220592585 ps
T151	/workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.2092988913	Jul 31 05:20:45 PM PDT 24	Jul 31 05:22:12 PM PDT 24	765127649 ps
T819	/workspace/coverage/cover_reg_top/39.alert_handler_intr_test.3174892452	Jul 31 05:21:09 PM PDT 24	Jul 31 05:21:11 PM PDT 24	8188884 ps
T820	/workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.677372984	Jul 31 05:20:41 PM PDT 24	Jul 31 05:20:43 PM PDT 24	87154283 ps
T821	/workspace/coverage/cover_reg_top/36.alert_handler_intr_test.739080434	Jul 31 05:20:44 PM PDT 24	Jul 31 05:20:46 PM PDT 24	9042231 ps
T822	/workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.3741612991	Jul 31 05:20:49 PM PDT 24	Jul 31 05:22:01 PM PDT 24	803537493 ps
T823	/workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.925933231	Jul 31 05:20:39 PM PDT 24	Jul 31 05:20:46 PM PDT 24	98405481 ps
T824	/workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.2990054660	Jul 31 05:21:08 PM PDT 24	Jul 31 05:21:12 PM PDT 24	49514992 ps
T825	/workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.1161682482	Jul 31 05:20:52 PM PDT 24	Jul 31 05:20:57 PM PDT 24	108846305 ps
T826	/workspace/coverage/cover_reg_top/38.alert_handler_intr_test.1328865498	Jul 31 05:20:57 PM PDT 24	Jul 31 05:20:58 PM PDT 24	10248434 ps
T352	/workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.1863349653	Jul 31 05:21:15 PM PDT 24	Jul 31 05:28:14 PM PDT 24	12784776523 ps
T827	/workspace/coverage/cover_reg_top/31.alert_handler_intr_test.4252597871	Jul 31 05:20:53 PM PDT 24	Jul 31 05:20:55 PM PDT 24	9192554 ps
T828	/workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.3740765524	Jul 31 05:20:59 PM PDT 24	Jul 31 05:21:08 PM PDT 24	437915804 ps

Test location	/workspace/coverage/default/9.alert_handler_lpg_stub_clk.168634153
Short name	T8
Test name
Test status
Simulation time	18629549266 ps
CPU time	1550.44 seconds
Started	Jul 31 05:21:26 PM PDT 24
Finished	Jul 31 05:47:17 PM PDT 24
Peak memory	289228 kb
Host	smart-5357b0c8-ca27-43c2-bd59-f551691e7fa2
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=168634153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.168634153
Directory	/workspace/9.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/41.alert_handler_stress_all.2711203119
Short name	T26
Test name
Test status
Simulation time	35588560761 ps
CPU time	1999.96 seconds
Started	Jul 31 05:22:44 PM PDT 24
Finished	Jul 31 05:56:04 PM PDT 24
Peak memory	281164 kb
Host	smart-c07954f5-766b-4cb8-9970-04ef2694390d
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711203119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha ndler_stress_all.2711203119
Directory	/workspace/41.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.3669016721
Short name	T32
Test name
Test status
Simulation time	56688137254 ps
CPU time	502.55 seconds
Started	Jul 31 05:21:41 PM PDT 24
Finished	Jul 31 05:30:05 PM PDT 24
Peak memory	269612 kb
Host	smart-8eb2c1d1-a3ab-4351-876d-068774c8d464
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669016721 -assert nopostproc +UVM_TESTNAME=aler t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.3669016721
Directory	/workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/2.alert_handler_sec_cm.524210319
Short name	T4
Test name
Test status
Simulation time	1526586662 ps
CPU time	13.55 seconds
Started	Jul 31 05:21:03 PM PDT 24
Finished	Jul 31 05:21:16 PM PDT 24
Peak memory	270748 kb
Host	smart-024e2ffb-7b88-4374-97b5-067235200834
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=524210319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.524210319
Directory	/workspace/2.alert_handler_sec_cm/latest

Test location	/workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.1897502841
Short name	T153
Test name
Test status
Simulation time	183362593 ps
CPU time	20.21 seconds
Started	Jul 31 05:20:53 PM PDT 24
Finished	Jul 31 05:21:13 PM PDT 24
Peak memory	245828 kb
Host	smart-03ae9e23-b8f8-4179-838d-102c00d66690
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1897502841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.1897502841
Directory	/workspace/8.alert_handler_tl_intg_err/latest

Test location	/workspace/coverage/default/34.alert_handler_lpg.2058467442
Short name	T17
Test name
Test status
Simulation time	89647751022 ps
CPU time	1389.71 seconds
Started	Jul 31 05:22:20 PM PDT 24
Finished	Jul 31 05:45:30 PM PDT 24
Peak memory	272276 kb
Host	smart-61894037-2c21-4b1f-97b4-b4d7a80d2e33
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2058467442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.2058467442
Directory	/workspace/34.alert_handler_lpg/latest

Test location	/workspace/coverage/default/25.alert_handler_stress_all.1600041038
Short name	T73
Test name
Test status
Simulation time	118258668890 ps
CPU time	3748.53 seconds
Started	Jul 31 05:21:59 PM PDT 24
Finished	Jul 31 06:24:28 PM PDT 24
Peak memory	305700 kb
Host	smart-84181351-6efe-47d1-b143-f5f0c97aa1d7
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600041038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha ndler_stress_all.1600041038
Directory	/workspace/25.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/42.alert_handler_stress_all_with_rand_reset.3247614339
Short name	T29
Test name
Test status
Simulation time	45355815366 ps
CPU time	3015.23 seconds
Started	Jul 31 05:22:32 PM PDT 24
Finished	Jul 31 06:12:48 PM PDT 24
Peak memory	330732 kb
Host	smart-9afc7423-770d-43a4-8dfc-a8107a7ee3a9
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247614339 -assert nopostproc +UVM_TESTNAME=aler t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_stress_all_with_rand_reset.3247614339
Directory	/workspace/42.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.2391732510
Short name	T147
Test name
Test status
Simulation time	8968385053 ps
CPU time	195.92 seconds
Started	Jul 31 05:20:51 PM PDT 24
Finished	Jul 31 05:24:07 PM PDT 24
Peak memory	265792 kb
Host	smart-ef1eada9-c47c-4ffb-b95b-c0b2b0cd0e10
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2391732510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro rs.2391732510
Directory	/workspace/3.alert_handler_shadow_reg_errors/latest

Test location	/workspace/coverage/default/21.alert_handler_entropy.235509705
Short name	T33
Test name
Test status
Simulation time	104504119114 ps
CPU time	831.24 seconds
Started	Jul 31 05:22:09 PM PDT 24
Finished	Jul 31 05:36:01 PM PDT 24
Peak memory	272932 kb
Host	smart-17534190-2a9e-4acc-9eae-70f9e89bbcd1
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=235509705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.235509705
Directory	/workspace/21.alert_handler_entropy/latest

Test location	/workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.977066911
Short name	T126
Test name
Test status
Simulation time	21796505172 ps
CPU time	846.11 seconds
Started	Jul 31 05:21:14 PM PDT 24
Finished	Jul 31 05:35:21 PM PDT 24
Peak memory	265420 kb
Host	smart-38084dca-4d2c-4da2-b4e6-57cc1d9a5fcd
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977066911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM _TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.977066911
Directory	/workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/default/30.alert_handler_smoke.270802705
Short name	T392
Test name
Test status
Simulation time	2185057759 ps
CPU time	35.5 seconds
Started	Jul 31 05:22:10 PM PDT 24
Finished	Jul 31 05:22:45 PM PDT 24
Peak memory	255532 kb
Host	smart-e0df2830-ef3f-48f8-be04-787b2a8d57cb
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27080 2705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.270802705
Directory	/workspace/30.alert_handler_smoke/latest

Test location	/workspace/coverage/default/40.alert_handler_entropy.1028278586
Short name	T30
Test name
Test status
Simulation time	133839907512 ps
CPU time	2882.83 seconds
Started	Jul 31 05:22:31 PM PDT 24
Finished	Jul 31 06:10:34 PM PDT 24
Peak memory	289068 kb
Host	smart-dc26ba0f-b7c2-4d26-8be6-789579f3c90b
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1028278586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.1028278586
Directory	/workspace/40.alert_handler_entropy/latest

Test location	/workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.1766164501
Short name	T134
Test name
Test status
Simulation time	17018896913 ps
CPU time	1161.73 seconds
Started	Jul 31 05:20:43 PM PDT 24
Finished	Jul 31 05:40:05 PM PDT 24
Peak memory	271412 kb
Host	smart-8993848f-c3a6-4b2e-8efa-8f803dbc9be1
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766164501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.1766164501
Directory	/workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.3929389159
Short name	T31
Test name
Test status
Simulation time	19221926363 ps
CPU time	2422.18 seconds
Started	Jul 31 05:22:03 PM PDT 24
Finished	Jul 31 06:02:26 PM PDT 24
Peak memory	318340 kb
Host	smart-4e6bf308-eff8-453c-815b-15e8eef6f579
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929389159 -assert nopostproc +UVM_TESTNAME=aler t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.3929389159
Directory	/workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/31.alert_handler_lpg.2568087228
Short name	T104
Test name
Test status
Simulation time	44750406541 ps
CPU time	2343.98 seconds
Started	Jul 31 05:22:30 PM PDT 24
Finished	Jul 31 06:01:34 PM PDT 24
Peak memory	281152 kb
Host	smart-d9707dca-95db-4517-9fd9-73ebfc7fc833
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2568087228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.2568087228
Directory	/workspace/31.alert_handler_lpg/latest

Test location	/workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.1947326569
Short name	T150
Test name
Test status
Simulation time	4460858102 ps
CPU time	668.98 seconds
Started	Jul 31 05:21:03 PM PDT 24
Finished	Jul 31 05:32:12 PM PDT 24
Peak memory	272900 kb
Host	smart-ebba73ae-b2b2-45c3-b78f-44351cd49b8f
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947326569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.1947326569
Directory	/workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.alert_handler_intr_test.2013492495
Short name	T251
Test name
Test status
Simulation time	18200331 ps
CPU time	1.87 seconds
Started	Jul 31 05:20:39 PM PDT 24
Finished	Jul 31 05:20:41 PM PDT 24
Peak memory	236720 kb
Host	smart-581402f8-966d-4c0e-b2e0-745b0b410d67
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2013492495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.2013492495
Directory	/workspace/9.alert_handler_intr_test/latest

Test location	/workspace/coverage/default/33.alert_handler_ping_timeout.729900620
Short name	T19
Test name
Test status
Simulation time	11413164507 ps
CPU time	478.78 seconds
Started	Jul 31 05:22:25 PM PDT 24
Finished	Jul 31 05:30:24 PM PDT 24
Peak memory	248388 kb
Host	smart-9bf5806c-e239-432d-bb57-dac2f9702949
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=729900620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.729900620
Directory	/workspace/33.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.606392268
Short name	T116
Test name
Test status
Simulation time	8167267841 ps
CPU time	292.83 seconds
Started	Jul 31 05:20:50 PM PDT 24
Finished	Jul 31 05:25:43 PM PDT 24
Peak memory	265732 kb
Host	smart-01e2dcce-f65c-43e1-b3de-a3e980c47727
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606392268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM _TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.606392268
Directory	/workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.1830510050
Short name	T52
Test name
Test status
Simulation time	408249523707 ps
CPU time	9682.57 seconds
Started	Jul 31 05:22:07 PM PDT 24
Finished	Jul 31 08:03:31 PM PDT 24
Peak memory	371312 kb
Host	smart-5375b63f-c2c2-41aa-9ff0-2bec9136fe5c
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830510050 -assert nopostproc +UVM_TESTNAME=aler t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.1830510050
Directory	/workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/16.alert_handler_esc_intr_timeout.3436266586
Short name	T11
Test name
Test status
Simulation time	2589866502 ps
CPU time	41.92 seconds
Started	Jul 31 05:21:37 PM PDT 24
Finished	Jul 31 05:22:19 PM PDT 24
Peak memory	248336 kb
Host	smart-ce40ccbe-efa7-4612-a98e-83726fe5b03f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34362 66586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.3436266586
Directory	/workspace/16.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.1945093080
Short name	T125
Test name
Test status
Simulation time	3615065189 ps
CPU time	236.27 seconds
Started	Jul 31 05:20:55 PM PDT 24
Finished	Jul 31 05:24:52 PM PDT 24
Peak memory	265592 kb
Host	smart-d947739a-e685-4622-b5b4-2e5780140509
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1945093080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err ors.1945093080
Directory	/workspace/12.alert_handler_shadow_reg_errors/latest

Test location	/workspace/coverage/default/32.alert_handler_lpg.553217739
Short name	T314
Test name
Test status
Simulation time	36526032334 ps
CPU time	2324.91 seconds
Started	Jul 31 05:22:22 PM PDT 24
Finished	Jul 31 06:01:07 PM PDT 24
Peak memory	287760 kb
Host	smart-94b5035f-3e02-4f8a-8232-bf202030146b
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=553217739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.553217739
Directory	/workspace/32.alert_handler_lpg/latest

Test location	/workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.2203983170
Short name	T74
Test name
Test status
Simulation time	72091638112 ps
CPU time	2268.16 seconds
Started	Jul 31 05:21:52 PM PDT 24
Finished	Jul 31 05:59:41 PM PDT 24
Peak memory	289500 kb
Host	smart-b6ef3cd9-bdc5-4460-8916-8b063487a8ee
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203983170 -assert nopostproc +UVM_TESTNAME=aler t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.2203983170
Directory	/workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/30.alert_handler_ping_timeout.1816948215
Short name	T303
Test name
Test status
Simulation time	14355507203 ps
CPU time	602.27 seconds
Started	Jul 31 05:22:14 PM PDT 24
Finished	Jul 31 05:32:17 PM PDT 24
Peak memory	248356 kb
Host	smart-3e4a1a9d-a34d-4b07-bf93-72883ccb75b5
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1816948215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.1816948215
Directory	/workspace/30.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/47.alert_handler_lpg.1787831773
Short name	T58
Test name
Test status
Simulation time	39678295550 ps
CPU time	2283.89 seconds
Started	Jul 31 05:22:53 PM PDT 24
Finished	Jul 31 06:00:58 PM PDT 24
Peak memory	283736 kb
Host	smart-bd9da0fd-c599-44cc-8b57-755632dd9d0b
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1787831773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.1787831773
Directory	/workspace/47.alert_handler_lpg/latest

Test location	/workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.280677273
Short name	T120
Test name
Test status
Simulation time	15495434511 ps
CPU time	1253.64 seconds
Started	Jul 31 05:20:50 PM PDT 24
Finished	Jul 31 05:41:44 PM PDT 24
Peak memory	265596 kb
Host	smart-4f12d2f8-86c4-4825-a72e-ca7dafbb884f
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280677273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM _TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.280677273
Directory	/workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/default/32.alert_handler_ping_timeout.1848188240
Short name	T3
Test name
Test status
Simulation time	21905964038 ps
CPU time	484.67 seconds
Started	Jul 31 05:22:22 PM PDT 24
Finished	Jul 31 05:30:27 PM PDT 24
Peak memory	248344 kb
Host	smart-0278e280-7884-4d74-ad6e-ad7130b98c79
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1848188240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.1848188240
Directory	/workspace/32.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/42.alert_handler_stress_all.138875705
Short name	T78
Test name
Test status
Simulation time	11560218011 ps
CPU time	1034.29 seconds
Started	Jul 31 05:22:35 PM PDT 24
Finished	Jul 31 05:39:49 PM PDT 24
Peak memory	272984 kb
Host	smart-68342c1b-6487-4608-a959-82382c665130
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138875705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_han dler_stress_all.138875705
Directory	/workspace/42.alert_handler_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.2258449403
Short name	T144
Test name
Test status
Simulation time	4796706649 ps
CPU time	355.46 seconds
Started	Jul 31 05:21:03 PM PDT 24
Finished	Jul 31 05:26:58 PM PDT 24
Peak memory	272760 kb
Host	smart-faf3d840-17ae-44de-b1c4-331d6de2bcf5
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2258449403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro rs.2258449403
Directory	/workspace/5.alert_handler_shadow_reg_errors/latest

Test location	/workspace/coverage/default/0.alert_handler_lpg.1167620420
Short name	T226
Test name
Test status
Simulation time	114525132275 ps
CPU time	3306.79 seconds
Started	Jul 31 05:20:49 PM PDT 24
Finished	Jul 31 06:15:56 PM PDT 24
Peak memory	281156 kb
Host	smart-ad1074fb-7cc0-415a-83d0-d29986eabc7a
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1167620420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.1167620420
Directory	/workspace/0.alert_handler_lpg/latest

Test location	/workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.206507125
Short name	T124
Test name
Test status
Simulation time	5966396564 ps
CPU time	470.38 seconds
Started	Jul 31 05:20:53 PM PDT 24
Finished	Jul 31 05:28:43 PM PDT 24
Peak memory	265652 kb
Host	smart-7e465bed-8104-497b-b72b-ed2ea95b895b
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206507125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM _TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.206507125
Directory	/workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/default/12.alert_handler_esc_alert_accum.1684254589
Short name	T2
Test name
Test status
Simulation time	2010878041 ps
CPU time	130.42 seconds
Started	Jul 31 05:21:32 PM PDT 24
Finished	Jul 31 05:23:42 PM PDT 24
Peak memory	256068 kb
Host	smart-2c01a392-4224-468a-9057-9440dac68ab6
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16842 54589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.1684254589
Directory	/workspace/12.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/1.alert_handler_ping_timeout.1929344867
Short name	T318
Test name
Test status
Simulation time	55740126319 ps
CPU time	586.28 seconds
Started	Jul 31 05:20:47 PM PDT 24
Finished	Jul 31 05:30:34 PM PDT 24
Peak memory	248356 kb
Host	smart-7e10c586-0719-4cc9-9ddc-5eab28bb0f1d
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1929344867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.1929344867
Directory	/workspace/1.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/cover_reg_top/34.alert_handler_intr_test.10870212
Short name	T250
Test name
Test status
Simulation time	9906438 ps
CPU time	1.51 seconds
Started	Jul 31 05:21:04 PM PDT 24
Finished	Jul 31 05:21:05 PM PDT 24
Peak memory	236844 kb
Host	smart-92a25f29-3ea8-48c5-a3a7-0495f0275d5f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=10870212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.10870212
Directory	/workspace/34.alert_handler_intr_test/latest

Test location	/workspace/coverage/default/16.alert_handler_lpg.2267704539
Short name	T182
Test name
Test status
Simulation time	106486517288 ps
CPU time	1714.77 seconds
Started	Jul 31 05:21:43 PM PDT 24
Finished	Jul 31 05:50:18 PM PDT 24
Peak memory	272244 kb
Host	smart-03fdb8ae-3f21-4b6a-9198-1cedb36d4f4d
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2267704539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.2267704539
Directory	/workspace/16.alert_handler_lpg/latest

Test location	/workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.1435825271
Short name	T121
Test name
Test status
Simulation time	3223231940 ps
CPU time	203.27 seconds
Started	Jul 31 05:21:04 PM PDT 24
Finished	Jul 31 05:24:28 PM PDT 24
Peak memory	273396 kb
Host	smart-cf60f38e-817c-4104-8b8a-894163ecf445
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1435825271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro rs.1435825271
Directory	/workspace/6.alert_handler_shadow_reg_errors/latest

Test location	/workspace/coverage/default/22.alert_handler_stress_all_with_rand_reset.2285540178
Short name	T175
Test name
Test status
Simulation time	41094939424 ps
CPU time	2609.68 seconds
Started	Jul 31 05:21:56 PM PDT 24
Finished	Jul 31 06:05:26 PM PDT 24
Peak memory	289480 kb
Host	smart-aa20d361-fa31-4ada-bbea-0fd1b9b26c28
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285540178 -assert nopostproc +UVM_TESTNAME=aler t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_stress_all_with_rand_reset.2285540178
Directory	/workspace/22.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/28.alert_handler_ping_timeout.3987177025
Short name	T305
Test name
Test status
Simulation time	8321948269 ps
CPU time	337.09 seconds
Started	Jul 31 05:22:28 PM PDT 24
Finished	Jul 31 05:28:05 PM PDT 24
Peak memory	248544 kb
Host	smart-1f327553-d4c7-401e-a5f4-01e85494102f
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3987177025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.3987177025
Directory	/workspace/28.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/29.alert_handler_lpg.3038536697
Short name	T585
Test name
Test status
Simulation time	152160731920 ps
CPU time	2209.31 seconds
Started	Jul 31 05:22:31 PM PDT 24
Finished	Jul 31 05:59:20 PM PDT 24
Peak memory	272868 kb
Host	smart-020d9cfe-d8ea-49d5-802e-3f567e782596
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3038536697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.3038536697
Directory	/workspace/29.alert_handler_lpg/latest

Test location	/workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.1004510831
Short name	T169
Test name
Test status
Simulation time	216560604 ps
CPU time	1.88 seconds
Started	Jul 31 05:20:49 PM PDT 24
Finished	Jul 31 05:20:51 PM PDT 24
Peak memory	237996 kb
Host	smart-13d996ac-75c8-44d9-9cda-5cb4a848b273
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1004510831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.1004510831
Directory	/workspace/1.alert_handler_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.3340683318
Short name	T135
Test name
Test status
Simulation time	8400136430 ps
CPU time	349.53 seconds
Started	Jul 31 05:20:49 PM PDT 24
Finished	Jul 31 05:26:38 PM PDT 24
Peak memory	270480 kb
Host	smart-a3ffa3e4-ac0e-4a4a-b0fa-548ccb46ee67
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340683318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.3340683318
Directory	/workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/default/13.alert_handler_random_classes.402690106
Short name	T289
Test name
Test status
Simulation time	5840730214 ps
CPU time	45.27 seconds
Started	Jul 31 05:21:42 PM PDT 24
Finished	Jul 31 05:22:28 PM PDT 24
Peak memory	248096 kb
Host	smart-e58c7a2a-c5b1-4bf1-b8db-046725ba90a2
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40269 0106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.402690106
Directory	/workspace/13.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/26.alert_handler_lpg.98566110
Short name	T231
Test name
Test status
Simulation time	150667211693 ps
CPU time	2202.71 seconds
Started	Jul 31 05:22:09 PM PDT 24
Finished	Jul 31 05:58:52 PM PDT 24
Peak memory	281104 kb
Host	smart-b5e8fea1-4192-4b6b-b250-19a5257c7e72
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=98566110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.98566110
Directory	/workspace/26.alert_handler_lpg/latest

Test location	/workspace/coverage/default/7.alert_handler_stress_all.4226213811
Short name	T255
Test name
Test status
Simulation time	26382556348 ps
CPU time	743.1 seconds
Started	Jul 31 05:21:24 PM PDT 24
Finished	Jul 31 05:33:47 PM PDT 24
Peak memory	264796 kb
Host	smart-2aab7bcc-deaa-4e21-b134-d29f7a83cf2f
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226213811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han dler_stress_all.4226213811
Directory	/workspace/7.alert_handler_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.668930059
Short name	T123
Test name
Test status
Simulation time	4495000952 ps
CPU time	678.08 seconds
Started	Jul 31 05:20:38 PM PDT 24
Finished	Jul 31 05:31:56 PM PDT 24
Peak memory	273204 kb
Host	smart-04a36de2-3aed-40d9-aca0-fc14553395ae
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668930059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM _TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.668930059
Directory	/workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/default/13.alert_handler_ping_timeout.3317214913
Short name	T310
Test name
Test status
Simulation time	15363773630 ps
CPU time	637.48 seconds
Started	Jul 31 05:21:54 PM PDT 24
Finished	Jul 31 05:32:31 PM PDT 24
Peak memory	248368 kb
Host	smart-24927305-0767-4859-aa87-b33b5d7548c0
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3317214913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.3317214913
Directory	/workspace/13.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/31.alert_handler_ping_timeout.4284111190
Short name	T113
Test name
Test status
Simulation time	61921499171 ps
CPU time	663.14 seconds
Started	Jul 31 05:22:12 PM PDT 24
Finished	Jul 31 05:33:15 PM PDT 24
Peak memory	248388 kb
Host	smart-f1e2fb35-ccbd-4b08-96a3-57b84af23b43
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4284111190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.4284111190
Directory	/workspace/31.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.2106795115
Short name	T283
Test name
Test status
Simulation time	38947325031 ps
CPU time	2505.5 seconds
Started	Jul 31 05:22:25 PM PDT 24
Finished	Jul 31 06:04:11 PM PDT 24
Peak memory	305360 kb
Host	smart-01c1b168-0ee4-4912-82f9-7574984b2b04
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106795115 -assert nopostproc +UVM_TESTNAME=aler t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.2106795115
Directory	/workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/2.alert_handler_alert_accum_saturation.3254743625
Short name	T36
Test name
Test status
Simulation time	58976649 ps
CPU time	4.42 seconds
Started	Jul 31 05:21:10 PM PDT 24
Finished	Jul 31 05:21:14 PM PDT 24
Peak memory	248628 kb
Host	smart-70409cb3-0e0e-4592-82f1-5f9eaa179a79
User	root
Command	/workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=3254743625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.3254743625
Directory	/workspace/2.alert_handler_alert_accum_saturation/latest

Test location	/workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.3044959675
Short name	T149
Test name
Test status
Simulation time	1840693089 ps
CPU time	129.84 seconds
Started	Jul 31 05:20:57 PM PDT 24
Finished	Jul 31 05:23:12 PM PDT 24
Peak memory	257304 kb
Host	smart-885bb202-3090-4dc3-88da-4a34ac95ca8b
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3044959675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro rs.3044959675
Directory	/workspace/4.alert_handler_shadow_reg_errors/latest

Test location	/workspace/coverage/default/1.alert_handler_alert_accum_saturation.1500840686
Short name	T200
Test name
Test status
Simulation time	126542847 ps
CPU time	2.32 seconds
Started	Jul 31 05:21:23 PM PDT 24
Finished	Jul 31 05:21:25 PM PDT 24
Peak memory	248596 kb
Host	smart-2dc6178c-91b9-4a71-b076-3ba2eba84cc1
User	root
Command	/workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1500840686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.1500840686
Directory	/workspace/1.alert_handler_alert_accum_saturation/latest

Test location	/workspace/coverage/default/12.alert_handler_alert_accum_saturation.2282285689
Short name	T214
Test name
Test status
Simulation time	39422599 ps
CPU time	2.33 seconds
Started	Jul 31 05:21:35 PM PDT 24
Finished	Jul 31 05:21:37 PM PDT 24
Peak memory	248596 kb
Host	smart-86aa1824-0263-494b-8bea-eb24036dfac7
User	root
Command	/workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=2282285689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.2282285689
Directory	/workspace/12.alert_handler_alert_accum_saturation/latest

Test location	/workspace/coverage/default/14.alert_handler_alert_accum_saturation.1363235013
Short name	T201
Test name
Test status
Simulation time	222372723 ps
CPU time	2.67 seconds
Started	Jul 31 05:21:57 PM PDT 24
Finished	Jul 31 05:22:00 PM PDT 24
Peak memory	248612 kb
Host	smart-16c77708-20b6-4002-8079-93ef365bd426
User	root
Command	/workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1363235013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.1363235013
Directory	/workspace/14.alert_handler_alert_accum_saturation/latest

Test location	/workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.4192249207
Short name	T266
Test name
Test status
Simulation time	21692756052 ps
CPU time	2733.15 seconds
Started	Jul 31 05:21:07 PM PDT 24
Finished	Jul 31 06:06:40 PM PDT 24
Peak memory	305900 kb
Host	smart-935a2821-66b2-45a7-ad65-12aa49c73b83
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192249207 -assert nopostproc +UVM_TESTNAME=aler t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.4192249207
Directory	/workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.790433249
Short name	T187
Test name
Test status
Simulation time	69329409276 ps
CPU time	4384.08 seconds
Started	Jul 31 05:21:41 PM PDT 24
Finished	Jul 31 06:34:47 PM PDT 24
Peak memory	321488 kb
Host	smart-4c1e61ef-4f49-4e0e-9912-9b6b1d8f62ba
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790433249 -assert nopostproc +UVM_TESTNAME=alert _handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.790433249
Directory	/workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/26.alert_handler_stress_all_with_rand_reset.2941996749
Short name	T260
Test name
Test status
Simulation time	2001793676472 ps
CPU time	6834.27 seconds
Started	Jul 31 05:22:07 PM PDT 24
Finished	Jul 31 07:16:02 PM PDT 24
Peak memory	321032 kb
Host	smart-770d9935-22f4-4aeb-8e49-b2cdeb9bd12c
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941996749 -assert nopostproc +UVM_TESTNAME=aler t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_stress_all_with_rand_reset.2941996749
Directory	/workspace/26.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.2556900119
Short name	T49
Test name
Test status
Simulation time	188253420385 ps
CPU time	5971.46 seconds
Started	Jul 31 05:22:26 PM PDT 24
Finished	Jul 31 07:01:58 PM PDT 24
Peak memory	320276 kb
Host	smart-c6cd37d3-2a44-43a9-827f-1ecd4842de13
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556900119 -assert nopostproc +UVM_TESTNAME=aler t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.2556900119
Directory	/workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/41.alert_handler_stress_all_with_rand_reset.2322139049
Short name	T259
Test name
Test status
Simulation time	70366018085 ps
CPU time	2315.25 seconds
Started	Jul 31 05:22:36 PM PDT 24
Finished	Jul 31 06:01:11 PM PDT 24
Peak memory	297684 kb
Host	smart-f449cf74-f239-44d8-94b3-e622844a08ac
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322139049 -assert nopostproc +UVM_TESTNAME=aler t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_stress_all_with_rand_reset.2322139049
Directory	/workspace/41.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/15.alert_handler_stress_all.1130158684
Short name	T614
Test name
Test status
Simulation time	44593901102 ps
CPU time	2971.47 seconds
Started	Jul 31 05:21:47 PM PDT 24
Finished	Jul 31 06:11:19 PM PDT 24
Peak memory	304848 kb
Host	smart-5307e199-fb79-46fb-ab39-590a80cae096
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130158684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha ndler_stress_all.1130158684
Directory	/workspace/15.alert_handler_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.2715370078
Short name	T137
Test name
Test status
Simulation time	136739317774 ps
CPU time	1218.31 seconds
Started	Jul 31 05:20:51 PM PDT 24
Finished	Jul 31 05:41:09 PM PDT 24
Peak memory	265652 kb
Host	smart-0ae05c77-2340-4bdf-b81b-9d91282a028d
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715370078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.2715370078
Directory	/workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.alert_handler_intr_test.1571370616
Short name	T227
Test name
Test status
Simulation time	8962550 ps
CPU time	1.51 seconds
Started	Jul 31 05:20:39 PM PDT 24
Finished	Jul 31 05:20:41 PM PDT 24
Peak memory	236812 kb
Host	smart-91c408aa-9acb-4cfd-bccc-7bb677d39526
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1571370616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.1571370616
Directory	/workspace/11.alert_handler_intr_test/latest

Test location	/workspace/coverage/default/1.alert_handler_esc_intr_timeout.1550614255
Short name	T402
Test name
Test status
Simulation time	586713974 ps
CPU time	11.74 seconds
Started	Jul 31 05:21:10 PM PDT 24
Finished	Jul 31 05:21:22 PM PDT 24
Peak memory	248924 kb
Host	smart-13d6b48b-5ff4-4834-ab6f-77c23a6a8610
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15506 14255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.1550614255
Directory	/workspace/1.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/1.alert_handler_lpg.24030486
Short name	T334
Test name
Test status
Simulation time	117339188532 ps
CPU time	2947.32 seconds
Started	Jul 31 05:21:16 PM PDT 24
Finished	Jul 31 06:10:23 PM PDT 24
Peak memory	288812 kb
Host	smart-1660077f-9d60-4ece-824e-2f608f3edea7
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=24030486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.24030486
Directory	/workspace/1.alert_handler_lpg/latest

Test location	/workspace/coverage/default/10.alert_handler_stress_all.377050526
Short name	T55
Test name
Test status
Simulation time	17009037182 ps
CPU time	906.3 seconds
Started	Jul 31 05:21:28 PM PDT 24
Finished	Jul 31 05:36:35 PM PDT 24
Peak memory	284268 kb
Host	smart-75bf1440-374f-4f38-94ba-08df2db2be7f
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377050526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_han dler_stress_all.377050526
Directory	/workspace/10.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/15.alert_handler_sig_int_fail.4139108444
Short name	T66
Test name
Test status
Simulation time	1536137207 ps
CPU time	23.23 seconds
Started	Jul 31 05:21:55 PM PDT 24
Finished	Jul 31 05:22:18 PM PDT 24
Peak memory	256536 kb
Host	smart-081e2988-2bbf-4f33-bf62-c72fc4d48b05
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41391 08444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.4139108444
Directory	/workspace/15.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.3046382443
Short name	T188
Test name
Test status
Simulation time	81129839381 ps
CPU time	4027.46 seconds
Started	Jul 31 05:21:43 PM PDT 24
Finished	Jul 31 06:28:51 PM PDT 24
Peak memory	337944 kb
Host	smart-6f370834-f643-42a9-8f2e-c8f820bae432
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046382443 -assert nopostproc +UVM_TESTNAME=aler t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.3046382443
Directory	/workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/21.alert_handler_random_classes.933993848
Short name	T45
Test name
Test status
Simulation time	501214985 ps
CPU time	27.8 seconds
Started	Jul 31 05:22:04 PM PDT 24
Finished	Jul 31 05:22:32 PM PDT 24
Peak memory	248296 kb
Host	smart-d7760549-52d7-47df-a7ff-8d075bda60a5
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93399 3848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.933993848
Directory	/workspace/21.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/22.alert_handler_random_classes.1115798615
Short name	T269
Test name
Test status
Simulation time	1415888193 ps
CPU time	21.59 seconds
Started	Jul 31 05:22:16 PM PDT 24
Finished	Jul 31 05:22:38 PM PDT 24
Peak memory	247764 kb
Host	smart-55d1da82-74e7-4805-88d0-1e005bd73442
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11157 98615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.1115798615
Directory	/workspace/22.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/24.alert_handler_esc_alert_accum.3232048552
Short name	T296
Test name
Test status
Simulation time	1389141824 ps
CPU time	116.86 seconds
Started	Jul 31 05:22:23 PM PDT 24
Finished	Jul 31 05:24:20 PM PDT 24
Peak memory	256460 kb
Host	smart-180cb83e-2e8a-4956-9663-0bd01b14852d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32320 48552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.3232048552
Directory	/workspace/24.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/25.alert_handler_sig_int_fail.2999403602
Short name	T262
Test name
Test status
Simulation time	85628690 ps
CPU time	5.83 seconds
Started	Jul 31 05:22:02 PM PDT 24
Finished	Jul 31 05:22:08 PM PDT 24
Peak memory	240120 kb
Host	smart-433ba143-b69a-4116-97c2-9081e29e10ae
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29994 03602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.2999403602
Directory	/workspace/25.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/35.alert_handler_lpg.3391688992
Short name	T330
Test name
Test status
Simulation time	27049049916 ps
CPU time	739.67 seconds
Started	Jul 31 05:22:37 PM PDT 24
Finished	Jul 31 05:34:57 PM PDT 24
Peak memory	272044 kb
Host	smart-8298e4f3-4be5-4026-822d-3520c35c12e1
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3391688992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.3391688992
Directory	/workspace/35.alert_handler_lpg/latest

Test location	/workspace/coverage/default/35.alert_handler_sig_int_fail.4294316547
Short name	T271
Test name
Test status
Simulation time	1518085180 ps
CPU time	30.04 seconds
Started	Jul 31 05:22:24 PM PDT 24
Finished	Jul 31 05:22:55 PM PDT 24
Peak memory	255336 kb
Host	smart-62df178b-1dbf-4c8f-8846-83137d233fe4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42943 16547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.4294316547
Directory	/workspace/35.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/35.alert_handler_stress_all.4166795538
Short name	T108
Test name
Test status
Simulation time	147935241650 ps
CPU time	2121.84 seconds
Started	Jul 31 05:22:23 PM PDT 24
Finished	Jul 31 05:57:45 PM PDT 24
Peak memory	285088 kb
Host	smart-93d4a049-a775-415f-b01a-77c18da181f1
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166795538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha ndler_stress_all.4166795538
Directory	/workspace/35.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/38.alert_handler_sig_int_fail.3931458345
Short name	T106
Test name
Test status
Simulation time	1300192852 ps
CPU time	43.89 seconds
Started	Jul 31 05:22:33 PM PDT 24
Finished	Jul 31 05:23:17 PM PDT 24
Peak memory	248692 kb
Host	smart-d0294ad1-54ea-4eeb-82ca-3b637a20e559
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39314 58345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.3931458345
Directory	/workspace/38.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/38.alert_handler_stress_all.2838209334
Short name	T258
Test name
Test status
Simulation time	26998549469 ps
CPU time	1791.36 seconds
Started	Jul 31 05:22:33 PM PDT 24
Finished	Jul 31 05:52:25 PM PDT 24
Peak memory	283320 kb
Host	smart-0623df31-3ff2-4eee-9ab7-2d1c765f35d7
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838209334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha ndler_stress_all.2838209334
Directory	/workspace/38.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/0.alert_handler_sec_cm.2096817229
Short name	T34
Test name
Test status
Simulation time	695846278 ps
CPU time	11.81 seconds
Started	Jul 31 05:20:59 PM PDT 24
Finished	Jul 31 05:21:11 PM PDT 24
Peak memory	270772 kb
Host	smart-d5953a60-de32-4849-baed-57dd66351305
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2096817229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.2096817229
Directory	/workspace/0.alert_handler_sec_cm/latest

Test location	/workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.1418831136
Short name	T165
Test name
Test status
Simulation time	1271810643 ps
CPU time	40.63 seconds
Started	Jul 31 05:20:41 PM PDT 24
Finished	Jul 31 05:21:22 PM PDT 24
Peak memory	237880 kb
Host	smart-8ddb65ed-b8db-413b-95d7-0e31f5b6125f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1418831136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.1418831136
Directory	/workspace/12.alert_handler_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.211829099
Short name	T142
Test name
Test status
Simulation time	8341092598 ps
CPU time	657.18 seconds
Started	Jul 31 05:20:52 PM PDT 24
Finished	Jul 31 05:31:49 PM PDT 24
Peak memory	265632 kb
Host	smart-4ac5975b-767f-4679-8de3-61c25a94b0e9
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211829099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM _TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.211829099
Directory	/workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.2816417875
Short name	T155
Test name
Test status
Simulation time	169620836 ps
CPU time	3.68 seconds
Started	Jul 31 05:20:57 PM PDT 24
Finished	Jul 31 05:21:01 PM PDT 24
Peak memory	237692 kb
Host	smart-7e432a8d-51d6-4b67-9b3a-0c1c36223c2b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2816417875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.2816417875
Directory	/workspace/15.alert_handler_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.3400262103
Short name	T115
Test name
Test status
Simulation time	3184612337 ps
CPU time	191.72 seconds
Started	Jul 31 05:20:52 PM PDT 24
Finished	Jul 31 05:24:04 PM PDT 24
Peak memory	265448 kb
Host	smart-d0ce491a-d80c-46b7-abcb-c0bb646e80f7
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3400262103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err ors.3400262103
Directory	/workspace/18.alert_handler_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.331305457
Short name	T164
Test name
Test status
Simulation time	1211049324 ps
CPU time	37.77 seconds
Started	Jul 31 05:20:41 PM PDT 24
Finished	Jul 31 05:21:19 PM PDT 24
Peak memory	240640 kb
Host	smart-73d677aa-371d-471f-be66-1769febf7b9e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=331305457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.331305457
Directory	/workspace/0.alert_handler_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.3111338314
Short name	T168
Test name
Test status
Simulation time	155938859 ps
CPU time	23.44 seconds
Started	Jul 31 05:21:22 PM PDT 24
Finished	Jul 31 05:21:45 PM PDT 24
Peak memory	248860 kb
Host	smart-c2393817-28fe-4dac-b32b-f5978edd7ecd
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3111338314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.3111338314
Directory	/workspace/17.alert_handler_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.2254383747
Short name	T159
Test name
Test status
Simulation time	625740721 ps
CPU time	3.69 seconds
Started	Jul 31 05:20:38 PM PDT 24
Finished	Jul 31 05:20:42 PM PDT 24
Peak memory	237660 kb
Host	smart-bd088658-cc7e-45f8-917f-7cef196ed2ae
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2254383747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.2254383747
Directory	/workspace/2.alert_handler_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.2433155500
Short name	T122
Test name
Test status
Simulation time	827751155 ps
CPU time	90.61 seconds
Started	Jul 31 05:20:38 PM PDT 24
Finished	Jul 31 05:22:08 PM PDT 24
Peak memory	265256 kb
Host	smart-9de1721b-97fc-44e8-bbb3-ea87364e9231
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2433155500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro rs.2433155500
Directory	/workspace/1.alert_handler_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.2310689924
Short name	T162
Test name
Test status
Simulation time	57559084 ps
CPU time	2.09 seconds
Started	Jul 31 05:20:57 PM PDT 24
Finished	Jul 31 05:20:59 PM PDT 24
Peak memory	236832 kb
Host	smart-17b65142-1a52-4820-b7d6-cd6540eb4def
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2310689924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.2310689924
Directory	/workspace/13.alert_handler_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.1159801848
Short name	T148
Test name
Test status
Simulation time	20666047667 ps
CPU time	702.95 seconds
Started	Jul 31 05:20:44 PM PDT 24
Finished	Jul 31 05:32:27 PM PDT 24
Peak memory	265740 kb
Host	smart-86e799ad-45d1-4915-8707-2d5aa5310b06
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159801848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.1159801848
Directory	/workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.659756968
Short name	T160
Test name
Test status
Simulation time	370274255 ps
CPU time	49.07 seconds
Started	Jul 31 05:20:49 PM PDT 24
Finished	Jul 31 05:21:38 PM PDT 24
Peak memory	246008 kb
Host	smart-c17745a1-0339-4633-b052-11059c3b8b6d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=659756968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.659756968
Directory	/workspace/4.alert_handler_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.1897145570
Short name	T167
Test name
Test status
Simulation time	6140528200 ps
CPU time	67.82 seconds
Started	Jul 31 05:20:50 PM PDT 24
Finished	Jul 31 05:21:58 PM PDT 24
Peak memory	240668 kb
Host	smart-61819882-2424-4454-849b-0ebf17ddbe10
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1897145570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.1897145570
Directory	/workspace/6.alert_handler_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.1746262829
Short name	T131
Test name
Test status
Simulation time	23480243214 ps
CPU time	407.08 seconds
Started	Jul 31 05:20:44 PM PDT 24
Finished	Jul 31 05:27:31 PM PDT 24
Peak memory	266704 kb
Host	smart-70ccd111-9b91-4731-bbfe-e86180d570f5
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1746262829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro rs.1746262829
Directory	/workspace/8.alert_handler_shadow_reg_errors/latest

Test location	/workspace/coverage/default/0.alert_handler_esc_alert_accum.3564970423
Short name	T15
Test name
Test status
Simulation time	14992266815 ps
CPU time	232.13 seconds
Started	Jul 31 05:20:49 PM PDT 24
Finished	Jul 31 05:24:41 PM PDT 24
Peak memory	255700 kb
Host	smart-51c90dc8-3539-4da1-a2db-053b2878a975
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35649 70423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.3564970423
Directory	/workspace/0.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.2600820955
Short name	T163
Test name
Test status
Simulation time	138750306 ps
CPU time	6.63 seconds
Started	Jul 31 05:20:55 PM PDT 24
Finished	Jul 31 05:21:02 PM PDT 24
Peak memory	237444 kb
Host	smart-d6c3e71c-4e5f-4113-ba09-8d6636eae891
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2600820955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.2600820955
Directory	/workspace/10.alert_handler_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.3640737561
Short name	T166
Test name
Test status
Simulation time	108971993 ps
CPU time	3.88 seconds
Started	Jul 31 05:20:49 PM PDT 24
Finished	Jul 31 05:20:52 PM PDT 24
Peak memory	236824 kb
Host	smart-d32b8b9f-28ee-4c2e-8cbc-5360deb51018
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3640737561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.3640737561
Directory	/workspace/11.alert_handler_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.1249927899
Short name	T174
Test name
Test status
Simulation time	2496098091 ps
CPU time	42.39 seconds
Started	Jul 31 05:21:02 PM PDT 24
Finished	Jul 31 05:21:45 PM PDT 24
Peak memory	237880 kb
Host	smart-35e8a535-5fea-4cf2-a1d6-eb7c21275002
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1249927899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.1249927899
Directory	/workspace/14.alert_handler_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.2434650283
Short name	T173
Test name
Test status
Simulation time	91489900 ps
CPU time	2.5 seconds
Started	Jul 31 05:20:47 PM PDT 24
Finished	Jul 31 05:20:50 PM PDT 24
Peak memory	238664 kb
Host	smart-76abe370-95e8-4abd-a0b7-3f7b016f7a13
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2434650283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.2434650283
Directory	/workspace/9.alert_handler_tl_intg_err/latest

Test location	/workspace/coverage/default/31.alert_handler_esc_intr_timeout.3287826501
Short name	T27
Test name
Test status
Simulation time	1794331060 ps
CPU time	56.34 seconds
Started	Jul 31 05:22:30 PM PDT 24
Finished	Jul 31 05:23:26 PM PDT 24
Peak memory	248396 kb
Host	smart-bd4f7167-bd8b-479d-99d0-bd04f2da4c02
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32878 26501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.3287826501
Directory	/workspace/31.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.1775570265
Short name	T195
Test name
Test status
Simulation time	18020301934 ps
CPU time	141.73 seconds
Started	Jul 31 05:20:41 PM PDT 24
Finished	Jul 31 05:23:03 PM PDT 24
Peak memory	240752 kb
Host	smart-a6ccbdfa-a55c-4e11-8f95-0808b5349ff6
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1775570265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.1775570265
Directory	/workspace/0.alert_handler_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.3366432130
Short name	T786
Test name
Test status
Simulation time	22786792624 ps
CPU time	366.23 seconds
Started	Jul 31 05:20:39 PM PDT 24
Finished	Jul 31 05:26:45 PM PDT 24
Peak memory	236940 kb
Host	smart-8ca46a7c-64ad-496c-96a6-1d4e6a59a784
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3366432130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.3366432130
Directory	/workspace/0.alert_handler_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.422776727
Short name	T777
Test name
Test status
Simulation time	40438624 ps
CPU time	5.71 seconds
Started	Jul 31 05:20:48 PM PDT 24
Finished	Jul 31 05:20:53 PM PDT 24
Peak memory	240608 kb
Host	smart-3a970579-dca0-4736-a2f6-816d1748fb0f
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=422776727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.422776727
Directory	/workspace/0.alert_handler_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.226796260
Short name	T197
Test name
Test status
Simulation time	31468210 ps
CPU time	5.09 seconds
Started	Jul 31 05:20:51 PM PDT 24
Finished	Jul 31 05:20:57 PM PDT 24
Peak memory	256996 kb
Host	smart-ecf3e436-985c-4198-b36b-bb32350bc4b8
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226796260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 0.alert_handler_csr_mem_rw_with_rand_reset.226796260
Directory	/workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.925933231
Short name	T823
Test name
Test status
Simulation time	98405481 ps
CPU time	6.99 seconds
Started	Jul 31 05:20:39 PM PDT 24
Finished	Jul 31 05:20:46 PM PDT 24
Peak memory	236768 kb
Host	smart-40eddb7d-5b6d-4c6a-9d49-ba45f58b082d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=925933231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.925933231
Directory	/workspace/0.alert_handler_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.alert_handler_intr_test.928110845
Short name	T345
Test name
Test status
Simulation time	12242152 ps
CPU time	1.51 seconds
Started	Jul 31 05:20:23 PM PDT 24
Finished	Jul 31 05:20:25 PM PDT 24
Peak memory	236800 kb
Host	smart-6fe91772-9669-453a-9866-e3edb66bf3bd
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=928110845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.928110845
Directory	/workspace/0.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.524642130
Short name	T171
Test name
Test status
Simulation time	330053116 ps
CPU time	10.49 seconds
Started	Jul 31 05:20:45 PM PDT 24
Finished	Jul 31 05:21:01 PM PDT 24
Peak memory	245024 kb
Host	smart-8ea3b263-23d0-4daf-8f00-1568a8c2a4da
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=524642130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_outs tanding.524642130
Directory	/workspace/0.alert_handler_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.1721498829
Short name	T129
Test name
Test status
Simulation time	2063279041 ps
CPU time	151.82 seconds
Started	Jul 31 05:20:37 PM PDT 24
Finished	Jul 31 05:23:09 PM PDT 24
Peak memory	265496 kb
Host	smart-e03f1f9c-2fc2-40f6-ab7b-3a427f174e2a
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1721498829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro rs.1721498829
Directory	/workspace/0.alert_handler_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.3708764621
Short name	T787
Test name
Test status
Simulation time	298600983 ps
CPU time	9 seconds
Started	Jul 31 05:20:36 PM PDT 24
Finished	Jul 31 05:20:45 PM PDT 24
Peak memory	248264 kb
Host	smart-f52ffb17-3e43-4cac-854e-3a19adf7c162
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3708764621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.3708764621
Directory	/workspace/0.alert_handler_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.3741612991
Short name	T822
Test name
Test status
Simulation time	803537493 ps
CPU time	71.78 seconds
Started	Jul 31 05:20:49 PM PDT 24
Finished	Jul 31 05:22:01 PM PDT 24
Peak memory	240644 kb
Host	smart-414477fc-2b5d-4479-90cd-391868a9ff6d
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3741612991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.3741612991
Directory	/workspace/1.alert_handler_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.3797481060
Short name	T790
Test name
Test status
Simulation time	857855194 ps
CPU time	105.92 seconds
Started	Jul 31 05:20:40 PM PDT 24
Finished	Jul 31 05:22:27 PM PDT 24
Peak memory	237756 kb
Host	smart-73a76690-1fed-402d-b922-a7967b79f81a
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3797481060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.3797481060
Directory	/workspace/1.alert_handler_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.1019965622
Short name	T732
Test name
Test status
Simulation time	77583448 ps
CPU time	3.25 seconds
Started	Jul 31 05:21:05 PM PDT 24
Finished	Jul 31 05:21:08 PM PDT 24
Peak memory	248828 kb
Host	smart-0c36133d-7528-4cc7-9457-6086e2e24400
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1019965622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.1019965622
Directory	/workspace/1.alert_handler_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.2624973079
Short name	T730
Test name
Test status
Simulation time	281090475 ps
CPU time	7.09 seconds
Started	Jul 31 05:20:46 PM PDT 24
Finished	Jul 31 05:20:53 PM PDT 24
Peak memory	239964 kb
Host	smart-0faebf45-77ce-4b3c-878a-0bcd44e3f6a6
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624973079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 1.alert_handler_csr_mem_rw_with_rand_reset.2624973079
Directory	/workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.1877620383
Short name	T194
Test name
Test status
Simulation time	19541690 ps
CPU time	3.37 seconds
Started	Jul 31 05:20:46 PM PDT 24
Finished	Jul 31 05:20:50 PM PDT 24
Peak memory	237636 kb
Host	smart-047b45f8-e207-4bb9-9329-874f3257dd9c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=1877620383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.1877620383
Directory	/workspace/1.alert_handler_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.alert_handler_intr_test.1338321325
Short name	T782
Test name
Test status
Simulation time	9368932 ps
CPU time	1.32 seconds
Started	Jul 31 05:21:09 PM PDT 24
Finished	Jul 31 05:21:11 PM PDT 24
Peak memory	237688 kb
Host	smart-c290a083-527c-4a63-9c2d-da81312ac7a9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1338321325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.1338321325
Directory	/workspace/1.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.1820020603
Short name	T748
Test name
Test status
Simulation time	90115894 ps
CPU time	12.76 seconds
Started	Jul 31 05:20:49 PM PDT 24
Finished	Jul 31 05:21:02 PM PDT 24
Peak memory	245920 kb
Host	smart-7d60c6f5-718f-4e1f-9709-2e1e73268159
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1820020603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out standing.1820020603
Directory	/workspace/1.alert_handler_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.513060072
Short name	T139
Test name
Test status
Simulation time	12767246401 ps
CPU time	1018.19 seconds
Started	Jul 31 05:21:22 PM PDT 24
Finished	Jul 31 05:38:20 PM PDT 24
Peak memory	265652 kb
Host	smart-79f41805-d264-40b5-aab2-0f794246c538
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513060072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM _TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.513060072
Directory	/workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.3240528508
Short name	T716
Test name
Test status
Simulation time	100256579 ps
CPU time	10.95 seconds
Started	Jul 31 05:20:47 PM PDT 24
Finished	Jul 31 05:20:58 PM PDT 24
Peak memory	256864 kb
Host	smart-af3a5276-c31a-4922-a60c-bdafbadfbf17
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3240528508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.3240528508
Directory	/workspace/1.alert_handler_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.969638897
Short name	T348
Test name
Test status
Simulation time	31748923 ps
CPU time	4.75 seconds
Started	Jul 31 05:20:51 PM PDT 24
Finished	Jul 31 05:20:56 PM PDT 24
Peak memory	240720 kb
Host	smart-b56e0325-031c-4b1a-aad8-283c2f5f96f4
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969638897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 10.alert_handler_csr_mem_rw_with_rand_reset.969638897
Directory	/workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.3108600577
Short name	T763
Test name
Test status
Simulation time	489191098 ps
CPU time	9.81 seconds
Started	Jul 31 05:20:54 PM PDT 24
Finished	Jul 31 05:21:04 PM PDT 24
Peak memory	237724 kb
Host	smart-8286d8ab-4ed1-469d-979a-9ab99d6ebfdd
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=3108600577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.3108600577
Directory	/workspace/10.alert_handler_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.alert_handler_intr_test.1214326957
Short name	T762
Test name
Test status
Simulation time	9794908 ps
CPU time	1.22 seconds
Started	Jul 31 05:20:45 PM PDT 24
Finished	Jul 31 05:20:46 PM PDT 24
Peak memory	237660 kb
Host	smart-1e7d1e52-1187-4824-94eb-d93e9f28c69a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1214326957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.1214326957
Directory	/workspace/10.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.2079386641
Short name	T751
Test name
Test status
Simulation time	516595686 ps
CPU time	43.04 seconds
Started	Jul 31 05:20:46 PM PDT 24
Finished	Jul 31 05:21:29 PM PDT 24
Peak memory	245904 kb
Host	smart-326de54c-4744-49eb-95a4-2e718d835c7b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2079386641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou tstanding.2079386641
Directory	/workspace/10.alert_handler_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.2474047649
Short name	T117
Test name
Test status
Simulation time	2298517906 ps
CPU time	232.16 seconds
Started	Jul 31 05:20:50 PM PDT 24
Finished	Jul 31 05:24:42 PM PDT 24
Peak memory	265612 kb
Host	smart-21c1886a-28e7-477b-83bc-63ad12b2545d
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2474047649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err ors.2474047649
Directory	/workspace/10.alert_handler_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.2267118731
Short name	T736
Test name
Test status
Simulation time	138683402 ps
CPU time	5.08 seconds
Started	Jul 31 05:21:00 PM PDT 24
Finished	Jul 31 05:21:06 PM PDT 24
Peak memory	249904 kb
Host	smart-58a2fdcb-02fd-442c-93b4-c5adc8732033
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2267118731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.2267118731
Directory	/workspace/10.alert_handler_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.769770884
Short name	T808
Test name
Test status
Simulation time	75823808 ps
CPU time	6.45 seconds
Started	Jul 31 05:21:00 PM PDT 24
Finished	Jul 31 05:21:06 PM PDT 24
Peak memory	240656 kb
Host	smart-fa39e2d3-a571-4e03-925b-31e64bf10630
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769770884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 11.alert_handler_csr_mem_rw_with_rand_reset.769770884
Directory	/workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.25497295
Short name	T760
Test name
Test status
Simulation time	57901743 ps
CPU time	3.7 seconds
Started	Jul 31 05:20:53 PM PDT 24
Finished	Jul 31 05:20:57 PM PDT 24
Peak memory	237700 kb
Host	smart-efe9d900-471a-4b20-94cf-bba3fd008538
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=25497295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.25497295
Directory	/workspace/11.alert_handler_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.1214451147
Short name	T778
Test name
Test status
Simulation time	173769276 ps
CPU time	22.77 seconds
Started	Jul 31 05:20:46 PM PDT 24
Finished	Jul 31 05:21:09 PM PDT 24
Peak memory	244992 kb
Host	smart-0e158f29-a529-4149-8248-00d9c643e3bc
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1214451147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou tstanding.1214451147
Directory	/workspace/11.alert_handler_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.2092988913
Short name	T151
Test name
Test status
Simulation time	765127649 ps
CPU time	86.41 seconds
Started	Jul 31 05:20:45 PM PDT 24
Finished	Jul 31 05:22:12 PM PDT 24
Peak memory	265600 kb
Host	smart-1f6d3b00-9838-4ea3-9cba-c8c204a051c0
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2092988913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err ors.2092988913
Directory	/workspace/11.alert_handler_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.635994711
Short name	T793
Test name
Test status
Simulation time	156192771 ps
CPU time	12.03 seconds
Started	Jul 31 05:20:45 PM PDT 24
Finished	Jul 31 05:20:58 PM PDT 24
Peak memory	248856 kb
Host	smart-713588f0-1a71-473f-ada6-5918ed29ecf8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=635994711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.635994711
Directory	/workspace/11.alert_handler_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.1423659508
Short name	T758
Test name
Test status
Simulation time	61227325 ps
CPU time	8.75 seconds
Started	Jul 31 05:20:47 PM PDT 24
Finished	Jul 31 05:20:56 PM PDT 24
Peak memory	256920 kb
Host	smart-4dfca8b0-398d-481b-b768-93bd23198c8e
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423659508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 12.alert_handler_csr_mem_rw_with_rand_reset.1423659508
Directory	/workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.2188793719
Short name	T799
Test name
Test status
Simulation time	90788273 ps
CPU time	4.58 seconds
Started	Jul 31 05:20:51 PM PDT 24
Finished	Jul 31 05:20:55 PM PDT 24
Peak memory	240524 kb
Host	smart-b26fa798-defa-46e1-af14-2c2f86bb70f1
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=2188793719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.2188793719
Directory	/workspace/12.alert_handler_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.alert_handler_intr_test.524819622
Short name	T729
Test name
Test status
Simulation time	7407121 ps
CPU time	1.44 seconds
Started	Jul 31 05:20:46 PM PDT 24
Finished	Jul 31 05:20:48 PM PDT 24
Peak memory	235728 kb
Host	smart-85bf477a-c9d0-40f5-9ec4-f2183ec3e50b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=524819622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.524819622
Directory	/workspace/12.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.514073338
Short name	T726
Test name
Test status
Simulation time	425603798 ps
CPU time	21.07 seconds
Started	Jul 31 05:21:19 PM PDT 24
Finished	Jul 31 05:21:40 PM PDT 24
Peak memory	248836 kb
Host	smart-acfe9fc8-1335-4a53-a803-0c499886f79c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=514073338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_out standing.514073338
Directory	/workspace/12.alert_handler_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.309230418
Short name	T133
Test name
Test status
Simulation time	13046709123 ps
CPU time	511.53 seconds
Started	Jul 31 05:20:52 PM PDT 24
Finished	Jul 31 05:29:24 PM PDT 24
Peak memory	265652 kb
Host	smart-b2741e6d-e1bb-46de-aba3-05b5656a0356
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309230418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM _TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.309230418
Directory	/workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.3491229673
Short name	T809
Test name
Test status
Simulation time	302270672 ps
CPU time	17.3 seconds
Started	Jul 31 05:20:39 PM PDT 24
Finished	Jul 31 05:20:56 PM PDT 24
Peak memory	248168 kb
Host	smart-867fb176-ce02-4530-a9f1-d0ef52c10d6b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3491229673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.3491229673
Directory	/workspace/12.alert_handler_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.3626999401
Short name	T739
Test name
Test status
Simulation time	37792736 ps
CPU time	5.7 seconds
Started	Jul 31 05:21:19 PM PDT 24
Finished	Jul 31 05:21:25 PM PDT 24
Peak memory	239980 kb
Host	smart-9578849b-8419-4d2f-8090-b18fc29fb07e
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626999401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 13.alert_handler_csr_mem_rw_with_rand_reset.3626999401
Directory	/workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.2990054660
Short name	T824
Test name
Test status
Simulation time	49514992 ps
CPU time	4.57 seconds
Started	Jul 31 05:21:08 PM PDT 24
Finished	Jul 31 05:21:12 PM PDT 24
Peak memory	240432 kb
Host	smart-aecf9612-ff5d-4ff0-b603-7fe35e4941f0
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=2990054660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.2990054660
Directory	/workspace/13.alert_handler_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.alert_handler_intr_test.3377474905
Short name	T795
Test name
Test status
Simulation time	25804346 ps
CPU time	1.48 seconds
Started	Jul 31 05:20:52 PM PDT 24
Finished	Jul 31 05:20:53 PM PDT 24
Peak memory	237724 kb
Host	smart-45e4051d-d102-4f7b-8523-098d471d5620
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3377474905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.3377474905
Directory	/workspace/13.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.2880421349
Short name	T189
Test name
Test status
Simulation time	98122418 ps
CPU time	12.75 seconds
Started	Jul 31 05:21:04 PM PDT 24
Finished	Jul 31 05:21:17 PM PDT 24
Peak memory	245916 kb
Host	smart-aa75fb23-215d-414b-bcba-1c790c1491e3
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2880421349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou tstanding.2880421349
Directory	/workspace/13.alert_handler_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.1805363069
Short name	T143
Test name
Test status
Simulation time	1465832605 ps
CPU time	104.38 seconds
Started	Jul 31 05:20:48 PM PDT 24
Finished	Jul 31 05:22:33 PM PDT 24
Peak memory	256996 kb
Host	smart-e992132b-0a95-4988-b0d1-b7ee1857cce9
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1805363069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err ors.1805363069
Directory	/workspace/13.alert_handler_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.1185333784
Short name	T779
Test name
Test status
Simulation time	29967286 ps
CPU time	4.08 seconds
Started	Jul 31 05:20:50 PM PDT 24
Finished	Jul 31 05:20:54 PM PDT 24
Peak memory	248884 kb
Host	smart-648c2d2f-cbfb-44d1-a8fa-a6d8f225f0d7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1185333784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.1185333784
Directory	/workspace/13.alert_handler_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.2036867437
Short name	T813
Test name
Test status
Simulation time	103158912 ps
CPU time	4.39 seconds
Started	Jul 31 05:21:04 PM PDT 24
Finished	Jul 31 05:21:08 PM PDT 24
Peak memory	240524 kb
Host	smart-b45d33a0-090c-4967-9592-08957ce8d53f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036867437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 14.alert_handler_csr_mem_rw_with_rand_reset.2036867437
Directory	/workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.2333301334
Short name	T764
Test name
Test status
Simulation time	96809727 ps
CPU time	8.17 seconds
Started	Jul 31 05:20:58 PM PDT 24
Finished	Jul 31 05:21:06 PM PDT 24
Peak memory	240668 kb
Host	smart-5f452e2a-d1b6-4d1f-a160-3894e36cbcea
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=2333301334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.2333301334
Directory	/workspace/14.alert_handler_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.alert_handler_intr_test.3662389231
Short name	T765
Test name
Test status
Simulation time	10308666 ps
CPU time	1.54 seconds
Started	Jul 31 05:21:23 PM PDT 24
Finished	Jul 31 05:21:25 PM PDT 24
Peak memory	236532 kb
Host	smart-cf1b928b-476c-4b47-aada-5d785f3d04a2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3662389231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.3662389231
Directory	/workspace/14.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.4250889659
Short name	T190
Test name
Test status
Simulation time	511974270 ps
CPU time	38.99 seconds
Started	Jul 31 05:20:52 PM PDT 24
Finished	Jul 31 05:21:31 PM PDT 24
Peak memory	248856 kb
Host	smart-7d946c1b-29a8-42ed-b31b-7553add87212
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4250889659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou tstanding.4250889659
Directory	/workspace/14.alert_handler_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.1080526712
Short name	T146
Test name
Test status
Simulation time	3224942820 ps
CPU time	113.37 seconds
Started	Jul 31 05:20:51 PM PDT 24
Finished	Jul 31 05:22:45 PM PDT 24
Peak memory	257328 kb
Host	smart-366934ac-5087-47f6-9671-d6c3eb5081c0
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1080526712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err ors.1080526712
Directory	/workspace/14.alert_handler_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.4273795939
Short name	T136
Test name
Test status
Simulation time	27846437098 ps
CPU time	593.73 seconds
Started	Jul 31 05:20:46 PM PDT 24
Finished	Jul 31 05:30:40 PM PDT 24
Peak memory	265644 kb
Host	smart-a66f9ac4-0f8e-4cc2-870b-8667d4c96001
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273795939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.4273795939
Directory	/workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.2274766433
Short name	T805
Test name
Test status
Simulation time	765559343 ps
CPU time	26.8 seconds
Started	Jul 31 05:20:41 PM PDT 24
Finished	Jul 31 05:21:08 PM PDT 24
Peak memory	255704 kb
Host	smart-46a42a91-9e82-4cb9-9c7c-2cd1614efbbb
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2274766433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.2274766433
Directory	/workspace/14.alert_handler_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.4053635019
Short name	T776
Test name
Test status
Simulation time	29817168 ps
CPU time	4.95 seconds
Started	Jul 31 05:21:25 PM PDT 24
Finished	Jul 31 05:21:30 PM PDT 24
Peak memory	240124 kb
Host	smart-6ad19e11-f1d0-40cf-9b04-4c0c8cf2ec19
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053635019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 15.alert_handler_csr_mem_rw_with_rand_reset.4053635019
Directory	/workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.3662850626
Short name	T769
Test name
Test status
Simulation time	256769428 ps
CPU time	5.31 seconds
Started	Jul 31 05:20:54 PM PDT 24
Finished	Jul 31 05:20:59 PM PDT 24
Peak memory	237716 kb
Host	smart-8caecc5f-00ca-4352-b2ce-5bc5cf811b54
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=3662850626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.3662850626
Directory	/workspace/15.alert_handler_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.alert_handler_intr_test.2457120320
Short name	T718
Test name
Test status
Simulation time	25025616 ps
CPU time	1.38 seconds
Started	Jul 31 05:21:23 PM PDT 24
Finished	Jul 31 05:21:25 PM PDT 24
Peak memory	237540 kb
Host	smart-ad5db20b-b5de-4efa-a4b6-c3365bd49002
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2457120320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.2457120320
Directory	/workspace/15.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.2723732833
Short name	T767
Test name
Test status
Simulation time	1274463836 ps
CPU time	20.5 seconds
Started	Jul 31 05:20:52 PM PDT 24
Finished	Jul 31 05:21:13 PM PDT 24
Peak memory	248848 kb
Host	smart-0ce39e65-4772-422e-9937-2844e38b1f3a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2723732833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou tstanding.2723732833
Directory	/workspace/15.alert_handler_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.2380086953
Short name	T140
Test name
Test status
Simulation time	1125096615 ps
CPU time	110.07 seconds
Started	Jul 31 05:20:50 PM PDT 24
Finished	Jul 31 05:22:41 PM PDT 24
Peak memory	265572 kb
Host	smart-8f777942-e31f-4ef2-8cec-91ef0de2307b
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2380086953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err ors.2380086953
Directory	/workspace/15.alert_handler_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.3801712727
Short name	T812
Test name
Test status
Simulation time	3451384476 ps
CPU time	16.5 seconds
Started	Jul 31 05:20:59 PM PDT 24
Finished	Jul 31 05:21:16 PM PDT 24
Peak memory	253420 kb
Host	smart-ddffb0a4-7799-4af8-9940-29fdcbe3b799
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3801712727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.3801712727
Directory	/workspace/15.alert_handler_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.1152272904
Short name	T733
Test name
Test status
Simulation time	205297382 ps
CPU time	4.39 seconds
Started	Jul 31 05:20:50 PM PDT 24
Finished	Jul 31 05:20:55 PM PDT 24
Peak memory	257064 kb
Host	smart-570f3a91-e12b-460b-80d9-52ffa6a9231d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152272904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 16.alert_handler_csr_mem_rw_with_rand_reset.1152272904
Directory	/workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.3717593656
Short name	T794
Test name
Test status
Simulation time	608314674 ps
CPU time	8.49 seconds
Started	Jul 31 05:21:12 PM PDT 24
Finished	Jul 31 05:21:24 PM PDT 24
Peak memory	240652 kb
Host	smart-f24ba61d-b592-4e56-b74f-c9bf0d7114ba
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=3717593656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.3717593656
Directory	/workspace/16.alert_handler_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.alert_handler_intr_test.1083370386
Short name	T800
Test name
Test status
Simulation time	8077062 ps
CPU time	1.44 seconds
Started	Jul 31 05:20:56 PM PDT 24
Finished	Jul 31 05:20:58 PM PDT 24
Peak memory	235744 kb
Host	smart-ad03a601-505d-4e1a-b775-1efbe8b251a0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1083370386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.1083370386
Directory	/workspace/16.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.3932756815
Short name	T242
Test name
Test status
Simulation time	1299451297 ps
CPU time	37.41 seconds
Started	Jul 31 05:21:17 PM PDT 24
Finished	Jul 31 05:21:54 PM PDT 24
Peak memory	245736 kb
Host	smart-1bbe9789-128a-4f11-a625-f67d392aba79
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3932756815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou tstanding.3932756815
Directory	/workspace/16.alert_handler_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.2425985680
Short name	T152
Test name
Test status
Simulation time	9665536749 ps
CPU time	178.84 seconds
Started	Jul 31 05:21:00 PM PDT 24
Finished	Jul 31 05:23:59 PM PDT 24
Peak memory	265676 kb
Host	smart-89c3c857-8105-4d22-9756-386801e086f4
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2425985680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err ors.2425985680
Directory	/workspace/16.alert_handler_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.2914435435
Short name	T792
Test name
Test status
Simulation time	689725059 ps
CPU time	13.14 seconds
Started	Jul 31 05:21:09 PM PDT 24
Finished	Jul 31 05:21:23 PM PDT 24
Peak memory	248808 kb
Host	smart-0458a37f-9c66-4349-bd2b-fdfca02894f6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2914435435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.2914435435
Directory	/workspace/16.alert_handler_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.4059776665
Short name	T154
Test name
Test status
Simulation time	357952276 ps
CPU time	2.84 seconds
Started	Jul 31 05:21:03 PM PDT 24
Finished	Jul 31 05:21:06 PM PDT 24
Peak memory	237564 kb
Host	smart-521f28ee-2ead-4886-a78d-ab247eb3b3ce
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=4059776665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.4059776665
Directory	/workspace/16.alert_handler_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.4169307417
Short name	T349
Test name
Test status
Simulation time	137939823 ps
CPU time	8.06 seconds
Started	Jul 31 05:20:47 PM PDT 24
Finished	Jul 31 05:20:55 PM PDT 24
Peak memory	238244 kb
Host	smart-06d65854-3a86-4b99-ad65-30bc7d8ae6f5
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169307417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 17.alert_handler_csr_mem_rw_with_rand_reset.4169307417
Directory	/workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.2026481743
Short name	T172
Test name
Test status
Simulation time	154836621 ps
CPU time	3.36 seconds
Started	Jul 31 05:20:50 PM PDT 24
Finished	Jul 31 05:20:53 PM PDT 24
Peak memory	240560 kb
Host	smart-fe057808-728a-49d0-9d78-38e015db2194
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=2026481743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.2026481743
Directory	/workspace/17.alert_handler_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.alert_handler_intr_test.21413113
Short name	T796
Test name
Test status
Simulation time	11944261 ps
CPU time	1.39 seconds
Started	Jul 31 05:21:03 PM PDT 24
Finished	Jul 31 05:21:05 PM PDT 24
Peak memory	237716 kb
Host	smart-ee81cd50-50de-4777-a1db-a973f6f3abf7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=21413113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.21413113
Directory	/workspace/17.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.3683267749
Short name	T249
Test name
Test status
Simulation time	1239960839 ps
CPU time	40.48 seconds
Started	Jul 31 05:20:45 PM PDT 24
Finished	Jul 31 05:21:26 PM PDT 24
Peak memory	245016 kb
Host	smart-7e04966f-0005-4e32-b203-199f5016a91f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3683267749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou tstanding.3683267749
Directory	/workspace/17.alert_handler_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.1443858427
Short name	T145
Test name
Test status
Simulation time	18203021994 ps
CPU time	154.31 seconds
Started	Jul 31 05:21:06 PM PDT 24
Finished	Jul 31 05:23:41 PM PDT 24
Peak memory	265668 kb
Host	smart-5b1bf393-01dc-4e62-9fab-aa7943e3330a
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1443858427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err ors.1443858427
Directory	/workspace/17.alert_handler_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.3348290159
Short name	T724
Test name
Test status
Simulation time	349400498 ps
CPU time	11.48 seconds
Started	Jul 31 05:20:55 PM PDT 24
Finished	Jul 31 05:21:06 PM PDT 24
Peak memory	248648 kb
Host	smart-0523fba8-b292-4d28-8761-cc109d58ab53
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3348290159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.3348290159
Directory	/workspace/17.alert_handler_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.2715201698
Short name	T775
Test name
Test status
Simulation time	307395293 ps
CPU time	4.62 seconds
Started	Jul 31 05:20:47 PM PDT 24
Finished	Jul 31 05:20:57 PM PDT 24
Peak memory	248932 kb
Host	smart-9fa17384-cad1-41db-b7f5-df5306132895
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715201698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 18.alert_handler_csr_mem_rw_with_rand_reset.2715201698
Directory	/workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.2066564280
Short name	T766
Test name
Test status
Simulation time	33618512 ps
CPU time	5.47 seconds
Started	Jul 31 05:21:14 PM PDT 24
Finished	Jul 31 05:21:20 PM PDT 24
Peak memory	237532 kb
Host	smart-cf986a16-3c58-46aa-a29c-dd2878086d68
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=2066564280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.2066564280
Directory	/workspace/18.alert_handler_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.alert_handler_intr_test.2230300949
Short name	T780
Test name
Test status
Simulation time	23187886 ps
CPU time	2.01 seconds
Started	Jul 31 05:21:14 PM PDT 24
Finished	Jul 31 05:21:17 PM PDT 24
Peak memory	237516 kb
Host	smart-9714fe76-6074-4ef9-9012-6d6399f85522
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2230300949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.2230300949
Directory	/workspace/18.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.1439127131
Short name	T755
Test name
Test status
Simulation time	180808183 ps
CPU time	18.55 seconds
Started	Jul 31 05:21:14 PM PDT 24
Finished	Jul 31 05:21:33 PM PDT 24
Peak memory	248808 kb
Host	smart-6c51dd21-c4bd-4cf8-aa1f-fdf5f18d6a85
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1439127131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou tstanding.1439127131
Directory	/workspace/18.alert_handler_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.2606425262
Short name	T130
Test name
Test status
Simulation time	30640712084 ps
CPU time	1134.01 seconds
Started	Jul 31 05:20:43 PM PDT 24
Finished	Jul 31 05:39:37 PM PDT 24
Peak memory	265568 kb
Host	smart-84e11162-0d65-4a12-8615-872a6f4d5e44
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606425262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.2606425262
Directory	/workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.528540644
Short name	T715
Test name
Test status
Simulation time	130677003 ps
CPU time	5.38 seconds
Started	Jul 31 05:20:53 PM PDT 24
Finished	Jul 31 05:20:59 PM PDT 24
Peak memory	249024 kb
Host	smart-5bb401a4-6069-48aa-9046-790008134d5d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=528540644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.528540644
Directory	/workspace/18.alert_handler_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.2193323508
Short name	T161
Test name
Test status
Simulation time	679054334 ps
CPU time	46.49 seconds
Started	Jul 31 05:21:05 PM PDT 24
Finished	Jul 31 05:21:51 PM PDT 24
Peak memory	240596 kb
Host	smart-2533debe-2810-46e5-831d-cf55312d988d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2193323508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.2193323508
Directory	/workspace/18.alert_handler_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.1214607819
Short name	T350
Test name
Test status
Simulation time	236286486 ps
CPU time	8.53 seconds
Started	Jul 31 05:20:47 PM PDT 24
Finished	Jul 31 05:20:56 PM PDT 24
Peak memory	248920 kb
Host	smart-417d31d4-d4ea-43c1-b4b6-85cb8127471c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214607819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 19.alert_handler_csr_mem_rw_with_rand_reset.1214607819
Directory	/workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.1161787380
Short name	T198
Test name
Test status
Simulation time	356560592 ps
CPU time	4.93 seconds
Started	Jul 31 05:21:07 PM PDT 24
Finished	Jul 31 05:21:12 PM PDT 24
Peak memory	240648 kb
Host	smart-27d79242-276c-468b-b228-4ccc5afdcb00
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=1161787380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.1161787380
Directory	/workspace/19.alert_handler_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.alert_handler_intr_test.3651009378
Short name	T817
Test name
Test status
Simulation time	12139096 ps
CPU time	1.37 seconds
Started	Jul 31 05:21:00 PM PDT 24
Finished	Jul 31 05:21:02 PM PDT 24
Peak memory	236844 kb
Host	smart-46abc472-650c-4db7-ad56-7d51f43fa234
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3651009378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.3651009378
Directory	/workspace/19.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.3808040999
Short name	T768
Test name
Test status
Simulation time	2674660029 ps
CPU time	44.37 seconds
Started	Jul 31 05:20:46 PM PDT 24
Finished	Jul 31 05:21:31 PM PDT 24
Peak memory	246156 kb
Host	smart-5b2a8e69-3b08-4cd7-afa9-6448ba7dc9ea
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3808040999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou tstanding.3808040999
Directory	/workspace/19.alert_handler_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.3156406743
Short name	T118
Test name
Test status
Simulation time	2041986900 ps
CPU time	171.01 seconds
Started	Jul 31 05:21:20 PM PDT 24
Finished	Jul 31 05:24:11 PM PDT 24
Peak memory	265564 kb
Host	smart-a9780066-2318-4e86-8825-e7a5bb5fd22e
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3156406743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err ors.3156406743
Directory	/workspace/19.alert_handler_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.1863349653
Short name	T352
Test name
Test status
Simulation time	12784776523 ps
CPU time	419.49 seconds
Started	Jul 31 05:21:15 PM PDT 24
Finished	Jul 31 05:28:14 PM PDT 24
Peak memory	265564 kb
Host	smart-39e7773a-d955-41be-ab3b-c2c22602440d
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863349653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.1863349653
Directory	/workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.3700513569
Short name	T721
Test name
Test status
Simulation time	58675047 ps
CPU time	3.6 seconds
Started	Jul 31 05:20:53 PM PDT 24
Finished	Jul 31 05:20:57 PM PDT 24
Peak memory	249072 kb
Host	smart-7f0c784a-fcdd-433a-aaec-6c74ee648a6b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3700513569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.3700513569
Directory	/workspace/19.alert_handler_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.1330962123
Short name	T798
Test name
Test status
Simulation time	46657174 ps
CPU time	3.33 seconds
Started	Jul 31 05:20:52 PM PDT 24
Finished	Jul 31 05:20:56 PM PDT 24
Peak memory	237700 kb
Host	smart-231a29cd-e71a-4a21-ad2c-7a908b8b48b2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1330962123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.1330962123
Directory	/workspace/19.alert_handler_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.1303770255
Short name	T727
Test name
Test status
Simulation time	5273187853 ps
CPU time	72.37 seconds
Started	Jul 31 05:20:44 PM PDT 24
Finished	Jul 31 05:21:56 PM PDT 24
Peak memory	240744 kb
Host	smart-d3bd2031-34d0-42f5-a15a-eb1eaaff8e34
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1303770255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.1303770255
Directory	/workspace/2.alert_handler_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.3729536045
Short name	T784
Test name
Test status
Simulation time	3883956318 ps
CPU time	232.81 seconds
Started	Jul 31 05:20:40 PM PDT 24
Finished	Jul 31 05:24:33 PM PDT 24
Peak memory	236804 kb
Host	smart-d83dccb2-2ab2-4362-8997-906594a50496
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3729536045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.3729536045
Directory	/workspace/2.alert_handler_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.104416430
Short name	T240
Test name
Test status
Simulation time	291317296 ps
CPU time	5.74 seconds
Started	Jul 31 05:20:45 PM PDT 24
Finished	Jul 31 05:20:51 PM PDT 24
Peak memory	240520 kb
Host	smart-78a70bef-f706-4aa8-8be5-a0c1de9f3ce9
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=104416430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.104416430
Directory	/workspace/2.alert_handler_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.3762576430
Short name	T818
Test name
Test status
Simulation time	220592585 ps
CPU time	7.84 seconds
Started	Jul 31 05:20:47 PM PDT 24
Finished	Jul 31 05:20:54 PM PDT 24
Peak memory	238536 kb
Host	smart-5b5af820-ff96-440b-931c-b8e3b7463433
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762576430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 2.alert_handler_csr_mem_rw_with_rand_reset.3762576430
Directory	/workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.1161682482
Short name	T825
Test name
Test status
Simulation time	108846305 ps
CPU time	5.35 seconds
Started	Jul 31 05:20:52 PM PDT 24
Finished	Jul 31 05:20:57 PM PDT 24
Peak memory	237608 kb
Host	smart-73656472-eb31-427e-9389-671f0281cfda
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=1161682482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.1161682482
Directory	/workspace/2.alert_handler_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.alert_handler_intr_test.1175691139
Short name	T737
Test name
Test status
Simulation time	19686713 ps
CPU time	1.38 seconds
Started	Jul 31 05:20:52 PM PDT 24
Finished	Jul 31 05:20:53 PM PDT 24
Peak memory	236860 kb
Host	smart-01fdb825-0251-449d-a227-829d0fc56af3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1175691139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.1175691139
Directory	/workspace/2.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.464308726
Short name	T742
Test name
Test status
Simulation time	1171944146 ps
CPU time	22.53 seconds
Started	Jul 31 05:20:47 PM PDT 24
Finished	Jul 31 05:21:10 PM PDT 24
Peak memory	248856 kb
Host	smart-49ecc6e1-0fbe-45b0-99df-bab71e284145
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=464308726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_outs tanding.464308726
Directory	/workspace/2.alert_handler_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.2893065780
Short name	T138
Test name
Test status
Simulation time	2687913390 ps
CPU time	200.05 seconds
Started	Jul 31 05:20:41 PM PDT 24
Finished	Jul 31 05:24:01 PM PDT 24
Peak memory	267124 kb
Host	smart-baa05c6c-52f4-4744-96fb-d840625ab452
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2893065780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro rs.2893065780
Directory	/workspace/2.alert_handler_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.1320021643
Short name	T248
Test name
Test status
Simulation time	161111600 ps
CPU time	9.36 seconds
Started	Jul 31 05:20:59 PM PDT 24
Finished	Jul 31 05:21:09 PM PDT 24
Peak memory	249088 kb
Host	smart-96628910-f041-4d0e-a572-53cd99c25683
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1320021643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.1320021643
Directory	/workspace/2.alert_handler_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/20.alert_handler_intr_test.4191811162
Short name	T156
Test name
Test status
Simulation time	10358471 ps
CPU time	1.29 seconds
Started	Jul 31 05:20:50 PM PDT 24
Finished	Jul 31 05:20:51 PM PDT 24
Peak memory	236784 kb
Host	smart-aa76f4c6-3e26-4222-af0d-d2dfab1b5580
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4191811162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.4191811162
Directory	/workspace/20.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/21.alert_handler_intr_test.1156923494
Short name	T816
Test name
Test status
Simulation time	12299542 ps
CPU time	1.68 seconds
Started	Jul 31 05:20:50 PM PDT 24
Finished	Jul 31 05:20:52 PM PDT 24
Peak memory	236804 kb
Host	smart-0525dfd1-d675-4bfc-bf17-0ae1a0f12204
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1156923494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.1156923494
Directory	/workspace/21.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/22.alert_handler_intr_test.2663954326
Short name	T722
Test name
Test status
Simulation time	14929427 ps
CPU time	1.28 seconds
Started	Jul 31 05:21:36 PM PDT 24
Finished	Jul 31 05:21:37 PM PDT 24
Peak memory	237696 kb
Host	smart-a02e29a3-dedd-403c-ada9-d168537e0482
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2663954326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.2663954326
Directory	/workspace/22.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/23.alert_handler_intr_test.1616748404
Short name	T734
Test name
Test status
Simulation time	15431108 ps
CPU time	1.34 seconds
Started	Jul 31 05:20:59 PM PDT 24
Finished	Jul 31 05:21:01 PM PDT 24
Peak memory	237900 kb
Host	smart-59d26068-b91f-4ebd-88f1-d3d70eb81868
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1616748404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.1616748404
Directory	/workspace/23.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/24.alert_handler_intr_test.2323693207
Short name	T745
Test name
Test status
Simulation time	12014535 ps
CPU time	1.31 seconds
Started	Jul 31 05:21:05 PM PDT 24
Finished	Jul 31 05:21:06 PM PDT 24
Peak memory	237684 kb
Host	smart-fde60815-f07d-4017-a96a-4c63a5436a95
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2323693207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.2323693207
Directory	/workspace/24.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/25.alert_handler_intr_test.1607126637
Short name	T789
Test name
Test status
Simulation time	12525722 ps
CPU time	1.46 seconds
Started	Jul 31 05:21:18 PM PDT 24
Finished	Jul 31 05:21:20 PM PDT 24
Peak memory	237684 kb
Host	smart-d44d941b-5f44-41af-a55e-5eeed2dd3eb4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1607126637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.1607126637
Directory	/workspace/25.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/26.alert_handler_intr_test.3407964651
Short name	T750
Test name
Test status
Simulation time	16949924 ps
CPU time	1.35 seconds
Started	Jul 31 05:21:03 PM PDT 24
Finished	Jul 31 05:21:05 PM PDT 24
Peak memory	235684 kb
Host	smart-47dcef13-9e12-4ef9-a789-f05ca5c4a1d9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3407964651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.3407964651
Directory	/workspace/26.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/27.alert_handler_intr_test.1764366855
Short name	T731
Test name
Test status
Simulation time	80734564 ps
CPU time	1.35 seconds
Started	Jul 31 05:21:17 PM PDT 24
Finished	Jul 31 05:21:19 PM PDT 24
Peak memory	236648 kb
Host	smart-45c5e99b-9c59-4fa1-924b-6e2876ada88f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1764366855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.1764366855
Directory	/workspace/27.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/28.alert_handler_intr_test.1723322028
Short name	T725
Test name
Test status
Simulation time	6668968 ps
CPU time	1.47 seconds
Started	Jul 31 05:21:14 PM PDT 24
Finished	Jul 31 05:21:16 PM PDT 24
Peak memory	237720 kb
Host	smart-d8845860-6132-497b-84c8-d6899b91c74a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1723322028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.1723322028
Directory	/workspace/28.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/29.alert_handler_intr_test.1124204256
Short name	T744
Test name
Test status
Simulation time	10072620 ps
CPU time	1.26 seconds
Started	Jul 31 05:21:12 PM PDT 24
Finished	Jul 31 05:21:14 PM PDT 24
Peak memory	237684 kb
Host	smart-d843c838-d264-4585-9c79-9888afee32bb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1124204256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.1124204256
Directory	/workspace/29.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.3885218198
Short name	T351
Test name
Test status
Simulation time	2272862122 ps
CPU time	167.78 seconds
Started	Jul 31 05:20:56 PM PDT 24
Finished	Jul 31 05:23:44 PM PDT 24
Peak memory	240732 kb
Host	smart-11d4c98f-789a-4230-894f-ef0df636a8b2
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3885218198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.3885218198
Directory	/workspace/3.alert_handler_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.1521074194
Short name	T783
Test name
Test status
Simulation time	14860837284 ps
CPU time	236.42 seconds
Started	Jul 31 05:21:14 PM PDT 24
Finished	Jul 31 05:25:12 PM PDT 24
Peak memory	236952 kb
Host	smart-99a2e7ed-5608-4fc5-af2b-a639c71f775c
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1521074194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.1521074194
Directory	/workspace/3.alert_handler_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.2283844567
Short name	T241
Test name
Test status
Simulation time	120420896 ps
CPU time	9.04 seconds
Started	Jul 31 05:20:49 PM PDT 24
Finished	Jul 31 05:20:58 PM PDT 24
Peak memory	248816 kb
Host	smart-a7c65ea8-123b-43e5-a769-11a43905c6aa
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2283844567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.2283844567
Directory	/workspace/3.alert_handler_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.1227506287
Short name	T791
Test name
Test status
Simulation time	54206037 ps
CPU time	7.95 seconds
Started	Jul 31 05:20:55 PM PDT 24
Finished	Jul 31 05:21:03 PM PDT 24
Peak memory	252680 kb
Host	smart-ebab6083-be88-4c8b-9ee1-431373a8ba20
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227506287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 3.alert_handler_csr_mem_rw_with_rand_reset.1227506287
Directory	/workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.1164587942
Short name	T788
Test name
Test status
Simulation time	285121294 ps
CPU time	4.69 seconds
Started	Jul 31 05:21:06 PM PDT 24
Finished	Jul 31 05:21:11 PM PDT 24
Peak memory	237720 kb
Host	smart-5283cdbb-1f12-40cd-9bd2-cb1f449b6005
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=1164587942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.1164587942
Directory	/workspace/3.alert_handler_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.alert_handler_intr_test.3798040199
Short name	T738
Test name
Test status
Simulation time	6729553 ps
CPU time	1.45 seconds
Started	Jul 31 05:21:17 PM PDT 24
Finished	Jul 31 05:21:19 PM PDT 24
Peak memory	236700 kb
Host	smart-5e99270e-d95e-4b2b-90d0-dc3916d4bc1c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3798040199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.3798040199
Directory	/workspace/3.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.122301754
Short name	T772
Test name
Test status
Simulation time	1353473359 ps
CPU time	17.68 seconds
Started	Jul 31 05:20:50 PM PDT 24
Finished	Jul 31 05:21:08 PM PDT 24
Peak memory	240652 kb
Host	smart-668b5dd1-9719-4cd3-af58-b37f22dc9dc5
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=122301754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_outs tanding.122301754
Directory	/workspace/3.alert_handler_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.2471319703
Short name	T746
Test name
Test status
Simulation time	422263778 ps
CPU time	28.52 seconds
Started	Jul 31 05:20:51 PM PDT 24
Finished	Jul 31 05:21:20 PM PDT 24
Peak memory	248496 kb
Host	smart-a9b70e07-b74a-4ca1-a548-4f95d6eb946d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2471319703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.2471319703
Directory	/workspace/3.alert_handler_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.677372984
Short name	T820
Test name
Test status
Simulation time	87154283 ps
CPU time	2.34 seconds
Started	Jul 31 05:20:41 PM PDT 24
Finished	Jul 31 05:20:43 PM PDT 24
Peak memory	236836 kb
Host	smart-70fd3191-2a1f-480e-8be6-f861c968728e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=677372984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.677372984
Directory	/workspace/3.alert_handler_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/30.alert_handler_intr_test.76061197
Short name	T158
Test name
Test status
Simulation time	17456943 ps
CPU time	1.33 seconds
Started	Jul 31 05:21:08 PM PDT 24
Finished	Jul 31 05:21:10 PM PDT 24
Peak memory	237712 kb
Host	smart-5b0f7c40-6f43-43a0-b53c-2d2d32127d39
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=76061197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.76061197
Directory	/workspace/30.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/31.alert_handler_intr_test.4252597871
Short name	T827
Test name
Test status
Simulation time	9192554 ps
CPU time	1.55 seconds
Started	Jul 31 05:20:53 PM PDT 24
Finished	Jul 31 05:20:55 PM PDT 24
Peak memory	235772 kb
Host	smart-a3d622ea-e150-4ea2-830f-3d8683bc83a7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4252597871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.4252597871
Directory	/workspace/31.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/32.alert_handler_intr_test.1405675701
Short name	T785
Test name
Test status
Simulation time	11503275 ps
CPU time	1.5 seconds
Started	Jul 31 05:20:47 PM PDT 24
Finished	Jul 31 05:20:48 PM PDT 24
Peak memory	236860 kb
Host	smart-e5547d7f-4d53-4d14-9362-9f0d28cf7f03
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1405675701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.1405675701
Directory	/workspace/32.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/33.alert_handler_intr_test.2733493730
Short name	T752
Test name
Test status
Simulation time	27002244 ps
CPU time	1.68 seconds
Started	Jul 31 05:21:03 PM PDT 24
Finished	Jul 31 05:21:10 PM PDT 24
Peak memory	237648 kb
Host	smart-a7b8363f-4bd3-4669-82af-21e68f53064e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2733493730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.2733493730
Directory	/workspace/33.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/35.alert_handler_intr_test.2347743483
Short name	T346
Test name
Test status
Simulation time	21665297 ps
CPU time	1.43 seconds
Started	Jul 31 05:20:58 PM PDT 24
Finished	Jul 31 05:21:00 PM PDT 24
Peak memory	236760 kb
Host	smart-a8701d36-5ed4-4792-ab80-35f49491cc98
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2347743483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.2347743483
Directory	/workspace/35.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/36.alert_handler_intr_test.739080434
Short name	T821
Test name
Test status
Simulation time	9042231 ps
CPU time	1.25 seconds
Started	Jul 31 05:20:44 PM PDT 24
Finished	Jul 31 05:20:46 PM PDT 24
Peak memory	237716 kb
Host	smart-121c4205-64b8-4c63-aac3-cf6c7019dbb4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=739080434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.739080434
Directory	/workspace/36.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/37.alert_handler_intr_test.618507459
Short name	T740
Test name
Test status
Simulation time	12718759 ps
CPU time	1.5 seconds
Started	Jul 31 05:21:23 PM PDT 24
Finished	Jul 31 05:21:24 PM PDT 24
Peak memory	236784 kb
Host	smart-4bdd8446-60e4-48b6-8568-96bd66500bac
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=618507459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.618507459
Directory	/workspace/37.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/38.alert_handler_intr_test.1328865498
Short name	T826
Test name
Test status
Simulation time	10248434 ps
CPU time	1.32 seconds
Started	Jul 31 05:20:57 PM PDT 24
Finished	Jul 31 05:20:58 PM PDT 24
Peak memory	236820 kb
Host	smart-33044333-ccae-41c7-8098-076f36b2cf89
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1328865498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.1328865498
Directory	/workspace/38.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/39.alert_handler_intr_test.3174892452
Short name	T819
Test name
Test status
Simulation time	8188884 ps
CPU time	1.29 seconds
Started	Jul 31 05:21:09 PM PDT 24
Finished	Jul 31 05:21:11 PM PDT 24
Peak memory	237616 kb
Host	smart-4d637598-6eaf-471d-a32d-6cd569fdd2f3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3174892452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.3174892452
Directory	/workspace/39.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.1978056863
Short name	T754
Test name
Test status
Simulation time	2235028103 ps
CPU time	62.84 seconds
Started	Jul 31 05:20:49 PM PDT 24
Finished	Jul 31 05:21:52 PM PDT 24
Peak memory	240580 kb
Host	smart-f1c1fc4b-7439-4fbc-bab5-67e7d6abdcad
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1978056863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.1978056863
Directory	/workspace/4.alert_handler_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.649266198
Short name	T741
Test name
Test status
Simulation time	3027278629 ps
CPU time	94.29 seconds
Started	Jul 31 05:20:52 PM PDT 24
Finished	Jul 31 05:22:26 PM PDT 24
Peak memory	236824 kb
Host	smart-8d81d71b-517d-4e1b-9af5-43ba006585cd
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=649266198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.649266198
Directory	/workspace/4.alert_handler_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.1850383011
Short name	T801
Test name
Test status
Simulation time	537662530 ps
CPU time	10.44 seconds
Started	Jul 31 05:20:53 PM PDT 24
Finished	Jul 31 05:21:03 PM PDT 24
Peak memory	249308 kb
Host	smart-fcbb7b19-6303-4f02-be4e-42024262b3ac
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1850383011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.1850383011
Directory	/workspace/4.alert_handler_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.2498446412
Short name	T353
Test name
Test status
Simulation time	200707845 ps
CPU time	7.91 seconds
Started	Jul 31 05:20:51 PM PDT 24
Finished	Jul 31 05:20:59 PM PDT 24
Peak memory	240332 kb
Host	smart-73fbbe5e-08e3-45c0-b982-06f088b2fcda
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498446412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 4.alert_handler_csr_mem_rw_with_rand_reset.2498446412
Directory	/workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.1848137542
Short name	T749
Test name
Test status
Simulation time	185780030 ps
CPU time	3.49 seconds
Started	Jul 31 05:20:44 PM PDT 24
Finished	Jul 31 05:20:47 PM PDT 24
Peak memory	237564 kb
Host	smart-31e22570-465a-4fd9-95e5-c2948edfabf0
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=1848137542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.1848137542
Directory	/workspace/4.alert_handler_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.alert_handler_intr_test.1578836689
Short name	T806
Test name
Test status
Simulation time	10669241 ps
CPU time	1.25 seconds
Started	Jul 31 05:20:43 PM PDT 24
Finished	Jul 31 05:20:44 PM PDT 24
Peak memory	237652 kb
Host	smart-cfaff111-ad37-4010-828c-cdc95c827822
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1578836689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.1578836689
Directory	/workspace/4.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.939331216
Short name	T191
Test name
Test status
Simulation time	168594501 ps
CPU time	23.42 seconds
Started	Jul 31 05:20:47 PM PDT 24
Finished	Jul 31 05:21:11 PM PDT 24
Peak memory	245900 kb
Host	smart-d660f948-cbad-49b8-8034-83fa87478be2
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=939331216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_outs tanding.939331216
Directory	/workspace/4.alert_handler_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.779904251
Short name	T127
Test name
Test status
Simulation time	16458031275 ps
CPU time	1207.55 seconds
Started	Jul 31 05:21:01 PM PDT 24
Finished	Jul 31 05:41:08 PM PDT 24
Peak memory	272640 kb
Host	smart-65a2f9ab-6bd1-491b-962f-cc450fb496ee
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779904251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM _TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.779904251
Directory	/workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.4164604178
Short name	T723
Test name
Test status
Simulation time	69299348 ps
CPU time	5.13 seconds
Started	Jul 31 05:21:25 PM PDT 24
Finished	Jul 31 05:21:31 PM PDT 24
Peak memory	240224 kb
Host	smart-c95c6ee7-aa27-4580-9d2b-7a10901009c3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4164604178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.4164604178
Directory	/workspace/4.alert_handler_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/40.alert_handler_intr_test.2190309317
Short name	T719
Test name
Test status
Simulation time	9953193 ps
CPU time	1.25 seconds
Started	Jul 31 05:20:49 PM PDT 24
Finished	Jul 31 05:20:51 PM PDT 24
Peak memory	237728 kb
Host	smart-1e4c3af5-29b3-49a4-9580-429f07d2cf71
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2190309317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.2190309317
Directory	/workspace/40.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/41.alert_handler_intr_test.3622927248
Short name	T771
Test name
Test status
Simulation time	7652493 ps
CPU time	1.26 seconds
Started	Jul 31 05:20:57 PM PDT 24
Finished	Jul 31 05:20:58 PM PDT 24
Peak memory	237712 kb
Host	smart-6548dddb-55a0-4e63-a83b-88f7e045420c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3622927248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.3622927248
Directory	/workspace/41.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/42.alert_handler_intr_test.2057205723
Short name	T728
Test name
Test status
Simulation time	26082614 ps
CPU time	1.26 seconds
Started	Jul 31 05:20:52 PM PDT 24
Finished	Jul 31 05:20:53 PM PDT 24
Peak memory	237732 kb
Host	smart-a8a4f5c3-bc0b-49aa-87a9-70d99e30fe3a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2057205723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.2057205723
Directory	/workspace/42.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/43.alert_handler_intr_test.1437836368
Short name	T735
Test name
Test status
Simulation time	8606054 ps
CPU time	1.72 seconds
Started	Jul 31 05:21:23 PM PDT 24
Finished	Jul 31 05:21:25 PM PDT 24
Peak memory	236880 kb
Host	smart-781f9c49-af4f-41a6-8338-f2c5770be2e1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1437836368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.1437836368
Directory	/workspace/43.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/44.alert_handler_intr_test.242012431
Short name	T781
Test name
Test status
Simulation time	8241015 ps
CPU time	1.53 seconds
Started	Jul 31 05:21:02 PM PDT 24
Finished	Jul 31 05:21:04 PM PDT 24
Peak memory	235976 kb
Host	smart-8513d907-150c-4a41-9354-9c4d5d8b30c7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=242012431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.242012431
Directory	/workspace/44.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/45.alert_handler_intr_test.1596727949
Short name	T343
Test name
Test status
Simulation time	15263768 ps
CPU time	1.4 seconds
Started	Jul 31 05:21:05 PM PDT 24
Finished	Jul 31 05:21:06 PM PDT 24
Peak memory	236840 kb
Host	smart-b522ba3b-466a-4b3a-aa12-9b1feeed82f4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1596727949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.1596727949
Directory	/workspace/45.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/46.alert_handler_intr_test.3052619059
Short name	T803
Test name
Test status
Simulation time	7863364 ps
CPU time	1.47 seconds
Started	Jul 31 05:20:51 PM PDT 24
Finished	Jul 31 05:20:52 PM PDT 24
Peak memory	237700 kb
Host	smart-3e82ec4a-5d4e-4dcc-a56c-002b15b1895d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3052619059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.3052619059
Directory	/workspace/46.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/47.alert_handler_intr_test.1565979184
Short name	T810
Test name
Test status
Simulation time	10193061 ps
CPU time	1.31 seconds
Started	Jul 31 05:21:07 PM PDT 24
Finished	Jul 31 05:21:09 PM PDT 24
Peak memory	235736 kb
Host	smart-064adede-fc62-4f8e-b0fb-3cb6fca09541
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1565979184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.1565979184
Directory	/workspace/47.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.alert_handler_intr_test.1796785124
Short name	T759
Test name
Test status
Simulation time	6492479 ps
CPU time	1.39 seconds
Started	Jul 31 05:20:45 PM PDT 24
Finished	Jul 31 05:20:47 PM PDT 24
Peak memory	237680 kb
Host	smart-de355c37-23e6-4402-a6f4-7d8da9363b2a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1796785124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.1796785124
Directory	/workspace/48.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/49.alert_handler_intr_test.4156695735
Short name	T770
Test name
Test status
Simulation time	19419085 ps
CPU time	1.88 seconds
Started	Jul 31 05:21:19 PM PDT 24
Finished	Jul 31 05:21:21 PM PDT 24
Peak memory	236868 kb
Host	smart-89a1c3e6-19e0-4521-ba8a-1add0a79ae12
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4156695735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.4156695735
Directory	/workspace/49.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.108805063
Short name	T807
Test name
Test status
Simulation time	406742236 ps
CPU time	5.63 seconds
Started	Jul 31 05:20:39 PM PDT 24
Finished	Jul 31 05:20:45 PM PDT 24
Peak memory	240400 kb
Host	smart-37f70900-cf81-4186-b8a3-29b67055d311
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108805063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 5.alert_handler_csr_mem_rw_with_rand_reset.108805063
Directory	/workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.1243290775
Short name	T193
Test name
Test status
Simulation time	33750624 ps
CPU time	5.25 seconds
Started	Jul 31 05:20:41 PM PDT 24
Finished	Jul 31 05:20:46 PM PDT 24
Peak memory	240568 kb
Host	smart-38183e88-5dd7-46f2-9a42-941ac22d1b6e
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=1243290775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.1243290775
Directory	/workspace/5.alert_handler_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.alert_handler_intr_test.5395276
Short name	T157
Test name
Test status
Simulation time	55540110 ps
CPU time	1.28 seconds
Started	Jul 31 05:20:40 PM PDT 24
Finished	Jul 31 05:20:42 PM PDT 24
Peak memory	236712 kb
Host	smart-4aa3f23a-c722-47b2-911c-0baf376d2943
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=5395276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.5395276
Directory	/workspace/5.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.889316141
Short name	T757
Test name
Test status
Simulation time	570683929 ps
CPU time	26.27 seconds
Started	Jul 31 05:20:45 PM PDT 24
Finished	Jul 31 05:21:11 PM PDT 24
Peak memory	245880 kb
Host	smart-df02f786-3dd8-43fc-9e14-483143dd9a97
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=889316141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_outs tanding.889316141
Directory	/workspace/5.alert_handler_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.3484663555
Short name	T814
Test name
Test status
Simulation time	62678563419 ps
CPU time	1145.44 seconds
Started	Jul 31 05:20:42 PM PDT 24
Finished	Jul 31 05:39:48 PM PDT 24
Peak memory	273136 kb
Host	smart-9e65cf2b-c2c0-41cf-83c6-965687437a5d
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484663555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.3484663555
Directory	/workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.1976311970
Short name	T811
Test name
Test status
Simulation time	53840273 ps
CPU time	6.3 seconds
Started	Jul 31 05:21:06 PM PDT 24
Finished	Jul 31 05:21:13 PM PDT 24
Peak memory	251396 kb
Host	smart-851da0ca-5078-46f8-89e6-f3e015a3e662
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1976311970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.1976311970
Directory	/workspace/5.alert_handler_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.3898228961
Short name	T196
Test name
Test status
Simulation time	23728519 ps
CPU time	2.39 seconds
Started	Jul 31 05:20:44 PM PDT 24
Finished	Jul 31 05:20:47 PM PDT 24
Peak memory	238720 kb
Host	smart-3f18ffc1-3d85-4d3b-b522-ee3348121ab3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3898228961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.3898228961
Directory	/workspace/5.alert_handler_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.2257330285
Short name	T756
Test name
Test status
Simulation time	174517144 ps
CPU time	4.39 seconds
Started	Jul 31 05:20:46 PM PDT 24
Finished	Jul 31 05:20:51 PM PDT 24
Peak memory	240636 kb
Host	smart-47b6889d-c92b-44f0-a8bd-05322817f9da
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257330285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 6.alert_handler_csr_mem_rw_with_rand_reset.2257330285
Directory	/workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.3740765524
Short name	T828
Test name
Test status
Simulation time	437915804 ps
CPU time	8.97 seconds
Started	Jul 31 05:20:59 PM PDT 24
Finished	Jul 31 05:21:08 PM PDT 24
Peak memory	236784 kb
Host	smart-8ec6f29c-22df-4982-a9d8-1319fd8eaaa8
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=3740765524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.3740765524
Directory	/workspace/6.alert_handler_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.alert_handler_intr_test.2964806804
Short name	T717
Test name
Test status
Simulation time	13685774 ps
CPU time	1.31 seconds
Started	Jul 31 05:20:36 PM PDT 24
Finished	Jul 31 05:20:37 PM PDT 24
Peak memory	237700 kb
Host	smart-c79fb016-de4e-4b75-b290-d1ba44c6abda
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2964806804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.2964806804
Directory	/workspace/6.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.3773062426
Short name	T804
Test name
Test status
Simulation time	180567186 ps
CPU time	25.63 seconds
Started	Jul 31 05:20:50 PM PDT 24
Finished	Jul 31 05:21:15 PM PDT 24
Peak memory	245856 kb
Host	smart-2ecb9161-327d-498a-839e-7660430c5da1
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3773062426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out standing.3773062426
Directory	/workspace/6.alert_handler_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.806500071
Short name	T141
Test name
Test status
Simulation time	4172613566 ps
CPU time	295.96 seconds
Started	Jul 31 05:20:45 PM PDT 24
Finished	Jul 31 05:25:41 PM PDT 24
Peak memory	273060 kb
Host	smart-793c543d-eed0-4c77-9b25-3feb8f4d61cc
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806500071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM _TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.806500071
Directory	/workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.1345432649
Short name	T743
Test name
Test status
Simulation time	26287284 ps
CPU time	3.59 seconds
Started	Jul 31 05:20:43 PM PDT 24
Finished	Jul 31 05:20:46 PM PDT 24
Peak memory	248784 kb
Host	smart-d2d0c444-5f2c-4d87-bbe1-3bd9ad870db1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1345432649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.1345432649
Directory	/workspace/6.alert_handler_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.594195889
Short name	T774
Test name
Test status
Simulation time	120445997 ps
CPU time	5.44 seconds
Started	Jul 31 05:20:46 PM PDT 24
Finished	Jul 31 05:20:51 PM PDT 24
Peak memory	257056 kb
Host	smart-8c99a93d-adeb-42af-9913-07b02d47dd0b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594195889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 7.alert_handler_csr_mem_rw_with_rand_reset.594195889
Directory	/workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.2902217061
Short name	T347
Test name
Test status
Simulation time	365274794 ps
CPU time	6.79 seconds
Started	Jul 31 05:20:47 PM PDT 24
Finished	Jul 31 05:20:54 PM PDT 24
Peak memory	236764 kb
Host	smart-d0653b97-2e02-4ee0-84f1-538d120f9d9e
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=2902217061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.2902217061
Directory	/workspace/7.alert_handler_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.alert_handler_intr_test.868354408
Short name	T344
Test name
Test status
Simulation time	7493151 ps
CPU time	1.47 seconds
Started	Jul 31 05:21:07 PM PDT 24
Finished	Jul 31 05:21:09 PM PDT 24
Peak memory	236804 kb
Host	smart-64119b7a-c4e0-4053-8d35-9fc41a85dfd6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=868354408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.868354408
Directory	/workspace/7.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.3478656236
Short name	T802
Test name
Test status
Simulation time	715120723 ps
CPU time	51.82 seconds
Started	Jul 31 05:20:47 PM PDT 24
Finished	Jul 31 05:21:39 PM PDT 24
Peak memory	245928 kb
Host	smart-3c74d0e3-5f8b-413c-a788-8fa0e632c02c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3478656236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out standing.3478656236
Directory	/workspace/7.alert_handler_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.2018306963
Short name	T119
Test name
Test status
Simulation time	6484817550 ps
CPU time	285.29 seconds
Started	Jul 31 05:21:00 PM PDT 24
Finished	Jul 31 05:25:46 PM PDT 24
Peak memory	265668 kb
Host	smart-1ea2bc36-30e1-46d2-8609-adcfffa2b3e2
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2018306963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro rs.2018306963
Directory	/workspace/7.alert_handler_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.38752357
Short name	T247
Test name
Test status
Simulation time	261724957 ps
CPU time	10.06 seconds
Started	Jul 31 05:21:10 PM PDT 24
Finished	Jul 31 05:21:20 PM PDT 24
Peak memory	249896 kb
Host	smart-5d4fca6b-05c4-4838-81e0-d2d9ff8b5f0f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=38752357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.38752357
Directory	/workspace/7.alert_handler_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.975807868
Short name	T253
Test name
Test status
Simulation time	61233094 ps
CPU time	2.17 seconds
Started	Jul 31 05:20:51 PM PDT 24
Finished	Jul 31 05:20:54 PM PDT 24
Peak memory	238712 kb
Host	smart-465d22cc-b951-4ea1-9adb-a3e5e95bf34d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=975807868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.975807868
Directory	/workspace/7.alert_handler_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.776960349
Short name	T761
Test name
Test status
Simulation time	181357659 ps
CPU time	7.91 seconds
Started	Jul 31 05:21:07 PM PDT 24
Finished	Jul 31 05:21:15 PM PDT 24
Peak memory	241176 kb
Host	smart-4aa7be12-6bcb-433f-b0b2-2167beb4abb2
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776960349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 8.alert_handler_csr_mem_rw_with_rand_reset.776960349
Directory	/workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.3513397194
Short name	T192
Test name
Test status
Simulation time	125996786 ps
CPU time	5.24 seconds
Started	Jul 31 05:20:46 PM PDT 24
Finished	Jul 31 05:20:51 PM PDT 24
Peak memory	237624 kb
Host	smart-0e16607d-0634-44c2-b811-60bfd7e2c36b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=3513397194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.3513397194
Directory	/workspace/8.alert_handler_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.alert_handler_intr_test.1713787615
Short name	T815
Test name
Test status
Simulation time	11793680 ps
CPU time	1.28 seconds
Started	Jul 31 05:20:46 PM PDT 24
Finished	Jul 31 05:20:47 PM PDT 24
Peak memory	236784 kb
Host	smart-51f33b85-312d-4e87-ad6a-ab21f21459ae
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1713787615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.1713787615
Directory	/workspace/8.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.3881106178
Short name	T753
Test name
Test status
Simulation time	622046111 ps
CPU time	24.14 seconds
Started	Jul 31 05:21:04 PM PDT 24
Finished	Jul 31 05:21:29 PM PDT 24
Peak memory	240592 kb
Host	smart-61a3bf9f-d7c5-4a3d-aa14-027df46ecdf3
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3881106178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out standing.3881106178
Directory	/workspace/8.alert_handler_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.3089689741
Short name	T720
Test name
Test status
Simulation time	119377297 ps
CPU time	12.86 seconds
Started	Jul 31 05:21:08 PM PDT 24
Finished	Jul 31 05:21:21 PM PDT 24
Peak memory	248880 kb
Host	smart-24f89a6c-ef8f-4021-8334-72210299eb92
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3089689741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.3089689741
Directory	/workspace/8.alert_handler_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.3497498067
Short name	T170
Test name
Test status
Simulation time	320590484 ps
CPU time	5.66 seconds
Started	Jul 31 05:20:46 PM PDT 24
Finished	Jul 31 05:20:57 PM PDT 24
Peak memory	240172 kb
Host	smart-6b62437b-2b73-4b1b-8a10-3d18db888bb9
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497498067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 9.alert_handler_csr_mem_rw_with_rand_reset.3497498067
Directory	/workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.2824709131
Short name	T747
Test name
Test status
Simulation time	253938292 ps
CPU time	5.25 seconds
Started	Jul 31 05:20:54 PM PDT 24
Finished	Jul 31 05:20:59 PM PDT 24
Peak memory	240604 kb
Host	smart-aef2ea9f-a620-4229-90ba-b15226920f68
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=2824709131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.2824709131
Directory	/workspace/9.alert_handler_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.3366185473
Short name	T773
Test name
Test status
Simulation time	327541057 ps
CPU time	11.87 seconds
Started	Jul 31 05:20:41 PM PDT 24
Finished	Jul 31 05:20:53 PM PDT 24
Peak memory	245928 kb
Host	smart-7780d6f3-5550-40ee-857e-8d2e492ddb1d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3366185473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out standing.3366185473
Directory	/workspace/9.alert_handler_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.4060755190
Short name	T128
Test name
Test status
Simulation time	4494031014 ps
CPU time	170.83 seconds
Started	Jul 31 05:20:48 PM PDT 24
Finished	Jul 31 05:23:39 PM PDT 24
Peak memory	265624 kb
Host	smart-d5351ed2-b650-450c-8293-b63e768069b0
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4060755190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro rs.4060755190
Directory	/workspace/9.alert_handler_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.699133715
Short name	T132
Test name
Test status
Simulation time	7943570707 ps
CPU time	625.02 seconds
Started	Jul 31 05:21:18 PM PDT 24
Finished	Jul 31 05:31:43 PM PDT 24
Peak memory	265652 kb
Host	smart-04e8b14e-c8ac-47a0-9e01-687f764a1b79
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699133715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM _TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.699133715
Directory	/workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.3857714376
Short name	T797
Test name
Test status
Simulation time	118503075 ps
CPU time	8.62 seconds
Started	Jul 31 05:20:38 PM PDT 24
Finished	Jul 31 05:20:47 PM PDT 24
Peak memory	249928 kb
Host	smart-0bf785b2-9c41-4a99-b612-ccd5e42e7eae
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3857714376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.3857714376
Directory	/workspace/9.alert_handler_tl_errors/latest

Test location	/workspace/coverage/default/0.alert_handler_alert_accum_saturation.1645960925
Short name	T203
Test name
Test status
Simulation time	161096993 ps
CPU time	3.13 seconds
Started	Jul 31 05:21:28 PM PDT 24
Finished	Jul 31 05:21:32 PM PDT 24
Peak memory	248608 kb
Host	smart-2b0a2e9d-b087-4675-9745-27881c199481
User	root
Command	/workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1645960925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.1645960925
Directory	/workspace/0.alert_handler_alert_accum_saturation/latest

Test location	/workspace/coverage/default/0.alert_handler_entropy.2349924324
Short name	T683
Test name
Test status
Simulation time	30244543440 ps
CPU time	1736.75 seconds
Started	Jul 31 05:20:59 PM PDT 24
Finished	Jul 31 05:49:56 PM PDT 24
Peak memory	272920 kb
Host	smart-c7147a3b-8a47-4382-ab44-7ac605c743c9
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2349924324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.2349924324
Directory	/workspace/0.alert_handler_entropy/latest

Test location	/workspace/coverage/default/0.alert_handler_entropy_stress.2636723274
Short name	T508
Test name
Test status
Simulation time	2346621585 ps
CPU time	17.97 seconds
Started	Jul 31 05:21:17 PM PDT 24
Finished	Jul 31 05:21:35 PM PDT 24
Peak memory	248400 kb
Host	smart-fb083d09-1cc8-437f-9c31-944b36f5a13a
User	root
Command	/workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=2636723274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.2636723274
Directory	/workspace/0.alert_handler_entropy_stress/latest

Test location	/workspace/coverage/default/0.alert_handler_esc_intr_timeout.1134404895
Short name	T103
Test name
Test status
Simulation time	4878993933 ps
CPU time	50.59 seconds
Started	Jul 31 05:21:19 PM PDT 24
Finished	Jul 31 05:22:10 PM PDT 24
Peak memory	256772 kb
Host	smart-b8ca3747-4ac5-4247-b2b2-e2d31460e21c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11344 04895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.1134404895
Directory	/workspace/0.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/0.alert_handler_lpg_stub_clk.3920417213
Short name	T419
Test name
Test status
Simulation time	12908641891 ps
CPU time	1230.95 seconds
Started	Jul 31 05:21:32 PM PDT 24
Finished	Jul 31 05:42:03 PM PDT 24
Peak memory	281160 kb
Host	smart-8082b80f-d34a-4c8e-a0d8-9fbd7833f07e
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3920417213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.3920417213
Directory	/workspace/0.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/0.alert_handler_ping_timeout.2038822623
Short name	T669
Test name
Test status
Simulation time	18228751774 ps
CPU time	132.01 seconds
Started	Jul 31 05:20:58 PM PDT 24
Finished	Jul 31 05:23:10 PM PDT 24
Peak memory	254928 kb
Host	smart-64670166-7db1-4050-9ae5-e9a945f51b2f
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2038822623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.2038822623
Directory	/workspace/0.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/0.alert_handler_random_alerts.3972818438
Short name	T688
Test name
Test status
Simulation time	492203396 ps
CPU time	8.18 seconds
Started	Jul 31 05:21:21 PM PDT 24
Finished	Jul 31 05:21:30 PM PDT 24
Peak memory	248332 kb
Host	smart-3cef935e-bb22-4d86-b2b9-700a8f8c2331
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39728 18438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.3972818438
Directory	/workspace/0.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/0.alert_handler_random_classes.3043861450
Short name	T492
Test name
Test status
Simulation time	41598254 ps
CPU time	3.86 seconds
Started	Jul 31 05:21:06 PM PDT 24
Finished	Jul 31 05:21:10 PM PDT 24
Peak memory	239680 kb
Host	smart-0bf6f414-bb6d-4442-9fae-3127616e9f58
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30438 61450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.3043861450
Directory	/workspace/0.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/0.alert_handler_sig_int_fail.2993602528
Short name	T531
Test name
Test status
Simulation time	2596190320 ps
CPU time	40.03 seconds
Started	Jul 31 05:20:44 PM PDT 24
Finished	Jul 31 05:21:24 PM PDT 24
Peak memory	248328 kb
Host	smart-c9fa5625-e40b-4fe3-94fa-4700347e0287
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29936 02528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.2993602528
Directory	/workspace/0.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/0.alert_handler_smoke.636559237
Short name	T654
Test name
Test status
Simulation time	254822598 ps
CPU time	21.04 seconds
Started	Jul 31 05:21:17 PM PDT 24
Finished	Jul 31 05:21:38 PM PDT 24
Peak memory	256468 kb
Host	smart-866549bc-4a10-4607-b25b-183c53f19d04
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63655 9237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.636559237
Directory	/workspace/0.alert_handler_smoke/latest

Test location	/workspace/coverage/default/0.alert_handler_stress_all.969888247
Short name	T516
Test name
Test status
Simulation time	9114883984 ps
CPU time	502.55 seconds
Started	Jul 31 05:20:51 PM PDT 24
Finished	Jul 31 05:29:14 PM PDT 24
Peak memory	256588 kb
Host	smart-3e8ae2ee-1f0f-4a93-8272-1454805dd95b
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969888247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_hand ler_stress_all.969888247
Directory	/workspace/0.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/1.alert_handler_entropy.731795756
Short name	T48
Test name
Test status
Simulation time	36967723669 ps
CPU time	810.93 seconds
Started	Jul 31 05:21:04 PM PDT 24
Finished	Jul 31 05:34:35 PM PDT 24
Peak memory	272596 kb
Host	smart-42acd860-3df6-40b2-9848-a4b70858ed8f
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=731795756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.731795756
Directory	/workspace/1.alert_handler_entropy/latest

Test location	/workspace/coverage/default/1.alert_handler_entropy_stress.1467663103
Short name	T406
Test name
Test status
Simulation time	193642640 ps
CPU time	11.49 seconds
Started	Jul 31 05:21:00 PM PDT 24
Finished	Jul 31 05:21:11 PM PDT 24
Peak memory	248256 kb
Host	smart-57a6a813-c1c8-4425-aee2-25e7d217d23e
User	root
Command	/workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1467663103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.1467663103
Directory	/workspace/1.alert_handler_entropy_stress/latest

Test location	/workspace/coverage/default/1.alert_handler_esc_alert_accum.1592822237
Short name	T671
Test name
Test status
Simulation time	4301666683 ps
CPU time	240.01 seconds
Started	Jul 31 05:20:55 PM PDT 24
Finished	Jul 31 05:24:55 PM PDT 24
Peak memory	256544 kb
Host	smart-fc09dd4f-bbd0-41ae-b4ce-526cc8724bc9
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15928 22237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.1592822237
Directory	/workspace/1.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/1.alert_handler_lpg_stub_clk.3527311080
Short name	T7
Test name
Test status
Simulation time	82997179875 ps
CPU time	2064.4 seconds
Started	Jul 31 05:21:32 PM PDT 24
Finished	Jul 31 05:55:57 PM PDT 24
Peak memory	287304 kb
Host	smart-0572d93e-dd5d-49a3-a094-b59f0a703f27
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3527311080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.3527311080
Directory	/workspace/1.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/1.alert_handler_random_alerts.1644601341
Short name	T409
Test name
Test status
Simulation time	274356769 ps
CPU time	26.08 seconds
Started	Jul 31 05:21:12 PM PDT 24
Finished	Jul 31 05:21:38 PM PDT 24
Peak memory	255704 kb
Host	smart-e6758942-fa75-4343-86fa-39e8eca78928
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16446 01341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.1644601341
Directory	/workspace/1.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/1.alert_handler_random_classes.3647732481
Short name	T13
Test name
Test status
Simulation time	697147004 ps
CPU time	21.53 seconds
Started	Jul 31 05:21:09 PM PDT 24
Finished	Jul 31 05:21:31 PM PDT 24
Peak memory	247724 kb
Host	smart-d5b46475-e732-41d9-81ba-a2caf740f5d5
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36477 32481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.3647732481
Directory	/workspace/1.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/1.alert_handler_sec_cm.2879793046
Short name	T10
Test name
Test status
Simulation time	496306767 ps
CPU time	15.49 seconds
Started	Jul 31 05:20:55 PM PDT 24
Finished	Jul 31 05:21:10 PM PDT 24
Peak memory	270732 kb
Host	smart-83b3534c-f53c-4e25-ad73-22fefa210a13
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2879793046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.2879793046
Directory	/workspace/1.alert_handler_sec_cm/latest

Test location	/workspace/coverage/default/1.alert_handler_sig_int_fail.116082329
Short name	T100
Test name
Test status
Simulation time	65380252 ps
CPU time	8.25 seconds
Started	Jul 31 05:20:55 PM PDT 24
Finished	Jul 31 05:21:03 PM PDT 24
Peak memory	247916 kb
Host	smart-e1df40b1-99f4-4fba-8c08-be4eccc761ea
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11608 2329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.116082329
Directory	/workspace/1.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/1.alert_handler_smoke.2209949677
Short name	T246
Test name
Test status
Simulation time	905013467 ps
CPU time	19.59 seconds
Started	Jul 31 05:21:09 PM PDT 24
Finished	Jul 31 05:21:29 PM PDT 24
Peak memory	256508 kb
Host	smart-719bf840-3d85-4961-b947-aecbcc353501
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22099 49677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.2209949677
Directory	/workspace/1.alert_handler_smoke/latest

Test location	/workspace/coverage/default/1.alert_handler_stress_all.3966068949
Short name	T466
Test name
Test status
Simulation time	82929636655 ps
CPU time	2459.28 seconds
Started	Jul 31 05:20:58 PM PDT 24
Finished	Jul 31 06:01:57 PM PDT 24
Peak memory	288860 kb
Host	smart-a06155a5-90c0-4b51-953b-8d13476d5a9c
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966068949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han dler_stress_all.3966068949
Directory	/workspace/1.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/10.alert_handler_alert_accum_saturation.2306729598
Short name	T209
Test name
Test status
Simulation time	198589588 ps
CPU time	3.39 seconds
Started	Jul 31 05:21:38 PM PDT 24
Finished	Jul 31 05:21:41 PM PDT 24
Peak memory	248644 kb
Host	smart-0f9bc6d3-ab7a-47cb-ba15-61dbc1b37ee0
User	root
Command	/workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=2306729598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.2306729598
Directory	/workspace/10.alert_handler_alert_accum_saturation/latest

Test location	/workspace/coverage/default/10.alert_handler_entropy.1278868604
Short name	T588
Test name
Test status
Simulation time	238912384171 ps
CPU time	2020.57 seconds
Started	Jul 31 05:21:33 PM PDT 24
Finished	Jul 31 05:55:14 PM PDT 24
Peak memory	283556 kb
Host	smart-572ec8d6-0e88-4993-a9f5-0419f36c600f
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1278868604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.1278868604
Directory	/workspace/10.alert_handler_entropy/latest

Test location	/workspace/coverage/default/10.alert_handler_entropy_stress.172209163
Short name	T228
Test name
Test status
Simulation time	2179322779 ps
CPU time	27.8 seconds
Started	Jul 31 05:21:32 PM PDT 24
Finished	Jul 31 05:22:00 PM PDT 24
Peak memory	248368 kb
Host	smart-12683f64-0325-455e-ab68-6ab56c93b814
User	root
Command	/workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=172209163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.172209163
Directory	/workspace/10.alert_handler_entropy_stress/latest

Test location	/workspace/coverage/default/10.alert_handler_esc_alert_accum.2062775130
Short name	T447
Test name
Test status
Simulation time	4375090045 ps
CPU time	155.11 seconds
Started	Jul 31 05:21:35 PM PDT 24
Finished	Jul 31 05:24:10 PM PDT 24
Peak memory	249384 kb
Host	smart-e869c6c0-ce47-4e2e-8885-155e46e2ec37
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20627 75130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.2062775130
Directory	/workspace/10.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/10.alert_handler_esc_intr_timeout.3833383810
Short name	T507
Test name
Test status
Simulation time	1196029963 ps
CPU time	41.26 seconds
Started	Jul 31 05:21:34 PM PDT 24
Finished	Jul 31 05:22:16 PM PDT 24
Peak memory	247764 kb
Host	smart-0d71517f-defc-494b-a421-4d28ecfee1a8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38333 83810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.3833383810
Directory	/workspace/10.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/10.alert_handler_lpg.1951346962
Short name	T316
Test name
Test status
Simulation time	18846499084 ps
CPU time	1422.03 seconds
Started	Jul 31 05:21:34 PM PDT 24
Finished	Jul 31 05:45:17 PM PDT 24
Peak memory	289268 kb
Host	smart-37361f90-565f-4fee-b386-1ef276890d11
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1951346962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.1951346962
Directory	/workspace/10.alert_handler_lpg/latest

Test location	/workspace/coverage/default/10.alert_handler_lpg_stub_clk.737310808
Short name	T221
Test name
Test status
Simulation time	78399513951 ps
CPU time	1772.93 seconds
Started	Jul 31 05:21:30 PM PDT 24
Finished	Jul 31 05:51:03 PM PDT 24
Peak memory	288752 kb
Host	smart-65e74fcc-130a-4155-8148-f3878b6b7d01
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=737310808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.737310808
Directory	/workspace/10.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/10.alert_handler_ping_timeout.706102983
Short name	T553
Test name
Test status
Simulation time	2911653511 ps
CPU time	118.57 seconds
Started	Jul 31 05:21:46 PM PDT 24
Finished	Jul 31 05:23:44 PM PDT 24
Peak memory	255164 kb
Host	smart-8e913a73-0c73-4481-8882-979d7c2469fb
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=706102983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.706102983
Directory	/workspace/10.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/10.alert_handler_random_alerts.1681250668
Short name	T709
Test name
Test status
Simulation time	508515036 ps
CPU time	4.93 seconds
Started	Jul 31 05:21:28 PM PDT 24
Finished	Jul 31 05:21:33 PM PDT 24
Peak memory	248368 kb
Host	smart-a7740e50-89da-44a1-80b7-4bd0ece5a057
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16812 50668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.1681250668
Directory	/workspace/10.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/10.alert_handler_random_classes.3006061656
Short name	T613
Test name
Test status
Simulation time	1507114553 ps
CPU time	26.25 seconds
Started	Jul 31 05:21:30 PM PDT 24
Finished	Jul 31 05:21:56 PM PDT 24
Peak memory	247976 kb
Host	smart-5fc2570c-4abc-471f-bc83-3a2e11b6acac
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30060 61656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.3006061656
Directory	/workspace/10.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/10.alert_handler_sig_int_fail.1231704110
Short name	T101
Test name
Test status
Simulation time	1950984534 ps
CPU time	24.09 seconds
Started	Jul 31 05:21:36 PM PDT 24
Finished	Jul 31 05:22:00 PM PDT 24
Peak memory	248340 kb
Host	smart-8d88bd1e-4072-40b6-9342-316c8be995b6
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12317 04110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.1231704110
Directory	/workspace/10.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/10.alert_handler_smoke.1275059428
Short name	T495
Test name
Test status
Simulation time	559983355 ps
CPU time	10.3 seconds
Started	Jul 31 05:21:18 PM PDT 24
Finished	Jul 31 05:21:29 PM PDT 24
Peak memory	248696 kb
Host	smart-4e543702-161d-4c81-ab27-9d77d46f18f3
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12750 59428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.1275059428
Directory	/workspace/10.alert_handler_smoke/latest

Test location	/workspace/coverage/default/11.alert_handler_alert_accum_saturation.3145436524
Short name	T60
Test name
Test status
Simulation time	15504795 ps
CPU time	2.62 seconds
Started	Jul 31 05:22:09 PM PDT 24
Finished	Jul 31 05:22:12 PM PDT 24
Peak memory	248640 kb
Host	smart-91e25128-065b-4400-be04-01396d4817a8
User	root
Command	/workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=3145436524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.3145436524
Directory	/workspace/11.alert_handler_alert_accum_saturation/latest

Test location	/workspace/coverage/default/11.alert_handler_entropy.1298044969
Short name	T667
Test name
Test status
Simulation time	36329491284 ps
CPU time	2511.06 seconds
Started	Jul 31 05:21:26 PM PDT 24
Finished	Jul 31 06:03:18 PM PDT 24
Peak memory	289292 kb
Host	smart-427b7a50-7e2c-4e27-8c99-5fd6d9872ba2
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1298044969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.1298044969
Directory	/workspace/11.alert_handler_entropy/latest

Test location	/workspace/coverage/default/11.alert_handler_entropy_stress.1145661736
Short name	T546
Test name
Test status
Simulation time	373716396 ps
CPU time	18.26 seconds
Started	Jul 31 05:21:29 PM PDT 24
Finished	Jul 31 05:21:47 PM PDT 24
Peak memory	248224 kb
Host	smart-8311d395-631a-46f7-9fc7-8edaabecc718
User	root
Command	/workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1145661736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.1145661736
Directory	/workspace/11.alert_handler_entropy_stress/latest

Test location	/workspace/coverage/default/11.alert_handler_esc_alert_accum.1033359602
Short name	T442
Test name
Test status
Simulation time	4886235538 ps
CPU time	163.95 seconds
Started	Jul 31 05:21:37 PM PDT 24
Finished	Jul 31 05:24:21 PM PDT 24
Peak memory	256512 kb
Host	smart-544ac92f-e1ed-4a32-b953-ba2cc771fb03
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10333 59602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.1033359602
Directory	/workspace/11.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/11.alert_handler_esc_intr_timeout.1103111262
Short name	T479
Test name
Test status
Simulation time	290327719 ps
CPU time	26.85 seconds
Started	Jul 31 05:21:46 PM PDT 24
Finished	Jul 31 05:22:13 PM PDT 24
Peak memory	248048 kb
Host	smart-04453cc3-e37c-4d53-b4e8-21c6ee5060de
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11031 11262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.1103111262
Directory	/workspace/11.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/11.alert_handler_lpg.3357842954
Short name	T220
Test name
Test status
Simulation time	141902126308 ps
CPU time	978.94 seconds
Started	Jul 31 05:22:02 PM PDT 24
Finished	Jul 31 05:38:21 PM PDT 24
Peak memory	273132 kb
Host	smart-faba0f73-5341-4876-989d-86765df63c12
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3357842954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.3357842954
Directory	/workspace/11.alert_handler_lpg/latest

Test location	/workspace/coverage/default/11.alert_handler_lpg_stub_clk.4223413398
Short name	T234
Test name
Test status
Simulation time	118574710774 ps
CPU time	1618.96 seconds
Started	Jul 31 05:21:43 PM PDT 24
Finished	Jul 31 05:48:42 PM PDT 24
Peak memory	272488 kb
Host	smart-6307b434-036a-40de-bdf6-ac15c0f79dbe
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4223413398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.4223413398
Directory	/workspace/11.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/11.alert_handler_ping_timeout.817050240
Short name	T595
Test name
Test status
Simulation time	3532622402 ps
CPU time	144.24 seconds
Started	Jul 31 05:21:46 PM PDT 24
Finished	Jul 31 05:24:10 PM PDT 24
Peak memory	248408 kb
Host	smart-fed1af5e-e833-400d-8871-05a457292d05
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=817050240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.817050240
Directory	/workspace/11.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/11.alert_handler_random_alerts.235073859
Short name	T714
Test name
Test status
Simulation time	281784928 ps
CPU time	18.67 seconds
Started	Jul 31 05:21:37 PM PDT 24
Finished	Jul 31 05:21:56 PM PDT 24
Peak memory	255856 kb
Host	smart-3d8cbb38-3fa3-4390-82df-0dcafe8eddee
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23507 3859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.235073859
Directory	/workspace/11.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/11.alert_handler_random_classes.2491626988
Short name	T568
Test name
Test status
Simulation time	128424330 ps
CPU time	12.65 seconds
Started	Jul 31 05:21:52 PM PDT 24
Finished	Jul 31 05:22:05 PM PDT 24
Peak memory	256084 kb
Host	smart-0f845b2f-f02d-410e-b141-46a81ca6323e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24916 26988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.2491626988
Directory	/workspace/11.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/11.alert_handler_sig_int_fail.4065828857
Short name	T357
Test name
Test status
Simulation time	507044486 ps
CPU time	31.38 seconds
Started	Jul 31 05:21:47 PM PDT 24
Finished	Jul 31 05:22:18 PM PDT 24
Peak memory	247892 kb
Host	smart-933d3fa8-29ee-44e3-8656-79d5fbb79c39
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40658 28857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.4065828857
Directory	/workspace/11.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/11.alert_handler_smoke.342434932
Short name	T356
Test name
Test status
Simulation time	279307472 ps
CPU time	10.76 seconds
Started	Jul 31 05:21:42 PM PDT 24
Finished	Jul 31 05:21:53 PM PDT 24
Peak memory	248388 kb
Host	smart-7c1c24e4-c109-4b04-91fb-2308274474ab
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34243 4932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.342434932
Directory	/workspace/11.alert_handler_smoke/latest

Test location	/workspace/coverage/default/11.alert_handler_stress_all.4168534505
Short name	T621
Test name
Test status
Simulation time	104206503826 ps
CPU time	840.97 seconds
Started	Jul 31 05:21:32 PM PDT 24
Finished	Jul 31 05:35:33 PM PDT 24
Peak memory	272748 kb
Host	smart-841fb16b-8d2d-4f61-8754-156a53e827c1
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168534505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha ndler_stress_all.4168534505
Directory	/workspace/11.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/12.alert_handler_entropy.451919580
Short name	T548
Test name
Test status
Simulation time	12549838389 ps
CPU time	1389.71 seconds
Started	Jul 31 05:21:42 PM PDT 24
Finished	Jul 31 05:44:52 PM PDT 24
Peak memory	288648 kb
Host	smart-2fcdeff2-182d-431e-a1c8-fa69aacfe0d4
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=451919580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.451919580
Directory	/workspace/12.alert_handler_entropy/latest

Test location	/workspace/coverage/default/12.alert_handler_entropy_stress.3460302370
Short name	T494
Test name
Test status
Simulation time	372798340 ps
CPU time	19.44 seconds
Started	Jul 31 05:21:41 PM PDT 24
Finished	Jul 31 05:22:02 PM PDT 24
Peak memory	248164 kb
Host	smart-88f6c0ab-eb23-433e-b996-f14bcc7966d1
User	root
Command	/workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=3460302370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.3460302370
Directory	/workspace/12.alert_handler_entropy_stress/latest

Test location	/workspace/coverage/default/12.alert_handler_esc_intr_timeout.3605762701
Short name	T570
Test name
Test status
Simulation time	374257891 ps
CPU time	21.51 seconds
Started	Jul 31 05:22:05 PM PDT 24
Finished	Jul 31 05:22:26 PM PDT 24
Peak memory	247920 kb
Host	smart-0118207b-7594-440d-9a9a-43732a779a10
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36057 62701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.3605762701
Directory	/workspace/12.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/12.alert_handler_lpg.2405149174
Short name	T319
Test name
Test status
Simulation time	19037567342 ps
CPU time	1139.45 seconds
Started	Jul 31 05:21:42 PM PDT 24
Finished	Jul 31 05:40:42 PM PDT 24
Peak memory	264600 kb
Host	smart-7c865ec5-d7ef-4238-80aa-9ee7199ed6de
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2405149174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.2405149174
Directory	/workspace/12.alert_handler_lpg/latest

Test location	/workspace/coverage/default/12.alert_handler_lpg_stub_clk.1956120228
Short name	T397
Test name
Test status
Simulation time	30062775933 ps
CPU time	1726.32 seconds
Started	Jul 31 05:21:30 PM PDT 24
Finished	Jul 31 05:50:17 PM PDT 24
Peak memory	272848 kb
Host	smart-56e942a4-4781-408f-9e15-c47a4f9fc4ab
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1956120228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.1956120228
Directory	/workspace/12.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/12.alert_handler_ping_timeout.1893319763
Short name	T217
Test name
Test status
Simulation time	10268984074 ps
CPU time	200.1 seconds
Started	Jul 31 05:21:54 PM PDT 24
Finished	Jul 31 05:25:14 PM PDT 24
Peak memory	248348 kb
Host	smart-7326f931-4f65-4f36-baae-5c73a92fd587
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1893319763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.1893319763
Directory	/workspace/12.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/12.alert_handler_random_alerts.2071513948
Short name	T575
Test name
Test status
Simulation time	346701409 ps
CPU time	29.94 seconds
Started	Jul 31 05:21:43 PM PDT 24
Finished	Jul 31 05:22:13 PM PDT 24
Peak memory	248272 kb
Host	smart-6d6ef224-6183-4bd5-9bcb-f1a212aea9dc
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20715 13948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.2071513948
Directory	/workspace/12.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/12.alert_handler_random_classes.2184352266
Short name	T416
Test name
Test status
Simulation time	1729768664 ps
CPU time	39.12 seconds
Started	Jul 31 05:21:30 PM PDT 24
Finished	Jul 31 05:22:09 PM PDT 24
Peak memory	248336 kb
Host	smart-eb28e54c-a553-4bed-833a-23ffb7fd8bc6
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21843 52266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.2184352266
Directory	/workspace/12.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/12.alert_handler_sig_int_fail.2957704448
Short name	T264
Test name
Test status
Simulation time	325136806 ps
CPU time	12.04 seconds
Started	Jul 31 05:21:36 PM PDT 24
Finished	Jul 31 05:21:49 PM PDT 24
Peak memory	247800 kb
Host	smart-25189257-f91c-4a32-8ebf-2521e5a45b9d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29577 04448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.2957704448
Directory	/workspace/12.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/12.alert_handler_smoke.2986624705
Short name	T40
Test name
Test status
Simulation time	1325538571 ps
CPU time	22 seconds
Started	Jul 31 05:21:35 PM PDT 24
Finished	Jul 31 05:21:57 PM PDT 24
Peak memory	256208 kb
Host	smart-8b776e10-38c3-4711-bbed-076381bc572f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29866 24705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.2986624705
Directory	/workspace/12.alert_handler_smoke/latest

Test location	/workspace/coverage/default/12.alert_handler_stress_all.2733356233
Short name	T41
Test name
Test status
Simulation time	40216152286 ps
CPU time	2134.47 seconds
Started	Jul 31 05:21:49 PM PDT 24
Finished	Jul 31 05:57:24 PM PDT 24
Peak memory	288756 kb
Host	smart-64cfeea4-af2a-43f3-b922-985a82fb993c
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733356233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha ndler_stress_all.2733356233
Directory	/workspace/12.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/13.alert_handler_alert_accum_saturation.928040722
Short name	T199
Test name
Test status
Simulation time	24768401 ps
CPU time	2.58 seconds
Started	Jul 31 05:21:39 PM PDT 24
Finished	Jul 31 05:21:42 PM PDT 24
Peak memory	248640 kb
Host	smart-343b4712-02d5-476a-9008-f92640acd1a8
User	root
Command	/workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=928040722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.928040722
Directory	/workspace/13.alert_handler_alert_accum_saturation/latest

Test location	/workspace/coverage/default/13.alert_handler_entropy.3293057054
Short name	T301
Test name
Test status
Simulation time	31601191138 ps
CPU time	1207.3 seconds
Started	Jul 31 05:21:53 PM PDT 24
Finished	Jul 31 05:42:00 PM PDT 24
Peak memory	283268 kb
Host	smart-22ceddbe-c870-47c1-8d31-90d697cd984f
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3293057054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.3293057054
Directory	/workspace/13.alert_handler_entropy/latest

Test location	/workspace/coverage/default/13.alert_handler_entropy_stress.3144460571
Short name	T543
Test name
Test status
Simulation time	481038707 ps
CPU time	13.97 seconds
Started	Jul 31 05:21:43 PM PDT 24
Finished	Jul 31 05:21:57 PM PDT 24
Peak memory	248340 kb
Host	smart-7ddcbe40-5fac-4031-9041-073e61dde0a5
User	root
Command	/workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=3144460571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.3144460571
Directory	/workspace/13.alert_handler_entropy_stress/latest

Test location	/workspace/coverage/default/13.alert_handler_esc_alert_accum.2320615122
Short name	T418
Test name
Test status
Simulation time	4921143419 ps
CPU time	273.59 seconds
Started	Jul 31 05:21:43 PM PDT 24
Finished	Jul 31 05:26:18 PM PDT 24
Peak memory	256544 kb
Host	smart-4189d04e-edfb-49b0-ad95-6711db733e0d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23206 15122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.2320615122
Directory	/workspace/13.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/13.alert_handler_esc_intr_timeout.2984038049
Short name	T414
Test name
Test status
Simulation time	200396252 ps
CPU time	5.46 seconds
Started	Jul 31 05:21:59 PM PDT 24
Finished	Jul 31 05:22:09 PM PDT 24
Peak memory	251936 kb
Host	smart-6aa94734-3434-4f82-bddd-85044b7b6b28
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29840 38049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.2984038049
Directory	/workspace/13.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/13.alert_handler_lpg.3557799238
Short name	T341
Test name
Test status
Simulation time	8299287701 ps
CPU time	799.25 seconds
Started	Jul 31 05:22:02 PM PDT 24
Finished	Jul 31 05:35:26 PM PDT 24
Peak memory	272868 kb
Host	smart-c15ef128-6257-49d0-ac6c-00df33e3358a
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3557799238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.3557799238
Directory	/workspace/13.alert_handler_lpg/latest

Test location	/workspace/coverage/default/13.alert_handler_lpg_stub_clk.3961204802
Short name	T609
Test name
Test status
Simulation time	29215995258 ps
CPU time	1977.02 seconds
Started	Jul 31 05:21:42 PM PDT 24
Finished	Jul 31 05:54:40 PM PDT 24
Peak memory	288500 kb
Host	smart-4364f4d4-dbf2-422a-9da7-c5316df7cc23
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3961204802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.3961204802
Directory	/workspace/13.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/13.alert_handler_random_alerts.4211224566
Short name	T514
Test name
Test status
Simulation time	17916518095 ps
CPU time	67.09 seconds
Started	Jul 31 05:21:54 PM PDT 24
Finished	Jul 31 05:23:01 PM PDT 24
Peak memory	256572 kb
Host	smart-1120ab32-ecd4-4898-acdb-a40c4dc1dea7
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42112 24566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.4211224566
Directory	/workspace/13.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/13.alert_handler_sig_int_fail.2911148010
Short name	T76
Test name
Test status
Simulation time	643741157 ps
CPU time	16.9 seconds
Started	Jul 31 05:21:54 PM PDT 24
Finished	Jul 31 05:22:11 PM PDT 24
Peak memory	248300 kb
Host	smart-c8a381a8-5630-4041-b147-fec1d9922c28
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29111 48010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.2911148010
Directory	/workspace/13.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/13.alert_handler_smoke.3595909701
Short name	T653
Test name
Test status
Simulation time	376076901 ps
CPU time	13.64 seconds
Started	Jul 31 05:21:57 PM PDT 24
Finished	Jul 31 05:22:11 PM PDT 24
Peak memory	248288 kb
Host	smart-ff0e4b0d-b6c1-4f75-8155-30ac41ce6b33
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35959 09701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.3595909701
Directory	/workspace/13.alert_handler_smoke/latest

Test location	/workspace/coverage/default/13.alert_handler_stress_all.1128992169
Short name	T77
Test name
Test status
Simulation time	29895188050 ps
CPU time	1392.9 seconds
Started	Jul 31 05:21:57 PM PDT 24
Finished	Jul 31 05:45:11 PM PDT 24
Peak memory	289324 kb
Host	smart-dc6a9d87-4f46-4348-b5eb-a2d46ffb8453
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128992169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha ndler_stress_all.1128992169
Directory	/workspace/13.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.956307897
Short name	T505
Test name
Test status
Simulation time	151198983414 ps
CPU time	6501.29 seconds
Started	Jul 31 05:21:41 PM PDT 24
Finished	Jul 31 07:10:04 PM PDT 24
Peak memory	353424 kb
Host	smart-a103e287-afd9-402b-88a5-ef59179f002e
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956307897 -assert nopostproc +UVM_TESTNAME=alert _handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.956307897
Directory	/workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/14.alert_handler_entropy.1678839136
Short name	T485
Test name
Test status
Simulation time	26190059666 ps
CPU time	752.52 seconds
Started	Jul 31 05:21:50 PM PDT 24
Finished	Jul 31 05:34:23 PM PDT 24
Peak memory	272624 kb
Host	smart-49c80fa4-fb74-4c9c-8244-a45be40722e5
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1678839136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.1678839136
Directory	/workspace/14.alert_handler_entropy/latest

Test location	/workspace/coverage/default/14.alert_handler_entropy_stress.2694176677
Short name	T237
Test name
Test status
Simulation time	1016427503 ps
CPU time	39.46 seconds
Started	Jul 31 05:21:47 PM PDT 24
Finished	Jul 31 05:22:26 PM PDT 24
Peak memory	248172 kb
Host	smart-9c019cde-4c71-47a6-8fc8-dcde6445c0c3
User	root
Command	/workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=2694176677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.2694176677
Directory	/workspace/14.alert_handler_entropy_stress/latest

Test location	/workspace/coverage/default/14.alert_handler_esc_alert_accum.1939843767
Short name	T410
Test name
Test status
Simulation time	4264486249 ps
CPU time	249.19 seconds
Started	Jul 31 05:21:46 PM PDT 24
Finished	Jul 31 05:25:55 PM PDT 24
Peak memory	256088 kb
Host	smart-1c7dacbc-69a0-4223-b8e2-36d628a75404
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19398 43767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.1939843767
Directory	/workspace/14.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/14.alert_handler_esc_intr_timeout.721269539
Short name	T564
Test name
Test status
Simulation time	470242402 ps
CPU time	29.51 seconds
Started	Jul 31 05:21:42 PM PDT 24
Finished	Jul 31 05:22:12 PM PDT 24
Peak memory	248256 kb
Host	smart-1ffd59ba-13bf-4048-a699-17561331ab97
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72126 9539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.721269539
Directory	/workspace/14.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/14.alert_handler_lpg.187039947
Short name	T574
Test name
Test status
Simulation time	28009934890 ps
CPU time	1304.05 seconds
Started	Jul 31 05:21:43 PM PDT 24
Finished	Jul 31 05:43:27 PM PDT 24
Peak memory	287912 kb
Host	smart-f59eead3-0b48-4996-811a-eaba45b552ee
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=187039947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.187039947
Directory	/workspace/14.alert_handler_lpg/latest

Test location	/workspace/coverage/default/14.alert_handler_lpg_stub_clk.3850710442
Short name	T89
Test name
Test status
Simulation time	19623958664 ps
CPU time	1286.9 seconds
Started	Jul 31 05:21:51 PM PDT 24
Finished	Jul 31 05:43:18 PM PDT 24
Peak memory	272776 kb
Host	smart-42f4620d-5acb-4b7f-890f-fc8a81fc9c54
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3850710442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.3850710442
Directory	/workspace/14.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/14.alert_handler_ping_timeout.3346199835
Short name	T307
Test name
Test status
Simulation time	39869705921 ps
CPU time	281.01 seconds
Started	Jul 31 05:21:55 PM PDT 24
Finished	Jul 31 05:26:36 PM PDT 24
Peak memory	248388 kb
Host	smart-07e9f307-275c-43ea-9642-5f700a3586a1
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3346199835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.3346199835
Directory	/workspace/14.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/14.alert_handler_random_alerts.1505267843
Short name	T696
Test name
Test status
Simulation time	602722862 ps
CPU time	29.66 seconds
Started	Jul 31 05:21:35 PM PDT 24
Finished	Jul 31 05:22:05 PM PDT 24
Peak memory	255804 kb
Host	smart-0ed73cfd-7fbd-4eee-a51e-0cca3238acd8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15052 67843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.1505267843
Directory	/workspace/14.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/14.alert_handler_random_classes.937534243
Short name	T708
Test name
Test status
Simulation time	2194826683 ps
CPU time	14.65 seconds
Started	Jul 31 05:21:47 PM PDT 24
Finished	Jul 31 05:22:02 PM PDT 24
Peak memory	255700 kb
Host	smart-0e0d773c-11c5-4ea5-b4f9-2c67e8cfd7ef
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93753 4243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.937534243
Directory	/workspace/14.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/14.alert_handler_sig_int_fail.2433107098
Short name	T254
Test name
Test status
Simulation time	643320050 ps
CPU time	44.7 seconds
Started	Jul 31 05:22:10 PM PDT 24
Finished	Jul 31 05:22:55 PM PDT 24
Peak memory	255840 kb
Host	smart-ea2a9230-1949-4511-a22a-09b406df9e9f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24331 07098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.2433107098
Directory	/workspace/14.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/14.alert_handler_smoke.149363323
Short name	T524
Test name
Test status
Simulation time	82490431 ps
CPU time	8.71 seconds
Started	Jul 31 05:21:39 PM PDT 24
Finished	Jul 31 05:21:48 PM PDT 24
Peak memory	248372 kb
Host	smart-005fde44-a12f-4689-9bf3-5efc75f34492
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14936 3323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.149363323
Directory	/workspace/14.alert_handler_smoke/latest

Test location	/workspace/coverage/default/14.alert_handler_stress_all.215803586
Short name	T579
Test name
Test status
Simulation time	56121793693 ps
CPU time	1909.41 seconds
Started	Jul 31 05:21:51 PM PDT 24
Finished	Jul 31 05:53:41 PM PDT 24
Peak memory	283464 kb
Host	smart-72c780ac-4ae3-48d8-965f-712f9434f3ee
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215803586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_han dler_stress_all.215803586
Directory	/workspace/14.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/14.alert_handler_stress_all_with_rand_reset.370816185
Short name	T491
Test name
Test status
Simulation time	125455293302 ps
CPU time	7212.59 seconds
Started	Jul 31 05:21:45 PM PDT 24
Finished	Jul 31 07:21:58 PM PDT 24
Peak memory	338544 kb
Host	smart-78f8a6b2-e677-4627-81ac-42511d968bbe
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370816185 -assert nopostproc +UVM_TESTNAME=alert _handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 14.alert_handler_stress_all_with_rand_reset.370816185
Directory	/workspace/14.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/15.alert_handler_alert_accum_saturation.1080202009
Short name	T213
Test name
Test status
Simulation time	14003295 ps
CPU time	2.6 seconds
Started	Jul 31 05:21:44 PM PDT 24
Finished	Jul 31 05:21:46 PM PDT 24
Peak memory	248668 kb
Host	smart-0b39995e-3539-4fc9-ab93-17a9d4315a6f
User	root
Command	/workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1080202009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.1080202009
Directory	/workspace/15.alert_handler_alert_accum_saturation/latest

Test location	/workspace/coverage/default/15.alert_handler_entropy.1268487611
Short name	T462
Test name
Test status
Simulation time	37078101347 ps
CPU time	1370.21 seconds
Started	Jul 31 05:21:45 PM PDT 24
Finished	Jul 31 05:44:36 PM PDT 24
Peak memory	287972 kb
Host	smart-9a87ec66-755b-47db-bc8e-72b6d5b10cee
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1268487611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.1268487611
Directory	/workspace/15.alert_handler_entropy/latest

Test location	/workspace/coverage/default/15.alert_handler_entropy_stress.3610816712
Short name	T427
Test name
Test status
Simulation time	2644685131 ps
CPU time	27.51 seconds
Started	Jul 31 05:21:46 PM PDT 24
Finished	Jul 31 05:22:14 PM PDT 24
Peak memory	248336 kb
Host	smart-3d96b7cb-df36-4763-8b3b-21e1e8e7aa72
User	root
Command	/workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=3610816712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.3610816712
Directory	/workspace/15.alert_handler_entropy_stress/latest

Test location	/workspace/coverage/default/15.alert_handler_esc_alert_accum.1859136770
Short name	T454
Test name
Test status
Simulation time	23460628460 ps
CPU time	300.57 seconds
Started	Jul 31 05:21:48 PM PDT 24
Finished	Jul 31 05:26:49 PM PDT 24
Peak memory	255868 kb
Host	smart-3aaee3b7-11a1-4590-99e9-342a93144c05
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18591 36770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.1859136770
Directory	/workspace/15.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/15.alert_handler_esc_intr_timeout.1023883024
Short name	T396
Test name
Test status
Simulation time	311545786 ps
CPU time	21.41 seconds
Started	Jul 31 05:21:43 PM PDT 24
Finished	Jul 31 05:22:05 PM PDT 24
Peak memory	247872 kb
Host	smart-58c65068-f0f5-4913-bd85-d80882c1961a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10238 83024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.1023883024
Directory	/workspace/15.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/15.alert_handler_lpg.3962134174
Short name	T556
Test name
Test status
Simulation time	29555956846 ps
CPU time	566.77 seconds
Started	Jul 31 05:21:50 PM PDT 24
Finished	Jul 31 05:31:17 PM PDT 24
Peak memory	272860 kb
Host	smart-2fb81e0b-880a-47ae-83c9-ded3053217e8
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3962134174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.3962134174
Directory	/workspace/15.alert_handler_lpg/latest

Test location	/workspace/coverage/default/15.alert_handler_lpg_stub_clk.2580170662
Short name	T684
Test name
Test status
Simulation time	232769390192 ps
CPU time	1343.6 seconds
Started	Jul 31 05:21:52 PM PDT 24
Finished	Jul 31 05:44:16 PM PDT 24
Peak memory	264756 kb
Host	smart-0aa619bc-d957-48ea-b556-d431b2b320e0
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2580170662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.2580170662
Directory	/workspace/15.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/15.alert_handler_ping_timeout.2532082068
Short name	T322
Test name
Test status
Simulation time	9664321458 ps
CPU time	195.52 seconds
Started	Jul 31 05:21:59 PM PDT 24
Finished	Jul 31 05:25:15 PM PDT 24
Peak memory	247244 kb
Host	smart-80b87287-066d-48f2-8fa6-7fc9ab158d05
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2532082068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.2532082068
Directory	/workspace/15.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/15.alert_handler_random_alerts.2174217810
Short name	T476
Test name
Test status
Simulation time	89014822 ps
CPU time	7.18 seconds
Started	Jul 31 05:21:45 PM PDT 24
Finished	Jul 31 05:21:52 PM PDT 24
Peak memory	248268 kb
Host	smart-d0e2537b-3e88-4ffd-a252-708e6123ffdb
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21742 17810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.2174217810
Directory	/workspace/15.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/15.alert_handler_random_classes.716870647
Short name	T698
Test name
Test status
Simulation time	1027619169 ps
CPU time	19.11 seconds
Started	Jul 31 05:21:58 PM PDT 24
Finished	Jul 31 05:22:17 PM PDT 24
Peak memory	247824 kb
Host	smart-3c1b6558-01af-4005-9b6a-6ff630a1c58b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71687 0647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.716870647
Directory	/workspace/15.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/15.alert_handler_smoke.873415862
Short name	T359
Test name
Test status
Simulation time	104613045 ps
CPU time	2.54 seconds
Started	Jul 31 05:21:44 PM PDT 24
Finished	Jul 31 05:21:47 PM PDT 24
Peak memory	250604 kb
Host	smart-83c34bcf-33f9-410c-be4d-2c0f0cff0b32
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87341 5862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.873415862
Directory	/workspace/15.alert_handler_smoke/latest

Test location	/workspace/coverage/default/16.alert_handler_alert_accum_saturation.266376783
Short name	T207
Test name
Test status
Simulation time	16646993 ps
CPU time	3 seconds
Started	Jul 31 05:22:00 PM PDT 24
Finished	Jul 31 05:22:04 PM PDT 24
Peak memory	248660 kb
Host	smart-e6e11d3b-9e00-4d6a-a246-2ab761f72fb0
User	root
Command	/workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=266376783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.266376783
Directory	/workspace/16.alert_handler_alert_accum_saturation/latest

Test location	/workspace/coverage/default/16.alert_handler_entropy.4034499876
Short name	T504
Test name
Test status
Simulation time	21956314609 ps
CPU time	1337.62 seconds
Started	Jul 31 05:21:50 PM PDT 24
Finished	Jul 31 05:44:08 PM PDT 24
Peak memory	272256 kb
Host	smart-96698ac9-af3a-46e7-99f8-637018b32093
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4034499876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.4034499876
Directory	/workspace/16.alert_handler_entropy/latest

Test location	/workspace/coverage/default/16.alert_handler_entropy_stress.1746773455
Short name	T445
Test name
Test status
Simulation time	1782893037 ps
CPU time	70.43 seconds
Started	Jul 31 05:22:13 PM PDT 24
Finished	Jul 31 05:23:24 PM PDT 24
Peak memory	248292 kb
Host	smart-c2875222-3645-4638-a2cf-d2822fd7ea51
User	root
Command	/workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1746773455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.1746773455
Directory	/workspace/16.alert_handler_entropy_stress/latest

Test location	/workspace/coverage/default/16.alert_handler_esc_alert_accum.4036128341
Short name	T216
Test name
Test status
Simulation time	2178289647 ps
CPU time	27.39 seconds
Started	Jul 31 05:21:42 PM PDT 24
Finished	Jul 31 05:22:10 PM PDT 24
Peak memory	255620 kb
Host	smart-6280b1b7-4978-4523-98e9-cb16490c01de
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40361 28341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.4036128341
Directory	/workspace/16.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/16.alert_handler_lpg_stub_clk.3209856769
Short name	T423
Test name
Test status
Simulation time	26398004391 ps
CPU time	1547.47 seconds
Started	Jul 31 05:21:44 PM PDT 24
Finished	Jul 31 05:47:31 PM PDT 24
Peak memory	265792 kb
Host	smart-5976fe5a-0a41-4375-ac23-32988e789bc7
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3209856769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.3209856769
Directory	/workspace/16.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/16.alert_handler_ping_timeout.4211222141
Short name	T62
Test name
Test status
Simulation time	26024313291 ps
CPU time	273.31 seconds
Started	Jul 31 05:21:57 PM PDT 24
Finished	Jul 31 05:26:30 PM PDT 24
Peak memory	248416 kb
Host	smart-842b2853-4c19-416f-98c5-c5b424eea69f
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4211222141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.4211222141
Directory	/workspace/16.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/16.alert_handler_random_alerts.1001804881
Short name	T43
Test name
Test status
Simulation time	1766497435 ps
CPU time	29.84 seconds
Started	Jul 31 05:21:51 PM PDT 24
Finished	Jul 31 05:22:22 PM PDT 24
Peak memory	255504 kb
Host	smart-f531f2bd-7b31-4836-a3f5-5827e6f5f98e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10018 04881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.1001804881
Directory	/workspace/16.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/16.alert_handler_random_classes.23821782
Short name	T522
Test name
Test status
Simulation time	33753881 ps
CPU time	4.35 seconds
Started	Jul 31 05:22:05 PM PDT 24
Finished	Jul 31 05:22:09 PM PDT 24
Peak memory	239676 kb
Host	smart-0ada3b61-0d74-48c0-8123-fb4651864964
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23821 782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.23821782
Directory	/workspace/16.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/16.alert_handler_sig_int_fail.3219948048
Short name	T561
Test name
Test status
Simulation time	1141900170 ps
CPU time	30.19 seconds
Started	Jul 31 05:21:43 PM PDT 24
Finished	Jul 31 05:22:14 PM PDT 24
Peak memory	255916 kb
Host	smart-7538bcbe-f740-41c0-ae63-b24289dd9221
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32199 48048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.3219948048
Directory	/workspace/16.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/16.alert_handler_smoke.2965999609
Short name	T499
Test name
Test status
Simulation time	1624489538 ps
CPU time	26.98 seconds
Started	Jul 31 05:21:44 PM PDT 24
Finished	Jul 31 05:22:11 PM PDT 24
Peak memory	248292 kb
Host	smart-922ef983-d382-4a24-bda3-646585242d38
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29659 99609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.2965999609
Directory	/workspace/16.alert_handler_smoke/latest

Test location	/workspace/coverage/default/16.alert_handler_stress_all.2569541367
Short name	T600
Test name
Test status
Simulation time	463311857346 ps
CPU time	3721.29 seconds
Started	Jul 31 05:22:07 PM PDT 24
Finished	Jul 31 06:24:08 PM PDT 24
Peak memory	304332 kb
Host	smart-996d0de2-15b2-4229-93c1-2d5ebad6e2ea
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569541367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha ndler_stress_all.2569541367
Directory	/workspace/16.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/17.alert_handler_alert_accum_saturation.3926033010
Short name	T204
Test name
Test status
Simulation time	73402092 ps
CPU time	2.91 seconds
Started	Jul 31 05:22:09 PM PDT 24
Finished	Jul 31 05:22:12 PM PDT 24
Peak memory	248628 kb
Host	smart-f8375cb7-5014-46c6-84f1-c8353e296ec6
User	root
Command	/workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=3926033010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.3926033010
Directory	/workspace/17.alert_handler_alert_accum_saturation/latest

Test location	/workspace/coverage/default/17.alert_handler_entropy.1934582763
Short name	T643
Test name
Test status
Simulation time	43045899198 ps
CPU time	957.29 seconds
Started	Jul 31 05:21:46 PM PDT 24
Finished	Jul 31 05:37:43 PM PDT 24
Peak memory	269924 kb
Host	smart-1d0f6933-e0d4-47ce-9c01-85bad34b7721
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1934582763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.1934582763
Directory	/workspace/17.alert_handler_entropy/latest

Test location	/workspace/coverage/default/17.alert_handler_entropy_stress.3289354141
Short name	T424
Test name
Test status
Simulation time	606708812 ps
CPU time	10.51 seconds
Started	Jul 31 05:21:58 PM PDT 24
Finished	Jul 31 05:22:09 PM PDT 24
Peak memory	248332 kb
Host	smart-29600cb6-217d-4c4c-926e-13cb2230eeee
User	root
Command	/workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=3289354141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.3289354141
Directory	/workspace/17.alert_handler_entropy_stress/latest

Test location	/workspace/coverage/default/17.alert_handler_esc_alert_accum.232204682
Short name	T395
Test name
Test status
Simulation time	6588107947 ps
CPU time	137.18 seconds
Started	Jul 31 05:22:14 PM PDT 24
Finished	Jul 31 05:24:31 PM PDT 24
Peak memory	255828 kb
Host	smart-ff083962-9fe3-4ae4-9965-33179c1f5f6e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23220 4682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.232204682
Directory	/workspace/17.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/17.alert_handler_esc_intr_timeout.4092090945
Short name	T449
Test name
Test status
Simulation time	249741398 ps
CPU time	11.55 seconds
Started	Jul 31 05:22:04 PM PDT 24
Finished	Jul 31 05:22:16 PM PDT 24
Peak memory	254764 kb
Host	smart-904eb8f8-7c49-4643-be8c-8426b4171499
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40920 90945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.4092090945
Directory	/workspace/17.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/17.alert_handler_lpg.1431745848
Short name	T640
Test name
Test status
Simulation time	66602697454 ps
CPU time	2085.64 seconds
Started	Jul 31 05:21:49 PM PDT 24
Finished	Jul 31 05:56:35 PM PDT 24
Peak memory	272284 kb
Host	smart-ba4a079f-9e5b-468d-93be-dda2c58854f6
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1431745848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.1431745848
Directory	/workspace/17.alert_handler_lpg/latest

Test location	/workspace/coverage/default/17.alert_handler_lpg_stub_clk.3826436376
Short name	T378
Test name
Test status
Simulation time	142472981982 ps
CPU time	2349.52 seconds
Started	Jul 31 05:21:46 PM PDT 24
Finished	Jul 31 06:00:56 PM PDT 24
Peak memory	289036 kb
Host	smart-5cdeb04b-9ee7-4e8f-9b1c-d23de6c40bf4
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3826436376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.3826436376
Directory	/workspace/17.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/17.alert_handler_ping_timeout.1654763871
Short name	T311
Test name
Test status
Simulation time	5320659831 ps
CPU time	211.87 seconds
Started	Jul 31 05:21:47 PM PDT 24
Finished	Jul 31 05:25:19 PM PDT 24
Peak memory	248380 kb
Host	smart-302a88b4-1d36-4868-a765-0f8c3d989e46
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1654763871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.1654763871
Directory	/workspace/17.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/17.alert_handler_random_alerts.3206453151
Short name	T38
Test name
Test status
Simulation time	289517699 ps
CPU time	23.51 seconds
Started	Jul 31 05:21:53 PM PDT 24
Finished	Jul 31 05:22:17 PM PDT 24
Peak memory	255760 kb
Host	smart-ebec944a-e96e-4992-bcbe-e5ea217b7058
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32064 53151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.3206453151
Directory	/workspace/17.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/17.alert_handler_random_classes.3537630534
Short name	T674
Test name
Test status
Simulation time	1683696859 ps
CPU time	53.6 seconds
Started	Jul 31 05:21:47 PM PDT 24
Finished	Jul 31 05:22:41 PM PDT 24
Peak memory	247824 kb
Host	smart-e194dbec-f896-45de-b3fd-975bc499093c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35376 30534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.3537630534
Directory	/workspace/17.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/17.alert_handler_sig_int_fail.2758136542
Short name	T63
Test name
Test status
Simulation time	59977850 ps
CPU time	6.88 seconds
Started	Jul 31 05:21:45 PM PDT 24
Finished	Jul 31 05:21:52 PM PDT 24
Peak memory	248936 kb
Host	smart-c0ef6087-a58d-4d3c-ada1-5e78518b3584
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27581 36542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.2758136542
Directory	/workspace/17.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/17.alert_handler_smoke.2874884548
Short name	T382
Test name
Test status
Simulation time	1792480949 ps
CPU time	19.81 seconds
Started	Jul 31 05:21:52 PM PDT 24
Finished	Jul 31 05:22:12 PM PDT 24
Peak memory	255716 kb
Host	smart-75ba7c5e-72ff-4f18-96a7-556e5c582bc3
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28748 84548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.2874884548
Directory	/workspace/17.alert_handler_smoke/latest

Test location	/workspace/coverage/default/17.alert_handler_stress_all.48120210
Short name	T544
Test name
Test status
Simulation time	1779677871 ps
CPU time	40.65 seconds
Started	Jul 31 05:21:50 PM PDT 24
Finished	Jul 31 05:22:30 PM PDT 24
Peak memory	256604 kb
Host	smart-a1be4dfc-466c-4175-959f-0923a8d21384
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48120210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_hand ler_stress_all.48120210
Directory	/workspace/17.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/18.alert_handler_alert_accum_saturation.2984132962
Short name	T205
Test name
Test status
Simulation time	45140669 ps
CPU time	3.24 seconds
Started	Jul 31 05:21:49 PM PDT 24
Finished	Jul 31 05:21:53 PM PDT 24
Peak memory	248664 kb
Host	smart-0ddf313e-c4cf-4bbd-9f82-9fcd6e24ac09
User	root
Command	/workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=2984132962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.2984132962
Directory	/workspace/18.alert_handler_alert_accum_saturation/latest

Test location	/workspace/coverage/default/18.alert_handler_entropy.2474690115
Short name	T648
Test name
Test status
Simulation time	13713176712 ps
CPU time	973.72 seconds
Started	Jul 31 05:22:20 PM PDT 24
Finished	Jul 31 05:38:34 PM PDT 24
Peak memory	270912 kb
Host	smart-a331de9c-fba7-41dc-ad41-57a4a075da55
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2474690115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.2474690115
Directory	/workspace/18.alert_handler_entropy/latest

Test location	/workspace/coverage/default/18.alert_handler_entropy_stress.588552972
Short name	T502
Test name
Test status
Simulation time	773821906 ps
CPU time	11.86 seconds
Started	Jul 31 05:22:09 PM PDT 24
Finished	Jul 31 05:22:21 PM PDT 24
Peak memory	248260 kb
Host	smart-3e64a912-0389-43d3-b493-e78e3562d9b2
User	root
Command	/workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=588552972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.588552972
Directory	/workspace/18.alert_handler_entropy_stress/latest

Test location	/workspace/coverage/default/18.alert_handler_esc_alert_accum.2895964572
Short name	T16
Test name
Test status
Simulation time	9277627392 ps
CPU time	131.25 seconds
Started	Jul 31 05:21:48 PM PDT 24
Finished	Jul 31 05:24:00 PM PDT 24
Peak memory	256188 kb
Host	smart-f6eab5a2-b5f7-48ec-ad36-a70a2bec64d9
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28959 64572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.2895964572
Directory	/workspace/18.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/18.alert_handler_esc_intr_timeout.2160802181
Short name	T69
Test name
Test status
Simulation time	81871740 ps
CPU time	9.99 seconds
Started	Jul 31 05:21:43 PM PDT 24
Finished	Jul 31 05:21:54 PM PDT 24
Peak memory	247880 kb
Host	smart-195e735e-c568-433c-a0f1-513aa0ef1fc0
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21608 02181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.2160802181
Directory	/workspace/18.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/18.alert_handler_lpg_stub_clk.42673888
Short name	T180
Test name
Test status
Simulation time	92414431810 ps
CPU time	2803.99 seconds
Started	Jul 31 05:21:47 PM PDT 24
Finished	Jul 31 06:08:31 PM PDT 24
Peak memory	281156 kb
Host	smart-fac89321-eac4-4bc8-bb1a-04d95a4eab9b
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=42673888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.42673888
Directory	/workspace/18.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/18.alert_handler_ping_timeout.3544664378
Short name	T304
Test name
Test status
Simulation time	48197437601 ps
CPU time	489.43 seconds
Started	Jul 31 05:21:57 PM PDT 24
Finished	Jul 31 05:30:06 PM PDT 24
Peak memory	247296 kb
Host	smart-576afeed-573a-4667-b555-703f17aa9ed8
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3544664378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.3544664378
Directory	/workspace/18.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/18.alert_handler_random_alerts.1244991960
Short name	T369
Test name
Test status
Simulation time	223118128 ps
CPU time	6.26 seconds
Started	Jul 31 05:21:49 PM PDT 24
Finished	Jul 31 05:21:55 PM PDT 24
Peak memory	253056 kb
Host	smart-d89a42f7-9662-456a-9333-f9e73e07fae4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12449 91960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.1244991960
Directory	/workspace/18.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/18.alert_handler_random_classes.356626927
Short name	T649
Test name
Test status
Simulation time	567205556 ps
CPU time	30.91 seconds
Started	Jul 31 05:22:09 PM PDT 24
Finished	Jul 31 05:22:40 PM PDT 24
Peak memory	247640 kb
Host	smart-1cae0bae-a1df-4ae6-810f-aa657c75d583
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35662 6927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.356626927
Directory	/workspace/18.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/18.alert_handler_sig_int_fail.413680011
Short name	T534
Test name
Test status
Simulation time	1029866268 ps
CPU time	16.69 seconds
Started	Jul 31 05:21:55 PM PDT 24
Finished	Jul 31 05:22:12 PM PDT 24
Peak memory	248360 kb
Host	smart-b7308037-f8d6-412d-91ea-f72bfcb3029f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41368 0011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.413680011
Directory	/workspace/18.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/18.alert_handler_smoke.3822034581
Short name	T581
Test name
Test status
Simulation time	711573685 ps
CPU time	16.69 seconds
Started	Jul 31 05:22:03 PM PDT 24
Finished	Jul 31 05:22:20 PM PDT 24
Peak memory	256436 kb
Host	smart-5385c175-8fb6-4562-a34d-63670ee74892
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38220 34581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.3822034581
Directory	/workspace/18.alert_handler_smoke/latest

Test location	/workspace/coverage/default/18.alert_handler_stress_all.3787902933
Short name	T281
Test name
Test status
Simulation time	199982367752 ps
CPU time	2883.48 seconds
Started	Jul 31 05:21:53 PM PDT 24
Finished	Jul 31 06:09:57 PM PDT 24
Peak memory	288756 kb
Host	smart-fae9c89b-7148-4020-b473-ba953a2dfd0a
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787902933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha ndler_stress_all.3787902933
Directory	/workspace/18.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.777092438
Short name	T92
Test name
Test status
Simulation time	117626319253 ps
CPU time	10644.5 seconds
Started	Jul 31 05:22:19 PM PDT 24
Finished	Jul 31 08:19:44 PM PDT 24
Peak memory	370664 kb
Host	smart-573899ec-a2dd-4573-85b1-ecc930ca779d
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777092438 -assert nopostproc +UVM_TESTNAME=alert _handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.777092438
Directory	/workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/19.alert_handler_alert_accum_saturation.1310161827
Short name	T206
Test name
Test status
Simulation time	59198004 ps
CPU time	3.22 seconds
Started	Jul 31 05:21:57 PM PDT 24
Finished	Jul 31 05:22:00 PM PDT 24
Peak memory	248624 kb
Host	smart-0777a0d8-1db4-4b85-81bf-5f5a765b1fc6
User	root
Command	/workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1310161827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.1310161827
Directory	/workspace/19.alert_handler_alert_accum_saturation/latest

Test location	/workspace/coverage/default/19.alert_handler_entropy.322319333
Short name	T685
Test name
Test status
Simulation time	74049076219 ps
CPU time	1370.14 seconds
Started	Jul 31 05:21:55 PM PDT 24
Finished	Jul 31 05:44:45 PM PDT 24
Peak memory	265796 kb
Host	smart-606cb950-c2dd-4b5c-8eb6-0d706b28d443
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=322319333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.322319333
Directory	/workspace/19.alert_handler_entropy/latest

Test location	/workspace/coverage/default/19.alert_handler_entropy_stress.3930092403
Short name	T641
Test name
Test status
Simulation time	6485710401 ps
CPU time	45.04 seconds
Started	Jul 31 05:22:14 PM PDT 24
Finished	Jul 31 05:22:59 PM PDT 24
Peak memory	248400 kb
Host	smart-702c68e3-5393-4537-9d13-3f1e1fb3d04f
User	root
Command	/workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=3930092403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.3930092403
Directory	/workspace/19.alert_handler_entropy_stress/latest

Test location	/workspace/coverage/default/19.alert_handler_esc_alert_accum.2451305489
Short name	T430
Test name
Test status
Simulation time	3727541817 ps
CPU time	220.09 seconds
Started	Jul 31 05:22:14 PM PDT 24
Finished	Jul 31 05:25:54 PM PDT 24
Peak memory	256564 kb
Host	smart-ed352d05-c0fb-483c-94d5-59fc8e14e2c8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24513 05489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.2451305489
Directory	/workspace/19.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/19.alert_handler_esc_intr_timeout.500567204
Short name	T448
Test name
Test status
Simulation time	1083181874 ps
CPU time	62.24 seconds
Started	Jul 31 05:22:02 PM PDT 24
Finished	Jul 31 05:23:05 PM PDT 24
Peak memory	248232 kb
Host	smart-5bff5d86-4659-4446-85b7-47260f0dc0ac
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50056 7204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.500567204
Directory	/workspace/19.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/19.alert_handler_lpg_stub_clk.671284150
Short name	T526
Test name
Test status
Simulation time	421688984622 ps
CPU time	2902.42 seconds
Started	Jul 31 05:22:20 PM PDT 24
Finished	Jul 31 06:10:43 PM PDT 24
Peak memory	289340 kb
Host	smart-0878419c-6039-4e50-b59b-e8b0ffd9dbfc
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=671284150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.671284150
Directory	/workspace/19.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/19.alert_handler_ping_timeout.750441724
Short name	T511
Test name
Test status
Simulation time	5421242233 ps
CPU time	223.32 seconds
Started	Jul 31 05:22:01 PM PDT 24
Finished	Jul 31 05:25:44 PM PDT 24
Peak memory	256260 kb
Host	smart-2eebdce2-4512-4384-9a91-e5efcefb146b
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=750441724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.750441724
Directory	/workspace/19.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/19.alert_handler_random_alerts.1239757737
Short name	T628
Test name
Test status
Simulation time	1234228263 ps
CPU time	30.81 seconds
Started	Jul 31 05:21:59 PM PDT 24
Finished	Jul 31 05:22:30 PM PDT 24
Peak memory	248232 kb
Host	smart-aeeedece-663c-4a77-82a4-0173c0aeac7e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12397 57737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.1239757737
Directory	/workspace/19.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/19.alert_handler_random_classes.1919857797
Short name	T616
Test name
Test status
Simulation time	1539813377 ps
CPU time	19.15 seconds
Started	Jul 31 05:22:08 PM PDT 24
Finished	Jul 31 05:22:27 PM PDT 24
Peak memory	247876 kb
Host	smart-8f60d3fa-bb18-4155-8099-bebb36834b05
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19198 57797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.1919857797
Directory	/workspace/19.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/19.alert_handler_sig_int_fail.3928466237
Short name	T517
Test name
Test status
Simulation time	772894854 ps
CPU time	66.87 seconds
Started	Jul 31 05:22:12 PM PDT 24
Finished	Jul 31 05:23:19 PM PDT 24
Peak memory	248784 kb
Host	smart-6ff35410-5a2f-4cec-bc5e-9831ba750033
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39284 66237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.3928466237
Directory	/workspace/19.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/19.alert_handler_smoke.3302694358
Short name	T518
Test name
Test status
Simulation time	1965943031 ps
CPU time	29.57 seconds
Started	Jul 31 05:21:55 PM PDT 24
Finished	Jul 31 05:22:25 PM PDT 24
Peak memory	256476 kb
Host	smart-135e51c9-f680-4edd-bca0-0eec5f8e4005
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33026 94358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.3302694358
Directory	/workspace/19.alert_handler_smoke/latest

Test location	/workspace/coverage/default/19.alert_handler_stress_all.3765858718
Short name	T626
Test name
Test status
Simulation time	71052073041 ps
CPU time	2163.2 seconds
Started	Jul 31 05:22:01 PM PDT 24
Finished	Jul 31 05:58:05 PM PDT 24
Peak memory	289284 kb
Host	smart-99041081-7bb3-4c73-9d6a-88ba36acc99a
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765858718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha ndler_stress_all.3765858718
Directory	/workspace/19.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/19.alert_handler_stress_all_with_rand_reset.1470415049
Short name	T59
Test name
Test status
Simulation time	55481272503 ps
CPU time	1248.88 seconds
Started	Jul 31 05:22:04 PM PDT 24
Finished	Jul 31 05:42:53 PM PDT 24
Peak memory	289128 kb
Host	smart-c4ebba72-f343-42ea-bc87-06f8e213ff90
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470415049 -assert nopostproc +UVM_TESTNAME=aler t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_stress_all_with_rand_reset.1470415049
Directory	/workspace/19.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/2.alert_handler_entropy.1431106987
Short name	T21
Test name
Test status
Simulation time	34026339056 ps
CPU time	1103.91 seconds
Started	Jul 31 05:21:09 PM PDT 24
Finished	Jul 31 05:39:33 PM PDT 24
Peak memory	271988 kb
Host	smart-4660c54b-bc1a-47ca-b147-b1752bf4dd05
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1431106987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.1431106987
Directory	/workspace/2.alert_handler_entropy/latest

Test location	/workspace/coverage/default/2.alert_handler_entropy_stress.406248423
Short name	T563
Test name
Test status
Simulation time	473473913 ps
CPU time	12.77 seconds
Started	Jul 31 05:20:49 PM PDT 24
Finished	Jul 31 05:21:02 PM PDT 24
Peak memory	248328 kb
Host	smart-5ae25e00-928c-4531-8e55-dd5ddb2e8b10
User	root
Command	/workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=406248423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.406248423
Directory	/workspace/2.alert_handler_entropy_stress/latest

Test location	/workspace/coverage/default/2.alert_handler_esc_alert_accum.3532862066
Short name	T647
Test name
Test status
Simulation time	5518988644 ps
CPU time	161.1 seconds
Started	Jul 31 05:21:06 PM PDT 24
Finished	Jul 31 05:23:47 PM PDT 24
Peak memory	255924 kb
Host	smart-78a88aec-581b-44fe-bb7c-1a0895e970a0
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35328 62066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.3532862066
Directory	/workspace/2.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/2.alert_handler_esc_intr_timeout.491413791
Short name	T592
Test name
Test status
Simulation time	728536630 ps
CPU time	45.86 seconds
Started	Jul 31 05:21:11 PM PDT 24
Finished	Jul 31 05:21:57 PM PDT 24
Peak memory	248532 kb
Host	smart-94e34ccf-6fe8-442e-b8bb-120fab2efb92
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49141 3791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.491413791
Directory	/workspace/2.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/2.alert_handler_lpg.2222062032
Short name	T306
Test name
Test status
Simulation time	169839181915 ps
CPU time	2632.97 seconds
Started	Jul 31 05:20:49 PM PDT 24
Finished	Jul 31 06:04:42 PM PDT 24
Peak memory	281160 kb
Host	smart-6e0d6b48-985f-4315-a896-2a9534fd15e9
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2222062032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.2222062032
Directory	/workspace/2.alert_handler_lpg/latest

Test location	/workspace/coverage/default/2.alert_handler_lpg_stub_clk.4110762548
Short name	T619
Test name
Test status
Simulation time	144270633132 ps
CPU time	2487.82 seconds
Started	Jul 31 05:20:55 PM PDT 24
Finished	Jul 31 06:02:23 PM PDT 24
Peak memory	288820 kb
Host	smart-e0a5d962-2e77-41a7-86f5-5a76a2686b1a
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4110762548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.4110762548
Directory	/workspace/2.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/2.alert_handler_ping_timeout.2062081006
Short name	T636
Test name
Test status
Simulation time	17934096532 ps
CPU time	556.69 seconds
Started	Jul 31 05:21:19 PM PDT 24
Finished	Jul 31 05:30:36 PM PDT 24
Peak memory	248384 kb
Host	smart-608c6b15-7419-4990-a90e-f784875c5aa5
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2062081006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.2062081006
Directory	/workspace/2.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/2.alert_handler_random_alerts.1336459859
Short name	T372
Test name
Test status
Simulation time	1198006285 ps
CPU time	25.69 seconds
Started	Jul 31 05:20:48 PM PDT 24
Finished	Jul 31 05:21:14 PM PDT 24
Peak memory	255620 kb
Host	smart-faa99329-0929-4cbd-a4b8-020d8c45fec9
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13364 59859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.1336459859
Directory	/workspace/2.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/2.alert_handler_random_classes.1244484189
Short name	T657
Test name
Test status
Simulation time	283337567 ps
CPU time	16.82 seconds
Started	Jul 31 05:20:58 PM PDT 24
Finished	Jul 31 05:21:15 PM PDT 24
Peak memory	247996 kb
Host	smart-0b62823b-0e87-42aa-a5ae-bf1a23393c7b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12444 84189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.1244484189
Directory	/workspace/2.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/2.alert_handler_sig_int_fail.3863356724
Short name	T672
Test name
Test status
Simulation time	4530074431 ps
CPU time	65.24 seconds
Started	Jul 31 05:20:57 PM PDT 24
Finished	Jul 31 05:22:03 PM PDT 24
Peak memory	256604 kb
Host	smart-5ae7c0e3-294b-4aa4-b11a-d98d78dadbb0
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38633 56724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.3863356724
Directory	/workspace/2.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/2.alert_handler_smoke.3622937567
Short name	T219
Test name
Test status
Simulation time	2884079286 ps
CPU time	23.39 seconds
Started	Jul 31 05:20:50 PM PDT 24
Finished	Jul 31 05:21:13 PM PDT 24
Peak memory	248336 kb
Host	smart-4a97d16e-76eb-420e-a3f4-4ab6c0654205
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36229 37567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.3622937567
Directory	/workspace/2.alert_handler_smoke/latest

Test location	/workspace/coverage/default/2.alert_handler_stress_all.1807974526
Short name	T278
Test name
Test status
Simulation time	50122272877 ps
CPU time	2992.85 seconds
Started	Jul 31 05:21:05 PM PDT 24
Finished	Jul 31 06:10:58 PM PDT 24
Peak memory	300068 kb
Host	smart-6b14d83e-1d1f-492d-a7fa-bcc87179057a
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807974526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han dler_stress_all.1807974526
Directory	/workspace/2.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.1640734599
Short name	T186
Test name
Test status
Simulation time	172730701890 ps
CPU time	1987.16 seconds
Started	Jul 31 05:20:39 PM PDT 24
Finished	Jul 31 05:53:47 PM PDT 24
Peak memory	314380 kb
Host	smart-e78a819f-4829-4e1c-ba8c-2a6229401192
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640734599 -assert nopostproc +UVM_TESTNAME=aler t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.1640734599
Directory	/workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/20.alert_handler_entropy.2558637164
Short name	T90
Test name
Test status
Simulation time	111115349231 ps
CPU time	1789.91 seconds
Started	Jul 31 05:21:55 PM PDT 24
Finished	Jul 31 05:51:45 PM PDT 24
Peak memory	281068 kb
Host	smart-9eb0fbea-8bfb-4266-aa51-02180333153c
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2558637164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.2558637164
Directory	/workspace/20.alert_handler_entropy/latest

Test location	/workspace/coverage/default/20.alert_handler_esc_alert_accum.1358673193
Short name	T663
Test name
Test status
Simulation time	5669266800 ps
CPU time	104.97 seconds
Started	Jul 31 05:21:50 PM PDT 24
Finished	Jul 31 05:23:35 PM PDT 24
Peak memory	256096 kb
Host	smart-79f08bfb-a3fd-477e-8ba0-0a1b77d8acb2
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13586 73193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.1358673193
Directory	/workspace/20.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/20.alert_handler_esc_intr_timeout.3847396257
Short name	T618
Test name
Test status
Simulation time	925538781 ps
CPU time	40.84 seconds
Started	Jul 31 05:22:19 PM PDT 24
Finished	Jul 31 05:23:00 PM PDT 24
Peak memory	248412 kb
Host	smart-38c6a7bc-e071-4759-ab61-85e3e355721a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38473 96257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.3847396257
Directory	/workspace/20.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/20.alert_handler_lpg.966817403
Short name	T215
Test name
Test status
Simulation time	6699559191 ps
CPU time	730.44 seconds
Started	Jul 31 05:21:56 PM PDT 24
Finished	Jul 31 05:34:07 PM PDT 24
Peak memory	272908 kb
Host	smart-96c61c14-a0c6-40ca-8999-a20f42c2bb84
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=966817403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.966817403
Directory	/workspace/20.alert_handler_lpg/latest

Test location	/workspace/coverage/default/20.alert_handler_lpg_stub_clk.340724510
Short name	T379
Test name
Test status
Simulation time	35703551632 ps
CPU time	2339.26 seconds
Started	Jul 31 05:22:01 PM PDT 24
Finished	Jul 31 06:01:01 PM PDT 24
Peak memory	285668 kb
Host	smart-b7b0bc15-c652-4d72-bc03-ddc7d8473e6c
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=340724510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.340724510
Directory	/workspace/20.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/20.alert_handler_ping_timeout.838302661
Short name	T635
Test name
Test status
Simulation time	68112775807 ps
CPU time	634.11 seconds
Started	Jul 31 05:21:55 PM PDT 24
Finished	Jul 31 05:32:30 PM PDT 24
Peak memory	248416 kb
Host	smart-1d3c9afa-e3d6-4a0b-acd0-3ac5852291a2
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=838302661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.838302661
Directory	/workspace/20.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/20.alert_handler_random_alerts.1338555948
Short name	T401
Test name
Test status
Simulation time	127930621 ps
CPU time	9.07 seconds
Started	Jul 31 05:21:58 PM PDT 24
Finished	Jul 31 05:22:07 PM PDT 24
Peak memory	248308 kb
Host	smart-4477e688-fd86-44a6-8845-f94ed2e1c852
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13385 55948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.1338555948
Directory	/workspace/20.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/20.alert_handler_random_classes.1558947780
Short name	T503
Test name
Test status
Simulation time	590898420 ps
CPU time	44.34 seconds
Started	Jul 31 05:21:49 PM PDT 24
Finished	Jul 31 05:22:34 PM PDT 24
Peak memory	248108 kb
Host	smart-5e23c4f0-540f-4d26-9280-860ca1eb0b11
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15589 47780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.1558947780
Directory	/workspace/20.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/20.alert_handler_sig_int_fail.2848755283
Short name	T565
Test name
Test status
Simulation time	584978195 ps
CPU time	14.22 seconds
Started	Jul 31 05:22:19 PM PDT 24
Finished	Jul 31 05:22:34 PM PDT 24
Peak memory	248280 kb
Host	smart-3ac4c145-c091-49b3-a0a3-5741a579a7fb
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28487 55283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.2848755283
Directory	/workspace/20.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/20.alert_handler_smoke.1901817233
Short name	T384
Test name
Test status
Simulation time	341797976 ps
CPU time	30.76 seconds
Started	Jul 31 05:22:14 PM PDT 24
Finished	Jul 31 05:22:45 PM PDT 24
Peak memory	256516 kb
Host	smart-ba64feb3-5622-418f-801b-60b0546d22d5
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19018 17233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.1901817233
Directory	/workspace/20.alert_handler_smoke/latest

Test location	/workspace/coverage/default/20.alert_handler_stress_all.2349611935
Short name	T287
Test name
Test status
Simulation time	58041488927 ps
CPU time	1041.22 seconds
Started	Jul 31 05:21:54 PM PDT 24
Finished	Jul 31 05:39:15 PM PDT 24
Peak memory	282216 kb
Host	smart-5fb803e6-a8b5-42cb-9775-c573c0af8086
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349611935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha ndler_stress_all.2349611935
Directory	/workspace/20.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/21.alert_handler_esc_alert_accum.1146580911
Short name	T705
Test name
Test status
Simulation time	2716279871 ps
CPU time	164.87 seconds
Started	Jul 31 05:21:57 PM PDT 24
Finished	Jul 31 05:24:42 PM PDT 24
Peak memory	256616 kb
Host	smart-c2c43c1d-30b9-49bb-9b13-159e00087cd6
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11465 80911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.1146580911
Directory	/workspace/21.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/21.alert_handler_esc_intr_timeout.1502235004
Short name	T512
Test name
Test status
Simulation time	383664768 ps
CPU time	24.52 seconds
Started	Jul 31 05:22:23 PM PDT 24
Finished	Jul 31 05:22:48 PM PDT 24
Peak memory	247908 kb
Host	smart-38fee700-295f-4c8e-8f6f-08fd5f6eeada
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15022 35004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.1502235004
Directory	/workspace/21.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/21.alert_handler_lpg_stub_clk.2428500201
Short name	T646
Test name
Test status
Simulation time	44778813265 ps
CPU time	2329.98 seconds
Started	Jul 31 05:21:56 PM PDT 24
Finished	Jul 31 06:00:46 PM PDT 24
Peak memory	284208 kb
Host	smart-d1ee9549-7ba1-459a-90e8-98162e991ea6
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2428500201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.2428500201
Directory	/workspace/21.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/21.alert_handler_ping_timeout.4178594549
Short name	T550
Test name
Test status
Simulation time	158832245784 ps
CPU time	502.94 seconds
Started	Jul 31 05:22:18 PM PDT 24
Finished	Jul 31 05:30:41 PM PDT 24
Peak memory	247304 kb
Host	smart-869d4c7f-6436-4d78-8cfd-6ef45b49b045
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4178594549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.4178594549
Directory	/workspace/21.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/21.alert_handler_random_alerts.3641062675
Short name	T391
Test name
Test status
Simulation time	529340657 ps
CPU time	34.89 seconds
Started	Jul 31 05:21:54 PM PDT 24
Finished	Jul 31 05:22:29 PM PDT 24
Peak memory	255668 kb
Host	smart-dc4355ce-7f7b-4a19-9303-81f7257705b9
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36410 62675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.3641062675
Directory	/workspace/21.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/21.alert_handler_sig_int_fail.154842060
Short name	T421
Test name
Test status
Simulation time	1172076549 ps
CPU time	68.94 seconds
Started	Jul 31 05:22:14 PM PDT 24
Finished	Jul 31 05:23:23 PM PDT 24
Peak memory	256428 kb
Host	smart-0a5cf84d-bbea-4633-9823-ff63f21eeb84
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15484 2060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.154842060
Directory	/workspace/21.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/21.alert_handler_smoke.288541013
Short name	T606
Test name
Test status
Simulation time	703502477 ps
CPU time	45.42 seconds
Started	Jul 31 05:22:02 PM PDT 24
Finished	Jul 31 05:22:47 PM PDT 24
Peak memory	255384 kb
Host	smart-f788f8c9-4e48-47ae-aac0-4d61a866b4db
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28854 1013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.288541013
Directory	/workspace/21.alert_handler_smoke/latest

Test location	/workspace/coverage/default/21.alert_handler_stress_all.2401189249
Short name	T481
Test name
Test status
Simulation time	223168303551 ps
CPU time	3052.6 seconds
Started	Jul 31 05:22:27 PM PDT 24
Finished	Jul 31 06:13:20 PM PDT 24
Peak memory	297724 kb
Host	smart-3bf6fa3d-d21d-4d44-ab0c-a4ad9e0ee3a6
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401189249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha ndler_stress_all.2401189249
Directory	/workspace/21.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.3271320340
Short name	T238
Test name
Test status
Simulation time	211504307687 ps
CPU time	7308.47 seconds
Started	Jul 31 05:21:56 PM PDT 24
Finished	Jul 31 07:23:46 PM PDT 24
Peak memory	338612 kb
Host	smart-2716fe47-ba54-482c-9892-cb00e0ba4d4d
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271320340 -assert nopostproc +UVM_TESTNAME=aler t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.3271320340
Directory	/workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/22.alert_handler_entropy.1707029450
Short name	T692
Test name
Test status
Simulation time	17874559867 ps
CPU time	1195.79 seconds
Started	Jul 31 05:22:04 PM PDT 24
Finished	Jul 31 05:42:01 PM PDT 24
Peak memory	272528 kb
Host	smart-ccf9e24f-bb61-4961-9280-50d10af20966
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1707029450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.1707029450
Directory	/workspace/22.alert_handler_entropy/latest

Test location	/workspace/coverage/default/22.alert_handler_esc_alert_accum.4234879018
Short name	T373
Test name
Test status
Simulation time	490683118 ps
CPU time	51.68 seconds
Started	Jul 31 05:22:31 PM PDT 24
Finished	Jul 31 05:23:23 PM PDT 24
Peak memory	255944 kb
Host	smart-32277ef3-9da7-46c6-9fd4-aca4288fc988
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42348 79018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.4234879018
Directory	/workspace/22.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/22.alert_handler_esc_intr_timeout.2170859933
Short name	T681
Test name
Test status
Simulation time	621476536 ps
CPU time	29.56 seconds
Started	Jul 31 05:22:09 PM PDT 24
Finished	Jul 31 05:22:39 PM PDT 24
Peak memory	248260 kb
Host	smart-4c4cd5e1-6b19-45c8-b71f-28cbe35d1845
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21708 59933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.2170859933
Directory	/workspace/22.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/22.alert_handler_lpg.1596555566
Short name	T233
Test name
Test status
Simulation time	236099042079 ps
CPU time	2007.01 seconds
Started	Jul 31 05:22:12 PM PDT 24
Finished	Jul 31 05:55:39 PM PDT 24
Peak memory	287016 kb
Host	smart-e56a48b8-b063-4cdf-81fd-c8f383c97c49
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1596555566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.1596555566
Directory	/workspace/22.alert_handler_lpg/latest

Test location	/workspace/coverage/default/22.alert_handler_lpg_stub_clk.918507654
Short name	T580
Test name
Test status
Simulation time	111980929525 ps
CPU time	2938.58 seconds
Started	Jul 31 05:21:57 PM PDT 24
Finished	Jul 31 06:10:56 PM PDT 24
Peak memory	289200 kb
Host	smart-ccf205be-efa0-4f3b-8711-e2b53d72903c
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=918507654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.918507654
Directory	/workspace/22.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/22.alert_handler_ping_timeout.3747965833
Short name	T566
Test name
Test status
Simulation time	10994708439 ps
CPU time	117.56 seconds
Started	Jul 31 05:22:21 PM PDT 24
Finished	Jul 31 05:24:19 PM PDT 24
Peak memory	248368 kb
Host	smart-c030d53c-022d-4d24-9992-dcf00583d3f4
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3747965833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.3747965833
Directory	/workspace/22.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/22.alert_handler_random_alerts.1301760221
Short name	T702
Test name
Test status
Simulation time	317088850 ps
CPU time	32.31 seconds
Started	Jul 31 05:22:05 PM PDT 24
Finished	Jul 31 05:22:38 PM PDT 24
Peak memory	248324 kb
Host	smart-8cdb8f60-87a6-416e-ae6b-050125ce4a43
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13017 60221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.1301760221
Directory	/workspace/22.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/22.alert_handler_sig_int_fail.676073336
Short name	T47
Test name
Test status
Simulation time	3258632141 ps
CPU time	55.05 seconds
Started	Jul 31 05:22:09 PM PDT 24
Finished	Jul 31 05:23:04 PM PDT 24
Peak memory	255852 kb
Host	smart-f23e3bf3-b098-4c8e-9b67-7e7f957e2692
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67607 3336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.676073336
Directory	/workspace/22.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/22.alert_handler_smoke.1402300643
Short name	T712
Test name
Test status
Simulation time	347742552 ps
CPU time	21.16 seconds
Started	Jul 31 05:22:11 PM PDT 24
Finished	Jul 31 05:22:32 PM PDT 24
Peak memory	256256 kb
Host	smart-4f12a5e9-d5a4-4dca-bbfe-edd7ad555865
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14023 00643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.1402300643
Directory	/workspace/22.alert_handler_smoke/latest

Test location	/workspace/coverage/default/22.alert_handler_stress_all.1724332604
Short name	T407
Test name
Test status
Simulation time	651532525 ps
CPU time	72.1 seconds
Started	Jul 31 05:21:58 PM PDT 24
Finished	Jul 31 05:23:10 PM PDT 24
Peak memory	249408 kb
Host	smart-a6bae262-7f58-4f78-9359-5db5bf390916
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724332604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha ndler_stress_all.1724332604
Directory	/workspace/22.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/23.alert_handler_entropy.1234900574
Short name	T88
Test name
Test status
Simulation time	68518649507 ps
CPU time	2289.98 seconds
Started	Jul 31 05:22:04 PM PDT 24
Finished	Jul 31 06:00:14 PM PDT 24
Peak memory	285056 kb
Host	smart-2b98448b-01ac-4b50-892a-7b710ce62ae8
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1234900574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.1234900574
Directory	/workspace/23.alert_handler_entropy/latest

Test location	/workspace/coverage/default/23.alert_handler_esc_alert_accum.2548180926
Short name	T571
Test name
Test status
Simulation time	3808828240 ps
CPU time	62.12 seconds
Started	Jul 31 05:22:16 PM PDT 24
Finished	Jul 31 05:23:18 PM PDT 24
Peak memory	256596 kb
Host	smart-88dee524-87e4-47cc-9079-27a3755f0bba
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25481 80926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.2548180926
Directory	/workspace/23.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/23.alert_handler_esc_intr_timeout.1781503659
Short name	T610
Test name
Test status
Simulation time	4851453389 ps
CPU time	70.3 seconds
Started	Jul 31 05:22:01 PM PDT 24
Finished	Jul 31 05:23:11 PM PDT 24
Peak memory	248396 kb
Host	smart-831206a4-7081-4832-bff2-b0aba0f18688
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17815 03659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.1781503659
Directory	/workspace/23.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/23.alert_handler_lpg.250439348
Short name	T587
Test name
Test status
Simulation time	55088612364 ps
CPU time	939.17 seconds
Started	Jul 31 05:22:11 PM PDT 24
Finished	Jul 31 05:37:51 PM PDT 24
Peak memory	272696 kb
Host	smart-f351e3fa-d8cf-4e45-87b9-927393dc7f34
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=250439348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.250439348
Directory	/workspace/23.alert_handler_lpg/latest

Test location	/workspace/coverage/default/23.alert_handler_lpg_stub_clk.1658297860
Short name	T529
Test name
Test status
Simulation time	66537437900 ps
CPU time	1979.93 seconds
Started	Jul 31 05:22:03 PM PDT 24
Finished	Jul 31 05:55:04 PM PDT 24
Peak memory	288484 kb
Host	smart-b3ec82c3-a158-4ca5-a110-5c55f7bb9823
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1658297860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.1658297860
Directory	/workspace/23.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/23.alert_handler_ping_timeout.2013412430
Short name	T545
Test name
Test status
Simulation time	74208385112 ps
CPU time	299.11 seconds
Started	Jul 31 05:22:18 PM PDT 24
Finished	Jul 31 05:27:17 PM PDT 24
Peak memory	248368 kb
Host	smart-535cde94-a33d-4eb2-8af9-2c2b515eb13f
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2013412430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.2013412430
Directory	/workspace/23.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/23.alert_handler_random_alerts.1943677794
Short name	T622
Test name
Test status
Simulation time	1307091802 ps
CPU time	74.48 seconds
Started	Jul 31 05:22:24 PM PDT 24
Finished	Jul 31 05:23:38 PM PDT 24
Peak memory	255444 kb
Host	smart-4d50a0a6-93bd-48b6-8ed6-3ff13194e4fb
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19436 77794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.1943677794
Directory	/workspace/23.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/23.alert_handler_random_classes.2358318549
Short name	T602
Test name
Test status
Simulation time	436869092 ps
CPU time	37.9 seconds
Started	Jul 31 05:22:06 PM PDT 24
Finished	Jul 31 05:22:44 PM PDT 24
Peak memory	247452 kb
Host	smart-6b84ee11-c4a6-4bb1-bf6e-fbaf6146e3e8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23583 18549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.2358318549
Directory	/workspace/23.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/23.alert_handler_sig_int_fail.3085156531
Short name	T24
Test name
Test status
Simulation time	58148119 ps
CPU time	4.1 seconds
Started	Jul 31 05:22:28 PM PDT 24
Finished	Jul 31 05:22:32 PM PDT 24
Peak memory	239384 kb
Host	smart-86389d3c-7390-4e6b-962b-349e36005be5
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30851 56531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.3085156531
Directory	/workspace/23.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/23.alert_handler_smoke.3918954322
Short name	T555
Test name
Test status
Simulation time	544127924 ps
CPU time	35.14 seconds
Started	Jul 31 05:22:06 PM PDT 24
Finished	Jul 31 05:22:41 PM PDT 24
Peak memory	256480 kb
Host	smart-1520e01d-6549-43d6-91f5-3b50bb0a74a9
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39189 54322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.3918954322
Directory	/workspace/23.alert_handler_smoke/latest

Test location	/workspace/coverage/default/23.alert_handler_stress_all.1577551550
Short name	T612
Test name
Test status
Simulation time	158715726022 ps
CPU time	2709.74 seconds
Started	Jul 31 05:22:16 PM PDT 24
Finished	Jul 31 06:07:26 PM PDT 24
Peak memory	285944 kb
Host	smart-ff470509-6f02-42ed-968a-50b82de39262
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577551550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha ndler_stress_all.1577551550
Directory	/workspace/23.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/24.alert_handler_entropy.1657132103
Short name	T404
Test name
Test status
Simulation time	52288773432 ps
CPU time	1646.76 seconds
Started	Jul 31 05:22:04 PM PDT 24
Finished	Jul 31 05:49:31 PM PDT 24
Peak memory	272808 kb
Host	smart-f3724ede-4253-4ace-8639-32f587ed7491
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1657132103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.1657132103
Directory	/workspace/24.alert_handler_entropy/latest

Test location	/workspace/coverage/default/24.alert_handler_esc_intr_timeout.1925100485
Short name	T67
Test name
Test status
Simulation time	385174934 ps
CPU time	30.17 seconds
Started	Jul 31 05:22:02 PM PDT 24
Finished	Jul 31 05:22:32 PM PDT 24
Peak memory	247924 kb
Host	smart-330e16e6-06c5-481b-aeb1-392ef30d82f8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19251 00485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.1925100485
Directory	/workspace/24.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/24.alert_handler_lpg.2390076263
Short name	T112
Test name
Test status
Simulation time	551854302531 ps
CPU time	2155.94 seconds
Started	Jul 31 05:22:11 PM PDT 24
Finished	Jul 31 05:58:07 PM PDT 24
Peak memory	286484 kb
Host	smart-ae47a96b-c4ab-4575-9a9b-78cc5027f8a1
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2390076263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.2390076263
Directory	/workspace/24.alert_handler_lpg/latest

Test location	/workspace/coverage/default/24.alert_handler_lpg_stub_clk.2513503099
Short name	T279
Test name
Test status
Simulation time	42144925861 ps
CPU time	1257.9 seconds
Started	Jul 31 05:22:11 PM PDT 24
Finished	Jul 31 05:43:09 PM PDT 24
Peak memory	265748 kb
Host	smart-a742394b-27ec-42c0-aecc-3fb06c1de7f0
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2513503099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.2513503099
Directory	/workspace/24.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/24.alert_handler_ping_timeout.3635747107
Short name	T218
Test name
Test status
Simulation time	5238597881 ps
CPU time	203.96 seconds
Started	Jul 31 05:22:06 PM PDT 24
Finished	Jul 31 05:25:30 PM PDT 24
Peak memory	248384 kb
Host	smart-436ba368-966d-4c2a-80a3-49c10de09be3
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3635747107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.3635747107
Directory	/workspace/24.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/24.alert_handler_random_alerts.1729767699
Short name	T51
Test name
Test status
Simulation time	2955637566 ps
CPU time	45.37 seconds
Started	Jul 31 05:21:59 PM PDT 24
Finished	Jul 31 05:22:44 PM PDT 24
Peak memory	256552 kb
Host	smart-1d2c1425-479e-4a4c-8978-01a0ad5bc499
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17297 67699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.1729767699
Directory	/workspace/24.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/24.alert_handler_random_classes.1481066636
Short name	T297
Test name
Test status
Simulation time	300283084 ps
CPU time	35.59 seconds
Started	Jul 31 05:22:01 PM PDT 24
Finished	Jul 31 05:22:37 PM PDT 24
Peak memory	248356 kb
Host	smart-d6d9a79c-0516-4a19-be35-a6d6c71d67c3
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14810 66636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.1481066636
Directory	/workspace/24.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/24.alert_handler_sig_int_fail.984402552
Short name	T426
Test name
Test status
Simulation time	2806729742 ps
CPU time	47.08 seconds
Started	Jul 31 05:21:59 PM PDT 24
Finished	Jul 31 05:22:47 PM PDT 24
Peak memory	256644 kb
Host	smart-810d6174-eaf8-4da7-93bb-c431ba880c7e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98440 2552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.984402552
Directory	/workspace/24.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/24.alert_handler_smoke.1246556548
Short name	T470
Test name
Test status
Simulation time	1819060213 ps
CPU time	24.36 seconds
Started	Jul 31 05:22:15 PM PDT 24
Finished	Jul 31 05:22:39 PM PDT 24
Peak memory	248684 kb
Host	smart-9b4f52ea-6d28-478d-abbf-08eaf28618f0
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12465 56548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.1246556548
Directory	/workspace/24.alert_handler_smoke/latest

Test location	/workspace/coverage/default/24.alert_handler_stress_all.147839302
Short name	T93
Test name
Test status
Simulation time	259513138425 ps
CPU time	729.89 seconds
Started	Jul 31 05:22:19 PM PDT 24
Finished	Jul 31 05:34:29 PM PDT 24
Peak memory	264812 kb
Host	smart-be3d5309-5643-4fd0-aaba-595821045c88
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147839302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_han dler_stress_all.147839302
Directory	/workspace/24.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/24.alert_handler_stress_all_with_rand_reset.2728505620
Short name	T292
Test name
Test status
Simulation time	43674017628 ps
CPU time	798.15 seconds
Started	Jul 31 05:22:06 PM PDT 24
Finished	Jul 31 05:35:24 PM PDT 24
Peak memory	273100 kb
Host	smart-8b763bb9-6752-4952-bac2-169525810830
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728505620 -assert nopostproc +UVM_TESTNAME=aler t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_stress_all_with_rand_reset.2728505620
Directory	/workspace/24.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/25.alert_handler_entropy.2370154562
Short name	T662
Test name
Test status
Simulation time	11032062026 ps
CPU time	677.61 seconds
Started	Jul 31 05:22:00 PM PDT 24
Finished	Jul 31 05:33:17 PM PDT 24
Peak memory	264736 kb
Host	smart-52196933-3630-459e-9152-043303c16268
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2370154562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.2370154562
Directory	/workspace/25.alert_handler_entropy/latest

Test location	/workspace/coverage/default/25.alert_handler_esc_alert_accum.1821283157
Short name	T578
Test name
Test status
Simulation time	1612075624 ps
CPU time	53 seconds
Started	Jul 31 05:22:16 PM PDT 24
Finished	Jul 31 05:23:09 PM PDT 24
Peak memory	248344 kb
Host	smart-8e1e2ae0-bd93-480b-95e8-4a10e7a19e16
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18212 83157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.1821283157
Directory	/workspace/25.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/25.alert_handler_esc_intr_timeout.3482575641
Short name	T110
Test name
Test status
Simulation time	414457292 ps
CPU time	9.75 seconds
Started	Jul 31 05:22:27 PM PDT 24
Finished	Jul 31 05:22:37 PM PDT 24
Peak memory	255864 kb
Host	smart-4db212a4-1764-4a0f-a6d7-c52acd503837
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34825 75641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.3482575641
Directory	/workspace/25.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/25.alert_handler_lpg.3844233380
Short name	T333
Test name
Test status
Simulation time	409483219811 ps
CPU time	2534.41 seconds
Started	Jul 31 05:22:21 PM PDT 24
Finished	Jul 31 06:04:35 PM PDT 24
Peak memory	289332 kb
Host	smart-e398d87b-0500-4162-9462-f0528229fbf8
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3844233380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.3844233380
Directory	/workspace/25.alert_handler_lpg/latest

Test location	/workspace/coverage/default/25.alert_handler_lpg_stub_clk.3939712093
Short name	T176
Test name
Test status
Simulation time	88338795100 ps
CPU time	1690.41 seconds
Started	Jul 31 05:22:21 PM PDT 24
Finished	Jul 31 05:50:32 PM PDT 24
Peak memory	272988 kb
Host	smart-dffca22b-c645-4634-a279-acff569405c6
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3939712093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.3939712093
Directory	/workspace/25.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/25.alert_handler_ping_timeout.3251642780
Short name	T320
Test name
Test status
Simulation time	15924911941 ps
CPU time	650.28 seconds
Started	Jul 31 05:22:03 PM PDT 24
Finished	Jul 31 05:32:54 PM PDT 24
Peak memory	248412 kb
Host	smart-fc993264-ba49-426d-82b4-36c9abbac93d
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3251642780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.3251642780
Directory	/workspace/25.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/25.alert_handler_random_alerts.1154713965
Short name	T225
Test name
Test status
Simulation time	395846232 ps
CPU time	17.33 seconds
Started	Jul 31 05:22:15 PM PDT 24
Finished	Jul 31 05:22:32 PM PDT 24
Peak memory	248204 kb
Host	smart-19e3b64f-fe30-41b3-bcec-3900f94e2bab
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11547 13965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.1154713965
Directory	/workspace/25.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/25.alert_handler_random_classes.2863079076
Short name	T658
Test name
Test status
Simulation time	589857999 ps
CPU time	33.93 seconds
Started	Jul 31 05:22:11 PM PDT 24
Finished	Jul 31 05:22:45 PM PDT 24
Peak memory	255916 kb
Host	smart-2cdb405f-7ccb-4bbc-924d-9e4539597476
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28630 79076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.2863079076
Directory	/workspace/25.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/25.alert_handler_smoke.635474706
Short name	T660
Test name
Test status
Simulation time	124269875 ps
CPU time	8.55 seconds
Started	Jul 31 05:22:19 PM PDT 24
Finished	Jul 31 05:22:27 PM PDT 24
Peak memory	251412 kb
Host	smart-8336b66f-c722-4c09-8d92-e64cfa5fec98
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63547 4706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.635474706
Directory	/workspace/25.alert_handler_smoke/latest

Test location	/workspace/coverage/default/25.alert_handler_stress_all_with_rand_reset.3010014987
Short name	T256
Test name
Test status
Simulation time	112466324037 ps
CPU time	5848.97 seconds
Started	Jul 31 05:22:14 PM PDT 24
Finished	Jul 31 06:59:44 PM PDT 24
Peak memory	354560 kb
Host	smart-21a4dafd-876f-47ff-9994-7f232c8e660e
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010014987 -assert nopostproc +UVM_TESTNAME=aler t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_stress_all_with_rand_reset.3010014987
Directory	/workspace/25.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/26.alert_handler_entropy.4108812214
Short name	T425
Test name
Test status
Simulation time	47563711578 ps
CPU time	3148.79 seconds
Started	Jul 31 05:22:03 PM PDT 24
Finished	Jul 31 06:14:32 PM PDT 24
Peak memory	289332 kb
Host	smart-3c1fcc3a-9368-4200-9aa8-50a01b6f5dab
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4108812214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.4108812214
Directory	/workspace/26.alert_handler_entropy/latest

Test location	/workspace/coverage/default/26.alert_handler_esc_alert_accum.447552047
Short name	T704
Test name
Test status
Simulation time	2476556550 ps
CPU time	49.81 seconds
Started	Jul 31 05:22:23 PM PDT 24
Finished	Jul 31 05:23:13 PM PDT 24
Peak memory	256104 kb
Host	smart-eb496b51-256a-4888-8d13-52a99c1536f1
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44755 2047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.447552047
Directory	/workspace/26.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/26.alert_handler_esc_intr_timeout.145610890
Short name	T75
Test name
Test status
Simulation time	446056448 ps
CPU time	30.42 seconds
Started	Jul 31 05:22:00 PM PDT 24
Finished	Jul 31 05:22:30 PM PDT 24
Peak memory	255120 kb
Host	smart-697be34b-5cd1-4471-8ded-d858fb773037
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14561 0890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.145610890
Directory	/workspace/26.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/26.alert_handler_lpg_stub_clk.4055735324
Short name	T456
Test name
Test status
Simulation time	11801117180 ps
CPU time	1091.37 seconds
Started	Jul 31 05:22:08 PM PDT 24
Finished	Jul 31 05:40:19 PM PDT 24
Peak memory	288536 kb
Host	smart-64bd8654-bed8-4455-a8ec-440b174202f8
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4055735324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.4055735324
Directory	/workspace/26.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/26.alert_handler_ping_timeout.3978347695
Short name	T299
Test name
Test status
Simulation time	41170602266 ps
CPU time	184.95 seconds
Started	Jul 31 05:22:03 PM PDT 24
Finished	Jul 31 05:25:08 PM PDT 24
Peak memory	248396 kb
Host	smart-96be184b-2191-45a7-9c01-07d4996933a9
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3978347695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.3978347695
Directory	/workspace/26.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/26.alert_handler_random_alerts.2081671144
Short name	T375
Test name
Test status
Simulation time	312113615 ps
CPU time	10.7 seconds
Started	Jul 31 05:22:14 PM PDT 24
Finished	Jul 31 05:22:25 PM PDT 24
Peak memory	248360 kb
Host	smart-4a13105f-020b-4fb8-b119-944f42022e35
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20816 71144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.2081671144
Directory	/workspace/26.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/26.alert_handler_random_classes.210822870
Short name	T377
Test name
Test status
Simulation time	18678014 ps
CPU time	3.74 seconds
Started	Jul 31 05:22:01 PM PDT 24
Finished	Jul 31 05:22:05 PM PDT 24
Peak memory	239560 kb
Host	smart-7e01ece9-aa24-4d9d-9034-28d7f0a687a9
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21082 2870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.210822870
Directory	/workspace/26.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/26.alert_handler_sig_int_fail.521888204
Short name	T28
Test name
Test status
Simulation time	2371529587 ps
CPU time	49.41 seconds
Started	Jul 31 05:22:01 PM PDT 24
Finished	Jul 31 05:22:51 PM PDT 24
Peak memory	248364 kb
Host	smart-89d3f2e8-89e9-411c-8352-d00da1b8fb34
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52188 8204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.521888204
Directory	/workspace/26.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/26.alert_handler_smoke.2318440203
Short name	T711
Test name
Test status
Simulation time	1611944084 ps
CPU time	22.6 seconds
Started	Jul 31 05:22:23 PM PDT 24
Finished	Jul 31 05:22:46 PM PDT 24
Peak memory	256328 kb
Host	smart-220cf500-8fd6-47e9-a068-ccda791d09e3
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23184 40203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.2318440203
Directory	/workspace/26.alert_handler_smoke/latest

Test location	/workspace/coverage/default/26.alert_handler_stress_all.548290154
Short name	T452
Test name
Test status
Simulation time	37758243863 ps
CPU time	968.52 seconds
Started	Jul 31 05:22:18 PM PDT 24
Finished	Jul 31 05:38:27 PM PDT 24
Peak memory	282156 kb
Host	smart-40d6f9ce-f274-4114-9d55-93f640f3ecfd
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548290154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_han dler_stress_all.548290154
Directory	/workspace/26.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/27.alert_handler_entropy.2858537788
Short name	T521
Test name
Test status
Simulation time	131132719292 ps
CPU time	1457.48 seconds
Started	Jul 31 05:22:25 PM PDT 24
Finished	Jul 31 05:46:43 PM PDT 24
Peak memory	271896 kb
Host	smart-aafc0d04-4508-4b0f-b4b7-505adc957224
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2858537788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.2858537788
Directory	/workspace/27.alert_handler_entropy/latest

Test location	/workspace/coverage/default/27.alert_handler_esc_alert_accum.2640920544
Short name	T679
Test name
Test status
Simulation time	15275615941 ps
CPU time	223.45 seconds
Started	Jul 31 05:22:08 PM PDT 24
Finished	Jul 31 05:25:52 PM PDT 24
Peak memory	256624 kb
Host	smart-4756ebb1-0b39-4502-bcb2-4c3bcaf5b92e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26409 20544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.2640920544
Directory	/workspace/27.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/27.alert_handler_esc_intr_timeout.814862255
Short name	T572
Test name
Test status
Simulation time	2351881228 ps
CPU time	12.17 seconds
Started	Jul 31 05:22:23 PM PDT 24
Finished	Jul 31 05:22:35 PM PDT 24
Peak memory	247932 kb
Host	smart-a529da46-d13e-486f-84fa-d5fadff6ee68
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81486 2255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.814862255
Directory	/workspace/27.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/27.alert_handler_lpg.2838711164
Short name	T179
Test name
Test status
Simulation time	34001605863 ps
CPU time	1382.03 seconds
Started	Jul 31 05:22:23 PM PDT 24
Finished	Jul 31 05:45:25 PM PDT 24
Peak memory	288716 kb
Host	smart-9b8e1eba-f683-4e37-b262-2d124f4238c0
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2838711164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.2838711164
Directory	/workspace/27.alert_handler_lpg/latest

Test location	/workspace/coverage/default/27.alert_handler_lpg_stub_clk.4101860075
Short name	T232
Test name
Test status
Simulation time	835463047307 ps
CPU time	2355.61 seconds
Started	Jul 31 05:22:21 PM PDT 24
Finished	Jul 31 06:01:37 PM PDT 24
Peak memory	285028 kb
Host	smart-84938918-75e5-4584-b934-9d29cfb871c8
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4101860075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.4101860075
Directory	/workspace/27.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/27.alert_handler_ping_timeout.522731775
Short name	T497
Test name
Test status
Simulation time	9227205722 ps
CPU time	100.61 seconds
Started	Jul 31 05:22:08 PM PDT 24
Finished	Jul 31 05:23:48 PM PDT 24
Peak memory	247252 kb
Host	smart-7f6e8e11-81e9-4d82-92d4-5f1f9c8372d9
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=522731775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.522731775
Directory	/workspace/27.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/27.alert_handler_random_alerts.1904351319
Short name	T354
Test name
Test status
Simulation time	297742250 ps
CPU time	9.51 seconds
Started	Jul 31 05:22:24 PM PDT 24
Finished	Jul 31 05:22:34 PM PDT 24
Peak memory	256404 kb
Host	smart-5d259ca4-e17f-4273-84d3-9c83b64fa056
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19043 51319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.1904351319
Directory	/workspace/27.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/27.alert_handler_random_classes.2414130630
Short name	T282
Test name
Test status
Simulation time	103377823 ps
CPU time	9.16 seconds
Started	Jul 31 05:22:08 PM PDT 24
Finished	Jul 31 05:22:18 PM PDT 24
Peak memory	247892 kb
Host	smart-9129132c-4a9d-40da-b7ab-4feb1004f4f0
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24141 30630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.2414130630
Directory	/workspace/27.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/27.alert_handler_sig_int_fail.1751568
Short name	T583
Test name
Test status
Simulation time	205489577 ps
CPU time	4.65 seconds
Started	Jul 31 05:22:30 PM PDT 24
Finished	Jul 31 05:22:35 PM PDT 24
Peak memory	248816 kb
Host	smart-a6e502d7-8f37-4b07-bc69-2bbb15244119
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17515 68 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.1751568
Directory	/workspace/27.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/27.alert_handler_smoke.2921079993
Short name	T625
Test name
Test status
Simulation time	843572526 ps
CPU time	53.11 seconds
Started	Jul 31 05:22:27 PM PDT 24
Finished	Jul 31 05:23:20 PM PDT 24
Peak memory	255580 kb
Host	smart-665fcf7f-d9ce-41d9-8144-ca8cd57859a3
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29210 79993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.2921079993
Directory	/workspace/27.alert_handler_smoke/latest

Test location	/workspace/coverage/default/27.alert_handler_stress_all.1844236894
Short name	T293
Test name
Test status
Simulation time	42258731832 ps
CPU time	2570.73 seconds
Started	Jul 31 05:22:07 PM PDT 24
Finished	Jul 31 06:04:58 PM PDT 24
Peak memory	288696 kb
Host	smart-3215dc68-cab8-498b-bdcd-0735041568d5
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844236894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha ndler_stress_all.1844236894
Directory	/workspace/27.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/28.alert_handler_entropy.3516336958
Short name	T632
Test name
Test status
Simulation time	26613364811 ps
CPU time	898.61 seconds
Started	Jul 31 05:22:31 PM PDT 24
Finished	Jul 31 05:37:30 PM PDT 24
Peak memory	269920 kb
Host	smart-771043a0-7fb2-416c-a88b-0163adf9ef5e
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3516336958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.3516336958
Directory	/workspace/28.alert_handler_entropy/latest

Test location	/workspace/coverage/default/28.alert_handler_esc_alert_accum.650935628
Short name	T365
Test name
Test status
Simulation time	552822795 ps
CPU time	58.09 seconds
Started	Jul 31 05:22:16 PM PDT 24
Finished	Jul 31 05:23:14 PM PDT 24
Peak memory	256044 kb
Host	smart-7619179b-fc71-4531-9eca-11a7f8448497
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65093 5628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.650935628
Directory	/workspace/28.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/28.alert_handler_esc_intr_timeout.4181349964
Short name	T486
Test name
Test status
Simulation time	2727107467 ps
CPU time	44.61 seconds
Started	Jul 31 05:22:09 PM PDT 24
Finished	Jul 31 05:22:54 PM PDT 24
Peak memory	255908 kb
Host	smart-c0cf2c54-f987-4ff9-ab77-810ffe0fd7e2
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41813 49964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.4181349964
Directory	/workspace/28.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/28.alert_handler_lpg_stub_clk.3416358482
Short name	T680
Test name
Test status
Simulation time	132632769558 ps
CPU time	2419.36 seconds
Started	Jul 31 05:22:23 PM PDT 24
Finished	Jul 31 06:02:43 PM PDT 24
Peak memory	289332 kb
Host	smart-b2e4bc59-1d33-43da-bf2a-3fd8a1b4c4fc
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3416358482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.3416358482
Directory	/workspace/28.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/28.alert_handler_random_alerts.3433084396
Short name	T461
Test name
Test status
Simulation time	1115592749 ps
CPU time	73.78 seconds
Started	Jul 31 05:22:30 PM PDT 24
Finished	Jul 31 05:23:44 PM PDT 24
Peak memory	255428 kb
Host	smart-a19db251-d554-47c9-8627-8fb353407582
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34330 84396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.3433084396
Directory	/workspace/28.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/28.alert_handler_random_classes.3041093634
Short name	T540
Test name
Test status
Simulation time	4146383803 ps
CPU time	70.25 seconds
Started	Jul 31 05:22:10 PM PDT 24
Finished	Jul 31 05:23:20 PM PDT 24
Peak memory	249444 kb
Host	smart-99631dda-7098-4fcd-87ab-b3a7dd0afd0e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30410 93634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.3041093634
Directory	/workspace/28.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/28.alert_handler_sig_int_fail.1493897980
Short name	T528
Test name
Test status
Simulation time	524099258 ps
CPU time	36.71 seconds
Started	Jul 31 05:22:07 PM PDT 24
Finished	Jul 31 05:22:44 PM PDT 24
Peak memory	248060 kb
Host	smart-12c74ac8-b053-4c7e-ba06-92774bf6d913
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14938 97980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.1493897980
Directory	/workspace/28.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/28.alert_handler_smoke.3680019724
Short name	T699
Test name
Test status
Simulation time	1329219491 ps
CPU time	71.51 seconds
Started	Jul 31 05:22:13 PM PDT 24
Finished	Jul 31 05:23:24 PM PDT 24
Peak memory	248796 kb
Host	smart-91cc526b-9532-4485-8b8b-3e866e4a3b6d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36800 19724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.3680019724
Directory	/workspace/28.alert_handler_smoke/latest

Test location	/workspace/coverage/default/28.alert_handler_stress_all.126959552
Short name	T474
Test name
Test status
Simulation time	10844667497 ps
CPU time	850.18 seconds
Started	Jul 31 05:22:23 PM PDT 24
Finished	Jul 31 05:36:34 PM PDT 24
Peak memory	272976 kb
Host	smart-b88f85aa-bc55-4a64-9d8d-528836400e9f
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126959552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_han dler_stress_all.126959552
Directory	/workspace/28.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/29.alert_handler_entropy.510869468
Short name	T105
Test name
Test status
Simulation time	50381411382 ps
CPU time	1122.54 seconds
Started	Jul 31 05:22:28 PM PDT 24
Finished	Jul 31 05:41:11 PM PDT 24
Peak memory	272944 kb
Host	smart-d3d3e78a-0e36-4d1c-bca2-109e1d4a2333
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=510869468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.510869468
Directory	/workspace/29.alert_handler_entropy/latest

Test location	/workspace/coverage/default/29.alert_handler_esc_alert_accum.3566159821
Short name	T1
Test name
Test status
Simulation time	21743255999 ps
CPU time	69.08 seconds
Started	Jul 31 05:22:26 PM PDT 24
Finished	Jul 31 05:23:35 PM PDT 24
Peak memory	255924 kb
Host	smart-92a4827e-9b63-4534-bbd9-185cae3bae6b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35661 59821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.3566159821
Directory	/workspace/29.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/29.alert_handler_esc_intr_timeout.4225450461
Short name	T536
Test name
Test status
Simulation time	216686577 ps
CPU time	24.73 seconds
Started	Jul 31 05:22:10 PM PDT 24
Finished	Jul 31 05:22:35 PM PDT 24
Peak memory	247772 kb
Host	smart-cccc97ca-fa8c-4f94-a6d6-7b26886cf05e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42254 50461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.4225450461
Directory	/workspace/29.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/29.alert_handler_lpg_stub_clk.256743768
Short name	T690
Test name
Test status
Simulation time	28395089514 ps
CPU time	1344.9 seconds
Started	Jul 31 05:22:24 PM PDT 24
Finished	Jul 31 05:44:49 PM PDT 24
Peak memory	289316 kb
Host	smart-7cfda473-c20f-4afe-a613-fef4b0189e7b
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=256743768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.256743768
Directory	/workspace/29.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/29.alert_handler_ping_timeout.1051782902
Short name	T302
Test name
Test status
Simulation time	6658903045 ps
CPU time	129.78 seconds
Started	Jul 31 05:22:14 PM PDT 24
Finished	Jul 31 05:24:24 PM PDT 24
Peak memory	254888 kb
Host	smart-61463125-a859-4749-b0dd-7b091ffa3c00
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1051782902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.1051782902
Directory	/workspace/29.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/29.alert_handler_random_alerts.3731895810
Short name	T460
Test name
Test status
Simulation time	1724515697 ps
CPU time	29.98 seconds
Started	Jul 31 05:22:08 PM PDT 24
Finished	Jul 31 05:22:38 PM PDT 24
Peak memory	255744 kb
Host	smart-7ebab838-f2ac-4b8c-84a7-7bbcf29c8f72
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37318 95810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.3731895810
Directory	/workspace/29.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/29.alert_handler_random_classes.3614731193
Short name	T403
Test name
Test status
Simulation time	1687385574 ps
CPU time	51.67 seconds
Started	Jul 31 05:22:13 PM PDT 24
Finished	Jul 31 05:23:05 PM PDT 24
Peak memory	247732 kb
Host	smart-20c1a360-446a-4f15-be25-9eeea98966ac
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36147 31193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.3614731193
Directory	/workspace/29.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/29.alert_handler_sig_int_fail.1014698865
Short name	T420
Test name
Test status
Simulation time	120888286 ps
CPU time	9.61 seconds
Started	Jul 31 05:22:11 PM PDT 24
Finished	Jul 31 05:22:21 PM PDT 24
Peak memory	248872 kb
Host	smart-730004c5-31ca-4d1d-9fb0-f4c11504828a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10146 98865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.1014698865
Directory	/workspace/29.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/29.alert_handler_smoke.1298939261
Short name	T590
Test name
Test status
Simulation time	570153112 ps
CPU time	49.64 seconds
Started	Jul 31 05:22:07 PM PDT 24
Finished	Jul 31 05:22:57 PM PDT 24
Peak memory	256476 kb
Host	smart-c6c3d097-ccb1-4fad-aa55-be5b92607a13
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12989 39261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.1298939261
Directory	/workspace/29.alert_handler_smoke/latest

Test location	/workspace/coverage/default/29.alert_handler_stress_all.3769011810
Short name	T295
Test name
Test status
Simulation time	21876139506 ps
CPU time	1345.37 seconds
Started	Jul 31 05:22:31 PM PDT 24
Finished	Jul 31 05:44:56 PM PDT 24
Peak memory	272396 kb
Host	smart-1589709d-1586-4294-a5f0-c12f545eedd8
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769011810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha ndler_stress_all.3769011810
Directory	/workspace/29.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/3.alert_handler_alert_accum_saturation.1615156694
Short name	T39
Test name
Test status
Simulation time	52286760 ps
CPU time	2.32 seconds
Started	Jul 31 05:21:13 PM PDT 24
Finished	Jul 31 05:21:16 PM PDT 24
Peak memory	248684 kb
Host	smart-da8e8b71-17f5-4557-9951-285247c4397d
User	root
Command	/workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1615156694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.1615156694
Directory	/workspace/3.alert_handler_alert_accum_saturation/latest

Test location	/workspace/coverage/default/3.alert_handler_entropy.1614131805
Short name	T286
Test name
Test status
Simulation time	126864012933 ps
CPU time	1942.51 seconds
Started	Jul 31 05:20:59 PM PDT 24
Finished	Jul 31 05:53:22 PM PDT 24
Peak memory	272844 kb
Host	smart-275e7dfd-416a-4800-9289-214b404823e3
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1614131805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.1614131805
Directory	/workspace/3.alert_handler_entropy/latest

Test location	/workspace/coverage/default/3.alert_handler_entropy_stress.476033737
Short name	T686
Test name
Test status
Simulation time	3934875432 ps
CPU time	77.36 seconds
Started	Jul 31 05:20:53 PM PDT 24
Finished	Jul 31 05:22:11 PM PDT 24
Peak memory	248436 kb
Host	smart-8577abf6-a426-4b21-8559-14ec4d546633
User	root
Command	/workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=476033737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.476033737
Directory	/workspace/3.alert_handler_entropy_stress/latest

Test location	/workspace/coverage/default/3.alert_handler_esc_alert_accum.700516150
Short name	T415
Test name
Test status
Simulation time	7769304002 ps
CPU time	92.43 seconds
Started	Jul 31 05:21:09 PM PDT 24
Finished	Jul 31 05:22:42 PM PDT 24
Peak memory	256136 kb
Host	smart-d0e1b38d-fcf9-4950-9ed8-fa83c6357da3
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70051 6150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.700516150
Directory	/workspace/3.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/3.alert_handler_esc_intr_timeout.3264171990
Short name	T567
Test name
Test status
Simulation time	2545219288 ps
CPU time	38.83 seconds
Started	Jul 31 05:21:09 PM PDT 24
Finished	Jul 31 05:21:48 PM PDT 24
Peak memory	256612 kb
Host	smart-47c69112-b473-4794-b6e8-1d8cf8fff941
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32641 71990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.3264171990
Directory	/workspace/3.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/3.alert_handler_lpg.3452261939
Short name	T329
Test name
Test status
Simulation time	208124503626 ps
CPU time	1475.8 seconds
Started	Jul 31 05:21:13 PM PDT 24
Finished	Jul 31 05:45:49 PM PDT 24
Peak memory	272548 kb
Host	smart-99069321-2483-4581-9461-ab5d43a2e29c
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3452261939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.3452261939
Directory	/workspace/3.alert_handler_lpg/latest

Test location	/workspace/coverage/default/3.alert_handler_lpg_stub_clk.2189981089
Short name	T235
Test name
Test status
Simulation time	11199615297 ps
CPU time	953.15 seconds
Started	Jul 31 05:21:03 PM PDT 24
Finished	Jul 31 05:36:56 PM PDT 24
Peak memory	272836 kb
Host	smart-90a895fa-153f-43e2-951b-ce1c8ee30a46
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2189981089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.2189981089
Directory	/workspace/3.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/3.alert_handler_ping_timeout.1113892886
Short name	T308
Test name
Test status
Simulation time	22695565179 ps
CPU time	499.12 seconds
Started	Jul 31 05:21:09 PM PDT 24
Finished	Jul 31 05:29:28 PM PDT 24
Peak memory	248424 kb
Host	smart-13274c68-d637-45b2-932f-18381924d93d
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1113892886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.1113892886
Directory	/workspace/3.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/3.alert_handler_random_alerts.3874140334
Short name	T668
Test name
Test status
Simulation time	296200691 ps
CPU time	26.39 seconds
Started	Jul 31 05:21:12 PM PDT 24
Finished	Jul 31 05:21:39 PM PDT 24
Peak memory	255696 kb
Host	smart-f12babf0-10fd-4501-97f1-37c0e2ca97c4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38741 40334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.3874140334
Directory	/workspace/3.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/3.alert_handler_random_classes.1478575943
Short name	T387
Test name
Test status
Simulation time	5357853203 ps
CPU time	40.13 seconds
Started	Jul 31 05:21:00 PM PDT 24
Finished	Jul 31 05:21:40 PM PDT 24
Peak memory	256392 kb
Host	smart-627c3dbb-fae0-4b2a-9c9d-d22110655c2d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14785 75943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.1478575943
Directory	/workspace/3.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/3.alert_handler_sec_cm.2228746674
Short name	T35
Test name
Test status
Simulation time	2393930741 ps
CPU time	22.78 seconds
Started	Jul 31 05:20:57 PM PDT 24
Finished	Jul 31 05:21:20 PM PDT 24
Peak memory	271076 kb
Host	smart-d389381e-b8bc-4127-ad68-871fbdf3cf9c
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2228746674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.2228746674
Directory	/workspace/3.alert_handler_sec_cm/latest

Test location	/workspace/coverage/default/3.alert_handler_sig_int_fail.3943856513
Short name	T530
Test name
Test status
Simulation time	3995128313 ps
CPU time	26.31 seconds
Started	Jul 31 05:20:50 PM PDT 24
Finished	Jul 31 05:21:16 PM PDT 24
Peak memory	247760 kb
Host	smart-40f9c688-c270-4ede-8c39-4a1fa0fce58b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39438 56513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.3943856513
Directory	/workspace/3.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/3.alert_handler_smoke.1787353650
Short name	T360
Test name
Test status
Simulation time	1215652044 ps
CPU time	34.38 seconds
Started	Jul 31 05:21:01 PM PDT 24
Finished	Jul 31 05:21:35 PM PDT 24
Peak memory	248296 kb
Host	smart-35fccc41-30cf-4cfd-abe6-ee50c29a4590
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17873 53650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.1787353650
Directory	/workspace/3.alert_handler_smoke/latest

Test location	/workspace/coverage/default/3.alert_handler_stress_all.1521224525
Short name	T541
Test name
Test status
Simulation time	33134793729 ps
CPU time	1332.74 seconds
Started	Jul 31 05:21:10 PM PDT 24
Finished	Jul 31 05:43:23 PM PDT 24
Peak memory	288940 kb
Host	smart-a8c1d79d-eab6-4f89-9bd8-b5015fb66a60
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521224525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han dler_stress_all.1521224525
Directory	/workspace/3.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/30.alert_handler_entropy.90776877
Short name	T675
Test name
Test status
Simulation time	69219605822 ps
CPU time	1943.55 seconds
Started	Jul 31 05:22:10 PM PDT 24
Finished	Jul 31 05:54:34 PM PDT 24
Peak memory	272768 kb
Host	smart-3fc9d1db-d3e3-4877-9bce-f1beb57d395f
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=90776877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.90776877
Directory	/workspace/30.alert_handler_entropy/latest

Test location	/workspace/coverage/default/30.alert_handler_esc_alert_accum.651389498
Short name	T181
Test name
Test status
Simulation time	11348987820 ps
CPU time	249.84 seconds
Started	Jul 31 05:22:13 PM PDT 24
Finished	Jul 31 05:26:23 PM PDT 24
Peak memory	256568 kb
Host	smart-2bd74072-31d7-40da-aa35-110a2fcc91e8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65138 9498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.651389498
Directory	/workspace/30.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/30.alert_handler_esc_intr_timeout.2920510750
Short name	T664
Test name
Test status
Simulation time	1117847313 ps
CPU time	68.13 seconds
Started	Jul 31 05:22:33 PM PDT 24
Finished	Jul 31 05:23:41 PM PDT 24
Peak memory	256104 kb
Host	smart-6e909340-072c-4fea-b4c5-ecbed1d4cba6
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29205 10750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.2920510750
Directory	/workspace/30.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/30.alert_handler_lpg.1956076593
Short name	T99
Test name
Test status
Simulation time	73101437497 ps
CPU time	2300.93 seconds
Started	Jul 31 05:22:14 PM PDT 24
Finished	Jul 31 06:00:36 PM PDT 24
Peak memory	288916 kb
Host	smart-c3225634-9184-4c95-808b-f9df46b09031
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1956076593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.1956076593
Directory	/workspace/30.alert_handler_lpg/latest

Test location	/workspace/coverage/default/30.alert_handler_lpg_stub_clk.3738124153
Short name	T620
Test name
Test status
Simulation time	88987884538 ps
CPU time	3057.19 seconds
Started	Jul 31 05:22:30 PM PDT 24
Finished	Jul 31 06:13:27 PM PDT 24
Peak memory	289296 kb
Host	smart-5750557b-7e5e-4eb7-9a98-2b5afe44f272
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3738124153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.3738124153
Directory	/workspace/30.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/30.alert_handler_random_alerts.2843274079
Short name	T639
Test name
Test status
Simulation time	478521414 ps
CPU time	31.49 seconds
Started	Jul 31 05:22:29 PM PDT 24
Finished	Jul 31 05:23:00 PM PDT 24
Peak memory	248240 kb
Host	smart-ec858a89-0f9f-47fa-975a-68ebfb8cd9e4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28432 74079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.2843274079
Directory	/workspace/30.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/30.alert_handler_random_classes.2381472552
Short name	T85
Test name
Test status
Simulation time	1923603977 ps
CPU time	33.72 seconds
Started	Jul 31 05:22:11 PM PDT 24
Finished	Jul 31 05:22:45 PM PDT 24
Peak memory	254864 kb
Host	smart-a076f2bc-7a90-4f61-bf3e-9c15e7dd5ccd
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23814 72552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.2381472552
Directory	/workspace/30.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/30.alert_handler_sig_int_fail.405519372
Short name	T394
Test name
Test status
Simulation time	519406777 ps
CPU time	22.32 seconds
Started	Jul 31 05:22:14 PM PDT 24
Finished	Jul 31 05:22:37 PM PDT 24
Peak memory	255420 kb
Host	smart-77357869-9111-42cf-90ea-e0826259ef4e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40551 9372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.405519372
Directory	/workspace/30.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/30.alert_handler_stress_all.443286033
Short name	T458
Test name
Test status
Simulation time	39682342212 ps
CPU time	2126.21 seconds
Started	Jul 31 05:22:12 PM PDT 24
Finished	Jul 31 05:57:38 PM PDT 24
Peak memory	289056 kb
Host	smart-0993aa55-a1fc-4f2c-abdf-5eac5234a5a1
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443286033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_han dler_stress_all.443286033
Directory	/workspace/30.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/31.alert_handler_entropy.4048939681
Short name	T411
Test name
Test status
Simulation time	11562407861 ps
CPU time	1113.22 seconds
Started	Jul 31 05:22:33 PM PDT 24
Finished	Jul 31 05:41:07 PM PDT 24
Peak memory	288344 kb
Host	smart-c0fd33e2-c8f5-49fc-9edd-f8ddf7198c93
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4048939681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.4048939681
Directory	/workspace/31.alert_handler_entropy/latest

Test location	/workspace/coverage/default/31.alert_handler_esc_alert_accum.4239649115
Short name	T364
Test name
Test status
Simulation time	5918153316 ps
CPU time	364.17 seconds
Started	Jul 31 05:22:18 PM PDT 24
Finished	Jul 31 05:28:22 PM PDT 24
Peak memory	256616 kb
Host	smart-9e82a8fe-cd05-4a02-9081-0f465f8d76d7
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42396 49115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.4239649115
Directory	/workspace/31.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/31.alert_handler_lpg_stub_clk.1783684303
Short name	T549
Test name
Test status
Simulation time	65310867557 ps
CPU time	926.73 seconds
Started	Jul 31 05:22:21 PM PDT 24
Finished	Jul 31 05:37:48 PM PDT 24
Peak memory	270872 kb
Host	smart-f63888dd-5c9b-495b-9d33-56cc8596f10d
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1783684303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.1783684303
Directory	/workspace/31.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/31.alert_handler_random_alerts.2023017782
Short name	T697
Test name
Test status
Simulation time	1538813621 ps
CPU time	49.6 seconds
Started	Jul 31 05:22:29 PM PDT 24
Finished	Jul 31 05:23:18 PM PDT 24
Peak memory	248284 kb
Host	smart-735c6324-482a-4bbb-8b7b-b5197e3f8c72
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20230 17782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.2023017782
Directory	/workspace/31.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/31.alert_handler_random_classes.2661783207
Short name	T537
Test name
Test status
Simulation time	3028718663 ps
CPU time	43.6 seconds
Started	Jul 31 05:22:13 PM PDT 24
Finished	Jul 31 05:22:56 PM PDT 24
Peak memory	247860 kb
Host	smart-602b3a91-f527-4a86-9148-0a65ad0e67fc
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26617 83207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.2661783207
Directory	/workspace/31.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/31.alert_handler_sig_int_fail.1686992479
Short name	T291
Test name
Test status
Simulation time	232162603 ps
CPU time	7.73 seconds
Started	Jul 31 05:22:26 PM PDT 24
Finished	Jul 31 05:22:34 PM PDT 24
Peak memory	254004 kb
Host	smart-1f46e9ae-f699-40cd-beab-eb3c38d4bb2a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16869 92479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.1686992479
Directory	/workspace/31.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/31.alert_handler_smoke.792588101
Short name	T388
Test name
Test status
Simulation time	703337876 ps
CPU time	41.3 seconds
Started	Jul 31 05:22:28 PM PDT 24
Finished	Jul 31 05:23:09 PM PDT 24
Peak memory	256512 kb
Host	smart-41468baf-ac5c-473c-80b6-be2b2ceb26bb
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79258 8101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.792588101
Directory	/workspace/31.alert_handler_smoke/latest

Test location	/workspace/coverage/default/31.alert_handler_stress_all.2483810078
Short name	T294
Test name
Test status
Simulation time	58804422165 ps
CPU time	1945.25 seconds
Started	Jul 31 05:22:15 PM PDT 24
Finished	Jul 31 05:54:40 PM PDT 24
Peak memory	289336 kb
Host	smart-6e0a4acf-4458-49fb-a66c-b96c93cc6d99
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483810078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha ndler_stress_all.2483810078
Directory	/workspace/31.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.2360695165
Short name	T252
Test name
Test status
Simulation time	177233460399 ps
CPU time	4163.87 seconds
Started	Jul 31 05:22:25 PM PDT 24
Finished	Jul 31 06:31:49 PM PDT 24
Peak memory	321472 kb
Host	smart-c0f6f18c-72e9-46b7-bd56-9aa47d953878
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360695165 -assert nopostproc +UVM_TESTNAME=aler t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.2360695165
Directory	/workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/32.alert_handler_entropy.3743568207
Short name	T53
Test name
Test status
Simulation time	28935850286 ps
CPU time	1395.18 seconds
Started	Jul 31 05:22:35 PM PDT 24
Finished	Jul 31 05:45:51 PM PDT 24
Peak memory	288772 kb
Host	smart-7eedc6c2-031e-4cce-8c14-5727a16621eb
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3743568207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.3743568207
Directory	/workspace/32.alert_handler_entropy/latest

Test location	/workspace/coverage/default/32.alert_handler_esc_alert_accum.892825297
Short name	T358
Test name
Test status
Simulation time	4342611163 ps
CPU time	72.59 seconds
Started	Jul 31 05:22:31 PM PDT 24
Finished	Jul 31 05:23:44 PM PDT 24
Peak memory	256580 kb
Host	smart-dd2f528c-2236-4f6f-850a-b9ba13971ff3
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89282 5297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.892825297
Directory	/workspace/32.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/32.alert_handler_esc_intr_timeout.1983271033
Short name	T469
Test name
Test status
Simulation time	1045350570 ps
CPU time	32.18 seconds
Started	Jul 31 05:22:29 PM PDT 24
Finished	Jul 31 05:23:01 PM PDT 24
Peak memory	248324 kb
Host	smart-66a97bd9-e96b-473c-aa34-75751b5296c9
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19832 71033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.1983271033
Directory	/workspace/32.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/32.alert_handler_lpg_stub_clk.4086037905
Short name	T68
Test name
Test status
Simulation time	20777589954 ps
CPU time	1160.9 seconds
Started	Jul 31 05:22:27 PM PDT 24
Finished	Jul 31 05:41:49 PM PDT 24
Peak memory	272940 kb
Host	smart-4942c492-9056-40fb-922e-d66812937782
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4086037905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.4086037905
Directory	/workspace/32.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/32.alert_handler_random_alerts.998008510
Short name	T608
Test name
Test status
Simulation time	4459837250 ps
CPU time	36.73 seconds
Started	Jul 31 05:22:24 PM PDT 24
Finished	Jul 31 05:23:00 PM PDT 24
Peak memory	255888 kb
Host	smart-7162adc9-3e1c-4eef-8cf0-550adc55a2a6
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99800 8510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.998008510
Directory	/workspace/32.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/32.alert_handler_random_classes.3245507072
Short name	T61
Test name
Test status
Simulation time	1295843715 ps
CPU time	41.43 seconds
Started	Jul 31 05:22:27 PM PDT 24
Finished	Jul 31 05:23:09 PM PDT 24
Peak memory	248188 kb
Host	smart-279f113e-2998-4815-89dd-cc6265838c33
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32455 07072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.3245507072
Directory	/workspace/32.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/32.alert_handler_sig_int_fail.4035160510
Short name	T450
Test name
Test status
Simulation time	842423289 ps
CPU time	24.85 seconds
Started	Jul 31 05:22:21 PM PDT 24
Finished	Jul 31 05:22:46 PM PDT 24
Peak memory	247972 kb
Host	smart-9b208c16-dcb4-4704-8063-e2839338c6c3
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40351 60510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.4035160510
Directory	/workspace/32.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/32.alert_handler_smoke.1981485521
Short name	T383
Test name
Test status
Simulation time	920870740 ps
CPU time	24.56 seconds
Started	Jul 31 05:22:12 PM PDT 24
Finished	Jul 31 05:22:36 PM PDT 24
Peak memory	256500 kb
Host	smart-b967cc75-565d-4664-b305-54d58c11fede
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19814 85521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.1981485521
Directory	/workspace/32.alert_handler_smoke/latest

Test location	/workspace/coverage/default/32.alert_handler_stress_all.2500226819
Short name	T513
Test name
Test status
Simulation time	78204578195 ps
CPU time	2153.65 seconds
Started	Jul 31 05:22:32 PM PDT 24
Finished	Jul 31 05:58:26 PM PDT 24
Peak memory	289064 kb
Host	smart-e83756af-e99f-4032-99c1-bdf4f0efe55f
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500226819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha ndler_stress_all.2500226819
Directory	/workspace/32.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.3558478165
Short name	T443
Test name
Test status
Simulation time	235572350895 ps
CPU time	5402.31 seconds
Started	Jul 31 05:22:18 PM PDT 24
Finished	Jul 31 06:52:21 PM PDT 24
Peak memory	371072 kb
Host	smart-a6eecdf0-fbfe-4202-bd99-174b65d7c840
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558478165 -assert nopostproc +UVM_TESTNAME=aler t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.3558478165
Directory	/workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/33.alert_handler_entropy.1994101740
Short name	T584
Test name
Test status
Simulation time	34263071807 ps
CPU time	879.88 seconds
Started	Jul 31 05:22:30 PM PDT 24
Finished	Jul 31 05:37:10 PM PDT 24
Peak memory	289012 kb
Host	smart-387cbae7-0184-468a-9fb6-ebdf4ccfd7db
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1994101740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.1994101740
Directory	/workspace/33.alert_handler_entropy/latest

Test location	/workspace/coverage/default/33.alert_handler_esc_alert_accum.4188639485
Short name	T666
Test name
Test status
Simulation time	4582475632 ps
CPU time	107.8 seconds
Started	Jul 31 05:22:32 PM PDT 24
Finished	Jul 31 05:24:20 PM PDT 24
Peak memory	256104 kb
Host	smart-e25577e8-8fdc-4647-8a65-67d5b6823760
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41886 39485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.4188639485
Directory	/workspace/33.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/33.alert_handler_esc_intr_timeout.1971466157
Short name	T222
Test name
Test status
Simulation time	567334979 ps
CPU time	34.07 seconds
Started	Jul 31 05:22:19 PM PDT 24
Finished	Jul 31 05:22:53 PM PDT 24
Peak memory	256540 kb
Host	smart-fcc77d5d-ea13-4ae6-bed6-415eb0b3770b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19714 66157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.1971466157
Directory	/workspace/33.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/33.alert_handler_lpg.3542731376
Short name	T328
Test name
Test status
Simulation time	73997746786 ps
CPU time	1676.57 seconds
Started	Jul 31 05:22:25 PM PDT 24
Finished	Jul 31 05:50:22 PM PDT 24
Peak memory	289156 kb
Host	smart-e4f081c7-4ab3-4b4e-9b72-5a79f8848492
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3542731376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.3542731376
Directory	/workspace/33.alert_handler_lpg/latest

Test location	/workspace/coverage/default/33.alert_handler_lpg_stub_clk.4134896808
Short name	T370
Test name
Test status
Simulation time	17241978503 ps
CPU time	1544.03 seconds
Started	Jul 31 05:22:28 PM PDT 24
Finished	Jul 31 05:48:12 PM PDT 24
Peak memory	281152 kb
Host	smart-73662696-15ce-4af9-b5c3-cb38521f2516
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4134896808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.4134896808
Directory	/workspace/33.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/33.alert_handler_random_alerts.2561197511
Short name	T617
Test name
Test status
Simulation time	87037008 ps
CPU time	8.66 seconds
Started	Jul 31 05:22:27 PM PDT 24
Finished	Jul 31 05:22:36 PM PDT 24
Peak memory	248360 kb
Host	smart-346d6789-3125-4a05-b096-d41499a9d081
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25611 97511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.2561197511
Directory	/workspace/33.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/33.alert_handler_random_classes.2896682172
Short name	T500
Test name
Test status
Simulation time	1172752880 ps
CPU time	68.88 seconds
Started	Jul 31 05:22:19 PM PDT 24
Finished	Jul 31 05:23:28 PM PDT 24
Peak memory	256016 kb
Host	smart-d800cbd5-7b77-4dc4-bf9a-3ac902327829
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28966 82172 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.2896682172
Directory	/workspace/33.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/33.alert_handler_sig_int_fail.2587127599
Short name	T472
Test name
Test status
Simulation time	955274458 ps
CPU time	22.34 seconds
Started	Jul 31 05:22:18 PM PDT 24
Finished	Jul 31 05:22:41 PM PDT 24
Peak memory	256160 kb
Host	smart-9798e656-e9b1-458f-8c8a-0158e51d259f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25871 27599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.2587127599
Directory	/workspace/33.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/33.alert_handler_smoke.3016819098
Short name	T591
Test name
Test status
Simulation time	445110634 ps
CPU time	29.24 seconds
Started	Jul 31 05:22:28 PM PDT 24
Finished	Jul 31 05:22:57 PM PDT 24
Peak memory	255816 kb
Host	smart-370423dc-f305-4294-85a8-07d5bf4b2bbc
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30168 19098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.3016819098
Directory	/workspace/33.alert_handler_smoke/latest

Test location	/workspace/coverage/default/33.alert_handler_stress_all.274910204
Short name	T532
Test name
Test status
Simulation time	141570166912 ps
CPU time	4187.15 seconds
Started	Jul 31 05:22:16 PM PDT 24
Finished	Jul 31 06:32:04 PM PDT 24
Peak memory	305296 kb
Host	smart-56162cec-4f04-4a4a-a988-fe81a9ee878f
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274910204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_han dler_stress_all.274910204
Directory	/workspace/33.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/34.alert_handler_entropy.2075527189
Short name	T439
Test name
Test status
Simulation time	175240010790 ps
CPU time	2583.57 seconds
Started	Jul 31 05:22:17 PM PDT 24
Finished	Jul 31 06:05:21 PM PDT 24
Peak memory	284916 kb
Host	smart-719d8a9a-cef4-436b-9790-0d18ce4ec606
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2075527189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.2075527189
Directory	/workspace/34.alert_handler_entropy/latest

Test location	/workspace/coverage/default/34.alert_handler_esc_alert_accum.1821247506
Short name	T498
Test name
Test status
Simulation time	8325166941 ps
CPU time	161.58 seconds
Started	Jul 31 05:22:17 PM PDT 24
Finished	Jul 31 05:24:59 PM PDT 24
Peak memory	256576 kb
Host	smart-b620fdf5-002a-40c1-8452-b585339c4374
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18212 47506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.1821247506
Directory	/workspace/34.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/34.alert_handler_esc_intr_timeout.3391401010
Short name	T413
Test name
Test status
Simulation time	4256812493 ps
CPU time	48.55 seconds
Started	Jul 31 05:22:17 PM PDT 24
Finished	Jul 31 05:23:06 PM PDT 24
Peak memory	249372 kb
Host	smart-ee2ac456-384a-4f0d-8a68-a148ce565540
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33914 01010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.3391401010
Directory	/workspace/34.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/34.alert_handler_lpg_stub_clk.3485999777
Short name	T22
Test name
Test status
Simulation time	38173019460 ps
CPU time	2548.51 seconds
Started	Jul 31 05:22:21 PM PDT 24
Finished	Jul 31 06:04:50 PM PDT 24
Peak memory	289340 kb
Host	smart-8ec139b0-01a5-42af-9e1b-eb99215f08c4
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3485999777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.3485999777
Directory	/workspace/34.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/34.alert_handler_ping_timeout.123838735
Short name	T651
Test name
Test status
Simulation time	23464118597 ps
CPU time	204.51 seconds
Started	Jul 31 05:22:31 PM PDT 24
Finished	Jul 31 05:25:56 PM PDT 24
Peak memory	248176 kb
Host	smart-2bab55ad-af1c-48aa-b592-6892ef4193a3
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=123838735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.123838735
Directory	/workspace/34.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/34.alert_handler_random_alerts.2045821771
Short name	T464
Test name
Test status
Simulation time	1332674777 ps
CPU time	40.6 seconds
Started	Jul 31 05:22:20 PM PDT 24
Finished	Jul 31 05:23:01 PM PDT 24
Peak memory	248284 kb
Host	smart-6d051806-bf7a-4ad6-89ed-257f89a07504
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20458 21771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.2045821771
Directory	/workspace/34.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/34.alert_handler_random_classes.2036923502
Short name	T84
Test name
Test status
Simulation time	336094089 ps
CPU time	8.39 seconds
Started	Jul 31 05:22:20 PM PDT 24
Finished	Jul 31 05:22:29 PM PDT 24
Peak memory	253256 kb
Host	smart-26a747ce-9d86-416a-be45-f97568a1d446
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20369 23502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.2036923502
Directory	/workspace/34.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/34.alert_handler_sig_int_fail.2292815192
Short name	T261
Test name
Test status
Simulation time	455691618 ps
CPU time	24.18 seconds
Started	Jul 31 05:22:29 PM PDT 24
Finished	Jul 31 05:22:53 PM PDT 24
Peak memory	254536 kb
Host	smart-0741cbfc-8e54-4c95-8009-1517fc07c687
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22928 15192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.2292815192
Directory	/workspace/34.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/34.alert_handler_smoke.545560392
Short name	T633
Test name
Test status
Simulation time	157291546 ps
CPU time	18.53 seconds
Started	Jul 31 05:22:26 PM PDT 24
Finished	Jul 31 05:22:45 PM PDT 24
Peak memory	255592 kb
Host	smart-852c16bf-32d8-4e8d-94d3-710e8b2eb49d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54556 0392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.545560392
Directory	/workspace/34.alert_handler_smoke/latest

Test location	/workspace/coverage/default/34.alert_handler_stress_all.1944063834
Short name	T265
Test name
Test status
Simulation time	68976875143 ps
CPU time	2127.75 seconds
Started	Jul 31 05:22:32 PM PDT 24
Finished	Jul 31 05:58:00 PM PDT 24
Peak memory	282072 kb
Host	smart-4a0a3ad2-d77b-4bf7-8308-b6e9a0f94a7c
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944063834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha ndler_stress_all.1944063834
Directory	/workspace/34.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.1778171115
Short name	T44
Test name
Test status
Simulation time	37173715731 ps
CPU time	2524.2 seconds
Started	Jul 31 05:22:20 PM PDT 24
Finished	Jul 31 06:04:25 PM PDT 24
Peak memory	289096 kb
Host	smart-c1b4f704-b88c-4a6f-8962-8a5063ece786
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778171115 -assert nopostproc +UVM_TESTNAME=aler t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.1778171115
Directory	/workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/35.alert_handler_entropy.4136777310
Short name	T438
Test name
Test status
Simulation time	18821606916 ps
CPU time	832.16 seconds
Started	Jul 31 05:22:30 PM PDT 24
Finished	Jul 31 05:36:23 PM PDT 24
Peak memory	272980 kb
Host	smart-e326ef19-e445-4a91-9532-8d349275b775
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4136777310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.4136777310
Directory	/workspace/35.alert_handler_entropy/latest

Test location	/workspace/coverage/default/35.alert_handler_esc_alert_accum.2854897705
Short name	T355
Test name
Test status
Simulation time	902033760 ps
CPU time	42.29 seconds
Started	Jul 31 05:22:34 PM PDT 24
Finished	Jul 31 05:23:17 PM PDT 24
Peak memory	256060 kb
Host	smart-d4bcc0e3-1dd5-4614-ae9b-a48ea6198d9b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28548 97705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.2854897705
Directory	/workspace/35.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/35.alert_handler_esc_intr_timeout.1400885935
Short name	T71
Test name
Test status
Simulation time	1856038472 ps
CPU time	67.08 seconds
Started	Jul 31 05:22:20 PM PDT 24
Finished	Jul 31 05:23:27 PM PDT 24
Peak memory	248336 kb
Host	smart-26eb4f51-4ab3-494e-b0a4-0c806045d170
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14008 85935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.1400885935
Directory	/workspace/35.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/35.alert_handler_lpg_stub_clk.3549608283
Short name	T611
Test name
Test status
Simulation time	27498262021 ps
CPU time	1649.84 seconds
Started	Jul 31 05:22:34 PM PDT 24
Finished	Jul 31 05:50:04 PM PDT 24
Peak memory	285384 kb
Host	smart-bf5d4a1f-9a16-43dd-acbd-04a3b5885fe4
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3549608283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.3549608283
Directory	/workspace/35.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/35.alert_handler_ping_timeout.935045095
Short name	T446
Test name
Test status
Simulation time	26103954285 ps
CPU time	536.67 seconds
Started	Jul 31 05:22:33 PM PDT 24
Finished	Jul 31 05:31:29 PM PDT 24
Peak memory	248384 kb
Host	smart-0d4cbf77-b4cf-4c78-a1a7-78486efb9343
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=935045095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.935045095
Directory	/workspace/35.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/35.alert_handler_random_alerts.229639731
Short name	T542
Test name
Test status
Simulation time	350237118 ps
CPU time	9.52 seconds
Started	Jul 31 05:22:20 PM PDT 24
Finished	Jul 31 05:22:30 PM PDT 24
Peak memory	248364 kb
Host	smart-4bc21bcb-ce77-4572-adf9-37831f16264e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22963 9731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.229639731
Directory	/workspace/35.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/35.alert_handler_random_classes.1039543670
Short name	T97
Test name
Test status
Simulation time	842150090 ps
CPU time	55.8 seconds
Started	Jul 31 05:22:25 PM PDT 24
Finished	Jul 31 05:23:21 PM PDT 24
Peak memory	255888 kb
Host	smart-51b32376-5f76-4c00-8bf7-f5e9d1c9d44f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10395 43670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.1039543670
Directory	/workspace/35.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/35.alert_handler_smoke.3190278492
Short name	T694
Test name
Test status
Simulation time	188747902 ps
CPU time	13.16 seconds
Started	Jul 31 05:22:24 PM PDT 24
Finished	Jul 31 05:22:37 PM PDT 24
Peak memory	248392 kb
Host	smart-aa3570ef-bf95-418f-bbd2-a28916a6da34
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31902 78492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.3190278492
Directory	/workspace/35.alert_handler_smoke/latest

Test location	/workspace/coverage/default/36.alert_handler_entropy.3760545665
Short name	T707
Test name
Test status
Simulation time	8432021796 ps
CPU time	1025.13 seconds
Started	Jul 31 05:22:19 PM PDT 24
Finished	Jul 31 05:39:24 PM PDT 24
Peak memory	281188 kb
Host	smart-9a53400b-18df-46e4-9cab-abaef46806d4
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3760545665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.3760545665
Directory	/workspace/36.alert_handler_entropy/latest

Test location	/workspace/coverage/default/36.alert_handler_esc_alert_accum.1238596019
Short name	T501
Test name
Test status
Simulation time	25476589513 ps
CPU time	151.42 seconds
Started	Jul 31 05:22:34 PM PDT 24
Finished	Jul 31 05:25:06 PM PDT 24
Peak memory	256772 kb
Host	smart-7c640e3a-da71-4521-ae71-b46ca31d542b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12385 96019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.1238596019
Directory	/workspace/36.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/36.alert_handler_esc_intr_timeout.21042654
Short name	T389
Test name
Test status
Simulation time	1252425255 ps
CPU time	23.13 seconds
Started	Jul 31 05:22:24 PM PDT 24
Finished	Jul 31 05:22:48 PM PDT 24
Peak memory	247672 kb
Host	smart-f1d30b09-4687-4596-a1a9-a5f1de713f1f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21042 654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.21042654
Directory	/workspace/36.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/36.alert_handler_lpg.2641836334
Short name	T326
Test name
Test status
Simulation time	104122974022 ps
CPU time	1462.83 seconds
Started	Jul 31 05:22:32 PM PDT 24
Finished	Jul 31 05:46:55 PM PDT 24
Peak memory	272188 kb
Host	smart-674a2164-0685-4bfa-b5bd-61ad8490b2f0
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2641836334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.2641836334
Directory	/workspace/36.alert_handler_lpg/latest

Test location	/workspace/coverage/default/36.alert_handler_lpg_stub_clk.2308629500
Short name	T288
Test name
Test status
Simulation time	92867080409 ps
CPU time	823.64 seconds
Started	Jul 31 05:22:25 PM PDT 24
Finished	Jul 31 05:36:09 PM PDT 24
Peak memory	272556 kb
Host	smart-a48c16fe-1221-4a02-90af-c878ba630bf4
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2308629500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.2308629500
Directory	/workspace/36.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/36.alert_handler_ping_timeout.2412177069
Short name	T223
Test name
Test status
Simulation time	2664653915 ps
CPU time	117.15 seconds
Started	Jul 31 05:22:26 PM PDT 24
Finished	Jul 31 05:24:24 PM PDT 24
Peak memory	247104 kb
Host	smart-bce81c97-6b18-4917-b820-ea40b7598c62
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2412177069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.2412177069
Directory	/workspace/36.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/36.alert_handler_random_alerts.1735447869
Short name	T440
Test name
Test status
Simulation time	232297798 ps
CPU time	23.87 seconds
Started	Jul 31 05:22:23 PM PDT 24
Finished	Jul 31 05:22:47 PM PDT 24
Peak memory	256508 kb
Host	smart-d94a1d74-76aa-45c4-b6cb-8d7d1059df4a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17354 47869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.1735447869
Directory	/workspace/36.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/36.alert_handler_random_classes.1974181126
Short name	T87
Test name
Test status
Simulation time	255184950 ps
CPU time	30.15 seconds
Started	Jul 31 05:22:23 PM PDT 24
Finished	Jul 31 05:22:53 PM PDT 24
Peak memory	247812 kb
Host	smart-ed1193e0-a943-4a56-a805-e71c26b57831
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19741 81126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.1974181126
Directory	/workspace/36.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/36.alert_handler_sig_int_fail.2839908161
Short name	T710
Test name
Test status
Simulation time	751626727 ps
CPU time	51.95 seconds
Started	Jul 31 05:22:25 PM PDT 24
Finished	Jul 31 05:23:17 PM PDT 24
Peak memory	248280 kb
Host	smart-7d6b8a43-22f7-46dc-a3ae-d67a048a8e20
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28399 08161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.2839908161
Directory	/workspace/36.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/36.alert_handler_smoke.3115063335
Short name	T487
Test name
Test status
Simulation time	313138361 ps
CPU time	34.86 seconds
Started	Jul 31 05:22:32 PM PDT 24
Finished	Jul 31 05:23:07 PM PDT 24
Peak memory	256508 kb
Host	smart-1b67edf8-8d4b-4ce6-b667-95e2e319ad1e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31150 63335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.3115063335
Directory	/workspace/36.alert_handler_smoke/latest

Test location	/workspace/coverage/default/36.alert_handler_stress_all.458513211
Short name	T473
Test name
Test status
Simulation time	11063576184 ps
CPU time	1099.72 seconds
Started	Jul 31 05:22:26 PM PDT 24
Finished	Jul 31 05:40:46 PM PDT 24
Peak memory	284972 kb
Host	smart-78fd5823-1b32-45b5-a181-800affa367b3
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458513211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_han dler_stress_all.458513211
Directory	/workspace/36.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.1154659091
Short name	T107
Test name
Test status
Simulation time	77747324437 ps
CPU time	6634.47 seconds
Started	Jul 31 05:22:22 PM PDT 24
Finished	Jul 31 07:12:57 PM PDT 24
Peak memory	345584 kb
Host	smart-7b7afcf9-d712-44a3-b58a-a34fe88b7dfc
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154659091 -assert nopostproc +UVM_TESTNAME=aler t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.1154659091
Directory	/workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/37.alert_handler_entropy.3273020193
Short name	T82
Test name
Test status
Simulation time	263751250611 ps
CPU time	3046.17 seconds
Started	Jul 31 05:22:21 PM PDT 24
Finished	Jul 31 06:13:07 PM PDT 24
Peak memory	289024 kb
Host	smart-73b970cf-e359-4ef7-8cc9-3b2a064d2941
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3273020193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.3273020193
Directory	/workspace/37.alert_handler_entropy/latest

Test location	/workspace/coverage/default/37.alert_handler_esc_alert_accum.2724650031
Short name	T607
Test name
Test status
Simulation time	5762016442 ps
CPU time	89.8 seconds
Started	Jul 31 05:22:32 PM PDT 24
Finished	Jul 31 05:24:02 PM PDT 24
Peak memory	255744 kb
Host	smart-5534e5a1-9b6a-4065-b417-aac1b94ef8d7
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27246 50031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.2724650031
Directory	/workspace/37.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/37.alert_handler_esc_intr_timeout.2017783671
Short name	T433
Test name
Test status
Simulation time	2004378773 ps
CPU time	29.14 seconds
Started	Jul 31 05:22:29 PM PDT 24
Finished	Jul 31 05:22:59 PM PDT 24
Peak memory	248324 kb
Host	smart-2f1bdf0d-f00e-4f8d-9e1b-f671b7e7bbd3
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20177 83671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.2017783671
Directory	/workspace/37.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/37.alert_handler_lpg.3975995059
Short name	T224
Test name
Test status
Simulation time	32046560155 ps
CPU time	1357.52 seconds
Started	Jul 31 05:22:33 PM PDT 24
Finished	Jul 31 05:45:10 PM PDT 24
Peak memory	288388 kb
Host	smart-ab415d0d-03f3-4b42-a1c7-5867016a3371
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3975995059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.3975995059
Directory	/workspace/37.alert_handler_lpg/latest

Test location	/workspace/coverage/default/37.alert_handler_lpg_stub_clk.3452226252
Short name	T637
Test name
Test status
Simulation time	29530204090 ps
CPU time	1958.34 seconds
Started	Jul 31 05:22:32 PM PDT 24
Finished	Jul 31 05:55:11 PM PDT 24
Peak memory	281060 kb
Host	smart-1472c2a5-e1f3-451b-9393-9f8a7b0da4de
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3452226252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.3452226252
Directory	/workspace/37.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/37.alert_handler_ping_timeout.3282769835
Short name	T315
Test name
Test status
Simulation time	4713187346 ps
CPU time	190.23 seconds
Started	Jul 31 05:22:28 PM PDT 24
Finished	Jul 31 05:25:39 PM PDT 24
Peak memory	248324 kb
Host	smart-5160a96a-f2e4-4d22-a0a7-51feeb7f43ef
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3282769835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.3282769835
Directory	/workspace/37.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/37.alert_handler_random_alerts.2784559203
Short name	T400
Test name
Test status
Simulation time	1474767010 ps
CPU time	30.37 seconds
Started	Jul 31 05:22:26 PM PDT 24
Finished	Jul 31 05:22:56 PM PDT 24
Peak memory	248296 kb
Host	smart-57e486a4-7800-47f8-a5c9-b4b4a4b1973f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27845 59203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.2784559203
Directory	/workspace/37.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/37.alert_handler_random_classes.3479275566
Short name	T642
Test name
Test status
Simulation time	1266801659 ps
CPU time	81.47 seconds
Started	Jul 31 05:22:24 PM PDT 24
Finished	Jul 31 05:23:46 PM PDT 24
Peak memory	256136 kb
Host	smart-e1344586-53dd-4633-8173-d80df6e93164
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34792 75566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.3479275566
Directory	/workspace/37.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/37.alert_handler_sig_int_fail.1489237325
Short name	T267
Test name
Test status
Simulation time	41568530 ps
CPU time	6.03 seconds
Started	Jul 31 05:22:24 PM PDT 24
Finished	Jul 31 05:22:30 PM PDT 24
Peak memory	247832 kb
Host	smart-4f9a6ddc-0ccd-42ea-8299-d6c8c82739a0
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14892 37325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.1489237325
Directory	/workspace/37.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/37.alert_handler_smoke.2207327197
Short name	T111
Test name
Test status
Simulation time	325216716 ps
CPU time	19.82 seconds
Started	Jul 31 05:22:33 PM PDT 24
Finished	Jul 31 05:22:53 PM PDT 24
Peak memory	248356 kb
Host	smart-98e318b6-25f5-44ae-a093-36ed84b73f41
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22073 27197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.2207327197
Directory	/workspace/37.alert_handler_smoke/latest

Test location	/workspace/coverage/default/37.alert_handler_stress_all.3803924772
Short name	T5
Test name
Test status
Simulation time	45760735675 ps
CPU time	2561.58 seconds
Started	Jul 31 05:22:34 PM PDT 24
Finished	Jul 31 06:05:16 PM PDT 24
Peak memory	289372 kb
Host	smart-79eb2aad-e211-45b8-9490-75b5680dab22
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803924772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha ndler_stress_all.3803924772
Directory	/workspace/37.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/38.alert_handler_entropy.2893804718
Short name	T399
Test name
Test status
Simulation time	16465295673 ps
CPU time	958.33 seconds
Started	Jul 31 05:22:24 PM PDT 24
Finished	Jul 31 05:38:23 PM PDT 24
Peak memory	288308 kb
Host	smart-dc36627a-e80b-454f-b7e2-5b6b84f47b6e
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2893804718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.2893804718
Directory	/workspace/38.alert_handler_entropy/latest

Test location	/workspace/coverage/default/38.alert_handler_esc_alert_accum.1364735369
Short name	T361
Test name
Test status
Simulation time	10554469396 ps
CPU time	293.52 seconds
Started	Jul 31 05:22:26 PM PDT 24
Finished	Jul 31 05:27:20 PM PDT 24
Peak memory	256304 kb
Host	smart-5028a9bc-560d-43dc-9cbe-89dd288fa968
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13647 35369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.1364735369
Directory	/workspace/38.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/38.alert_handler_esc_intr_timeout.1126874684
Short name	T557
Test name
Test status
Simulation time	2909426951 ps
CPU time	44.4 seconds
Started	Jul 31 05:22:32 PM PDT 24
Finished	Jul 31 05:23:17 PM PDT 24
Peak memory	256616 kb
Host	smart-02491662-4331-49e5-8305-fd49cc15a46a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11268 74684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.1126874684
Directory	/workspace/38.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/38.alert_handler_lpg.1256484428
Short name	T340
Test name
Test status
Simulation time	41928532845 ps
CPU time	653.79 seconds
Started	Jul 31 05:22:22 PM PDT 24
Finished	Jul 31 05:33:16 PM PDT 24
Peak memory	272912 kb
Host	smart-f63306ae-2ffe-41ad-a26e-61ad6cf7e1fd
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1256484428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.1256484428
Directory	/workspace/38.alert_handler_lpg/latest

Test location	/workspace/coverage/default/38.alert_handler_lpg_stub_clk.2466912650
Short name	T535
Test name
Test status
Simulation time	37323176543 ps
CPU time	2368.87 seconds
Started	Jul 31 05:22:21 PM PDT 24
Finished	Jul 31 06:01:50 PM PDT 24
Peak memory	281068 kb
Host	smart-4e1a6e63-430b-4a6b-8449-5d6bcb5f574b
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2466912650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.2466912650
Directory	/workspace/38.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/38.alert_handler_ping_timeout.700004844
Short name	T599
Test name
Test status
Simulation time	17887905176 ps
CPU time	393.45 seconds
Started	Jul 31 05:22:22 PM PDT 24
Finished	Jul 31 05:28:56 PM PDT 24
Peak memory	255860 kb
Host	smart-4b2c57d1-de77-4601-a6ea-5948eed3b402
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=700004844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.700004844
Directory	/workspace/38.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/38.alert_handler_random_alerts.731409694
Short name	T12
Test name
Test status
Simulation time	1351148141 ps
CPU time	38.12 seconds
Started	Jul 31 05:22:23 PM PDT 24
Finished	Jul 31 05:23:01 PM PDT 24
Peak memory	256472 kb
Host	smart-d8dc8dd6-ccde-4034-9bce-dc5b963c6c6b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73140 9694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.731409694
Directory	/workspace/38.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/38.alert_handler_random_classes.3979128806
Short name	T94
Test name
Test status
Simulation time	412759038 ps
CPU time	23.31 seconds
Started	Jul 31 05:22:29 PM PDT 24
Finished	Jul 31 05:22:52 PM PDT 24
Peak memory	247844 kb
Host	smart-8de6e4c5-f344-4b04-a3c1-3a625de238e4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39791 28806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.3979128806
Directory	/workspace/38.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/38.alert_handler_smoke.1923788214
Short name	T645
Test name
Test status
Simulation time	578187464 ps
CPU time	38.61 seconds
Started	Jul 31 05:22:23 PM PDT 24
Finished	Jul 31 05:23:01 PM PDT 24
Peak memory	248356 kb
Host	smart-cc136716-bf87-4082-b5fa-96778031ddac
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19237 88214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.1923788214
Directory	/workspace/38.alert_handler_smoke/latest

Test location	/workspace/coverage/default/39.alert_handler_entropy.4268039114
Short name	T386
Test name
Test status
Simulation time	11094397494 ps
CPU time	1093.04 seconds
Started	Jul 31 05:22:27 PM PDT 24
Finished	Jul 31 05:40:40 PM PDT 24
Peak memory	281944 kb
Host	smart-78bbb799-3722-47a6-b858-aaf27e6942fb
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4268039114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.4268039114
Directory	/workspace/39.alert_handler_entropy/latest

Test location	/workspace/coverage/default/39.alert_handler_esc_alert_accum.2661998813
Short name	T533
Test name
Test status
Simulation time	12030806762 ps
CPU time	174.3 seconds
Started	Jul 31 05:22:27 PM PDT 24
Finished	Jul 31 05:25:21 PM PDT 24
Peak memory	255876 kb
Host	smart-1de19780-9751-495d-b887-898d48bf7cec
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26619 98813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.2661998813
Directory	/workspace/39.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/39.alert_handler_esc_intr_timeout.3421856487
Short name	T488
Test name
Test status
Simulation time	2577169799 ps
CPU time	73.22 seconds
Started	Jul 31 05:22:28 PM PDT 24
Finished	Jul 31 05:23:42 PM PDT 24
Peak memory	248372 kb
Host	smart-f0941887-3f61-4ae0-bd6a-871ab98d3dc4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34218 56487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.3421856487
Directory	/workspace/39.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/39.alert_handler_lpg.3608896477
Short name	T325
Test name
Test status
Simulation time	15197115649 ps
CPU time	1054.27 seconds
Started	Jul 31 05:22:40 PM PDT 24
Finished	Jul 31 05:40:14 PM PDT 24
Peak memory	282344 kb
Host	smart-f17aba8c-f7c9-426c-ba82-6530f5fa1f7b
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3608896477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.3608896477
Directory	/workspace/39.alert_handler_lpg/latest

Test location	/workspace/coverage/default/39.alert_handler_lpg_stub_clk.505445739
Short name	T273
Test name
Test status
Simulation time	14353653055 ps
CPU time	867.6 seconds
Started	Jul 31 05:22:32 PM PDT 24
Finished	Jul 31 05:36:59 PM PDT 24
Peak memory	272924 kb
Host	smart-c347f8b2-703a-4769-9a74-c695bcad9cc4
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=505445739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.505445739
Directory	/workspace/39.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/39.alert_handler_ping_timeout.430465725
Short name	T300
Test name
Test status
Simulation time	7508598050 ps
CPU time	167.3 seconds
Started	Jul 31 05:22:32 PM PDT 24
Finished	Jul 31 05:25:20 PM PDT 24
Peak memory	248188 kb
Host	smart-6c8e0d8e-916a-4e2f-b6a4-6f33a1b52e33
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=430465725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.430465725
Directory	/workspace/39.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/39.alert_handler_random_alerts.1762169754
Short name	T184
Test name
Test status
Simulation time	442961693 ps
CPU time	19.66 seconds
Started	Jul 31 05:22:30 PM PDT 24
Finished	Jul 31 05:22:50 PM PDT 24
Peak memory	255792 kb
Host	smart-099744e1-0e50-464a-8fbc-14bd746b2004
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17621 69754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.1762169754
Directory	/workspace/39.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/39.alert_handler_random_classes.4158662117
Short name	T434
Test name
Test status
Simulation time	769803646 ps
CPU time	44.79 seconds
Started	Jul 31 05:22:27 PM PDT 24
Finished	Jul 31 05:23:11 PM PDT 24
Peak memory	256160 kb
Host	smart-e6cae520-782a-41c9-a3d5-7e6b067d823c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41586 62117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.4158662117
Directory	/workspace/39.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/39.alert_handler_sig_int_fail.2529632096
Short name	T519
Test name
Test status
Simulation time	483965603 ps
CPU time	32.02 seconds
Started	Jul 31 05:22:32 PM PDT 24
Finished	Jul 31 05:23:04 PM PDT 24
Peak memory	255708 kb
Host	smart-e390cd00-251f-415c-9b95-f662bf0ad183
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25296 32096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.2529632096
Directory	/workspace/39.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/39.alert_handler_smoke.3996967733
Short name	T510
Test name
Test status
Simulation time	2305129397 ps
CPU time	68.02 seconds
Started	Jul 31 05:22:31 PM PDT 24
Finished	Jul 31 05:23:39 PM PDT 24
Peak memory	248396 kb
Host	smart-98d6687c-8b32-4dd8-ab50-2b0c67e68b54
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39969 67733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.3996967733
Directory	/workspace/39.alert_handler_smoke/latest

Test location	/workspace/coverage/default/39.alert_handler_stress_all.1923628673
Short name	T81
Test name
Test status
Simulation time	13627449976 ps
CPU time	1389.26 seconds
Started	Jul 31 05:22:26 PM PDT 24
Finished	Jul 31 05:45:36 PM PDT 24
Peak memory	288944 kb
Host	smart-1a04faf5-e3a5-4feb-a654-3b06dd80cbae
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923628673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha ndler_stress_all.1923628673
Directory	/workspace/39.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/4.alert_handler_alert_accum_saturation.3502908991
Short name	T208
Test name
Test status
Simulation time	122042385 ps
CPU time	3.3 seconds
Started	Jul 31 05:21:20 PM PDT 24
Finished	Jul 31 05:21:24 PM PDT 24
Peak memory	248628 kb
Host	smart-434a91bc-41e0-49e5-89a6-f49c6a4553c9
User	root
Command	/workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=3502908991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.3502908991
Directory	/workspace/4.alert_handler_alert_accum_saturation/latest

Test location	/workspace/coverage/default/4.alert_handler_entropy.1895811928
Short name	T670
Test name
Test status
Simulation time	92051571565 ps
CPU time	1646.88 seconds
Started	Jul 31 05:21:02 PM PDT 24
Finished	Jul 31 05:48:30 PM PDT 24
Peak memory	272952 kb
Host	smart-bfdc3d92-5441-435f-af55-de3d5bb2a6fd
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1895811928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.1895811928
Directory	/workspace/4.alert_handler_entropy/latest

Test location	/workspace/coverage/default/4.alert_handler_entropy_stress.1074326120
Short name	T178
Test name
Test status
Simulation time	1407220683 ps
CPU time	8.6 seconds
Started	Jul 31 05:21:15 PM PDT 24
Finished	Jul 31 05:21:23 PM PDT 24
Peak memory	248292 kb
Host	smart-423a1d3c-458a-4c97-b637-6ded2460b01d
User	root
Command	/workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1074326120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.1074326120
Directory	/workspace/4.alert_handler_entropy_stress/latest

Test location	/workspace/coverage/default/4.alert_handler_esc_alert_accum.3839274159
Short name	T661
Test name
Test status
Simulation time	44337941364 ps
CPU time	242.9 seconds
Started	Jul 31 05:20:55 PM PDT 24
Finished	Jul 31 05:24:58 PM PDT 24
Peak memory	256608 kb
Host	smart-bf2e0bdd-bb07-4d80-8910-cb2e4f17e94a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38392 74159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.3839274159
Directory	/workspace/4.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/4.alert_handler_esc_intr_timeout.949155779
Short name	T363
Test name
Test status
Simulation time	1797791740 ps
CPU time	48.16 seconds
Started	Jul 31 05:20:53 PM PDT 24
Finished	Jul 31 05:21:41 PM PDT 24
Peak memory	255724 kb
Host	smart-c1cad58a-3dae-4d39-b228-4a9426c90ba0
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94915 5779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.949155779
Directory	/workspace/4.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/4.alert_handler_lpg.1672341700
Short name	T655
Test name
Test status
Simulation time	15492586466 ps
CPU time	1340.42 seconds
Started	Jul 31 05:21:06 PM PDT 24
Finished	Jul 31 05:43:27 PM PDT 24
Peak memory	285044 kb
Host	smart-1a9a193e-1a1b-46c4-9664-b3f0aff5ffae
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1672341700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.1672341700
Directory	/workspace/4.alert_handler_lpg/latest

Test location	/workspace/coverage/default/4.alert_handler_lpg_stub_clk.371104976
Short name	T605
Test name
Test status
Simulation time	103045681917 ps
CPU time	3073.02 seconds
Started	Jul 31 05:20:50 PM PDT 24
Finished	Jul 31 06:12:03 PM PDT 24
Peak memory	280564 kb
Host	smart-839cd0b1-2925-406f-8a83-44e5868d8f3a
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=371104976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.371104976
Directory	/workspace/4.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/4.alert_handler_ping_timeout.2386521188
Short name	T18
Test name
Test status
Simulation time	10863964159 ps
CPU time	472.41 seconds
Started	Jul 31 05:21:06 PM PDT 24
Finished	Jul 31 05:28:58 PM PDT 24
Peak memory	247044 kb
Host	smart-091737ed-1a90-4e14-a69b-9b509397b783
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2386521188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.2386521188
Directory	/workspace/4.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/4.alert_handler_random_alerts.1766080959
Short name	T644
Test name
Test status
Simulation time	868489801 ps
CPU time	5.72 seconds
Started	Jul 31 05:21:10 PM PDT 24
Finished	Jul 31 05:21:15 PM PDT 24
Peak memory	240064 kb
Host	smart-40b745f5-5ab2-4e1b-b184-74eb40628486
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17660 80959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.1766080959
Directory	/workspace/4.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/4.alert_handler_random_classes.2877774209
Short name	T703
Test name
Test status
Simulation time	1120549993 ps
CPU time	25.89 seconds
Started	Jul 31 05:21:14 PM PDT 24
Finished	Jul 31 05:21:40 PM PDT 24
Peak memory	248360 kb
Host	smart-a03fa308-0f2e-48f7-ad14-ce1b09d7f931
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28777 74209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.2877774209
Directory	/workspace/4.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/4.alert_handler_sec_cm.128908780
Short name	T9
Test name
Test status
Simulation time	359240850 ps
CPU time	20.86 seconds
Started	Jul 31 05:21:04 PM PDT 24
Finished	Jul 31 05:21:25 PM PDT 24
Peak memory	270312 kb
Host	smart-5d8b323d-bcec-4835-a1fe-332457cd5046
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=128908780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.128908780
Directory	/workspace/4.alert_handler_sec_cm/latest

Test location	/workspace/coverage/default/4.alert_handler_sig_int_fail.3078543945
Short name	T56
Test name
Test status
Simulation time	2511144561 ps
CPU time	46.15 seconds
Started	Jul 31 05:21:09 PM PDT 24
Finished	Jul 31 05:21:55 PM PDT 24
Peak memory	248084 kb
Host	smart-28412143-aa2f-499f-b8aa-3dfe35f15313
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30785 43945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.3078543945
Directory	/workspace/4.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/4.alert_handler_smoke.3903911450
Short name	T451
Test name
Test status
Simulation time	129775284 ps
CPU time	8.95 seconds
Started	Jul 31 05:20:47 PM PDT 24
Finished	Jul 31 05:20:56 PM PDT 24
Peak memory	248420 kb
Host	smart-1f0c2989-5778-4069-b8c4-7985a9d6151e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39039 11450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.3903911450
Directory	/workspace/4.alert_handler_smoke/latest

Test location	/workspace/coverage/default/4.alert_handler_stress_all.618110149
Short name	T268
Test name
Test status
Simulation time	190711896744 ps
CPU time	2868.47 seconds
Started	Jul 31 05:21:10 PM PDT 24
Finished	Jul 31 06:08:59 PM PDT 24
Peak memory	288780 kb
Host	smart-a6299549-4fbb-4585-8e93-8800a0595b64
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618110149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_hand ler_stress_all.618110149
Directory	/workspace/4.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/40.alert_handler_esc_alert_accum.1371489519
Short name	T463
Test name
Test status
Simulation time	1482727835 ps
CPU time	83.6 seconds
Started	Jul 31 05:22:33 PM PDT 24
Finished	Jul 31 05:23:57 PM PDT 24
Peak memory	255896 kb
Host	smart-617edbed-2719-41e2-8f6a-7b7c8ea92df9
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13714 89519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.1371489519
Directory	/workspace/40.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/40.alert_handler_esc_intr_timeout.1040519456
Short name	T630
Test name
Test status
Simulation time	231460884 ps
CPU time	18.27 seconds
Started	Jul 31 05:22:35 PM PDT 24
Finished	Jul 31 05:22:54 PM PDT 24
Peak memory	255388 kb
Host	smart-5ac359e5-4abb-46ae-9b95-ab32a1e15e47
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10405 19456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.1040519456
Directory	/workspace/40.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/40.alert_handler_lpg.755005860
Short name	T336
Test name
Test status
Simulation time	240818227512 ps
CPU time	1716.02 seconds
Started	Jul 31 05:22:32 PM PDT 24
Finished	Jul 31 05:51:09 PM PDT 24
Peak memory	272200 kb
Host	smart-40c60177-ea20-40d4-8780-79f8c896f78c
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=755005860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.755005860
Directory	/workspace/40.alert_handler_lpg/latest

Test location	/workspace/coverage/default/40.alert_handler_lpg_stub_clk.3263842448
Short name	T629
Test name
Test status
Simulation time	15649252967 ps
CPU time	1443.79 seconds
Started	Jul 31 05:22:32 PM PDT 24
Finished	Jul 31 05:46:36 PM PDT 24
Peak memory	289084 kb
Host	smart-f8169c06-c064-41da-a74c-6a0ddcb15103
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3263842448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.3263842448
Directory	/workspace/40.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/40.alert_handler_ping_timeout.1326899692
Short name	T323
Test name
Test status
Simulation time	36651729647 ps
CPU time	167.22 seconds
Started	Jul 31 05:22:29 PM PDT 24
Finished	Jul 31 05:25:16 PM PDT 24
Peak memory	247476 kb
Host	smart-4b38fa02-b1d6-4eef-8d90-6e9f466c28c5
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1326899692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.1326899692
Directory	/workspace/40.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/40.alert_handler_random_alerts.969401469
Short name	T455
Test name
Test status
Simulation time	294827287 ps
CPU time	20.04 seconds
Started	Jul 31 05:22:28 PM PDT 24
Finished	Jul 31 05:22:48 PM PDT 24
Peak memory	248300 kb
Host	smart-ab6df232-720f-4a61-b4e0-9664b79c32df
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96940 1469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.969401469
Directory	/workspace/40.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/40.alert_handler_random_classes.1054315209
Short name	T598
Test name
Test status
Simulation time	15809522996 ps
CPU time	46.89 seconds
Started	Jul 31 05:22:33 PM PDT 24
Finished	Jul 31 05:23:20 PM PDT 24
Peak memory	255488 kb
Host	smart-8187cd9d-999c-4082-b3a7-d621b9699d0c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10543 15209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.1054315209
Directory	/workspace/40.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/40.alert_handler_sig_int_fail.3173928479
Short name	T496
Test name
Test status
Simulation time	960438523 ps
CPU time	24.24 seconds
Started	Jul 31 05:22:27 PM PDT 24
Finished	Jul 31 05:22:51 PM PDT 24
Peak memory	248700 kb
Host	smart-a07d3d04-033a-4343-a4e2-f526bdac9740
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31739 28479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.3173928479
Directory	/workspace/40.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/40.alert_handler_smoke.2243462427
Short name	T422
Test name
Test status
Simulation time	1827591162 ps
CPU time	32.1 seconds
Started	Jul 31 05:22:34 PM PDT 24
Finished	Jul 31 05:23:06 PM PDT 24
Peak memory	256444 kb
Host	smart-b36421a7-fc3b-428d-8ca9-cf36f2bbd408
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22434 62427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.2243462427
Directory	/workspace/40.alert_handler_smoke/latest

Test location	/workspace/coverage/default/40.alert_handler_stress_all.2703013370
Short name	T459
Test name
Test status
Simulation time	117066376644 ps
CPU time	1388.17 seconds
Started	Jul 31 05:22:31 PM PDT 24
Finished	Jul 31 05:45:39 PM PDT 24
Peak memory	272468 kb
Host	smart-b1918646-a61c-4d0f-9b33-5c21ac01946f
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703013370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha ndler_stress_all.2703013370
Directory	/workspace/40.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/41.alert_handler_entropy.3499459765
Short name	T597
Test name
Test status
Simulation time	20874281913 ps
CPU time	548.78 seconds
Started	Jul 31 05:22:36 PM PDT 24
Finished	Jul 31 05:31:45 PM PDT 24
Peak memory	272376 kb
Host	smart-faef570f-e9ec-4dfd-aff8-6d3d51c4a5d5
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3499459765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.3499459765
Directory	/workspace/41.alert_handler_entropy/latest

Test location	/workspace/coverage/default/41.alert_handler_esc_alert_accum.145357484
Short name	T558
Test name
Test status
Simulation time	5149018807 ps
CPU time	274.77 seconds
Started	Jul 31 05:22:40 PM PDT 24
Finished	Jul 31 05:27:15 PM PDT 24
Peak memory	256488 kb
Host	smart-0407d96f-2526-4263-a46a-7d5fd9c931e5
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14535 7484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.145357484
Directory	/workspace/41.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/41.alert_handler_esc_intr_timeout.1926479840
Short name	T380
Test name
Test status
Simulation time	429753923 ps
CPU time	40.27 seconds
Started	Jul 31 05:22:31 PM PDT 24
Finished	Jul 31 05:23:12 PM PDT 24
Peak memory	248252 kb
Host	smart-5cabb639-6e94-403e-b84d-9f83b7a88ba9
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19264 79840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.1926479840
Directory	/workspace/41.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/41.alert_handler_lpg.2212716340
Short name	T332
Test name
Test status
Simulation time	183823286217 ps
CPU time	2643.8 seconds
Started	Jul 31 05:22:38 PM PDT 24
Finished	Jul 31 06:06:43 PM PDT 24
Peak memory	288700 kb
Host	smart-f768f6ae-d3d0-4967-a96f-3459e6210560
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2212716340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.2212716340
Directory	/workspace/41.alert_handler_lpg/latest

Test location	/workspace/coverage/default/41.alert_handler_lpg_stub_clk.1595507222
Short name	T275
Test name
Test status
Simulation time	12099604754 ps
CPU time	1251.78 seconds
Started	Jul 31 05:22:36 PM PDT 24
Finished	Jul 31 05:43:28 PM PDT 24
Peak memory	272844 kb
Host	smart-afc24397-c4a8-4a8f-8da8-b6116c640225
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1595507222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.1595507222
Directory	/workspace/41.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/41.alert_handler_ping_timeout.1984450471
Short name	T64
Test name
Test status
Simulation time	11137129744 ps
CPU time	464.38 seconds
Started	Jul 31 05:22:35 PM PDT 24
Finished	Jul 31 05:30:20 PM PDT 24
Peak memory	248364 kb
Host	smart-327c4e24-259b-460e-a6ee-8adf2163664a
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1984450471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.1984450471
Directory	/workspace/41.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/41.alert_handler_random_alerts.271314103
Short name	T586
Test name
Test status
Simulation time	121370104 ps
CPU time	13.79 seconds
Started	Jul 31 05:22:30 PM PDT 24
Finished	Jul 31 05:22:44 PM PDT 24
Peak memory	255524 kb
Host	smart-743b2068-d555-463d-9b02-368e7b65d77a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27131 4103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.271314103
Directory	/workspace/41.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/41.alert_handler_random_classes.2776968253
Short name	T515
Test name
Test status
Simulation time	989435097 ps
CPU time	18.92 seconds
Started	Jul 31 05:22:42 PM PDT 24
Finished	Jul 31 05:23:01 PM PDT 24
Peak memory	255780 kb
Host	smart-019b3195-ae4e-4133-aac2-431f8b512214
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27769 68253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.2776968253
Directory	/workspace/41.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/41.alert_handler_sig_int_fail.4089877536
Short name	T482
Test name
Test status
Simulation time	380922350 ps
CPU time	7.83 seconds
Started	Jul 31 05:22:36 PM PDT 24
Finished	Jul 31 05:22:44 PM PDT 24
Peak memory	248700 kb
Host	smart-7d9ec583-a291-4747-9636-55e08434bb09
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40898 77536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.4089877536
Directory	/workspace/41.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/41.alert_handler_smoke.1628023798
Short name	T638
Test name
Test status
Simulation time	1130097637 ps
CPU time	65.85 seconds
Started	Jul 31 05:22:33 PM PDT 24
Finished	Jul 31 05:23:39 PM PDT 24
Peak memory	256508 kb
Host	smart-2632081a-2814-46ca-a705-625b435adf73
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16280 23798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.1628023798
Directory	/workspace/41.alert_handler_smoke/latest

Test location	/workspace/coverage/default/42.alert_handler_entropy.3579411157
Short name	T277
Test name
Test status
Simulation time	20859679798 ps
CPU time	1715.09 seconds
Started	Jul 31 05:22:36 PM PDT 24
Finished	Jul 31 05:51:11 PM PDT 24
Peak memory	289260 kb
Host	smart-3245333b-7e48-458d-bff6-bc63cd04ddf2
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3579411157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.3579411157
Directory	/workspace/42.alert_handler_entropy/latest

Test location	/workspace/coverage/default/42.alert_handler_esc_alert_accum.365329554
Short name	T362
Test name
Test status
Simulation time	332685188 ps
CPU time	21.9 seconds
Started	Jul 31 05:22:34 PM PDT 24
Finished	Jul 31 05:22:56 PM PDT 24
Peak memory	254536 kb
Host	smart-a4ca58c5-a1a4-4271-b7b8-597f777f1d29
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36532 9554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.365329554
Directory	/workspace/42.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/42.alert_handler_esc_intr_timeout.2595449271
Short name	T713
Test name
Test status
Simulation time	692286954 ps
CPU time	41.57 seconds
Started	Jul 31 05:22:43 PM PDT 24
Finished	Jul 31 05:23:24 PM PDT 24
Peak memory	248368 kb
Host	smart-54bfc635-a03b-46d8-ac7b-b6abf1757a99
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25954 49271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.2595449271
Directory	/workspace/42.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/42.alert_handler_lpg.12266059
Short name	T337
Test name
Test status
Simulation time	168344682895 ps
CPU time	2616.45 seconds
Started	Jul 31 05:22:41 PM PDT 24
Finished	Jul 31 06:06:17 PM PDT 24
Peak memory	288416 kb
Host	smart-b741358d-b9bf-4fc2-813f-e1751202b4e5
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=12266059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.12266059
Directory	/workspace/42.alert_handler_lpg/latest

Test location	/workspace/coverage/default/42.alert_handler_lpg_stub_clk.1416480407
Short name	T691
Test name
Test status
Simulation time	32507626768 ps
CPU time	1703.11 seconds
Started	Jul 31 05:22:45 PM PDT 24
Finished	Jul 31 05:51:09 PM PDT 24
Peak memory	272756 kb
Host	smart-1fd34cbe-0a30-4c1d-bc46-8a079429dd35
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1416480407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.1416480407
Directory	/workspace/42.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/42.alert_handler_ping_timeout.1734630300
Short name	T573
Test name
Test status
Simulation time	13015142038 ps
CPU time	155.32 seconds
Started	Jul 31 05:22:43 PM PDT 24
Finished	Jul 31 05:25:18 PM PDT 24
Peak memory	248360 kb
Host	smart-410d3005-9285-4eef-a93d-c1d753584db0
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1734630300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.1734630300
Directory	/workspace/42.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/42.alert_handler_random_alerts.2679912334
Short name	T42
Test name
Test status
Simulation time	250364846 ps
CPU time	22.38 seconds
Started	Jul 31 05:22:35 PM PDT 24
Finished	Jul 31 05:22:57 PM PDT 24
Peak memory	255760 kb
Host	smart-53e16ab8-812f-4444-8178-87a3f1ba1a8d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26799 12334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.2679912334
Directory	/workspace/42.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/42.alert_handler_random_classes.3658787329
Short name	T562
Test name
Test status
Simulation time	191642858 ps
CPU time	5.9 seconds
Started	Jul 31 05:22:38 PM PDT 24
Finished	Jul 31 05:22:44 PM PDT 24
Peak memory	240096 kb
Host	smart-dc76eecc-d751-4779-953c-c035bab53771
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36587 87329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.3658787329
Directory	/workspace/42.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/42.alert_handler_sig_int_fail.2469825206
Short name	T700
Test name
Test status
Simulation time	2442749616 ps
CPU time	46.29 seconds
Started	Jul 31 05:22:33 PM PDT 24
Finished	Jul 31 05:23:19 PM PDT 24
Peak memory	256120 kb
Host	smart-f77d835a-96cd-4a20-8e9d-ee6441c3f96c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24698 25206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.2469825206
Directory	/workspace/42.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/42.alert_handler_smoke.2067070450
Short name	T381
Test name
Test status
Simulation time	387522056 ps
CPU time	31.19 seconds
Started	Jul 31 05:22:33 PM PDT 24
Finished	Jul 31 05:23:04 PM PDT 24
Peak memory	256532 kb
Host	smart-a94b0957-a93e-4eb2-9fb5-ffb45533d012
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20670 70450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.2067070450
Directory	/workspace/42.alert_handler_smoke/latest

Test location	/workspace/coverage/default/43.alert_handler_entropy.1598458727
Short name	T57
Test name
Test status
Simulation time	186402199508 ps
CPU time	2524.62 seconds
Started	Jul 31 05:22:39 PM PDT 24
Finished	Jul 31 06:04:44 PM PDT 24
Peak memory	288672 kb
Host	smart-57187326-8352-46fa-a0b4-f407845dc8b8
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1598458727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.1598458727
Directory	/workspace/43.alert_handler_entropy/latest

Test location	/workspace/coverage/default/43.alert_handler_esc_alert_accum.184762978
Short name	T634
Test name
Test status
Simulation time	12608608152 ps
CPU time	99.12 seconds
Started	Jul 31 05:22:39 PM PDT 24
Finished	Jul 31 05:24:18 PM PDT 24
Peak memory	249508 kb
Host	smart-61611dbf-f9c8-42bb-b5b8-eb654ae3ce60
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18476 2978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.184762978
Directory	/workspace/43.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/43.alert_handler_esc_intr_timeout.489591718
Short name	T465
Test name
Test status
Simulation time	529259639 ps
CPU time	36.96 seconds
Started	Jul 31 05:22:32 PM PDT 24
Finished	Jul 31 05:23:09 PM PDT 24
Peak memory	255864 kb
Host	smart-abb7a2c3-ac85-43a4-b03c-2873d368f1c2
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48959 1718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.489591718
Directory	/workspace/43.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/43.alert_handler_lpg.2161155345
Short name	T80
Test name
Test status
Simulation time	42252562795 ps
CPU time	2612.04 seconds
Started	Jul 31 05:22:42 PM PDT 24
Finished	Jul 31 06:06:14 PM PDT 24
Peak memory	289328 kb
Host	smart-d25511f7-f7e5-4263-a455-6e0c5fd84e7d
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2161155345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.2161155345
Directory	/workspace/43.alert_handler_lpg/latest

Test location	/workspace/coverage/default/43.alert_handler_lpg_stub_clk.3506828302
Short name	T272
Test name
Test status
Simulation time	11587729218 ps
CPU time	1123.61 seconds
Started	Jul 31 05:22:41 PM PDT 24
Finished	Jul 31 05:41:25 PM PDT 24
Peak memory	288464 kb
Host	smart-3370bfd2-795a-42c3-8d6b-17a73cccb8eb
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3506828302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.3506828302
Directory	/workspace/43.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/43.alert_handler_ping_timeout.317633477
Short name	T324
Test name
Test status
Simulation time	62762595354 ps
CPU time	358.56 seconds
Started	Jul 31 05:22:41 PM PDT 24
Finished	Jul 31 05:28:40 PM PDT 24
Peak memory	248400 kb
Host	smart-41dffeaf-af88-486d-9f8d-9fe5df24d50a
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=317633477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.317633477
Directory	/workspace/43.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/43.alert_handler_random_alerts.997927031
Short name	T701
Test name
Test status
Simulation time	842989445 ps
CPU time	57.63 seconds
Started	Jul 31 05:22:33 PM PDT 24
Finished	Jul 31 05:23:30 PM PDT 24
Peak memory	248268 kb
Host	smart-49044867-4ea7-4811-8828-f30071cc37cb
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99792 7031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.997927031
Directory	/workspace/43.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/43.alert_handler_random_classes.3458423419
Short name	T437
Test name
Test status
Simulation time	127870676 ps
CPU time	14.47 seconds
Started	Jul 31 05:22:41 PM PDT 24
Finished	Jul 31 05:22:55 PM PDT 24
Peak memory	256480 kb
Host	smart-8e360753-80d3-44a0-addd-0685e5668af7
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34584 23419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.3458423419
Directory	/workspace/43.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/43.alert_handler_sig_int_fail.4167800283
Short name	T257
Test name
Test status
Simulation time	3158946308 ps
CPU time	51.13 seconds
Started	Jul 31 05:22:45 PM PDT 24
Finished	Jul 31 05:23:37 PM PDT 24
Peak memory	248768 kb
Host	smart-d0475bf9-f311-41eb-a821-7ac118a5de20
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41678 00283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.4167800283
Directory	/workspace/43.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/43.alert_handler_smoke.1423803167
Short name	T623
Test name
Test status
Simulation time	3308608221 ps
CPU time	50.66 seconds
Started	Jul 31 05:22:35 PM PDT 24
Finished	Jul 31 05:23:25 PM PDT 24
Peak memory	256576 kb
Host	smart-517ca32a-3051-42a4-b056-474712570e9d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14238 03167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.1423803167
Directory	/workspace/43.alert_handler_smoke/latest

Test location	/workspace/coverage/default/43.alert_handler_stress_all.1189646640
Short name	T677
Test name
Test status
Simulation time	45630565887 ps
CPU time	2999.67 seconds
Started	Jul 31 05:22:42 PM PDT 24
Finished	Jul 31 06:12:42 PM PDT 24
Peak memory	299632 kb
Host	smart-0b55cd00-a3f4-42bd-89ac-46242c674ffe
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189646640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha ndler_stress_all.1189646640
Directory	/workspace/43.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/44.alert_handler_entropy.3524799988
Short name	T471
Test name
Test status
Simulation time	56077476077 ps
CPU time	1179 seconds
Started	Jul 31 05:22:39 PM PDT 24
Finished	Jul 31 05:42:18 PM PDT 24
Peak memory	288276 kb
Host	smart-ee9b2ff4-2c13-4951-9663-fdfc96e7d6dc
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3524799988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.3524799988
Directory	/workspace/44.alert_handler_entropy/latest

Test location	/workspace/coverage/default/44.alert_handler_esc_alert_accum.3779989194
Short name	T412
Test name
Test status
Simulation time	2552354317 ps
CPU time	93.07 seconds
Started	Jul 31 05:22:41 PM PDT 24
Finished	Jul 31 05:24:14 PM PDT 24
Peak memory	256232 kb
Host	smart-b3bf3dfb-f868-4e7f-8ecf-76b7ce4fb0b9
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37799 89194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.3779989194
Directory	/workspace/44.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/44.alert_handler_esc_intr_timeout.2294123356
Short name	T650
Test name
Test status
Simulation time	603863493 ps
CPU time	40.95 seconds
Started	Jul 31 05:22:39 PM PDT 24
Finished	Jul 31 05:23:20 PM PDT 24
Peak memory	256576 kb
Host	smart-b7ca3958-7a94-40b2-93e7-263bf6ccef04
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22941 23356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.2294123356
Directory	/workspace/44.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/44.alert_handler_lpg.4017737468
Short name	T338
Test name
Test status
Simulation time	24892154447 ps
CPU time	1091.34 seconds
Started	Jul 31 05:22:39 PM PDT 24
Finished	Jul 31 05:40:50 PM PDT 24
Peak memory	281456 kb
Host	smart-eff802a6-e25f-4f64-94ca-d4439681aed2
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4017737468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.4017737468
Directory	/workspace/44.alert_handler_lpg/latest

Test location	/workspace/coverage/default/44.alert_handler_lpg_stub_clk.1183677000
Short name	T276
Test name
Test status
Simulation time	19611987423 ps
CPU time	1615.55 seconds
Started	Jul 31 05:22:42 PM PDT 24
Finished	Jul 31 05:49:38 PM PDT 24
Peak memory	288964 kb
Host	smart-beacc15e-7d3a-4737-b7f6-81b856793994
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1183677000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.1183677000
Directory	/workspace/44.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/44.alert_handler_ping_timeout.159995557
Short name	T321
Test name
Test status
Simulation time	8981154225 ps
CPU time	184.33 seconds
Started	Jul 31 05:22:39 PM PDT 24
Finished	Jul 31 05:25:44 PM PDT 24
Peak memory	255188 kb
Host	smart-043280c3-ff0d-47a1-962a-c5f848c8bde7
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=159995557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.159995557
Directory	/workspace/44.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/44.alert_handler_random_alerts.2624541121
Short name	T468
Test name
Test status
Simulation time	1412457309 ps
CPU time	54.26 seconds
Started	Jul 31 05:22:42 PM PDT 24
Finished	Jul 31 05:23:36 PM PDT 24
Peak memory	255848 kb
Host	smart-0b56474a-93c1-4d85-a2f0-0b3a0825851c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26245 41121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.2624541121
Directory	/workspace/44.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/44.alert_handler_random_classes.1447686399
Short name	T374
Test name
Test status
Simulation time	1142521089 ps
CPU time	14.9 seconds
Started	Jul 31 05:22:36 PM PDT 24
Finished	Jul 31 05:22:51 PM PDT 24
Peak memory	247980 kb
Host	smart-4bc15bd2-369a-4401-9f7b-ec716422c6c6
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14476 86399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.1447686399
Directory	/workspace/44.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/44.alert_handler_sig_int_fail.395293394
Short name	T46
Test name
Test status
Simulation time	1977232399 ps
CPU time	39.22 seconds
Started	Jul 31 05:22:43 PM PDT 24
Finished	Jul 31 05:23:22 PM PDT 24
Peak memory	255908 kb
Host	smart-db52e77f-54ce-46bd-a0ff-e922d303ab57
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39529 3394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.395293394
Directory	/workspace/44.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/44.alert_handler_smoke.2254524746
Short name	T244
Test name
Test status
Simulation time	221408227 ps
CPU time	19.93 seconds
Started	Jul 31 05:22:38 PM PDT 24
Finished	Jul 31 05:22:58 PM PDT 24
Peak memory	255596 kb
Host	smart-27088d03-7dab-4ef1-92e1-bc74b8dab03b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22545 24746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.2254524746
Directory	/workspace/44.alert_handler_smoke/latest

Test location	/workspace/coverage/default/44.alert_handler_stress_all.57809023
Short name	T96
Test name
Test status
Simulation time	107108013934 ps
CPU time	3032.48 seconds
Started	Jul 31 05:22:38 PM PDT 24
Finished	Jul 31 06:13:11 PM PDT 24
Peak memory	289248 kb
Host	smart-13508579-9174-4884-8399-fc562e8935ae
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57809023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_hand ler_stress_all.57809023
Directory	/workspace/44.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.2166150475
Short name	T54
Test name
Test status
Simulation time	53058427259 ps
CPU time	6297.7 seconds
Started	Jul 31 05:22:42 PM PDT 24
Finished	Jul 31 07:07:40 PM PDT 24
Peak memory	355044 kb
Host	smart-73c57002-742f-416d-8ef2-a4d33a9214a8
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166150475 -assert nopostproc +UVM_TESTNAME=aler t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.2166150475
Directory	/workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/45.alert_handler_entropy.410153017
Short name	T695
Test name
Test status
Simulation time	15032192885 ps
CPU time	738.79 seconds
Started	Jul 31 05:22:44 PM PDT 24
Finished	Jul 31 05:35:03 PM PDT 24
Peak memory	271376 kb
Host	smart-50cfc7e0-0db6-4304-9484-7e1f628402d6
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=410153017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.410153017
Directory	/workspace/45.alert_handler_entropy/latest

Test location	/workspace/coverage/default/45.alert_handler_esc_alert_accum.2174101284
Short name	T527
Test name
Test status
Simulation time	2095937454 ps
CPU time	186.17 seconds
Started	Jul 31 05:22:47 PM PDT 24
Finished	Jul 31 05:25:53 PM PDT 24
Peak memory	256476 kb
Host	smart-39ad84a4-a4d9-4231-bcbf-f607e8b5cc5d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21741 01284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.2174101284
Directory	/workspace/45.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/45.alert_handler_esc_intr_timeout.3645063457
Short name	T509
Test name
Test status
Simulation time	648700436 ps
CPU time	6.5 seconds
Started	Jul 31 05:22:44 PM PDT 24
Finished	Jul 31 05:22:51 PM PDT 24
Peak memory	247696 kb
Host	smart-4cc8912a-d1cf-4e32-89da-058482228146
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36450 63457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.3645063457
Directory	/workspace/45.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/45.alert_handler_lpg.808826543
Short name	T298
Test name
Test status
Simulation time	44435452183 ps
CPU time	1259.89 seconds
Started	Jul 31 05:22:44 PM PDT 24
Finished	Jul 31 05:43:44 PM PDT 24
Peak memory	288716 kb
Host	smart-48a00d8d-1a26-49a3-9b76-ea18ebcae326
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=808826543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.808826543
Directory	/workspace/45.alert_handler_lpg/latest

Test location	/workspace/coverage/default/45.alert_handler_lpg_stub_clk.3990260020
Short name	T431
Test name
Test status
Simulation time	42356893036 ps
CPU time	1399.95 seconds
Started	Jul 31 05:22:46 PM PDT 24
Finished	Jul 31 05:46:06 PM PDT 24
Peak memory	281088 kb
Host	smart-5f83575d-fadb-4495-9958-23eba10c0ad8
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3990260020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.3990260020
Directory	/workspace/45.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/45.alert_handler_ping_timeout.1236147972
Short name	T627
Test name
Test status
Simulation time	3007532894 ps
CPU time	64.22 seconds
Started	Jul 31 05:22:45 PM PDT 24
Finished	Jul 31 05:23:50 PM PDT 24
Peak memory	253756 kb
Host	smart-aa096bac-26c2-437d-a81d-890165673b2f
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1236147972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.1236147972
Directory	/workspace/45.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/45.alert_handler_random_alerts.2212630553
Short name	T408
Test name
Test status
Simulation time	28537429 ps
CPU time	3.81 seconds
Started	Jul 31 05:22:45 PM PDT 24
Finished	Jul 31 05:22:49 PM PDT 24
Peak memory	248272 kb
Host	smart-ae81e02c-787a-45fc-8798-ef6076593346
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22126 30553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.2212630553
Directory	/workspace/45.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/45.alert_handler_random_classes.1664783423
Short name	T444
Test name
Test status
Simulation time	460088054 ps
CPU time	27.79 seconds
Started	Jul 31 05:22:44 PM PDT 24
Finished	Jul 31 05:23:12 PM PDT 24
Peak memory	255736 kb
Host	smart-fa0fedab-4462-434d-9570-3e0d0d0a3652
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16647 83423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.1664783423
Directory	/workspace/45.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/45.alert_handler_sig_int_fail.2852908179
Short name	T436
Test name
Test status
Simulation time	421658795 ps
CPU time	6.51 seconds
Started	Jul 31 05:22:45 PM PDT 24
Finished	Jul 31 05:22:51 PM PDT 24
Peak memory	252308 kb
Host	smart-fcdd0cee-d33c-4335-afd7-13b8904626e4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28529 08179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.2852908179
Directory	/workspace/45.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/45.alert_handler_smoke.3216787494
Short name	T659
Test name
Test status
Simulation time	427539905 ps
CPU time	27.76 seconds
Started	Jul 31 05:22:43 PM PDT 24
Finished	Jul 31 05:23:11 PM PDT 24
Peak memory	256352 kb
Host	smart-1453b528-dff1-47a5-a662-84855f29b73a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32167 87494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.3216787494
Directory	/workspace/45.alert_handler_smoke/latest

Test location	/workspace/coverage/default/45.alert_handler_stress_all.2799984684
Short name	T441
Test name
Test status
Simulation time	29516026287 ps
CPU time	1312.33 seconds
Started	Jul 31 05:22:44 PM PDT 24
Finished	Jul 31 05:44:36 PM PDT 24
Peak memory	289344 kb
Host	smart-ee60ce34-bb03-4ff9-904d-572aebde8a85
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799984684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha ndler_stress_all.2799984684
Directory	/workspace/45.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.542587849
Short name	T185
Test name
Test status
Simulation time	22330662598 ps
CPU time	2294.85 seconds
Started	Jul 31 05:22:43 PM PDT 24
Finished	Jul 31 06:00:58 PM PDT 24
Peak memory	303936 kb
Host	smart-84994dd5-10f0-47e8-9bc6-811962a62782
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542587849 -assert nopostproc +UVM_TESTNAME=alert _handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.542587849
Directory	/workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/46.alert_handler_entropy.2012694497
Short name	T652
Test name
Test status
Simulation time	56181582435 ps
CPU time	1376.44 seconds
Started	Jul 31 05:22:50 PM PDT 24
Finished	Jul 31 05:45:47 PM PDT 24
Peak memory	272392 kb
Host	smart-80c28c72-ba5e-4edf-9df2-421ff4a688be
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2012694497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.2012694497
Directory	/workspace/46.alert_handler_entropy/latest

Test location	/workspace/coverage/default/46.alert_handler_esc_alert_accum.2860663253
Short name	T576
Test name
Test status
Simulation time	6187823768 ps
CPU time	85.77 seconds
Started	Jul 31 05:22:50 PM PDT 24
Finished	Jul 31 05:24:16 PM PDT 24
Peak memory	256144 kb
Host	smart-7373985a-f933-4791-8ac7-a0a6ac3f1aa6
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28606 63253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.2860663253
Directory	/workspace/46.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/46.alert_handler_esc_intr_timeout.1270587797
Short name	T183
Test name
Test status
Simulation time	1663210522 ps
CPU time	58.62 seconds
Started	Jul 31 05:22:51 PM PDT 24
Finished	Jul 31 05:23:50 PM PDT 24
Peak memory	248296 kb
Host	smart-d513aeb2-41fc-4b72-9e92-842191e2da5b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12705 87797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.1270587797
Directory	/workspace/46.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/46.alert_handler_lpg.4096986364
Short name	T342
Test name
Test status
Simulation time	206616992478 ps
CPU time	3388.33 seconds
Started	Jul 31 05:22:47 PM PDT 24
Finished	Jul 31 06:19:16 PM PDT 24
Peak memory	288608 kb
Host	smart-97fe953f-4e6c-4315-a24a-4216c16af507
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4096986364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.4096986364
Directory	/workspace/46.alert_handler_lpg/latest

Test location	/workspace/coverage/default/46.alert_handler_lpg_stub_clk.718811347
Short name	T398
Test name
Test status
Simulation time	33818387735 ps
CPU time	1990.74 seconds
Started	Jul 31 05:22:49 PM PDT 24
Finished	Jul 31 05:56:00 PM PDT 24
Peak memory	272892 kb
Host	smart-c1daa346-2319-47c1-842e-3cc5a5fa5043
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=718811347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.718811347
Directory	/workspace/46.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/46.alert_handler_ping_timeout.4097322357
Short name	T682
Test name
Test status
Simulation time	54831056630 ps
CPU time	551.92 seconds
Started	Jul 31 05:22:49 PM PDT 24
Finished	Jul 31 05:32:01 PM PDT 24
Peak memory	254732 kb
Host	smart-520f4df7-c347-49bd-8278-4a8e04325f8c
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4097322357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.4097322357
Directory	/workspace/46.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/46.alert_handler_random_alerts.1441078964
Short name	T109
Test name
Test status
Simulation time	66426991 ps
CPU time	6.42 seconds
Started	Jul 31 05:22:49 PM PDT 24
Finished	Jul 31 05:22:56 PM PDT 24
Peak memory	250940 kb
Host	smart-a7548307-0a81-42d9-95a7-3f5c0a092401
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14410 78964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.1441078964
Directory	/workspace/46.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/46.alert_handler_random_classes.4157489658
Short name	T601
Test name
Test status
Simulation time	425020780 ps
CPU time	28.71 seconds
Started	Jul 31 05:22:48 PM PDT 24
Finished	Jul 31 05:23:16 PM PDT 24
Peak memory	247672 kb
Host	smart-9a7e5e3c-f4a1-4c32-9b1b-f06abeb3a33a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41574 89658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.4157489658
Directory	/workspace/46.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/46.alert_handler_sig_int_fail.2876520934
Short name	T263
Test name
Test status
Simulation time	1352968305 ps
CPU time	24.6 seconds
Started	Jul 31 05:22:51 PM PDT 24
Finished	Jul 31 05:23:15 PM PDT 24
Peak memory	248856 kb
Host	smart-c75e59f5-8d5e-4d91-b256-41ec374cf7fb
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28765 20934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.2876520934
Directory	/workspace/46.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/46.alert_handler_smoke.3878720177
Short name	T390
Test name
Test status
Simulation time	1617925115 ps
CPU time	62.73 seconds
Started	Jul 31 05:22:49 PM PDT 24
Finished	Jul 31 05:23:52 PM PDT 24
Peak memory	256492 kb
Host	smart-efcbd8b1-c4c1-42f4-a299-4669283b3fb9
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38787 20177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.3878720177
Directory	/workspace/46.alert_handler_smoke/latest

Test location	/workspace/coverage/default/46.alert_handler_stress_all.1832905233
Short name	T6
Test name
Test status
Simulation time	16610607636 ps
CPU time	1255.12 seconds
Started	Jul 31 05:22:46 PM PDT 24
Finished	Jul 31 05:43:42 PM PDT 24
Peak memory	289116 kb
Host	smart-a4f15a0d-b379-4733-b0d9-65fc4d6270ab
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832905233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha ndler_stress_all.1832905233
Directory	/workspace/46.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/47.alert_handler_entropy.1608481590
Short name	T624
Test name
Test status
Simulation time	132512896301 ps
CPU time	2002.29 seconds
Started	Jul 31 05:22:49 PM PDT 24
Finished	Jul 31 05:56:12 PM PDT 24
Peak memory	272944 kb
Host	smart-c5d97378-7490-43ff-9790-60a926b0d694
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1608481590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.1608481590
Directory	/workspace/47.alert_handler_entropy/latest

Test location	/workspace/coverage/default/47.alert_handler_esc_alert_accum.4252439300
Short name	T467
Test name
Test status
Simulation time	1012960823 ps
CPU time	22.25 seconds
Started	Jul 31 05:22:48 PM PDT 24
Finished	Jul 31 05:23:10 PM PDT 24
Peak memory	255856 kb
Host	smart-8400be22-eded-4b84-81b1-5b111a0e4200
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42524 39300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.4252439300
Directory	/workspace/47.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/47.alert_handler_esc_intr_timeout.2176056669
Short name	T484
Test name
Test status
Simulation time	10691248438 ps
CPU time	46.93 seconds
Started	Jul 31 05:23:51 PM PDT 24
Finished	Jul 31 05:24:38 PM PDT 24
Peak memory	256060 kb
Host	smart-5cba1624-fffd-49b0-9cfd-722981f82ef7
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21760 56669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.2176056669
Directory	/workspace/47.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/47.alert_handler_lpg_stub_clk.2680722533
Short name	T367
Test name
Test status
Simulation time	53195093959 ps
CPU time	1190.59 seconds
Started	Jul 31 05:22:48 PM PDT 24
Finished	Jul 31 05:42:39 PM PDT 24
Peak memory	287328 kb
Host	smart-9b4e0121-dab3-48d2-9fea-688f258cc1de
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2680722533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.2680722533
Directory	/workspace/47.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/47.alert_handler_ping_timeout.3012582075
Short name	T594
Test name
Test status
Simulation time	9422270595 ps
CPU time	421.34 seconds
Started	Jul 31 05:22:53 PM PDT 24
Finished	Jul 31 05:29:55 PM PDT 24
Peak memory	248388 kb
Host	smart-a2a27f43-d71d-4dd7-a74e-aafa5f160a72
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3012582075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.3012582075
Directory	/workspace/47.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/47.alert_handler_random_alerts.1843512500
Short name	T560
Test name
Test status
Simulation time	491016673 ps
CPU time	34.67 seconds
Started	Jul 31 05:22:50 PM PDT 24
Finished	Jul 31 05:23:24 PM PDT 24
Peak memory	248356 kb
Host	smart-301c82db-9302-4cd7-91a0-7ba96fd908de
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18435 12500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.1843512500
Directory	/workspace/47.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/47.alert_handler_random_classes.4099305434
Short name	T102
Test name
Test status
Simulation time	1747907097 ps
CPU time	30.68 seconds
Started	Jul 31 05:22:51 PM PDT 24
Finished	Jul 31 05:23:22 PM PDT 24
Peak memory	255992 kb
Host	smart-1da595ae-5487-4a7e-919e-bb364e96bbfd
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40993 05434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.4099305434
Directory	/workspace/47.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/47.alert_handler_sig_int_fail.1943333851
Short name	T689
Test name
Test status
Simulation time	288183935 ps
CPU time	35.96 seconds
Started	Jul 31 05:22:49 PM PDT 24
Finished	Jul 31 05:23:25 PM PDT 24
Peak memory	248556 kb
Host	smart-65bebac7-a3a8-4897-a10d-63ad7f82812e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19433 33851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.1943333851
Directory	/workspace/47.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/47.alert_handler_smoke.1984588614
Short name	T432
Test name
Test status
Simulation time	3633629271 ps
CPU time	65.2 seconds
Started	Jul 31 05:22:53 PM PDT 24
Finished	Jul 31 05:23:58 PM PDT 24
Peak memory	248896 kb
Host	smart-7ac98d04-b004-4694-b89a-408ab62523e9
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19845 88614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.1984588614
Directory	/workspace/47.alert_handler_smoke/latest

Test location	/workspace/coverage/default/47.alert_handler_stress_all.4134992168
Short name	T229
Test name
Test status
Simulation time	34464568359 ps
CPU time	2076.26 seconds
Started	Jul 31 05:22:47 PM PDT 24
Finished	Jul 31 05:57:24 PM PDT 24
Peak memory	285304 kb
Host	smart-0e25d7d5-dadc-469c-86e1-60cbe47fe2c7
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134992168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha ndler_stress_all.4134992168
Directory	/workspace/47.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/48.alert_handler_entropy.4003557979
Short name	T230
Test name
Test status
Simulation time	63555117325 ps
CPU time	2112.35 seconds
Started	Jul 31 05:22:56 PM PDT 24
Finished	Jul 31 05:58:09 PM PDT 24
Peak memory	289092 kb
Host	smart-46e5e7a9-e615-403d-a90a-1efd13d01b2b
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4003557979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.4003557979
Directory	/workspace/48.alert_handler_entropy/latest

Test location	/workspace/coverage/default/48.alert_handler_esc_alert_accum.1990657678
Short name	T506
Test name
Test status
Simulation time	519164994 ps
CPU time	42.13 seconds
Started	Jul 31 05:22:54 PM PDT 24
Finished	Jul 31 05:23:36 PM PDT 24
Peak memory	249364 kb
Host	smart-0355d138-f719-4d6d-9f1a-47a667b8ee5d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19906 57678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.1990657678
Directory	/workspace/48.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/48.alert_handler_esc_intr_timeout.333038780
Short name	T520
Test name
Test status
Simulation time	543272374 ps
CPU time	20.19 seconds
Started	Jul 31 05:22:54 PM PDT 24
Finished	Jul 31 05:23:14 PM PDT 24
Peak memory	256468 kb
Host	smart-3ca7e4e2-6b90-4c68-b39d-949866adc4ec
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33303 8780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.333038780
Directory	/workspace/48.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/48.alert_handler_lpg.1186672950
Short name	T327
Test name
Test status
Simulation time	142997699948 ps
CPU time	1852.63 seconds
Started	Jul 31 05:22:56 PM PDT 24
Finished	Jul 31 05:53:49 PM PDT 24
Peak memory	272256 kb
Host	smart-abc265df-96f2-4235-9561-2342fb4751c4
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1186672950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.1186672950
Directory	/workspace/48.alert_handler_lpg/latest

Test location	/workspace/coverage/default/48.alert_handler_lpg_stub_clk.2352834789
Short name	T274
Test name
Test status
Simulation time	35286109915 ps
CPU time	758.42 seconds
Started	Jul 31 05:22:54 PM PDT 24
Finished	Jul 31 05:35:32 PM PDT 24
Peak memory	271680 kb
Host	smart-6057490a-326d-4eae-9174-f33ed850e380
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2352834789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.2352834789
Directory	/workspace/48.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/48.alert_handler_ping_timeout.7085039
Short name	T236
Test name
Test status
Simulation time	5246938619 ps
CPU time	162.99 seconds
Started	Jul 31 05:22:54 PM PDT 24
Finished	Jul 31 05:25:37 PM PDT 24
Peak memory	248388 kb
Host	smart-61fd81d9-0371-451c-b4e9-aaf98e436485
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=7085039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.7085039
Directory	/workspace/48.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/48.alert_handler_random_alerts.3774298727
Short name	T393
Test name
Test status
Simulation time	115855974 ps
CPU time	14.11 seconds
Started	Jul 31 05:22:57 PM PDT 24
Finished	Jul 31 05:23:11 PM PDT 24
Peak memory	255364 kb
Host	smart-a5282851-1964-4ad5-ba26-4b47f1f41b95
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37742 98727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.3774298727
Directory	/workspace/48.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/48.alert_handler_random_classes.848687332
Short name	T593
Test name
Test status
Simulation time	1473163190 ps
CPU time	43.19 seconds
Started	Jul 31 05:22:55 PM PDT 24
Finished	Jul 31 05:23:38 PM PDT 24
Peak memory	255620 kb
Host	smart-423e93fe-eacb-43bd-901d-225beff018b8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84868 7332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.848687332
Directory	/workspace/48.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/48.alert_handler_sig_int_fail.1521855852
Short name	T589
Test name
Test status
Simulation time	273164410 ps
CPU time	10.5 seconds
Started	Jul 31 05:22:54 PM PDT 24
Finished	Jul 31 05:23:05 PM PDT 24
Peak memory	247712 kb
Host	smart-77832116-fa60-4f41-8956-0ed1f22e910c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15218 55852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.1521855852
Directory	/workspace/48.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/48.alert_handler_smoke.4267139157
Short name	T678
Test name
Test status
Simulation time	96090750 ps
CPU time	4.33 seconds
Started	Jul 31 05:22:46 PM PDT 24
Finished	Jul 31 05:22:51 PM PDT 24
Peak memory	248356 kb
Host	smart-7f078516-2898-4ca5-b65a-75f49b645430
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42671 39157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.4267139157
Directory	/workspace/48.alert_handler_smoke/latest

Test location	/workspace/coverage/default/48.alert_handler_stress_all.3925138009
Short name	T428
Test name
Test status
Simulation time	11693499300 ps
CPU time	211.64 seconds
Started	Jul 31 05:22:53 PM PDT 24
Finished	Jul 31 05:26:25 PM PDT 24
Peak memory	256572 kb
Host	smart-61cd8601-f8b4-4a4d-b318-a1c85f730fa4
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925138009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha ndler_stress_all.3925138009
Directory	/workspace/48.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/49.alert_handler_entropy.2746956794
Short name	T477
Test name
Test status
Simulation time	8500975491 ps
CPU time	943.35 seconds
Started	Jul 31 05:23:00 PM PDT 24
Finished	Jul 31 05:38:43 PM PDT 24
Peak memory	272724 kb
Host	smart-336ef02a-f069-46d7-97f0-705ebaa9478f
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2746956794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.2746956794
Directory	/workspace/49.alert_handler_entropy/latest

Test location	/workspace/coverage/default/49.alert_handler_esc_alert_accum.3774561251
Short name	T37
Test name
Test status
Simulation time	557346641 ps
CPU time	12.08 seconds
Started	Jul 31 05:23:00 PM PDT 24
Finished	Jul 31 05:23:12 PM PDT 24
Peak memory	255784 kb
Host	smart-d10b9548-9b12-493d-ba06-c469aa79c178
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37745 61251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.3774561251
Directory	/workspace/49.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/49.alert_handler_esc_intr_timeout.2253484065
Short name	T615
Test name
Test status
Simulation time	765122369 ps
CPU time	42.97 seconds
Started	Jul 31 05:22:59 PM PDT 24
Finished	Jul 31 05:23:42 PM PDT 24
Peak memory	255892 kb
Host	smart-7bec2e2e-2f23-4295-bd00-830543f5cf2a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22534 84065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.2253484065
Directory	/workspace/49.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/49.alert_handler_lpg.2302746059
Short name	T335
Test name
Test status
Simulation time	16795603577 ps
CPU time	937.06 seconds
Started	Jul 31 05:23:00 PM PDT 24
Finished	Jul 31 05:38:37 PM PDT 24
Peak memory	272148 kb
Host	smart-39b30c47-a3a2-4b31-b455-28fcfacd4d6f
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2302746059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.2302746059
Directory	/workspace/49.alert_handler_lpg/latest

Test location	/workspace/coverage/default/49.alert_handler_lpg_stub_clk.832711058
Short name	T582
Test name
Test status
Simulation time	44857062041 ps
CPU time	2656.21 seconds
Started	Jul 31 05:22:59 PM PDT 24
Finished	Jul 31 06:07:15 PM PDT 24
Peak memory	283748 kb
Host	smart-149e84d0-72dd-4de5-954b-06c74b7d52d1
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=832711058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.832711058
Directory	/workspace/49.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/49.alert_handler_ping_timeout.4174797073
Short name	T569
Test name
Test status
Simulation time	80446267478 ps
CPU time	431.65 seconds
Started	Jul 31 05:22:58 PM PDT 24
Finished	Jul 31 05:30:10 PM PDT 24
Peak memory	248392 kb
Host	smart-d36f62b1-42e5-40c8-951a-4aa2e79e9198
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4174797073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.4174797073
Directory	/workspace/49.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/49.alert_handler_random_alerts.2388114819
Short name	T50
Test name
Test status
Simulation time	1275354571 ps
CPU time	27.86 seconds
Started	Jul 31 05:23:00 PM PDT 24
Finished	Jul 31 05:23:28 PM PDT 24
Peak memory	255804 kb
Host	smart-703cbbf9-75c4-4112-9181-062b7b62c826
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23881 14819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.2388114819
Directory	/workspace/49.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/49.alert_handler_random_classes.2000770904
Short name	T417
Test name
Test status
Simulation time	5001747986 ps
CPU time	53.22 seconds
Started	Jul 31 05:22:58 PM PDT 24
Finished	Jul 31 05:23:51 PM PDT 24
Peak memory	248476 kb
Host	smart-672c3b8c-54ba-4c16-83e0-d85b033571c1
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20007 70904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.2000770904
Directory	/workspace/49.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/49.alert_handler_sig_int_fail.33276661
Short name	T490
Test name
Test status
Simulation time	2348438885 ps
CPU time	17.28 seconds
Started	Jul 31 05:23:00 PM PDT 24
Finished	Jul 31 05:23:17 PM PDT 24
Peak memory	248304 kb
Host	smart-b364ef4a-5b0b-4b34-b21e-915dc138ab8b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33276 661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.33276661
Directory	/workspace/49.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/49.alert_handler_smoke.1429251995
Short name	T25
Test name
Test status
Simulation time	278919285 ps
CPU time	18.3 seconds
Started	Jul 31 05:22:58 PM PDT 24
Finished	Jul 31 05:23:17 PM PDT 24
Peak memory	248628 kb
Host	smart-5710e59e-2580-4f5a-9f9f-93694c453069
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14292 51995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.1429251995
Directory	/workspace/49.alert_handler_smoke/latest

Test location	/workspace/coverage/default/49.alert_handler_stress_all.4226415350
Short name	T554
Test name
Test status
Simulation time	248606937602 ps
CPU time	1764.76 seconds
Started	Jul 31 05:23:00 PM PDT 24
Finished	Jul 31 05:52:25 PM PDT 24
Peak memory	282752 kb
Host	smart-234f10ec-29cc-4a89-8306-7d94dfcb665b
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226415350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha ndler_stress_all.4226415350
Directory	/workspace/49.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/5.alert_handler_alert_accum_saturation.1080762691
Short name	T202
Test name
Test status
Simulation time	108556596 ps
CPU time	2.98 seconds
Started	Jul 31 05:21:12 PM PDT 24
Finished	Jul 31 05:21:19 PM PDT 24
Peak memory	248608 kb
Host	smart-e807d719-3430-420b-8143-7b0c72c9f79f
User	root
Command	/workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1080762691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.1080762691
Directory	/workspace/5.alert_handler_alert_accum_saturation/latest

Test location	/workspace/coverage/default/5.alert_handler_entropy.2842457491
Short name	T457
Test name
Test status
Simulation time	50843002733 ps
CPU time	1112.54 seconds
Started	Jul 31 05:21:15 PM PDT 24
Finished	Jul 31 05:39:48 PM PDT 24
Peak memory	286112 kb
Host	smart-b741f0a9-fccf-4833-aff4-db1cbe1f318d
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2842457491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.2842457491
Directory	/workspace/5.alert_handler_entropy/latest

Test location	/workspace/coverage/default/5.alert_handler_entropy_stress.2168195508
Short name	T539
Test name
Test status
Simulation time	4648461089 ps
CPU time	34.32 seconds
Started	Jul 31 05:21:06 PM PDT 24
Finished	Jul 31 05:21:41 PM PDT 24
Peak memory	248348 kb
Host	smart-50abfd56-fea4-4d33-89fb-b715d95fbfb2
User	root
Command	/workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=2168195508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.2168195508
Directory	/workspace/5.alert_handler_entropy_stress/latest

Test location	/workspace/coverage/default/5.alert_handler_esc_alert_accum.3520298800
Short name	T177
Test name
Test status
Simulation time	16000055880 ps
CPU time	233.76 seconds
Started	Jul 31 05:21:20 PM PDT 24
Finished	Jul 31 05:25:14 PM PDT 24
Peak memory	256108 kb
Host	smart-b20012c2-df58-4d2c-b604-83c3701dc5c5
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35202 98800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.3520298800
Directory	/workspace/5.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/5.alert_handler_esc_intr_timeout.3335972091
Short name	T480
Test name
Test status
Simulation time	1844017304 ps
CPU time	53.71 seconds
Started	Jul 31 05:21:06 PM PDT 24
Finished	Jul 31 05:22:00 PM PDT 24
Peak memory	248240 kb
Host	smart-80ffd648-66b0-4e7b-ab1f-d8cec3d87c4c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33359 72091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.3335972091
Directory	/workspace/5.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/5.alert_handler_lpg.1222430255
Short name	T309
Test name
Test status
Simulation time	333341727990 ps
CPU time	1574.05 seconds
Started	Jul 31 05:21:13 PM PDT 24
Finished	Jul 31 05:47:27 PM PDT 24
Peak memory	264752 kb
Host	smart-7480a7e6-521b-4f56-8914-63135707bb97
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1222430255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.1222430255
Directory	/workspace/5.alert_handler_lpg/latest

Test location	/workspace/coverage/default/5.alert_handler_lpg_stub_clk.943814400
Short name	T577
Test name
Test status
Simulation time	12209407181 ps
CPU time	793.93 seconds
Started	Jul 31 05:21:15 PM PDT 24
Finished	Jul 31 05:34:29 PM PDT 24
Peak memory	272304 kb
Host	smart-c2f6226e-1982-4e87-ac6e-f84fdf085b21
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=943814400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.943814400
Directory	/workspace/5.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/5.alert_handler_ping_timeout.3033552729
Short name	T317
Test name
Test status
Simulation time	34458604424 ps
CPU time	246.99 seconds
Started	Jul 31 05:21:19 PM PDT 24
Finished	Jul 31 05:25:26 PM PDT 24
Peak memory	247232 kb
Host	smart-21050f3d-579d-43c8-b645-72c4069c1977
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3033552729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.3033552729
Directory	/workspace/5.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/5.alert_handler_random_alerts.3872065726
Short name	T23
Test name
Test status
Simulation time	639253843 ps
CPU time	41.84 seconds
Started	Jul 31 05:21:16 PM PDT 24
Finished	Jul 31 05:21:58 PM PDT 24
Peak memory	255892 kb
Host	smart-9a3c46e1-16e0-4c59-9c95-fb5ebec2ce53
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38720 65726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.3872065726
Directory	/workspace/5.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/5.alert_handler_random_classes.1022013399
Short name	T14
Test name
Test status
Simulation time	199216728 ps
CPU time	13.68 seconds
Started	Jul 31 05:21:08 PM PDT 24
Finished	Jul 31 05:21:21 PM PDT 24
Peak memory	247560 kb
Host	smart-e7b7c9c8-3702-4687-b53d-b479a3818647
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10220 13399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.1022013399
Directory	/workspace/5.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/5.alert_handler_sig_int_fail.1597200199
Short name	T547
Test name
Test status
Simulation time	7419103520 ps
CPU time	68.45 seconds
Started	Jul 31 05:21:32 PM PDT 24
Finished	Jul 31 05:22:40 PM PDT 24
Peak memory	256328 kb
Host	smart-a3d5f27f-8aa4-4e0d-9d92-8df807842730
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15972 00199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.1597200199
Directory	/workspace/5.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/5.alert_handler_smoke.3526289288
Short name	T453
Test name
Test status
Simulation time	7979676559 ps
CPU time	53.68 seconds
Started	Jul 31 05:21:08 PM PDT 24
Finished	Jul 31 05:22:02 PM PDT 24
Peak memory	248884 kb
Host	smart-7ce3a9be-b315-4750-896b-354b70b3ca5e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35262 89288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.3526289288
Directory	/workspace/5.alert_handler_smoke/latest

Test location	/workspace/coverage/default/5.alert_handler_stress_all.4173789159
Short name	T65
Test name
Test status
Simulation time	157013857503 ps
CPU time	2321.37 seconds
Started	Jul 31 05:21:19 PM PDT 24
Finished	Jul 31 06:00:01 PM PDT 24
Peak memory	289356 kb
Host	smart-163fb913-45b4-4222-bd04-dbaa05227d51
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173789159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han dler_stress_all.4173789159
Directory	/workspace/5.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.114363113
Short name	T656
Test name
Test status
Simulation time	16537592235 ps
CPU time	1412.98 seconds
Started	Jul 31 05:21:24 PM PDT 24
Finished	Jul 31 05:44:57 PM PDT 24
Peak memory	289492 kb
Host	smart-554faaf3-433a-467a-97a1-e25ba56710e7
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114363113 -assert nopostproc +UVM_TESTNAME=alert _handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.114363113
Directory	/workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/6.alert_handler_alert_accum_saturation.2973856095
Short name	T98
Test name
Test status
Simulation time	121427036 ps
CPU time	3.33 seconds
Started	Jul 31 05:21:17 PM PDT 24
Finished	Jul 31 05:21:21 PM PDT 24
Peak memory	248648 kb
Host	smart-e80d384b-c3a4-48d1-aecf-c05fed3473dd
User	root
Command	/workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=2973856095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.2973856095
Directory	/workspace/6.alert_handler_alert_accum_saturation/latest

Test location	/workspace/coverage/default/6.alert_handler_entropy.3942763640
Short name	T371
Test name
Test status
Simulation time	39197731325 ps
CPU time	846.76 seconds
Started	Jul 31 05:21:19 PM PDT 24
Finished	Jul 31 05:35:31 PM PDT 24
Peak memory	272980 kb
Host	smart-bc0e2300-8753-4a14-a4cb-aaf8334691f2
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3942763640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.3942763640
Directory	/workspace/6.alert_handler_entropy/latest

Test location	/workspace/coverage/default/6.alert_handler_entropy_stress.1760698856
Short name	T489
Test name
Test status
Simulation time	1341450259 ps
CPU time	16.93 seconds
Started	Jul 31 05:21:18 PM PDT 24
Finished	Jul 31 05:21:35 PM PDT 24
Peak memory	248296 kb
Host	smart-cb750ae6-c06f-4920-a7f4-443e820dcc29
User	root
Command	/workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1760698856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.1760698856
Directory	/workspace/6.alert_handler_entropy_stress/latest

Test location	/workspace/coverage/default/6.alert_handler_esc_alert_accum.1550200152
Short name	T114
Test name
Test status
Simulation time	1863880758 ps
CPU time	169.2 seconds
Started	Jul 31 05:21:24 PM PDT 24
Finished	Jul 31 05:24:23 PM PDT 24
Peak memory	256448 kb
Host	smart-c19c8e9a-2136-4509-a385-fecf3a41253c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15502 00152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.1550200152
Directory	/workspace/6.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/6.alert_handler_esc_intr_timeout.1546761474
Short name	T20
Test name
Test status
Simulation time	3536030449 ps
CPU time	57.19 seconds
Started	Jul 31 05:21:18 PM PDT 24
Finished	Jul 31 05:22:16 PM PDT 24
Peak memory	248356 kb
Host	smart-1c45ed7d-09cf-424c-bb5a-5c855f2c24d7
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15467 61474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.1546761474
Directory	/workspace/6.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/6.alert_handler_lpg.3481373928
Short name	T559
Test name
Test status
Simulation time	225275807113 ps
CPU time	2820.02 seconds
Started	Jul 31 05:21:31 PM PDT 24
Finished	Jul 31 06:08:31 PM PDT 24
Peak memory	281088 kb
Host	smart-54546fae-54ce-4dd3-ba24-c600836f9077
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3481373928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.3481373928
Directory	/workspace/6.alert_handler_lpg/latest

Test location	/workspace/coverage/default/6.alert_handler_lpg_stub_clk.1256145543
Short name	T280
Test name
Test status
Simulation time	50634546388 ps
CPU time	3143.43 seconds
Started	Jul 31 05:21:19 PM PDT 24
Finished	Jul 31 06:13:43 PM PDT 24
Peak memory	287604 kb
Host	smart-86edc6a4-a87a-4274-9241-34f0a07617c1
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1256145543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.1256145543
Directory	/workspace/6.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/6.alert_handler_ping_timeout.652746108
Short name	T687
Test name
Test status
Simulation time	32251483924 ps
CPU time	334.94 seconds
Started	Jul 31 05:21:14 PM PDT 24
Finished	Jul 31 05:26:49 PM PDT 24
Peak memory	248236 kb
Host	smart-cf59c00a-1bf0-459c-a750-23b35a97cf0c
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=652746108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.652746108
Directory	/workspace/6.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/6.alert_handler_random_alerts.179710037
Short name	T285
Test name
Test status
Simulation time	1351213182 ps
CPU time	33.87 seconds
Started	Jul 31 05:21:26 PM PDT 24
Finished	Jul 31 05:22:00 PM PDT 24
Peak memory	255756 kb
Host	smart-06c66bb3-2515-4921-835f-e67a240e4ba4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17971 0037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.179710037
Directory	/workspace/6.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/6.alert_handler_random_classes.1214628898
Short name	T475
Test name
Test status
Simulation time	688071226 ps
CPU time	44.83 seconds
Started	Jul 31 05:21:21 PM PDT 24
Finished	Jul 31 05:22:06 PM PDT 24
Peak memory	255900 kb
Host	smart-cbae3ef9-79cf-4404-965b-5d99813d24f1
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12146 28898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.1214628898
Directory	/workspace/6.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/6.alert_handler_sig_int_fail.1650524239
Short name	T91
Test name
Test status
Simulation time	267760427 ps
CPU time	16.22 seconds
Started	Jul 31 05:21:16 PM PDT 24
Finished	Jul 31 05:21:32 PM PDT 24
Peak memory	247880 kb
Host	smart-cc7a4d24-1a7b-42d6-bc2d-0e251fd7fd59
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16505 24239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.1650524239
Directory	/workspace/6.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/6.alert_handler_smoke.2535164521
Short name	T376
Test name
Test status
Simulation time	1797256135 ps
CPU time	26.1 seconds
Started	Jul 31 05:21:22 PM PDT 24
Finished	Jul 31 05:21:49 PM PDT 24
Peak memory	255684 kb
Host	smart-7d00b072-2bb6-45dc-90a9-451ef28d9148
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25351 64521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.2535164521
Directory	/workspace/6.alert_handler_smoke/latest

Test location	/workspace/coverage/default/6.alert_handler_stress_all.101644033
Short name	T270
Test name
Test status
Simulation time	47215482465 ps
CPU time	2626.02 seconds
Started	Jul 31 05:21:25 PM PDT 24
Finished	Jul 31 06:05:12 PM PDT 24
Peak memory	287368 kb
Host	smart-6834620c-c9bb-4a1d-a1a3-745512a2e5ef
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101644033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_hand ler_stress_all.101644033
Directory	/workspace/6.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.2486683270
Short name	T290
Test name
Test status
Simulation time	80988931018 ps
CPU time	1617.63 seconds
Started	Jul 31 05:21:35 PM PDT 24
Finished	Jul 31 05:48:33 PM PDT 24
Peak memory	281248 kb
Host	smart-aa2971a7-6eb0-4c43-8dde-6fd4076d523f
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486683270 -assert nopostproc +UVM_TESTNAME=aler t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.2486683270
Directory	/workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/7.alert_handler_alert_accum_saturation.3251330092
Short name	T211
Test name
Test status
Simulation time	157689066 ps
CPU time	2.8 seconds
Started	Jul 31 05:21:41 PM PDT 24
Finished	Jul 31 05:21:45 PM PDT 24
Peak memory	248756 kb
Host	smart-1067fc10-d59a-49ea-a102-d82a4531985b
User	root
Command	/workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=3251330092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.3251330092
Directory	/workspace/7.alert_handler_alert_accum_saturation/latest

Test location	/workspace/coverage/default/7.alert_handler_entropy.3801053564
Short name	T603
Test name
Test status
Simulation time	30707718190 ps
CPU time	1549.88 seconds
Started	Jul 31 05:21:22 PM PDT 24
Finished	Jul 31 05:47:12 PM PDT 24
Peak memory	288916 kb
Host	smart-1ae7eebd-a299-4503-87f0-1dde7a32fc5f
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3801053564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.3801053564
Directory	/workspace/7.alert_handler_entropy/latest

Test location	/workspace/coverage/default/7.alert_handler_entropy_stress.643487344
Short name	T596
Test name
Test status
Simulation time	2223371327 ps
CPU time	22.47 seconds
Started	Jul 31 05:21:13 PM PDT 24
Finished	Jul 31 05:21:36 PM PDT 24
Peak memory	248560 kb
Host	smart-dcb5afa2-5103-4be3-a47f-94c597bdec14
User	root
Command	/workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=643487344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.643487344
Directory	/workspace/7.alert_handler_entropy_stress/latest

Test location	/workspace/coverage/default/7.alert_handler_esc_alert_accum.825320593
Short name	T435
Test name
Test status
Simulation time	2772147230 ps
CPU time	152.37 seconds
Started	Jul 31 05:21:31 PM PDT 24
Finished	Jul 31 05:24:04 PM PDT 24
Peak memory	256072 kb
Host	smart-78687747-a71b-49da-b2a1-fd56bd506ee5
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82532 0593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.825320593
Directory	/workspace/7.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/7.alert_handler_esc_intr_timeout.4030356232
Short name	T368
Test name
Test status
Simulation time	1045936735 ps
CPU time	19.66 seconds
Started	Jul 31 05:21:24 PM PDT 24
Finished	Jul 31 05:21:44 PM PDT 24
Peak memory	248108 kb
Host	smart-fbf84113-1d81-4a9d-be59-ad9a3d91812f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40303 56232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.4030356232
Directory	/workspace/7.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/7.alert_handler_lpg.1411141689
Short name	T706
Test name
Test status
Simulation time	120060939608 ps
CPU time	2012.21 seconds
Started	Jul 31 05:21:21 PM PDT 24
Finished	Jul 31 05:54:54 PM PDT 24
Peak memory	288076 kb
Host	smart-a397a1cb-b235-4bdd-ab48-cea603d51639
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1411141689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.1411141689
Directory	/workspace/7.alert_handler_lpg/latest

Test location	/workspace/coverage/default/7.alert_handler_lpg_stub_clk.216210088
Short name	T631
Test name
Test status
Simulation time	12171969024 ps
CPU time	994.15 seconds
Started	Jul 31 05:21:24 PM PDT 24
Finished	Jul 31 05:37:58 PM PDT 24
Peak memory	281080 kb
Host	smart-169c63a4-3cb5-4433-9032-f0e44c94faae
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=216210088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.216210088
Directory	/workspace/7.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/7.alert_handler_ping_timeout.3390935329
Short name	T312
Test name
Test status
Simulation time	34149949496 ps
CPU time	388.26 seconds
Started	Jul 31 05:21:30 PM PDT 24
Finished	Jul 31 05:27:59 PM PDT 24
Peak memory	255136 kb
Host	smart-4103dc5b-d3b3-46f0-86ae-ef2cb0702294
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3390935329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.3390935329
Directory	/workspace/7.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/7.alert_handler_random_alerts.2982248208
Short name	T79
Test name
Test status
Simulation time	19054978060 ps
CPU time	52 seconds
Started	Jul 31 05:21:24 PM PDT 24
Finished	Jul 31 05:22:16 PM PDT 24
Peak memory	256192 kb
Host	smart-b2db6d6a-f686-4f01-8fa2-13d11cfe4ff6
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29822 48208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.2982248208
Directory	/workspace/7.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/7.alert_handler_random_classes.3511599824
Short name	T95
Test name
Test status
Simulation time	1588342005 ps
CPU time	47.05 seconds
Started	Jul 31 05:21:32 PM PDT 24
Finished	Jul 31 05:22:19 PM PDT 24
Peak memory	256060 kb
Host	smart-0c57e437-c5bb-4727-bf6d-67d17d18da17
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35115 99824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.3511599824
Directory	/workspace/7.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/7.alert_handler_sig_int_fail.294801360
Short name	T243
Test name
Test status
Simulation time	2614650260 ps
CPU time	66.84 seconds
Started	Jul 31 05:21:13 PM PDT 24
Finished	Jul 31 05:22:20 PM PDT 24
Peak memory	256452 kb
Host	smart-f729c697-a84b-4f79-80d1-0100d63aa45d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29480 1360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.294801360
Directory	/workspace/7.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/7.alert_handler_smoke.1245732605
Short name	T551
Test name
Test status
Simulation time	659631690 ps
CPU time	44.11 seconds
Started	Jul 31 05:21:22 PM PDT 24
Finished	Jul 31 05:22:07 PM PDT 24
Peak memory	248220 kb
Host	smart-834a64cf-b52e-48f3-ac91-56e1c6fce822
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12457 32605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.1245732605
Directory	/workspace/7.alert_handler_smoke/latest

Test location	/workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.1062431988
Short name	T239
Test name
Test status
Simulation time	417530398589 ps
CPU time	6967.67 seconds
Started	Jul 31 05:21:36 PM PDT 24
Finished	Jul 31 07:17:45 PM PDT 24
Peak memory	321728 kb
Host	smart-88b88290-6882-438e-a5f7-b67d43241189
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062431988 -assert nopostproc +UVM_TESTNAME=aler t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.1062431988
Directory	/workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/8.alert_handler_alert_accum_saturation.3795258932
Short name	T210
Test name
Test status
Simulation time	34178671 ps
CPU time	3.56 seconds
Started	Jul 31 05:21:23 PM PDT 24
Finished	Jul 31 05:21:26 PM PDT 24
Peak memory	248560 kb
Host	smart-2e8f1062-c528-4ce4-9da2-0df85f660511
User	root
Command	/workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=3795258932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.3795258932
Directory	/workspace/8.alert_handler_alert_accum_saturation/latest

Test location	/workspace/coverage/default/8.alert_handler_entropy.665416326
Short name	T70
Test name
Test status
Simulation time	14092002139 ps
CPU time	1245.18 seconds
Started	Jul 31 05:21:27 PM PDT 24
Finished	Jul 31 05:42:12 PM PDT 24
Peak memory	288376 kb
Host	smart-6e346bad-70f3-42cb-b604-d664a64bfbb6
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=665416326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.665416326
Directory	/workspace/8.alert_handler_entropy/latest

Test location	/workspace/coverage/default/8.alert_handler_entropy_stress.3623851745
Short name	T665
Test name
Test status
Simulation time	7000274148 ps
CPU time	77.97 seconds
Started	Jul 31 05:21:22 PM PDT 24
Finished	Jul 31 05:22:40 PM PDT 24
Peak memory	248336 kb
Host	smart-d2c74959-dd51-424d-93c6-61601a1fa333
User	root
Command	/workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=3623851745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.3623851745
Directory	/workspace/8.alert_handler_entropy_stress/latest

Test location	/workspace/coverage/default/8.alert_handler_esc_alert_accum.2832631056
Short name	T366
Test name
Test status
Simulation time	319841251 ps
CPU time	6.87 seconds
Started	Jul 31 05:21:34 PM PDT 24
Finished	Jul 31 05:21:41 PM PDT 24
Peak memory	252900 kb
Host	smart-63ca4056-0c72-4506-abcb-f67fe3dbe39e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28326 31056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.2832631056
Directory	/workspace/8.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/8.alert_handler_esc_intr_timeout.3416953446
Short name	T385
Test name
Test status
Simulation time	203444714 ps
CPU time	8.26 seconds
Started	Jul 31 05:21:36 PM PDT 24
Finished	Jul 31 05:21:44 PM PDT 24
Peak memory	247832 kb
Host	smart-9557c0e1-bf49-43c9-a1d7-51ecafd02283
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34169 53446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.3416953446
Directory	/workspace/8.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/8.alert_handler_lpg.489135124
Short name	T339
Test name
Test status
Simulation time	32621913702 ps
CPU time	1647.14 seconds
Started	Jul 31 05:21:22 PM PDT 24
Finished	Jul 31 05:48:49 PM PDT 24
Peak memory	272992 kb
Host	smart-676028b6-4bca-4f30-8acc-db7f1b2523bb
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=489135124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.489135124
Directory	/workspace/8.alert_handler_lpg/latest

Test location	/workspace/coverage/default/8.alert_handler_lpg_stub_clk.2820522266
Short name	T405
Test name
Test status
Simulation time	67629408237 ps
CPU time	2258.9 seconds
Started	Jul 31 05:21:39 PM PDT 24
Finished	Jul 31 05:59:18 PM PDT 24
Peak memory	288708 kb
Host	smart-69e8c90a-7970-41ff-a05e-c166e91f437b
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2820522266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.2820522266
Directory	/workspace/8.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/8.alert_handler_ping_timeout.1798314665
Short name	T523
Test name
Test status
Simulation time	1734548830 ps
CPU time	80.32 seconds
Started	Jul 31 05:21:28 PM PDT 24
Finished	Jul 31 05:22:48 PM PDT 24
Peak memory	248324 kb
Host	smart-7d028631-f89a-4962-a84c-5f7b52696849
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1798314665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.1798314665
Directory	/workspace/8.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/8.alert_handler_random_alerts.2439099772
Short name	T676
Test name
Test status
Simulation time	3252104697 ps
CPU time	72.71 seconds
Started	Jul 31 05:21:26 PM PDT 24
Finished	Jul 31 05:22:39 PM PDT 24
Peak memory	255784 kb
Host	smart-ce925e56-6609-4ff1-a4ea-76316894b347
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24390 99772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.2439099772
Directory	/workspace/8.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/8.alert_handler_random_classes.3190097663
Short name	T525
Test name
Test status
Simulation time	330403226 ps
CPU time	3.85 seconds
Started	Jul 31 05:21:16 PM PDT 24
Finished	Jul 31 05:21:20 PM PDT 24
Peak memory	247764 kb
Host	smart-e16f7775-f804-42ef-8983-f8be9ff95fe2
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31900 97663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.3190097663
Directory	/workspace/8.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/8.alert_handler_sig_int_fail.4228065312
Short name	T83
Test name
Test status
Simulation time	2267144299 ps
CPU time	33.89 seconds
Started	Jul 31 05:21:23 PM PDT 24
Finished	Jul 31 05:21:57 PM PDT 24
Peak memory	248764 kb
Host	smart-aa6b7e59-bfea-44ac-9b27-6fe956c7ea64
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42280 65312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.4228065312
Directory	/workspace/8.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/8.alert_handler_smoke.1870802541
Short name	T493
Test name
Test status
Simulation time	367548027 ps
CPU time	19.06 seconds
Started	Jul 31 05:21:20 PM PDT 24
Finished	Jul 31 05:21:39 PM PDT 24
Peak memory	256388 kb
Host	smart-7e2cb280-3104-4fff-a6df-1cf1829e66cc
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18708 02541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.1870802541
Directory	/workspace/8.alert_handler_smoke/latest

Test location	/workspace/coverage/default/8.alert_handler_stress_all.1924785554
Short name	T693
Test name
Test status
Simulation time	204160459946 ps
CPU time	3312.07 seconds
Started	Jul 31 05:21:22 PM PDT 24
Finished	Jul 31 06:16:34 PM PDT 24
Peak memory	289116 kb
Host	smart-c2f49e9d-4239-4cc4-a202-719990504724
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924785554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han dler_stress_all.1924785554
Directory	/workspace/8.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.757924960
Short name	T86
Test name
Test status
Simulation time	9437226484 ps
CPU time	746.47 seconds
Started	Jul 31 05:21:19 PM PDT 24
Finished	Jul 31 05:33:46 PM PDT 24
Peak memory	268200 kb
Host	smart-77fe4767-74ae-4367-bc23-638a3ce79c16
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757924960 -assert nopostproc +UVM_TESTNAME=alert _handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.757924960
Directory	/workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/9.alert_handler_alert_accum_saturation.2658622011
Short name	T212
Test name
Test status
Simulation time	45639653 ps
CPU time	4.02 seconds
Started	Jul 31 05:21:29 PM PDT 24
Finished	Jul 31 05:21:33 PM PDT 24
Peak memory	248644 kb
Host	smart-76090d97-04f5-4cf2-928f-ea5699402153
User	root
Command	/workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=2658622011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.2658622011
Directory	/workspace/9.alert_handler_alert_accum_saturation/latest

Test location	/workspace/coverage/default/9.alert_handler_entropy.556318628
Short name	T478
Test name
Test status
Simulation time	15325752987 ps
CPU time	1023.32 seconds
Started	Jul 31 05:21:37 PM PDT 24
Finished	Jul 31 05:38:41 PM PDT 24
Peak memory	271996 kb
Host	smart-abc0f024-b2e3-4c24-bb52-0881d0df78fa
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=556318628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.556318628
Directory	/workspace/9.alert_handler_entropy/latest

Test location	/workspace/coverage/default/9.alert_handler_entropy_stress.3648254252
Short name	T552
Test name
Test status
Simulation time	571367831 ps
CPU time	8.68 seconds
Started	Jul 31 05:21:27 PM PDT 24
Finished	Jul 31 05:21:36 PM PDT 24
Peak memory	248288 kb
Host	smart-8d10724c-429d-4077-a691-21977b1509cc
User	root
Command	/workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=3648254252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.3648254252
Directory	/workspace/9.alert_handler_entropy_stress/latest

Test location	/workspace/coverage/default/9.alert_handler_esc_alert_accum.107229450
Short name	T245
Test name
Test status
Simulation time	691071580 ps
CPU time	39.19 seconds
Started	Jul 31 05:21:41 PM PDT 24
Finished	Jul 31 05:22:20 PM PDT 24
Peak memory	248360 kb
Host	smart-dae82a4e-0987-4588-83d7-ce6ba3066651
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10722 9450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.107229450
Directory	/workspace/9.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/9.alert_handler_esc_intr_timeout.1295702136
Short name	T72
Test name
Test status
Simulation time	1456610598 ps
CPU time	60.71 seconds
Started	Jul 31 05:21:33 PM PDT 24
Finished	Jul 31 05:22:34 PM PDT 24
Peak memory	248344 kb
Host	smart-29471dbb-aaa6-4709-8a6d-73feddad04d2
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12957 02136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.1295702136
Directory	/workspace/9.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/9.alert_handler_lpg.483713913
Short name	T331
Test name
Test status
Simulation time	9322255926 ps
CPU time	664.94 seconds
Started	Jul 31 05:21:36 PM PDT 24
Finished	Jul 31 05:32:41 PM PDT 24
Peak memory	272060 kb
Host	smart-5a55f692-cf95-4f89-8c82-ac00164477ac
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=483713913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.483713913
Directory	/workspace/9.alert_handler_lpg/latest

Test location	/workspace/coverage/default/9.alert_handler_ping_timeout.3132195241
Short name	T313
Test name
Test status
Simulation time	7488054254 ps
CPU time	159.01 seconds
Started	Jul 31 05:21:47 PM PDT 24
Finished	Jul 31 05:24:26 PM PDT 24
Peak memory	248344 kb
Host	smart-d3bf2727-98ee-4172-8f2f-9ef5a988a59d
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3132195241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.3132195241
Directory	/workspace/9.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/9.alert_handler_random_alerts.2238190771
Short name	T483
Test name
Test status
Simulation time	1359638508 ps
CPU time	25.72 seconds
Started	Jul 31 05:21:54 PM PDT 24
Finished	Jul 31 05:22:20 PM PDT 24
Peak memory	248272 kb
Host	smart-ce5d8091-2989-4534-a72d-c12cbfc0e0b7
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22381 90771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.2238190771
Directory	/workspace/9.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/9.alert_handler_random_classes.2494599390
Short name	T673
Test name
Test status
Simulation time	3492085566 ps
CPU time	28.75 seconds
Started	Jul 31 05:21:21 PM PDT 24
Finished	Jul 31 05:21:50 PM PDT 24
Peak memory	255948 kb
Host	smart-0f4a00e6-dba0-427d-a49c-41d9fbf69f81
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24945 99390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.2494599390
Directory	/workspace/9.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/9.alert_handler_sig_int_fail.2228521964
Short name	T604
Test name
Test status
Simulation time	924034092 ps
CPU time	27.03 seconds
Started	Jul 31 05:21:39 PM PDT 24
Finished	Jul 31 05:22:06 PM PDT 24
Peak memory	255632 kb
Host	smart-01f32ab2-8a97-4506-a81d-80b09d238d66
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22285 21964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.2228521964
Directory	/workspace/9.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/9.alert_handler_smoke.469765255
Short name	T538
Test name
Test status
Simulation time	776721196 ps
CPU time	47.46 seconds
Started	Jul 31 05:21:22 PM PDT 24
Finished	Jul 31 05:22:09 PM PDT 24
Peak memory	255908 kb
Host	smart-1cd283ed-4154-427d-a3af-57184b200a97
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46976 5255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.469765255
Directory	/workspace/9.alert_handler_smoke/latest

Test location	/workspace/coverage/default/9.alert_handler_stress_all.1915432835
Short name	T429
Test name
Test status
Simulation time	5888675334 ps
CPU time	189.79 seconds
Started	Jul 31 05:21:37 PM PDT 24
Finished	Jul 31 05:24:47 PM PDT 24
Peak memory	256608 kb
Host	smart-5eb5c1b3-265f-4589-ae09-1890bbd1c00e
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915432835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han dler_stress_all.1915432835
Directory	/workspace/9.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.4278682675
Short name	T284
Test name
Test status
Simulation time	37355713985 ps
CPU time	2224.71 seconds
Started	Jul 31 05:21:39 PM PDT 24
Finished	Jul 31 05:58:44 PM PDT 24
Peak memory	305524 kb
Host	smart-2f508dfb-c424-4fb8-a653-7b361078cdc1
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278682675 -assert nopostproc +UVM_TESTNAME=aler t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.4278682675
Directory	/workspace/9.alert_handler_stress_all_with_rand_reset/latest