Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	79855	1			T14	12		T15	1		T11	10
class_i[0x1]	66051	1			T3	3753		T14	3		T15	4
class_i[0x2]	48050	1			T14	6		T15	7		T5	3351
class_i[0x3]	49552	1			T15	10		T11	4095		T5	12

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	62788	1			T3	1022		T14	8		T15	11
alert[0x1]	58762	1			T3	868		T14	7		T15	3
alert[0x2]	61871	1			T3	937		T15	3		T11	973
alert[0x3]	60087	1			T3	926		T14	6		T15	5

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

243244

1

T3

3753

T14

13

T15

11

esc_ping_fail

264

1

T14

8

T15

11

T16

6

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	62710	1			T3	1022		T14	4		T15	7
esc_integrity_fail	alert[0x1]	58698	1			T3	868		T14	5		T15	2
esc_integrity_fail	alert[0x2]	61801	1			T3	937		T11	973		T5	900
esc_integrity_fail	alert[0x3]	60035	1			T3	926		T14	4		T15	2
esc_ping_fail	alert[0x0]	78	1			T14	4		T15	4		T16	1
esc_ping_fail	alert[0x1]	64	1			T14	2		T15	1		T16	2
esc_ping_fail	alert[0x2]	70	1			T15	3		T16	1		T64	1
esc_ping_fail	alert[0x3]	52	1			T14	2		T15	3		T16	2

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	79776	1			T14	11		T11	10		T5	5
esc_integrity_fail	class_i[0x1]	65995	1			T3	3753		T14	2		T15	3
esc_integrity_fail	class_i[0x2]	47988	1			T5	3351		T19	2807		T23	9
esc_integrity_fail	class_i[0x3]	49485	1			T15	8		T11	4095		T5	12
esc_ping_fail	class_i[0x0]	79	1			T14	1		T15	1		T16	6
esc_ping_fail	class_i[0x1]	56	1			T14	1		T15	1		T64	2
esc_ping_fail	class_i[0x2]	62	1			T14	6		T15	7		T113	5
esc_ping_fail	class_i[0x3]	67	1			T15	2		T317	2		T296	1