Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	670495040	0	0	621
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	670495040	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	670495040	670311745	0	0
tb.dut.CheckAccuCntDw	0	0	621	621	0	0
tb.dut.CheckEscCntDw	0	0	621	621	0	0
tb.dut.CheckNAlerts	0	0	621	621	0	0
tb.dut.CheckNClasses	0	0	621	621	0	0
tb.dut.CheckNEscSev	0	0	621	621	0	0
tb.dut.CrashdumpKnownO_A	0	0	670495040	670311745	0	0
tb.dut.EdnKnownO_A	0	0	670495040	670311745	0	0
tb.dut.EscPKnownO_A	0	0	670495040	670311745	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	670495040	90	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	670495040	90	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	670495040	90	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	670495040	90	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	670495040	90	0	0
tb.dut.IrqAKnownO_A	0	0	670495040	670311745	0	0
tb.dut.IrqBKnownO_A	0	0	670495040	670311745	0	0
tb.dut.IrqCKnownO_A	0	0	670495040	670311745	0	0
tb.dut.IrqDKnownO_A	0	0	670495040	670311745	0	0
tb.dut.TlAReadyKnownO_A	0	0	670495040	670311745	0	0
tb.dut.TlDValidKnownO_A	0	0	670495040	670311745	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	691510334	2883609	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	691510334	4826	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	691510334	5841	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	691510334	5884	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	691510334	5954	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	691510334	4714	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	691510334	4740	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	691510334	4753	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	691510334	4771	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	691510334	5818	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	691510334	5788	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	691510334	4946	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	691510334	4574	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	691510334	4794	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	691510334	5726	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	691510334	4624	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	691510334	4821	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	691510334	4861	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	691510334	5784	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	691510334	5762	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	691510334	4702	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	691510334	4914	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	691510334	4820	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	691510334	4745	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	691510334	4650	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	691510334	5699	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	691510334	5901	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	691510334	4925	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	691510334	5792	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	691510334	4490	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	691510334	5817	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	691510334	4674	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	691510334	4719	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	691510334	4531	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	691510334	4722	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	691510334	4708	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	691510334	4716	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	691510334	5914	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	691510334	4490	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	691510334	4781	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	691510334	5665	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	691510334	4757	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	691510334	5610	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	691510334	4706	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	691510334	5948	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	691510334	4780	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	691510334	4859	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	691510334	4711	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	691510334	5824	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	691510334	5998	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	691510334	4732	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	691510334	4479	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	691510334	5812	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	691510334	5833	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	691510334	4923	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	691510334	4787	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	691510334	4666	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	691510334	4720	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	691510334	4687	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	691510334	4814	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	691510334	5759	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	691510334	4663	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	691510334	4761	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	691510334	4549	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	691510334	6121	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	691510334	4545	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	691510334	4964	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	691510334	5807	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	691510334	4518	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	691510334	4636	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	691510334	9435	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	691510334	4795	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	691510334	4589	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	691510334	4892	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	691510334	4774	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	691510334	4728	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	691510334	4900	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	691510334	4702	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	691510334	5976	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	670495040	90	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	670495040	90	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	670495040	90	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	670495040	3787	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	670495040	257850	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	670495040	299878918	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	670495040	290	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	670495040	843	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	670495040	38	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	670495040	408	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	670206486	206659571	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	670495040	933	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	670495040	912	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	670495040	895	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	670495040	876	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	670495040	918	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	670495040	102527	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	670495040	815	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	670495040	65	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	670495040	1398	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	670495040	1128	0	0
tb.dut.gen_classes[0].u_esc_timer.EscStateOut_A	0	0	670205061	670136863	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	621	621	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	670495040	670311745	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	670495040	90	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	670495040	90	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	670495040	90	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	670495040	2603	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	670495040	190764	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	670495040	367211712	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	670495040	272	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	670495040	479	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	670495040	23	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	670495040	210	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	670206486	294646705	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	670495040	552	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	670495040	541	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	670495040	529	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	670495040	522	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	670495040	801	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	670495040	98940	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	670495040	716	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	670495040	60	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	670495040	1376	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	670495040	1106	0	0
tb.dut.gen_classes[1].u_esc_timer.EscStateOut_A	0	0	670205061	670136863	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	621	621	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	670495040	670311745	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	670495040	90	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	670495040	90	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	670495040	90	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	670495040	3945	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	670495040	172510	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	670495040	404746209	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	670495040	228	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	670495040	482	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	670495040	18	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	670495040	231	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	670206486	309650398	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	670495040	555	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	670495040	547	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	670495040	531	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	670495040	520	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	670495040	1299	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	670495040	141161	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	670495040	1216	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	670495040	62	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	670495040	1430	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	670495040	1160	0	0
tb.dut.gen_classes[2].u_esc_timer.EscStateOut_A	0	0	670205061	670136863	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	621	621	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	670495040	670311745	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	670495040	90	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	670495040	90	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	670495040	90	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	670495040	5829	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	670495040	172602	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	670495040	378174648	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	670495040	295	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	670495040	477	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	670495040	25	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	670495040	227	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	670206486	297569024	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	670495040	562	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	670495040	551	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	670495040	541	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	670495040	528	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	670495040	768	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	670495040	77791	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	670495040	673	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	670495040	69	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	670495040	1449	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	670495040	1179	0	0
tb.dut.gen_classes[3].u_esc_timer.EscStateOut_A	0	0	670205061	670136863	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	621	621	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	670495040	670311745	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	691510334	126888037	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	691510334	690844743	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	691510334	690844743	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	691510334	187586217	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	691510334	690844743	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	691510334	690844743	0	0
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