Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	0	40	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	0	40	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	65	1			T4	1		T34	4		T80	2
class_index[0x1]	60	1			T23	1		T76	1		T81	1
class_index[0x2]	62	1			T24	1		T29	1		T34	2
class_index[0x3]	69	1			T5	1		T23	1		T66	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	93	1			T5	1		T24	1		T76	1
intr_timeout_cnt[1]	60	1			T4	1		T23	2		T66	1
intr_timeout_cnt[2]	18	1			T34	2		T82	1		T92	1
intr_timeout_cnt[3]	19	1			T80	1		T89	4		T250	1
intr_timeout_cnt[4]	20	1			T34	2		T81	1		T82	1
intr_timeout_cnt[5]	9	1			T80	1		T84	1		T85	2
intr_timeout_cnt[6]	8	1			T83	1		T53	1		T61	1
intr_timeout_cnt[7]	8	1			T80	1		T240	1		T322	1
intr_timeout_cnt[8]	14	1			T34	1		T88	1		T89	3
intr_timeout_cnt[9]	7	1			T79	1		T89	1		T53	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	0	40	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	18	1			T83	1		T54	2		T55	2
class_index[0x0]	intr_timeout_cnt[1]	18	1			T4	1		T86	1		T87	1
class_index[0x0]	intr_timeout_cnt[2]	7	1			T34	1		T82	1		T323	1
class_index[0x0]	intr_timeout_cnt[3]	5	1			T80	1		T89	1		T324	1
class_index[0x0]	intr_timeout_cnt[4]	6	1			T34	2		T56	1		T260	1
class_index[0x0]	intr_timeout_cnt[5]	3	1			T84	1		T85	1		T325	1
class_index[0x0]	intr_timeout_cnt[6]	3	1			T240	1		T326	1		T327	1
class_index[0x0]	intr_timeout_cnt[7]	2	1			T80	1		T328	1		-	-
class_index[0x0]	intr_timeout_cnt[8]	2	1			T34	1		T329	1		-	-
class_index[0x0]	intr_timeout_cnt[9]	1	1			T54	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[0]	18	1			T76	1		T91	1		T56	1
class_index[0x1]	intr_timeout_cnt[1]	21	1			T23	1		T86	1		T87	1
class_index[0x1]	intr_timeout_cnt[2]	3	1			T92	1		T330	1		T331	1
class_index[0x1]	intr_timeout_cnt[3]	4	1			T250	1		T332	2		T333	1
class_index[0x1]	intr_timeout_cnt[4]	4	1			T81	1		T85	1		T264	1
class_index[0x1]	intr_timeout_cnt[5]	2	1			T85	1		T334	1		-	-
class_index[0x1]	intr_timeout_cnt[6]	2	1			T83	1		T61	1		-	-
class_index[0x1]	intr_timeout_cnt[7]	2	1			T240	1		T335	1		-	-
class_index[0x1]	intr_timeout_cnt[8]	1	1			T97	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[9]	3	1			T89	1		T53	1		T336	1
class_index[0x2]	intr_timeout_cnt[0]	29	1			T24	1		T29	1		T34	1
class_index[0x2]	intr_timeout_cnt[1]	8	1			T34	1		T337	1		T268	1
class_index[0x2]	intr_timeout_cnt[2]	3	1			T324	1		T338	1		T333	1
class_index[0x2]	intr_timeout_cnt[3]	3	1			T339	1		T329	1		T325	1
class_index[0x2]	intr_timeout_cnt[4]	3	1			T82	1		T52	1		T56	1
class_index[0x2]	intr_timeout_cnt[5]	3	1			T80	1		T277	1		T340	1
class_index[0x2]	intr_timeout_cnt[6]	1	1			T339	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[7]	3	1			T322	1		T326	1		T341	1
class_index[0x2]	intr_timeout_cnt[8]	7	1			T88	1		T55	1		T104	1
class_index[0x2]	intr_timeout_cnt[9]	2	1			T326	1		T332	1		-	-
class_index[0x3]	intr_timeout_cnt[0]	28	1			T5	1		T80	5		T106	1
class_index[0x3]	intr_timeout_cnt[1]	13	1			T23	1		T66	1		T72	1
class_index[0x3]	intr_timeout_cnt[2]	5	1			T34	1		T264	1		T109	1
class_index[0x3]	intr_timeout_cnt[3]	7	1			T89	3		T280	2		T323	1
class_index[0x3]	intr_timeout_cnt[4]	7	1			T342	1		T343	1		T344	3
class_index[0x3]	intr_timeout_cnt[5]	1	1			T211	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[6]	2	1			T53	1		T345	1		-	-
class_index[0x3]	intr_timeout_cnt[7]	1	1			T346	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[8]	4	1			T89	3		T240	1		-	-
class_index[0x3]	intr_timeout_cnt[9]	1	1			T79	1		-	-		-	-