Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	337316	1			T1	1425		T2	17		T3	1429
all_values[1]	337316	1			T1	1425		T2	17		T3	1429
all_values[2]	337316	1			T1	1425		T2	17		T3	1429
all_values[3]	337316	1			T1	1425		T2	17		T3	1429

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

671170

1

T1

2922

T2

39

T3

2871

auto[1]

678094

1

T1

2778

T2

29

T3

2845

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

805975

1

T1

2951

T2

36

T3

2889

auto[1]

543289

1

T1

2749

T2

32

T3

2827

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	97278	1			T1	407		T2	5		T3	391
all_values[0]	auto[0]	auto[1]	70568	1			T1	327		T2	4		T3	372
all_values[0]	auto[1]	auto[0]	98860	1			T1	395		T2	4		T3	335
all_values[0]	auto[1]	auto[1]	70610	1			T1	296		T2	4		T3	331
all_values[1]	auto[0]	auto[0]	101295	1			T1	361		T2	5		T3	346
all_values[1]	auto[0]	auto[1]	67140	1			T1	356		T2	4		T3	342
all_values[1]	auto[1]	auto[0]	101895	1			T1	355		T2	4		T3	373
all_values[1]	auto[1]	auto[1]	66986	1			T1	353		T2	4		T3	368
all_values[2]	auto[0]	auto[0]	101107	1			T1	378		T2	7		T3	372
all_values[2]	auto[0]	auto[1]	66494	1			T1	378		T2	6		T3	372
all_values[2]	auto[1]	auto[0]	103114	1			T1	335		T2	2		T3	344
all_values[2]	auto[1]	auto[1]	66601	1			T1	334		T2	2		T3	341
all_values[3]	auto[0]	auto[0]	100286	1			T1	363		T2	4		T3	342
all_values[3]	auto[0]	auto[1]	67002	1			T1	352		T2	4		T3	334
all_values[3]	auto[1]	auto[0]	102140	1			T1	357		T2	5		T3	386
all_values[3]	auto[1]	auto[1]	67888	1			T1	353		T2	4		T3	367