Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	337316	1			T1	1425		T2	17		T3	1429
all_pins[1]	337316	1			T1	1425		T2	17		T3	1429
all_pins[2]	337316	1			T1	1425		T2	17		T3	1429
all_pins[3]	337316	1			T1	1425		T2	17		T3	1429

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1077179	1			T1	4364		T2	54		T3	4309
values[0x1]	272085	1			T1	1336		T2	14		T3	1407
transitions[0x0=>0x1]	180693	1			T1	853		T2	7		T3	879
transitions[0x1=>0x0]	180952	1			T1	853		T2	8		T3	879

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	266706	1			T1	1129		T2	13		T3	1098
all_pins[0]	values[0x1]	70610	1			T1	296		T2	4		T3	331
all_pins[0]	transitions[0x0=>0x1]	69963	1			T1	296		T2	3		T3	331
all_pins[0]	transitions[0x1=>0x0]	67500	1			T1	353		T2	4		T3	367
all_pins[1]	values[0x0]	270330	1			T1	1072		T2	13		T3	1061
all_pins[1]	values[0x1]	66986	1			T1	353		T2	4		T3	368
all_pins[1]	transitions[0x0=>0x1]	36983	1			T1	209		T2	2		T3	194
all_pins[1]	transitions[0x1=>0x0]	40607	1			T1	152		T2	2		T3	157
all_pins[2]	values[0x0]	270715	1			T1	1091		T2	15		T3	1088
all_pins[2]	values[0x1]	66601	1			T1	334		T2	2		T3	341
all_pins[2]	transitions[0x0=>0x1]	36288	1			T1	169		T3	173		T12	29
all_pins[2]	transitions[0x1=>0x0]	36673	1			T1	188		T2	2		T3	200
all_pins[3]	values[0x0]	269428	1			T1	1072		T2	13		T3	1062
all_pins[3]	values[0x1]	67888	1			T1	353		T2	4		T3	367
all_pins[3]	transitions[0x0=>0x1]	37459	1			T1	179		T2	2		T3	181
all_pins[3]	transitions[0x1=>0x0]	36172	1			T1	160		T3	155		T12	22