Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	85593	1			T3	704		T7	996		T11	1063
accum_cnt_1000	229127	1			T3	723		T12	87		T7	1016
accum_cnt_100	26412	1			T3	42		T12	45		T7	70
accum_cnt_50	69639	1			T3	1077		T12	36		T7	50
accum_cnt_10	172744	1			T1	2159		T2	30		T3	1081
accum_cnt_0	364571	1			T1	2173		T2	34		T3	9

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	248682	1			T1	1083		T2	16		T3	1062
class_index[0x1]	248682	1			T1	1083		T2	16		T3	1062
class_index[0x2]	248682	1			T1	1083		T2	16		T3	1062
class_index[0x3]	248682	1			T1	1083		T2	16		T3	1062

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	26017	1			T7	563		T11	527		T5	329
class_index[0x0]	accum_cnt_1000	65860	1			T7	627		T11	478		T13	537
class_index[0x0]	accum_cnt_100	8765	1			T7	42		T11	28		T13	35
class_index[0x0]	accum_cnt_50	19474	1			T3	1051		T7	28		T11	21
class_index[0x0]	accum_cnt_10	43803	1			T3	6		T7	10		T11	2
class_index[0x0]	accum_cnt_0	70403	1			T1	1083		T2	16		T3	5
class_index[0x1]	accum_cnt_2000	19518	1			T3	224		T11	277		T18	255
class_index[0x1]	accum_cnt_1000	56236	1			T3	202		T12	42		T11	260
class_index[0x1]	accum_cnt_100	6523	1			T3	12		T12	21		T11	17
class_index[0x1]	accum_cnt_50	15123	1			T3	7		T12	17		T11	16
class_index[0x1]	accum_cnt_10	47160	1			T2	2		T3	3		T12	6
class_index[0x1]	accum_cnt_0	90707	1			T1	1083		T2	14		T3	2
class_index[0x2]	accum_cnt_2000	18570	1			T13	66		T5	269		T18	572
class_index[0x2]	accum_cnt_1000	50427	1			T12	45		T13	481		T5	344
class_index[0x2]	accum_cnt_100	5023	1			T12	24		T13	29		T5	67
class_index[0x2]	accum_cnt_50	20327	1			T12	19		T13	23		T5	54
class_index[0x2]	accum_cnt_10	46211	1			T1	1079		T2	13		T3	1062
class_index[0x2]	accum_cnt_0	98215	1			T1	4		T2	3		T12	2
class_index[0x3]	accum_cnt_2000	21488	1			T3	480		T7	433		T11	259
class_index[0x3]	accum_cnt_1000	56604	1			T3	521		T7	389		T11	243
class_index[0x3]	accum_cnt_100	6101	1			T3	30		T7	28		T11	9
class_index[0x3]	accum_cnt_50	14715	1			T3	19		T7	22		T15	28
class_index[0x3]	accum_cnt_10	35570	1			T1	1080		T2	15		T3	10
class_index[0x3]	accum_cnt_0	105246	1			T1	3		T2	1		T3	2