Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	6869	1			T18	13		T64	1		T23	1401
alert[0x1]	2680	1			T18	43		T68	298		T29	31
alert[0x2]	6885	1			T15	1		T11	56		T17	316
alert[0x3]	5579	1			T14	1		T11	25		T64	1
alert[0x4]	8658	1			T14	1		T11	61		T18	231
alert[0x5]	3590	1			T14	1		T11	37		T17	53
alert[0x6]	2094	1			T17	34		T18	97		T19	424
alert[0x7]	8138	1			T17	23		T23	3		T68	63
alert[0x8]	4567	1			T5	2		T64	1		T23	171
alert[0x9]	9133	1			T19	80		T23	615		T68	3096
alert[0xa]	4018	1			T17	620		T18	22		T23	4
alert[0xb]	10440	1			T17	21		T18	84		T19	1488
alert[0xc]	8325	1			T15	1		T11	947		T16	1
alert[0xd]	4944	1			T11	18		T17	24		T18	1575
alert[0xe]	3193	1			T15	2		T68	129		T69	24
alert[0xf]	2352	1			T18	38		T68	96		T69	65
alert[0x10]	4807	1			T14	1		T15	1		T11	29
alert[0x11]	2850	1			T14	1		T11	82		T17	38
alert[0x12]	6347	1			T11	159		T17	402		T23	274
alert[0x13]	7612	1			T14	1		T15	1		T11	42
alert[0x14]	4569	1			T11	30		T17	14		T18	10
alert[0x15]	6588	1			T15	1		T11	331		T5	2
alert[0x16]	3886	1			T14	1		T11	310		T18	368
alert[0x17]	5016	1			T11	479		T17	32		T18	5
alert[0x18]	6865	1			T14	1		T11	295		T17	8
alert[0x19]	2248	1			T15	1		T64	1		T66	12
alert[0x1a]	5420	1			T14	1		T11	4		T19	118
alert[0x1b]	8413	1			T17	521		T19	31		T68	263
alert[0x1c]	5711	1			T17	52		T69	14		T29	17
alert[0x1d]	6302	1			T3	1		T11	35		T16	1
alert[0x1e]	4784	1			T14	1		T18	37		T29	41
alert[0x1f]	6782	1			T14	1		T15	1		T17	183
alert[0x20]	6501	1			T17	812		T18	491		T19	90
alert[0x21]	4119	1			T18	29		T66	98		T288	15
alert[0x22]	5589	1			T11	230		T18	95		T19	76
alert[0x23]	5751	1			T66	53		T68	131		T288	3
alert[0x24]	5875	1			T15	1		T17	18		T64	1
alert[0x25]	4820	1			T15	1		T18	1		T65	5
alert[0x26]	8711	1			T15	1		T5	6		T23	281
alert[0x27]	5570	1			T15	1		T19	1142		T23	59
alert[0x28]	5958	1			T23	4		T29	177		T289	13
alert[0x29]	2940	1			T14	1		T11	8		T66	21
alert[0x2a]	2284	1			T11	260		T17	40		T18	173
alert[0x2b]	6139	1			T17	19		T18	27		T16	1
alert[0x2c]	4983	1			T14	1		T11	325		T23	84
alert[0x2d]	5297	1			T68	133		T69	2267		T29	19
alert[0x2e]	3035	1			T18	284		T29	284		T113	1
alert[0x2f]	3754	1			T23	100		T68	584		T29	3
alert[0x30]	9613	1			T15	1		T11	104		T17	22
alert[0x31]	3191	1			T18	279		T34	27		T274	189
alert[0x32]	6124	1			T15	1		T17	213		T16	1
alert[0x33]	6574	1			T11	46		T18	46		T66	941
alert[0x34]	2696	1			T14	1		T17	94		T18	123
alert[0x35]	5087	1			T14	1		T29	188		T290	1
alert[0x36]	9246	1			T16	1		T23	6		T29	24
alert[0x37]	11928	1			T68	20		T69	104		T29	19
alert[0x38]	2415	1			T15	1		T11	21		T17	10
alert[0x39]	5958	1			T11	9		T4	5		T17	57
alert[0x3a]	8370	1			T18	478		T69	17		T274	25
alert[0x3b]	4211	1			T11	28		T19	24		T23	6
alert[0x3c]	5154	1			T14	1		T18	90		T68	120
alert[0x3d]	5341	1			T17	3		T18	37		T23	45
alert[0x3e]	10797	1			T11	97		T17	35		T23	8
alert[0x3f]	3253	1			T11	14		T18	23		T19	3
alert[0x40]	5928	1			T17	8		T18	435		T65	20

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	105005	1			T5	1		T16	2		T64	7
class_i[0x1]	79308	1			T14	14		T15	1		T11	4073
class_i[0x2]	93686	1			T14	2		T11	3		T4	5
class_i[0x3]	88878	1			T3	1		T15	15		T11	6

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

366244

1

T3

1

T11

4082

T4

5

alert_ping_fail

633

1

T14

16

T15

16

T16

10

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	6862	1			T18	13		T23	1401		T66	418
alert_integrity_fail	alert[0x1]	2673	1			T18	43		T68	298		T29	31
alert_integrity_fail	alert[0x2]	6875	1			T11	56		T17	316		T68	65
alert_integrity_fail	alert[0x3]	5571	1			T11	25		T66	28		T68	289
alert_integrity_fail	alert[0x4]	8651	1			T11	61		T18	231		T68	499
alert_integrity_fail	alert[0x5]	3580	1			T11	37		T17	53		T18	75
alert_integrity_fail	alert[0x6]	2083	1			T17	34		T18	97		T19	424
alert_integrity_fail	alert[0x7]	8129	1			T17	23		T23	3		T68	63
alert_integrity_fail	alert[0x8]	4556	1			T5	2		T23	171		T68	57
alert_integrity_fail	alert[0x9]	9126	1			T19	80		T23	615		T68	3096
alert_integrity_fail	alert[0xa]	4003	1			T17	620		T18	22		T23	4
alert_integrity_fail	alert[0xb]	10435	1			T17	21		T18	84		T19	1488
alert_integrity_fail	alert[0xc]	8314	1			T11	947		T68	660		T69	74
alert_integrity_fail	alert[0xd]	4932	1			T11	18		T17	24		T18	1575
alert_integrity_fail	alert[0xe]	3181	1			T68	129		T69	24		T29	44
alert_integrity_fail	alert[0xf]	2345	1			T18	38		T68	96		T69	65
alert_integrity_fail	alert[0x10]	4803	1			T11	29		T23	9		T69	349
alert_integrity_fail	alert[0x11]	2839	1			T11	82		T17	38		T18	3
alert_integrity_fail	alert[0x12]	6340	1			T11	159		T17	402		T23	274
alert_integrity_fail	alert[0x13]	7602	1			T11	42		T17	15		T18	117
alert_integrity_fail	alert[0x14]	4559	1			T11	30		T17	14		T18	10
alert_integrity_fail	alert[0x15]	6576	1			T11	331		T5	2		T17	14
alert_integrity_fail	alert[0x16]	3868	1			T11	310		T18	368		T29	14
alert_integrity_fail	alert[0x17]	5002	1			T11	479		T17	32		T18	5
alert_integrity_fail	alert[0x18]	6854	1			T11	295		T17	8		T18	99
alert_integrity_fail	alert[0x19]	2240	1			T66	12		T29	6		T236	999
alert_integrity_fail	alert[0x1a]	5411	1			T11	4		T19	118		T66	7
alert_integrity_fail	alert[0x1b]	8406	1			T17	521		T19	31		T68	263
alert_integrity_fail	alert[0x1c]	5702	1			T17	52		T69	14		T29	17
alert_integrity_fail	alert[0x1d]	6293	1			T3	1		T11	35		T29	69
alert_integrity_fail	alert[0x1e]	4776	1			T18	37		T29	41		T34	2
alert_integrity_fail	alert[0x1f]	6766	1			T17	183		T18	451		T34	1
alert_integrity_fail	alert[0x20]	6483	1			T17	812		T18	491		T19	90
alert_integrity_fail	alert[0x21]	4110	1			T18	29		T66	98		T288	15
alert_integrity_fail	alert[0x22]	5574	1			T11	230		T18	95		T19	76
alert_integrity_fail	alert[0x23]	5743	1			T66	53		T68	131		T288	3
alert_integrity_fail	alert[0x24]	5864	1			T17	18		T68	366		T34	10
alert_integrity_fail	alert[0x25]	4806	1			T18	1		T65	5		T23	82
alert_integrity_fail	alert[0x26]	8707	1			T5	6		T23	281		T29	61
alert_integrity_fail	alert[0x27]	5562	1			T19	1142		T23	59		T68	23
alert_integrity_fail	alert[0x28]	5946	1			T23	4		T29	177		T289	13
alert_integrity_fail	alert[0x29]	2928	1			T11	8		T66	21		T69	2
alert_integrity_fail	alert[0x2a]	2275	1			T11	260		T17	40		T18	173
alert_integrity_fail	alert[0x2b]	6129	1			T17	19		T18	27		T274	62
alert_integrity_fail	alert[0x2c]	4972	1			T11	325		T23	84		T68	28
alert_integrity_fail	alert[0x2d]	5287	1			T68	133		T69	2267		T29	19
alert_integrity_fail	alert[0x2e]	3028	1			T18	284		T29	284		T80	230
alert_integrity_fail	alert[0x2f]	3745	1			T23	100		T68	584		T29	3
alert_integrity_fail	alert[0x30]	9606	1			T11	104		T17	22		T65	4
alert_integrity_fail	alert[0x31]	3180	1			T18	279		T34	27		T274	189
alert_integrity_fail	alert[0x32]	6114	1			T17	213		T66	47		T29	135
alert_integrity_fail	alert[0x33]	6561	1			T11	46		T18	46		T66	941
alert_integrity_fail	alert[0x34]	2684	1			T17	94		T18	123		T66	19
alert_integrity_fail	alert[0x35]	5070	1			T29	188		T32	13		T102	56
alert_integrity_fail	alert[0x36]	9238	1			T23	6		T29	24		T288	16
alert_integrity_fail	alert[0x37]	11921	1			T68	20		T69	104		T29	19
alert_integrity_fail	alert[0x38]	2406	1			T11	21		T17	10		T18	154
alert_integrity_fail	alert[0x39]	5946	1			T11	9		T4	5		T17	57
alert_integrity_fail	alert[0x3a]	8361	1			T18	478		T69	17		T274	25
alert_integrity_fail	alert[0x3b]	4208	1			T11	28		T19	24		T23	6
alert_integrity_fail	alert[0x3c]	5146	1			T18	90		T68	120		T69	11
alert_integrity_fail	alert[0x3d]	5328	1			T17	3		T18	37		T23	45
alert_integrity_fail	alert[0x3e]	10789	1			T11	97		T17	35		T23	8
alert_integrity_fail	alert[0x3f]	3248	1			T11	14		T18	23		T19	3
alert_integrity_fail	alert[0x40]	5926	1			T17	8		T18	435		T65	20
alert_ping_fail	alert[0x0]	7	1			T64	1		T290	1		T291	1
alert_ping_fail	alert[0x1]	7	1			T239	1		T292	1		T293	1
alert_ping_fail	alert[0x2]	10	1			T15	1		T16	1		T290	1
alert_ping_fail	alert[0x3]	8	1			T14	1		T64	1		T198	1
alert_ping_fail	alert[0x4]	7	1			T14	1		T239	1		T294	1
alert_ping_fail	alert[0x5]	10	1			T14	1		T295	1		T296	1
alert_ping_fail	alert[0x6]	11	1			T122	2		T249	1		T297	1
alert_ping_fail	alert[0x7]	9	1			T285	2		T298	1		T269	1
alert_ping_fail	alert[0x8]	11	1			T64	1		T299	2		T269	2
alert_ping_fail	alert[0x9]	7	1			T298	1		T300	1		T301	2
alert_ping_fail	alert[0xa]	15	1			T287	1		T249	2		T302	1
alert_ping_fail	alert[0xb]	5	1			T266	1		T239	1		T303	1
alert_ping_fail	alert[0xc]	11	1			T15	1		T16	1		T113	1
alert_ping_fail	alert[0xd]	12	1			T113	1		T304	1		T239	1
alert_ping_fail	alert[0xe]	12	1			T15	2		T113	1		T298	1
alert_ping_fail	alert[0xf]	7	1			T298	1		T300	1		T304	1
alert_ping_fail	alert[0x10]	4	1			T14	1		T15	1		T113	1
alert_ping_fail	alert[0x11]	11	1			T14	1		T16	1		T295	2
alert_ping_fail	alert[0x12]	7	1			T113	1		T296	1		T305	1
alert_ping_fail	alert[0x13]	10	1			T14	1		T15	1		T298	1
alert_ping_fail	alert[0x14]	10	1			T64	1		T123	1		T198	1
alert_ping_fail	alert[0x15]	12	1			T15	1		T198	1		T306	1
alert_ping_fail	alert[0x16]	18	1			T14	1		T123	1		T118	2
alert_ping_fail	alert[0x17]	14	1			T16	2		T295	1		T198	1
alert_ping_fail	alert[0x18]	11	1			T14	1		T298	1		T296	1
alert_ping_fail	alert[0x19]	8	1			T15	1		T64	1		T302	1
alert_ping_fail	alert[0x1a]	9	1			T14	1		T198	1		T300	1
alert_ping_fail	alert[0x1b]	7	1			T307	1		T308	1		T309	1
alert_ping_fail	alert[0x1c]	9	1			T298	1		T310	1		T311	2
alert_ping_fail	alert[0x1d]	9	1			T16	1		T295	1		T198	2
alert_ping_fail	alert[0x1e]	8	1			T14	1		T305	1		T304	1
alert_ping_fail	alert[0x1f]	16	1			T14	1		T15	1		T285	1
alert_ping_fail	alert[0x20]	18	1			T64	1		T113	1		T298	1
alert_ping_fail	alert[0x21]	9	1			T298	1		T198	1		T269	1
alert_ping_fail	alert[0x22]	15	1			T298	1		T290	1		T269	2
alert_ping_fail	alert[0x23]	8	1			T311	1		T301	1		T312	1
alert_ping_fail	alert[0x24]	11	1			T15	1		T64	1		T295	1
alert_ping_fail	alert[0x25]	14	1			T15	1		T310	1		T313	3
alert_ping_fail	alert[0x26]	4	1			T15	1		T245	1		T293	1
alert_ping_fail	alert[0x27]	8	1			T15	1		T290	1		T300	1
alert_ping_fail	alert[0x28]	12	1			T298	1		T295	1		T266	1
alert_ping_fail	alert[0x29]	12	1			T14	1		T298	2		T290	1
alert_ping_fail	alert[0x2a]	9	1			T123	1		T269	1		T314	1
alert_ping_fail	alert[0x2b]	10	1			T16	1		T298	1		T315	1
alert_ping_fail	alert[0x2c]	11	1			T14	1		T189	1		T307	1
alert_ping_fail	alert[0x2d]	10	1			T249	1		T316	1		T245	2
alert_ping_fail	alert[0x2e]	7	1			T113	1		T298	1		T302	1
alert_ping_fail	alert[0x2f]	9	1			T302	1		T297	1		T304	1
alert_ping_fail	alert[0x30]	7	1			T15	1		T302	1		T297	1
alert_ping_fail	alert[0x31]	11	1			T290	1		T297	1		T266	1
alert_ping_fail	alert[0x32]	10	1			T15	1		T16	1		T198	1
alert_ping_fail	alert[0x33]	13	1			T113	2		T198	1		T302	1
alert_ping_fail	alert[0x34]	12	1			T14	1		T16	1		T298	1
alert_ping_fail	alert[0x35]	17	1			T14	1		T290	1		T198	1
alert_ping_fail	alert[0x36]	8	1			T16	1		T239	1		T311	1
alert_ping_fail	alert[0x37]	7	1			T298	1		T266	1		T304	1
alert_ping_fail	alert[0x38]	9	1			T15	1		T113	1		T298	1
alert_ping_fail	alert[0x39]	12	1			T317	1		T298	1		T300	1
alert_ping_fail	alert[0x3a]	9	1			T290	1		T266	1		T314	1
alert_ping_fail	alert[0x3b]	3	1			T269	1		T318	1		T312	1
alert_ping_fail	alert[0x3c]	8	1			T14	1		T198	1		T239	1
alert_ping_fail	alert[0x3d]	13	1			T298	1		T307	1		T269	1
alert_ping_fail	alert[0x3e]	8	1			T317	1		T113	1		T302	1
alert_ping_fail	alert[0x3f]	5	1			T198	1		T318	1		T319	1
alert_ping_fail	alert[0x40]	2	1			T295	1		T320	1		-	-

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	104832	1			T5	1		T23	66		T68	10103
alert_integrity_fail	class_i[0x1]	79149	1			T11	4073		T18	6016		T23	6032
alert_integrity_fail	class_i[0x2]	93555	1			T11	3		T4	5		T5	2
alert_integrity_fail	class_i[0x3]	88708	1			T3	1		T11	6		T5	7
alert_ping_fail	class_i[0x0]	173	1			T16	2		T64	7		T285	3
alert_ping_fail	class_i[0x1]	159	1			T14	14		T15	1		T113	1
alert_ping_fail	class_i[0x2]	131	1			T14	2		T16	7		T123	3
alert_ping_fail	class_i[0x3]	170	1			T15	15		T16	1		T122	2