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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.26 99.99 98.69 97.09 100.00 100.00 99.38 99.64


Total test records in report: 826
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T770 /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.1682350742 Aug 01 06:26:23 PM PDT 24 Aug 01 06:26:24 PM PDT 24 9086107 ps
T771 /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.2087762521 Aug 01 06:26:34 PM PDT 24 Aug 01 06:26:36 PM PDT 24 15492558 ps
T772 /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.1173378649 Aug 01 06:26:20 PM PDT 24 Aug 01 06:26:24 PM PDT 24 37395727 ps
T773 /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.3365915710 Aug 01 06:26:21 PM PDT 24 Aug 01 06:26:23 PM PDT 24 12723803 ps
T774 /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.441947387 Aug 01 06:26:19 PM PDT 24 Aug 01 06:26:32 PM PDT 24 147220357 ps
T775 /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.292192135 Aug 01 06:26:17 PM PDT 24 Aug 01 06:26:30 PM PDT 24 189247784 ps
T776 /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.2596657768 Aug 01 06:26:32 PM PDT 24 Aug 01 06:26:34 PM PDT 24 41564512 ps
T777 /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.3399801216 Aug 01 06:26:23 PM PDT 24 Aug 01 06:26:25 PM PDT 24 6148646 ps
T778 /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.3190646152 Aug 01 06:26:32 PM PDT 24 Aug 01 06:26:33 PM PDT 24 18160521 ps
T156 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.4127757992 Aug 01 06:26:17 PM PDT 24 Aug 01 06:31:01 PM PDT 24 8785008800 ps
T779 /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.3831639008 Aug 01 06:26:17 PM PDT 24 Aug 01 06:26:19 PM PDT 24 17559147 ps
T158 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.2059336543 Aug 01 06:26:24 PM PDT 24 Aug 01 06:32:06 PM PDT 24 2253593962 ps
T780 /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.2105289591 Aug 01 06:26:58 PM PDT 24 Aug 01 06:26:59 PM PDT 24 9057820 ps
T781 /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.2303157049 Aug 01 06:26:15 PM PDT 24 Aug 01 06:26:38 PM PDT 24 1440029724 ps
T180 /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.1157495319 Aug 01 06:26:18 PM PDT 24 Aug 01 06:27:02 PM PDT 24 629920951 ps
T154 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.4155978662 Aug 01 06:26:14 PM PDT 24 Aug 01 06:31:24 PM PDT 24 25425574341 ps
T782 /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.1112786016 Aug 01 06:26:15 PM PDT 24 Aug 01 06:26:20 PM PDT 24 35797870 ps
T155 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.4126885585 Aug 01 06:26:23 PM PDT 24 Aug 01 06:35:31 PM PDT 24 17494961009 ps
T783 /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.1466046334 Aug 01 06:26:13 PM PDT 24 Aug 01 06:29:08 PM PDT 24 11431896614 ps
T147 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.3220602906 Aug 01 06:26:18 PM PDT 24 Aug 01 06:28:16 PM PDT 24 3441813801 ps
T784 /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.1534489896 Aug 01 06:26:29 PM PDT 24 Aug 01 06:26:30 PM PDT 24 14732706 ps
T785 /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.1251185835 Aug 01 06:26:26 PM PDT 24 Aug 01 06:26:31 PM PDT 24 292564691 ps
T786 /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.170329373 Aug 01 06:26:21 PM PDT 24 Aug 01 06:27:08 PM PDT 24 1908197419 ps
T787 /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.2144215231 Aug 01 06:26:55 PM PDT 24 Aug 01 06:26:57 PM PDT 24 47798060 ps
T788 /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.4258123550 Aug 01 06:26:31 PM PDT 24 Aug 01 06:26:32 PM PDT 24 71105785 ps
T161 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.3296509249 Aug 01 06:26:13 PM PDT 24 Aug 01 06:28:40 PM PDT 24 2165304356 ps
T789 /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.1414643952 Aug 01 06:26:38 PM PDT 24 Aug 01 06:26:40 PM PDT 24 43988443 ps
T790 /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.3444780688 Aug 01 06:26:12 PM PDT 24 Aug 01 06:26:21 PM PDT 24 107169369 ps
T153 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.4154448578 Aug 01 06:26:13 PM PDT 24 Aug 01 06:32:31 PM PDT 24 8573601215 ps
T791 /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.4054902414 Aug 01 06:26:22 PM PDT 24 Aug 01 06:27:11 PM PDT 24 5515695438 ps
T164 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.4288880807 Aug 01 06:26:35 PM PDT 24 Aug 01 06:31:19 PM PDT 24 13367408177 ps
T792 /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.3164976463 Aug 01 06:26:15 PM PDT 24 Aug 01 06:26:16 PM PDT 24 15749432 ps
T793 /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.2353544328 Aug 01 06:26:25 PM PDT 24 Aug 01 06:26:27 PM PDT 24 7624735 ps
T794 /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.634522154 Aug 01 06:26:26 PM PDT 24 Aug 01 06:26:35 PM PDT 24 95600794 ps
T184 /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.1451722395 Aug 01 06:26:29 PM PDT 24 Aug 01 06:26:32 PM PDT 24 35977672 ps
T795 /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.3932750750 Aug 01 06:26:26 PM PDT 24 Aug 01 06:27:05 PM PDT 24 1878623228 ps
T182 /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.2978584260 Aug 01 06:26:22 PM PDT 24 Aug 01 06:26:26 PM PDT 24 140019011 ps
T796 /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.2392645888 Aug 01 06:26:14 PM PDT 24 Aug 01 06:26:20 PM PDT 24 292056073 ps
T163 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.3455701599 Aug 01 06:26:17 PM PDT 24 Aug 01 06:29:00 PM PDT 24 43952950158 ps
T797 /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.2905815683 Aug 01 06:26:14 PM PDT 24 Aug 01 06:26:16 PM PDT 24 10554910 ps
T798 /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.2629995162 Aug 01 06:26:09 PM PDT 24 Aug 01 06:26:11 PM PDT 24 6399506 ps
T799 /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.1278145037 Aug 01 06:26:37 PM PDT 24 Aug 01 06:26:38 PM PDT 24 17108002 ps
T800 /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.4187778547 Aug 01 06:26:12 PM PDT 24 Aug 01 06:26:20 PM PDT 24 102396229 ps
T801 /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.2945435647 Aug 01 06:26:23 PM PDT 24 Aug 01 06:26:39 PM PDT 24 450798393 ps
T802 /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.2207624944 Aug 01 06:26:24 PM PDT 24 Aug 01 06:26:45 PM PDT 24 1097211646 ps
T803 /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.3321016004 Aug 01 06:26:10 PM PDT 24 Aug 01 06:26:47 PM PDT 24 511908661 ps
T804 /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.2691935966 Aug 01 06:26:30 PM PDT 24 Aug 01 06:26:38 PM PDT 24 210286185 ps
T805 /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.866393271 Aug 01 06:26:21 PM PDT 24 Aug 01 06:27:02 PM PDT 24 1994492191 ps
T806 /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.3007132185 Aug 01 06:26:33 PM PDT 24 Aug 01 06:26:35 PM PDT 24 6378850 ps
T807 /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.3256104955 Aug 01 06:26:13 PM PDT 24 Aug 01 06:26:19 PM PDT 24 129841671 ps
T165 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.1543911898 Aug 01 06:26:16 PM PDT 24 Aug 01 06:29:34 PM PDT 24 6600697415 ps
T160 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.2858606768 Aug 01 06:26:30 PM PDT 24 Aug 01 06:30:59 PM PDT 24 20412263125 ps
T808 /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.2566978479 Aug 01 06:26:13 PM PDT 24 Aug 01 06:26:19 PM PDT 24 62035184 ps
T809 /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.1796152593 Aug 01 06:26:31 PM PDT 24 Aug 01 06:26:36 PM PDT 24 62953383 ps
T144 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.405006400 Aug 01 06:26:27 PM PDT 24 Aug 01 06:32:51 PM PDT 24 5903159253 ps
T810 /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.4191922776 Aug 01 06:26:26 PM PDT 24 Aug 01 06:26:28 PM PDT 24 10040328 ps
T811 /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.4051430202 Aug 01 06:26:07 PM PDT 24 Aug 01 06:27:23 PM PDT 24 552455582 ps
T812 /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.2546972406 Aug 01 06:26:26 PM PDT 24 Aug 01 06:26:38 PM PDT 24 737662344 ps
T813 /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.1444206620 Aug 01 06:26:19 PM PDT 24 Aug 01 06:26:27 PM PDT 24 280092873 ps
T183 /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.689223190 Aug 01 06:26:25 PM PDT 24 Aug 01 06:26:29 PM PDT 24 120132869 ps
T814 /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.802822411 Aug 01 06:26:10 PM PDT 24 Aug 01 06:26:24 PM PDT 24 255921564 ps
T815 /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.450209046 Aug 01 06:26:17 PM PDT 24 Aug 01 06:26:24 PM PDT 24 73280669 ps
T816 /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.3187052012 Aug 01 06:26:24 PM PDT 24 Aug 01 06:26:26 PM PDT 24 34650992 ps
T817 /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.3444636268 Aug 01 06:26:17 PM PDT 24 Aug 01 06:28:52 PM PDT 24 14436020091 ps
T818 /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.2369281205 Aug 01 06:26:13 PM PDT 24 Aug 01 06:27:29 PM PDT 24 575230089 ps
T819 /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.11877553 Aug 01 06:26:26 PM PDT 24 Aug 01 06:26:29 PM PDT 24 25948720 ps
T820 /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.2538037427 Aug 01 06:26:25 PM PDT 24 Aug 01 06:26:47 PM PDT 24 1213354683 ps
T821 /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.1628133162 Aug 01 06:26:22 PM PDT 24 Aug 01 06:26:23 PM PDT 24 7253977 ps
T175 /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.2500730729 Aug 01 06:26:15 PM PDT 24 Aug 01 06:26:18 PM PDT 24 354398627 ps
T822 /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.869844110 Aug 01 06:26:31 PM PDT 24 Aug 01 06:26:33 PM PDT 24 16454366 ps
T823 /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.971798285 Aug 01 06:26:36 PM PDT 24 Aug 01 06:26:37 PM PDT 24 10781900 ps
T167 /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.3745695573 Aug 01 06:26:07 PM PDT 24 Aug 01 06:32:06 PM PDT 24 17473426087 ps
T824 /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.321613158 Aug 01 06:26:25 PM PDT 24 Aug 01 06:26:33 PM PDT 24 51618700 ps
T166 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.3575118840 Aug 01 06:26:27 PM PDT 24 Aug 01 06:30:56 PM PDT 24 3861448136 ps
T825 /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.461001505 Aug 01 06:26:30 PM PDT 24 Aug 01 06:26:32 PM PDT 24 11062746 ps
T826 /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.2619247232 Aug 01 06:26:16 PM PDT 24 Aug 01 06:26:21 PM PDT 24 32466695 ps

Test location /workspace/coverage/default/14.alert_handler_entropy.557330203
Short name T3
Test name
Test status
Simulation time 57148453219 ps
CPU time 1762.52 seconds
Started Aug 01 05:40:38 PM PDT 24
Finished Aug 01 06:10:01 PM PDT 24
Peak memory 283696 kb
Host smart-244226a3-e0fd-40d3-8cda-553d6f22bcf8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557330203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.557330203
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.732224446
Short name T23
Test name
Test status
Simulation time 250941284704 ps
CPU time 3467.09 seconds
Started Aug 01 05:39:34 PM PDT 24
Finished Aug 01 06:37:22 PM PDT 24
Peak memory 303424 kb
Host smart-5464b851-ef5b-4aaf-a053-d4b499d5ab7f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732224446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_hand
ler_stress_all.732224446
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.2871617805
Short name T80
Test name
Test status
Simulation time 235504033058 ps
CPU time 5116.4 seconds
Started Aug 01 05:42:47 PM PDT 24
Finished Aug 01 07:08:04 PM PDT 24
Peak memory 315996 kb
Host smart-d465bd66-a876-4e3c-97bf-c38ceafd8086
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871617805 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.2871617805
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.3795598597
Short name T8
Test name
Test status
Simulation time 327048655 ps
CPU time 11.63 seconds
Started Aug 01 05:39:49 PM PDT 24
Finished Aug 01 05:40:01 PM PDT 24
Peak memory 269556 kb
Host smart-1747b513-2e80-4d44-8cd2-a13748a2dacb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3795598597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.3795598597
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.1688832062
Short name T168
Test name
Test status
Simulation time 2189367387 ps
CPU time 36.03 seconds
Started Aug 01 06:26:26 PM PDT 24
Finished Aug 01 06:27:02 PM PDT 24
Peak memory 240704 kb
Host smart-a9b4e904-cf2c-49f7-a0b4-4cc1807ae07f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1688832062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.1688832062
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.3159847284
Short name T4
Test name
Test status
Simulation time 1488268942511 ps
CPU time 4368.24 seconds
Started Aug 01 05:40:38 PM PDT 24
Finished Aug 01 06:53:27 PM PDT 24
Peak memory 305068 kb
Host smart-b87a4d94-e62c-4e3c-80e7-0f8a46951f0a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159847284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.3159847284
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.2656148205
Short name T110
Test name
Test status
Simulation time 43949438443 ps
CPU time 2340.17 seconds
Started Aug 01 05:41:06 PM PDT 24
Finished Aug 01 06:20:06 PM PDT 24
Peak memory 287316 kb
Host smart-e9037850-0002-4f11-b7e3-7a3aedf3dd79
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656148205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.2656148205
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.3615595377
Short name T129
Test name
Test status
Simulation time 4675597678 ps
CPU time 682.75 seconds
Started Aug 01 06:26:21 PM PDT 24
Finished Aug 01 06:37:44 PM PDT 24
Peak memory 273636 kb
Host smart-30e4b939-ad38-48f6-8277-766d35de453a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615595377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.3615595377
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.2303630792
Short name T93
Test name
Test status
Simulation time 167980646625 ps
CPU time 2591.43 seconds
Started Aug 01 05:43:12 PM PDT 24
Finished Aug 01 06:26:24 PM PDT 24
Peak memory 304792 kb
Host smart-d37e463a-7014-4d83-b98c-927ceb29dc77
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303630792 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.2303630792
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.1156893554
Short name T285
Test name
Test status
Simulation time 294992170568 ps
CPU time 2897.25 seconds
Started Aug 01 05:39:49 PM PDT 24
Finished Aug 01 06:28:06 PM PDT 24
Peak memory 288992 kb
Host smart-c71df9ed-d345-4fe0-bb38-f5014f333923
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156893554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.1156893554
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.60610308
Short name T33
Test name
Test status
Simulation time 69002232080 ps
CPU time 2088.99 seconds
Started Aug 01 05:42:58 PM PDT 24
Finished Aug 01 06:17:48 PM PDT 24
Peak memory 286044 kb
Host smart-51aea1d9-627b-4f9c-8670-a20518906479
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60610308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.60610308
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.1106289156
Short name T142
Test name
Test status
Simulation time 18277266157 ps
CPU time 644.23 seconds
Started Aug 01 06:26:26 PM PDT 24
Finished Aug 01 06:37:11 PM PDT 24
Peak memory 265584 kb
Host smart-29d96406-5fed-4fe1-82ec-746fae5b38e2
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106289156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.1106289156
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.3644898248
Short name T55
Test name
Test status
Simulation time 69998949810 ps
CPU time 4003.34 seconds
Started Aug 01 05:41:01 PM PDT 24
Finished Aug 01 06:47:45 PM PDT 24
Peak memory 301668 kb
Host smart-e0dd52b7-ca99-4704-8e6a-1ac4a8d82427
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644898248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.3644898248
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.4116098940
Short name T130
Test name
Test status
Simulation time 174432152796 ps
CPU time 992.67 seconds
Started Aug 01 06:26:22 PM PDT 24
Finished Aug 01 06:42:55 PM PDT 24
Peak memory 265784 kb
Host smart-b6df4afa-ad4a-4f3a-92c5-a21e8b89a213
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116098940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.4116098940
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.1151210097
Short name T11
Test name
Test status
Simulation time 177434923042 ps
CPU time 2217.66 seconds
Started Aug 01 05:43:43 PM PDT 24
Finished Aug 01 06:20:41 PM PDT 24
Peak memory 287072 kb
Host smart-5d17667d-e07f-4071-85a1-be4447f96c1f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151210097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.1151210097
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.2150257708
Short name T83
Test name
Test status
Simulation time 30779946189 ps
CPU time 1524.72 seconds
Started Aug 01 05:41:51 PM PDT 24
Finished Aug 01 06:07:16 PM PDT 24
Peak memory 289272 kb
Host smart-378f4f3a-f8a0-4b32-b09f-b7ae0d473a51
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150257708 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.2150257708
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.2398527940
Short name T135
Test name
Test status
Simulation time 3766078864 ps
CPU time 300.53 seconds
Started Aug 01 06:26:13 PM PDT 24
Finished Aug 01 06:31:14 PM PDT 24
Peak memory 265524 kb
Host smart-243b9532-e734-49e0-a7d4-39aa8efce3c0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2398527940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.2398527940
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.3934465085
Short name T15
Test name
Test status
Simulation time 10316103331 ps
CPU time 428.93 seconds
Started Aug 01 05:43:16 PM PDT 24
Finished Aug 01 05:50:25 PM PDT 24
Peak memory 248300 kb
Host smart-c9a8f694-e6aa-4e6e-b58e-762cefbd5ae4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934465085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.3934465085
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.1569324258
Short name T249
Test name
Test status
Simulation time 51861255723 ps
CPU time 2830.33 seconds
Started Aug 01 05:40:35 PM PDT 24
Finished Aug 01 06:27:46 PM PDT 24
Peak memory 288476 kb
Host smart-de210fcd-7420-42d7-9eee-f8871efd4657
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569324258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.1569324258
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.742313773
Short name T376
Test name
Test status
Simulation time 10784061 ps
CPU time 1.3 seconds
Started Aug 01 06:26:24 PM PDT 24
Finished Aug 01 06:26:26 PM PDT 24
Peak memory 237704 kb
Host smart-2a970c7e-b87d-4db6-bb54-c174f6f7da9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=742313773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.742313773
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.1543911898
Short name T165
Test name
Test status
Simulation time 6600697415 ps
CPU time 197.02 seconds
Started Aug 01 06:26:16 PM PDT 24
Finished Aug 01 06:29:34 PM PDT 24
Peak memory 273676 kb
Host smart-7afbe1f5-abd8-4fab-aa69-8b63c5ea5a4c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1543911898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.1543911898
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.1688924125
Short name T29
Test name
Test status
Simulation time 17468099057 ps
CPU time 1904.27 seconds
Started Aug 01 05:40:02 PM PDT 24
Finished Aug 01 06:11:46 PM PDT 24
Peak memory 305020 kb
Host smart-50e34e4d-143a-4a26-9c1a-b24475d646fe
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688924125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.1688924125
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.2117009667
Short name T298
Test name
Test status
Simulation time 14174570952 ps
CPU time 596.52 seconds
Started Aug 01 05:40:42 PM PDT 24
Finished Aug 01 05:50:39 PM PDT 24
Peak memory 248084 kb
Host smart-a7f75e85-0ee3-4e7d-8830-327445cc7c77
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117009667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.2117009667
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.301899386
Short name T118
Test name
Test status
Simulation time 45690829266 ps
CPU time 2506.49 seconds
Started Aug 01 05:41:32 PM PDT 24
Finished Aug 01 06:23:19 PM PDT 24
Peak memory 289248 kb
Host smart-a6de5906-530b-4cd1-b5ef-e1adcefb05b3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301899386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.301899386
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.3859260061
Short name T131
Test name
Test status
Simulation time 4419797733 ps
CPU time 636.47 seconds
Started Aug 01 06:26:24 PM PDT 24
Finished Aug 01 06:37:01 PM PDT 24
Peak memory 265604 kb
Host smart-b0281537-e385-4e63-a8c6-3fc608cc0cc8
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859260061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.3859260061
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.446884718
Short name T34
Test name
Test status
Simulation time 45437276972 ps
CPU time 1102.8 seconds
Started Aug 01 05:42:30 PM PDT 24
Finished Aug 01 06:00:53 PM PDT 24
Peak memory 288264 kb
Host smart-42f3c38f-318f-4119-b8d9-7cb3105272bc
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446884718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_han
dler_stress_all.446884718
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.1874807015
Short name T351
Test name
Test status
Simulation time 317917417785 ps
CPU time 2253.45 seconds
Started Aug 01 05:40:07 PM PDT 24
Finished Aug 01 06:17:41 PM PDT 24
Peak memory 281744 kb
Host smart-df803e79-3a21-4750-8b00-0d005045d532
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874807015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.1874807015
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.657437536
Short name T291
Test name
Test status
Simulation time 11877544732 ps
CPU time 469.55 seconds
Started Aug 01 05:41:46 PM PDT 24
Finished Aug 01 05:49:36 PM PDT 24
Peak memory 248248 kb
Host smart-10d256e2-fa98-4e12-ac85-614e7f32b2cb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657437536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.657437536
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.3001343510
Short name T140
Test name
Test status
Simulation time 3084759728 ps
CPU time 206 seconds
Started Aug 01 06:26:27 PM PDT 24
Finished Aug 01 06:29:53 PM PDT 24
Peak memory 265608 kb
Host smart-21adb3f2-692d-459a-ae29-821c655a2682
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3001343510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.3001343510
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.3963420879
Short name T65
Test name
Test status
Simulation time 10243487956 ps
CPU time 1073.73 seconds
Started Aug 01 05:41:23 PM PDT 24
Finished Aug 01 05:59:17 PM PDT 24
Peak memory 280884 kb
Host smart-d746f0fb-8adf-472a-9bc1-953c80ad76ce
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963420879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.3963420879
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.1856195514
Short name T67
Test name
Test status
Simulation time 21371939028 ps
CPU time 806.71 seconds
Started Aug 01 05:43:13 PM PDT 24
Finished Aug 01 05:56:40 PM PDT 24
Peak memory 272580 kb
Host smart-55ae9d43-a094-4439-b334-f1a5ce5813da
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856195514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.1856195514
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.4269582439
Short name T54
Test name
Test status
Simulation time 257439292085 ps
CPU time 4113.37 seconds
Started Aug 01 05:40:18 PM PDT 24
Finished Aug 01 06:48:52 PM PDT 24
Peak memory 304100 kb
Host smart-9e1326dd-9a7b-439f-80c2-078424f8f9fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269582439 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.4269582439
Directory /workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.3575118840
Short name T166
Test name
Test status
Simulation time 3861448136 ps
CPU time 269.55 seconds
Started Aug 01 06:26:27 PM PDT 24
Finished Aug 01 06:30:56 PM PDT 24
Peak memory 265780 kb
Host smart-49a2c498-2f42-4c0b-aae6-7aa1f668aada
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3575118840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.3575118840
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.2237634407
Short name T240
Test name
Test status
Simulation time 300251658495 ps
CPU time 2982.52 seconds
Started Aug 01 05:43:01 PM PDT 24
Finished Aug 01 06:32:44 PM PDT 24
Peak memory 289212 kb
Host smart-fd51a53e-23d2-44a2-94ed-01baae5c03a2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237634407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.2237634407
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.3532257552
Short name T319
Test name
Test status
Simulation time 15164997272 ps
CPU time 314.1 seconds
Started Aug 01 05:41:04 PM PDT 24
Finished Aug 01 05:46:19 PM PDT 24
Peak memory 248152 kb
Host smart-594cad04-5899-49ed-87ed-a295f2b78676
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532257552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.3532257552
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.2702097031
Short name T301
Test name
Test status
Simulation time 11043321759 ps
CPU time 451.77 seconds
Started Aug 01 05:41:41 PM PDT 24
Finished Aug 01 05:49:13 PM PDT 24
Peak memory 248332 kb
Host smart-184d1849-84c7-44d5-88fc-3b53398084f9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702097031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.2702097031
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.596306953
Short name T369
Test name
Test status
Simulation time 44211605381 ps
CPU time 2364.56 seconds
Started Aug 01 05:43:23 PM PDT 24
Finished Aug 01 06:22:48 PM PDT 24
Peak memory 286684 kb
Host smart-6b8409b1-4155-415f-8cc4-a3123e4f6823
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596306953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.596306953
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.2978584260
Short name T182
Test name
Test status
Simulation time 140019011 ps
CPU time 3.63 seconds
Started Aug 01 06:26:22 PM PDT 24
Finished Aug 01 06:26:26 PM PDT 24
Peak memory 238148 kb
Host smart-df05c655-857c-4ae4-adfb-628ff203c1b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2978584260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.2978584260
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.873557381
Short name T97
Test name
Test status
Simulation time 293140627834 ps
CPU time 4093.47 seconds
Started Aug 01 05:42:35 PM PDT 24
Finished Aug 01 06:50:49 PM PDT 24
Peak memory 297176 kb
Host smart-4e7c9a3a-a556-42d1-b882-528ddba0d6f5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873557381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_han
dler_stress_all.873557381
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.3357820079
Short name T139
Test name
Test status
Simulation time 12853134416 ps
CPU time 968.01 seconds
Started Aug 01 06:26:07 PM PDT 24
Finished Aug 01 06:42:15 PM PDT 24
Peak memory 265680 kb
Host smart-20b248e6-07ef-4db7-a7e0-c44035e6a2d1
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357820079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.3357820079
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.1608278308
Short name T251
Test name
Test status
Simulation time 31526040 ps
CPU time 1.41 seconds
Started Aug 01 06:26:28 PM PDT 24
Finished Aug 01 06:26:30 PM PDT 24
Peak memory 236760 kb
Host smart-19b04797-611f-45b8-a685-ab0262fedea9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1608278308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.1608278308
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.1747508680
Short name T555
Test name
Test status
Simulation time 18664393825 ps
CPU time 212.62 seconds
Started Aug 01 05:43:00 PM PDT 24
Finished Aug 01 05:46:33 PM PDT 24
Peak memory 248212 kb
Host smart-5a63c04e-211d-4aa5-896c-0918e2fde519
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747508680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.1747508680
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.2619607591
Short name T128
Test name
Test status
Simulation time 1922096354 ps
CPU time 157.51 seconds
Started Aug 01 06:26:27 PM PDT 24
Finished Aug 01 06:29:05 PM PDT 24
Peak memory 267012 kb
Host smart-0c522c61-d246-4752-954d-c547869091a6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2619607591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.2619607591
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.3134170068
Short name T157
Test name
Test status
Simulation time 23192073747 ps
CPU time 459.34 seconds
Started Aug 01 06:26:30 PM PDT 24
Finished Aug 01 06:34:10 PM PDT 24
Peak memory 265036 kb
Host smart-89a6c253-9aa7-469b-84c4-155693c6d6fb
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134170068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.3134170068
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.3361809231
Short name T332
Test name
Test status
Simulation time 36277351850 ps
CPU time 2211.59 seconds
Started Aug 01 05:40:41 PM PDT 24
Finished Aug 01 06:17:33 PM PDT 24
Peak memory 289264 kb
Host smart-946407a1-53f0-46e8-b38d-2f7053b77d3a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361809231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.3361809231
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.1065796198
Short name T85
Test name
Test status
Simulation time 238241401847 ps
CPU time 3816.85 seconds
Started Aug 01 05:40:44 PM PDT 24
Finished Aug 01 06:44:21 PM PDT 24
Peak memory 300204 kb
Host smart-413bdb39-d23e-4b7e-9cde-7fb608ddd4a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065796198 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.1065796198
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.1335523450
Short name T364
Test name
Test status
Simulation time 190364413716 ps
CPU time 2561.88 seconds
Started Aug 01 05:44:28 PM PDT 24
Finished Aug 01 06:27:10 PM PDT 24
Peak memory 284112 kb
Host smart-8b647817-5e8d-427f-8843-5f54fc23dc09
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335523450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.1335523450
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.1817854053
Short name T271
Test name
Test status
Simulation time 33042024997 ps
CPU time 1337.37 seconds
Started Aug 01 05:42:33 PM PDT 24
Finished Aug 01 06:04:51 PM PDT 24
Peak memory 288548 kb
Host smart-adc61561-1283-4d08-b34a-4cfd250f8736
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817854053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.1817854053
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.2958218949
Short name T134
Test name
Test status
Simulation time 4657106184 ps
CPU time 311.32 seconds
Started Aug 01 06:26:26 PM PDT 24
Finished Aug 01 06:31:38 PM PDT 24
Peak memory 265616 kb
Host smart-076a6fae-112d-4873-a47f-003c0b5cbcd4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2958218949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.2958218949
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.3395209813
Short name T346
Test name
Test status
Simulation time 9174568254 ps
CPU time 58.18 seconds
Started Aug 01 05:40:47 PM PDT 24
Finished Aug 01 05:41:46 PM PDT 24
Peak memory 247808 kb
Host smart-2997db16-3f4d-4deb-a164-2dff91857ea9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33952
09813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.3395209813
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.3550246250
Short name T100
Test name
Test status
Simulation time 630110814 ps
CPU time 16.61 seconds
Started Aug 01 05:39:51 PM PDT 24
Finished Aug 01 05:40:08 PM PDT 24
Peak memory 247700 kb
Host smart-af0523b2-ccc4-4006-b9cd-c0d40d98ff51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35502
46250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.3550246250
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.2222623969
Short name T176
Test name
Test status
Simulation time 312850239 ps
CPU time 43.59 seconds
Started Aug 01 06:26:15 PM PDT 24
Finished Aug 01 06:26:59 PM PDT 24
Peak memory 237804 kb
Host smart-6ad6f907-3f93-4604-9941-04adc79f2e0f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2222623969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.2222623969
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.1013296211
Short name T223
Test name
Test status
Simulation time 27611142 ps
CPU time 2.44 seconds
Started Aug 01 05:39:34 PM PDT 24
Finished Aug 01 05:39:37 PM PDT 24
Peak memory 248584 kb
Host smart-158060ca-3975-4c20-a717-a9bf3afbb25c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1013296211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.1013296211
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.1385679886
Short name T215
Test name
Test status
Simulation time 16937329 ps
CPU time 2.66 seconds
Started Aug 01 05:39:49 PM PDT 24
Finished Aug 01 05:39:51 PM PDT 24
Peak memory 248540 kb
Host smart-fb7c8039-78d2-4fa7-bdb0-fb09b09eb1f8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1385679886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.1385679886
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.112127626
Short name T221
Test name
Test status
Simulation time 59438696 ps
CPU time 2.96 seconds
Started Aug 01 05:40:17 PM PDT 24
Finished Aug 01 05:40:21 PM PDT 24
Peak memory 248420 kb
Host smart-ec079cc8-bb74-45bf-a7b7-cbdaf83fc8ee
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=112127626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.112127626
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.8325126
Short name T229
Test name
Test status
Simulation time 15164166 ps
CPU time 2.68 seconds
Started Aug 01 05:39:56 PM PDT 24
Finished Aug 01 05:39:58 PM PDT 24
Peak memory 248524 kb
Host smart-0aecafa0-3c09-46c3-96d7-5c86a5e2bfdd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=8325126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.8325126
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.3932345618
Short name T146
Test name
Test status
Simulation time 14746953073 ps
CPU time 301.71 seconds
Started Aug 01 06:26:15 PM PDT 24
Finished Aug 01 06:31:17 PM PDT 24
Peak memory 270568 kb
Host smart-0e28ecef-3519-4f8e-a56b-1577f0c82952
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3932345618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.3932345618
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.902293020
Short name T360
Test name
Test status
Simulation time 90448896654 ps
CPU time 1816.91 seconds
Started Aug 01 05:39:37 PM PDT 24
Finished Aug 01 06:09:54 PM PDT 24
Peak memory 289116 kb
Host smart-d4655492-2c83-4289-90e5-2dbfc287f874
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902293020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.902293020
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.1299147797
Short name T324
Test name
Test status
Simulation time 192629993338 ps
CPU time 2595.02 seconds
Started Aug 01 05:41:10 PM PDT 24
Finished Aug 01 06:24:26 PM PDT 24
Peak memory 289264 kb
Host smart-8946a27d-252e-4010-8f8e-73f37f08ef03
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299147797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.1299147797
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.3818456776
Short name T53
Test name
Test status
Simulation time 1866683967 ps
CPU time 29.89 seconds
Started Aug 01 05:43:13 PM PDT 24
Finished Aug 01 05:43:43 PM PDT 24
Peak memory 247464 kb
Host smart-5bc47fe7-9375-40b7-91fd-df5d9b426b65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38184
56776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.3818456776
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.2209610663
Short name T266
Test name
Test status
Simulation time 5976734232 ps
CPU time 258.22 seconds
Started Aug 01 05:43:58 PM PDT 24
Finished Aug 01 05:48:16 PM PDT 24
Peak memory 247124 kb
Host smart-08bd7ba8-12bf-42be-8d54-64ad0af53d9c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209610663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.2209610663
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.3043785471
Short name T263
Test name
Test status
Simulation time 3789262653 ps
CPU time 50.37 seconds
Started Aug 01 05:39:54 PM PDT 24
Finished Aug 01 05:40:44 PM PDT 24
Peak memory 256140 kb
Host smart-52b874eb-a4f0-45de-bff8-b204f5b38c66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30437
85471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.3043785471
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.477485468
Short name T339
Test name
Test status
Simulation time 142479691314 ps
CPU time 4186.67 seconds
Started Aug 01 05:40:14 PM PDT 24
Finished Aug 01 06:50:01 PM PDT 24
Peak memory 370640 kb
Host smart-8f88d063-7c1b-45c7-b519-9a444dc01a6b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477485468 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.477485468
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.3417935512
Short name T149
Test name
Test status
Simulation time 6034549591 ps
CPU time 470.31 seconds
Started Aug 01 06:26:17 PM PDT 24
Finished Aug 01 06:34:08 PM PDT 24
Peak memory 272924 kb
Host smart-8b8c230c-430b-4d17-b78d-d94543802173
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417935512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.3417935512
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.3505585158
Short name T377
Test name
Test status
Simulation time 10195021 ps
CPU time 1.47 seconds
Started Aug 01 06:26:29 PM PDT 24
Finished Aug 01 06:26:31 PM PDT 24
Peak memory 237100 kb
Host smart-567af4ff-6582-4af3-8657-dbfc5de70251
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3505585158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.3505585158
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.509841772
Short name T342
Test name
Test status
Simulation time 3592489378 ps
CPU time 46.28 seconds
Started Aug 01 05:39:36 PM PDT 24
Finished Aug 01 05:40:23 PM PDT 24
Peak memory 255972 kb
Host smart-00afd178-4d7e-4634-8168-46bdfcec1575
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50984
1772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.509841772
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.3576391267
Short name T295
Test name
Test status
Simulation time 7503952983 ps
CPU time 279.09 seconds
Started Aug 01 05:39:50 PM PDT 24
Finished Aug 01 05:44:29 PM PDT 24
Peak memory 248252 kb
Host smart-dd44119e-e09f-4a1b-9114-2936eb863e53
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576391267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.3576391267
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.3395659549
Short name T350
Test name
Test status
Simulation time 108273255001 ps
CPU time 2951.02 seconds
Started Aug 01 05:40:20 PM PDT 24
Finished Aug 01 06:29:31 PM PDT 24
Peak memory 288420 kb
Host smart-fb3ee8ae-a01a-47a2-851c-bed21bc401bc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395659549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.3395659549
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.878277020
Short name T353
Test name
Test status
Simulation time 53906574826 ps
CPU time 1100.98 seconds
Started Aug 01 05:40:44 PM PDT 24
Finished Aug 01 05:59:05 PM PDT 24
Peak memory 272820 kb
Host smart-97dc42f1-9ef7-43ca-983f-b1cdbadcf0ab
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878277020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.878277020
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.1783938174
Short name T305
Test name
Test status
Simulation time 32267742732 ps
CPU time 369.21 seconds
Started Aug 01 05:40:47 PM PDT 24
Finished Aug 01 05:46:56 PM PDT 24
Peak memory 254940 kb
Host smart-aac97b95-dcaf-4d07-9adf-725928f8521a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783938174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.1783938174
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.3736461809
Short name T318
Test name
Test status
Simulation time 1958124126 ps
CPU time 89.13 seconds
Started Aug 01 05:40:42 PM PDT 24
Finished Aug 01 05:42:12 PM PDT 24
Peak memory 248260 kb
Host smart-88f5b4ba-6128-4c09-8810-a5a911b3401c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736461809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.3736461809
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.2243223981
Short name T52
Test name
Test status
Simulation time 51139888239 ps
CPU time 4398.89 seconds
Started Aug 01 05:39:48 PM PDT 24
Finished Aug 01 06:53:08 PM PDT 24
Peak memory 321748 kb
Host smart-510fca69-ad77-4d32-9c17-8243cb5a61c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243223981 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.2243223981
Directory /workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.2076119527
Short name T326
Test name
Test status
Simulation time 243711927663 ps
CPU time 3756.87 seconds
Started Aug 01 05:43:25 PM PDT 24
Finished Aug 01 06:46:02 PM PDT 24
Peak memory 297104 kb
Host smart-7c84a9b9-7f25-43a3-b5e5-bfe399287a6e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076119527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.2076119527
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.2650381663
Short name T272
Test name
Test status
Simulation time 54020237209 ps
CPU time 1895.65 seconds
Started Aug 01 05:41:43 PM PDT 24
Finished Aug 01 06:13:19 PM PDT 24
Peak memory 272816 kb
Host smart-851e1e1a-44b4-4ced-b6e8-bbd8a4f78f20
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650381663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.2650381663
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.4116879013
Short name T284
Test name
Test status
Simulation time 1307530375 ps
CPU time 26.44 seconds
Started Aug 01 05:43:13 PM PDT 24
Finished Aug 01 05:43:40 PM PDT 24
Peak memory 247736 kb
Host smart-17b67a04-7a0d-4ad2-8c08-3da4da8fe6d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41168
79013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.4116879013
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all_with_rand_reset.4034794404
Short name T92
Test name
Test status
Simulation time 325668726764 ps
CPU time 2028.79 seconds
Started Aug 01 05:41:37 PM PDT 24
Finished Aug 01 06:15:26 PM PDT 24
Peak memory 305756 kb
Host smart-b7059174-5cbc-4671-a194-6d4cc53a201d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034794404 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.alert_handler_stress_all_with_rand_reset.4034794404
Directory /workspace/26.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.2882156581
Short name T79
Test name
Test status
Simulation time 81956772 ps
CPU time 10.12 seconds
Started Aug 01 05:42:58 PM PDT 24
Finished Aug 01 05:43:09 PM PDT 24
Peak memory 246784 kb
Host smart-985c0d9c-c179-4eba-8d5d-f7ab17f29c9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28821
56581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.2882156581
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.3033591104
Short name T17
Test name
Test status
Simulation time 210722675955 ps
CPU time 1318.06 seconds
Started Aug 01 05:42:05 PM PDT 24
Finished Aug 01 06:04:04 PM PDT 24
Peak memory 271560 kb
Host smart-c02a6b50-0a5d-4c88-81a5-7fd4e3bd2e0c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033591104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.3033591104
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.2244648647
Short name T211
Test name
Test status
Simulation time 29347887640 ps
CPU time 2924.66 seconds
Started Aug 01 05:42:35 PM PDT 24
Finished Aug 01 06:31:20 PM PDT 24
Peak memory 321648 kb
Host smart-9df85161-a857-4e0a-916b-223dc19c7128
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244648647 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.2244648647
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.2866122335
Short name T264
Test name
Test status
Simulation time 1670378690 ps
CPU time 57.73 seconds
Started Aug 01 05:43:07 PM PDT 24
Finished Aug 01 05:44:05 PM PDT 24
Peak memory 248596 kb
Host smart-3df7e62b-da19-47ce-9a9c-37ae3d0a12a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28661
22335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.2866122335
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.1990021427
Short name T9
Test name
Test status
Simulation time 1840725295 ps
CPU time 25.54 seconds
Started Aug 01 05:39:38 PM PDT 24
Finished Aug 01 05:40:04 PM PDT 24
Peak memory 273848 kb
Host smart-9003c197-c1c8-4c93-989f-d1544932008b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1990021427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.1990021427
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.2858606768
Short name T160
Test name
Test status
Simulation time 20412263125 ps
CPU time 268.85 seconds
Started Aug 01 06:26:30 PM PDT 24
Finished Aug 01 06:30:59 PM PDT 24
Peak memory 266664 kb
Host smart-32f25b0f-b0d8-4670-bbed-3ccbfd19b901
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2858606768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.2858606768
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.2500730729
Short name T175
Test name
Test status
Simulation time 354398627 ps
CPU time 3.08 seconds
Started Aug 01 06:26:15 PM PDT 24
Finished Aug 01 06:26:18 PM PDT 24
Peak memory 237728 kb
Host smart-5853f2a1-5fae-4194-b5d9-d3e7db4e80e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2500730729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.2500730729
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.2024565474
Short name T132
Test name
Test status
Simulation time 15059854234 ps
CPU time 280.37 seconds
Started Aug 01 06:26:23 PM PDT 24
Finished Aug 01 06:31:04 PM PDT 24
Peak memory 265640 kb
Host smart-6884e643-f523-4c91-9238-2ce6aaefd8f3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2024565474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.2024565474
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.2453605030
Short name T178
Test name
Test status
Simulation time 1741313835 ps
CPU time 33.08 seconds
Started Aug 01 06:26:27 PM PDT 24
Finished Aug 01 06:27:00 PM PDT 24
Peak memory 248840 kb
Host smart-d27397fe-ba26-47f0-a373-746d631c6c59
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2453605030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.2453605030
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.1451722395
Short name T184
Test name
Test status
Simulation time 35977672 ps
CPU time 2.86 seconds
Started Aug 01 06:26:29 PM PDT 24
Finished Aug 01 06:26:32 PM PDT 24
Peak memory 236204 kb
Host smart-6b9cef49-f8c9-4092-8363-2b4b511e3fd1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1451722395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.1451722395
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.689223190
Short name T183
Test name
Test status
Simulation time 120132869 ps
CPU time 4.45 seconds
Started Aug 01 06:26:25 PM PDT 24
Finished Aug 01 06:26:29 PM PDT 24
Peak memory 237672 kb
Host smart-306cdebe-68a0-493f-a5f1-56db57b534a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=689223190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.689223190
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.4126885585
Short name T155
Test name
Test status
Simulation time 17494961009 ps
CPU time 547.22 seconds
Started Aug 01 06:26:23 PM PDT 24
Finished Aug 01 06:35:31 PM PDT 24
Peak memory 273516 kb
Host smart-a088ae8e-0882-4be6-b620-35fd384b8ca7
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126885585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.4126885585
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.1157495319
Short name T180
Test name
Test status
Simulation time 629920951 ps
CPU time 43.29 seconds
Started Aug 01 06:26:18 PM PDT 24
Finished Aug 01 06:27:02 PM PDT 24
Peak memory 245920 kb
Host smart-a7209479-6990-4d9e-8e62-671b26ed20fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1157495319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.1157495319
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.588013888
Short name T174
Test name
Test status
Simulation time 197624992 ps
CPU time 2.45 seconds
Started Aug 01 06:26:28 PM PDT 24
Finished Aug 01 06:26:31 PM PDT 24
Peak memory 238100 kb
Host smart-ae06af44-6d5e-46a9-b5f6-14bf41e94446
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=588013888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.588013888
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.1768092823
Short name T170
Test name
Test status
Simulation time 171089554 ps
CPU time 3.97 seconds
Started Aug 01 06:26:31 PM PDT 24
Finished Aug 01 06:26:35 PM PDT 24
Peak memory 237696 kb
Host smart-ee18f8ca-572f-4e5d-bb09-d23ffbf85b4d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1768092823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.1768092823
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.1573547367
Short name T181
Test name
Test status
Simulation time 633237034 ps
CPU time 42.46 seconds
Started Aug 01 06:26:12 PM PDT 24
Finished Aug 01 06:26:54 PM PDT 24
Peak memory 240616 kb
Host smart-7ee4d55d-cbee-4b37-b771-582df151722d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1573547367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.1573547367
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.585862032
Short name T179
Test name
Test status
Simulation time 37500935 ps
CPU time 2.85 seconds
Started Aug 01 06:26:27 PM PDT 24
Finished Aug 01 06:26:30 PM PDT 24
Peak memory 238676 kb
Host smart-55d4c357-fd4c-4bbb-b775-3dfb58d71bbb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=585862032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.585862032
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.1251768830
Short name T177
Test name
Test status
Simulation time 68694204 ps
CPU time 4.55 seconds
Started Aug 01 06:26:20 PM PDT 24
Finished Aug 01 06:26:25 PM PDT 24
Peak memory 236808 kb
Host smart-e2f620df-dd95-4c29-8dd6-fb890f11942d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1251768830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.1251768830
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.1685872799
Short name T169
Test name
Test status
Simulation time 182366610 ps
CPU time 2.58 seconds
Started Aug 01 06:26:30 PM PDT 24
Finished Aug 01 06:26:33 PM PDT 24
Peak memory 237940 kb
Host smart-84b175c3-6f7c-46b9-9bd9-2f084974b536
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1685872799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.1685872799
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.3746429317
Short name T22
Test name
Test status
Simulation time 208983914055 ps
CPU time 2929.75 seconds
Started Aug 01 05:41:42 PM PDT 24
Finished Aug 01 06:30:32 PM PDT 24
Peak memory 288552 kb
Host smart-493bf8fe-7adb-4627-b6cf-29d8218940ef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746429317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.3746429317
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.2296520946
Short name T21
Test name
Test status
Simulation time 278681670 ps
CPU time 16.29 seconds
Started Aug 01 05:42:19 PM PDT 24
Finished Aug 01 05:42:36 PM PDT 24
Peak memory 256424 kb
Host smart-d912dab7-252e-4c13-bd7e-5c3bec3c3408
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22965
20946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.2296520946
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.4051430202
Short name T811
Test name
Test status
Simulation time 552455582 ps
CPU time 75.89 seconds
Started Aug 01 06:26:07 PM PDT 24
Finished Aug 01 06:27:23 PM PDT 24
Peak memory 237700 kb
Host smart-fdaabc6d-938c-4a1e-b1ba-adf472640fb0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4051430202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.4051430202
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.1396575889
Short name T731
Test name
Test status
Simulation time 3204482901 ps
CPU time 242.31 seconds
Started Aug 01 06:26:19 PM PDT 24
Finished Aug 01 06:30:21 PM PDT 24
Peak memory 240704 kb
Host smart-642acaec-e9a9-49ed-bcd0-9a35a43b5376
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1396575889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.1396575889
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.3444780688
Short name T790
Test name
Test status
Simulation time 107169369 ps
CPU time 9.31 seconds
Started Aug 01 06:26:12 PM PDT 24
Finished Aug 01 06:26:21 PM PDT 24
Peak memory 249300 kb
Host smart-080e0093-dc6e-488d-912b-fff40cacd3a8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3444780688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.3444780688
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.4187778547
Short name T800
Test name
Test status
Simulation time 102396229 ps
CPU time 8.11 seconds
Started Aug 01 06:26:12 PM PDT 24
Finished Aug 01 06:26:20 PM PDT 24
Peak memory 241108 kb
Host smart-2a8381b5-a67b-40c0-97f5-f9df681df93a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187778547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.4187778547
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.2591722560
Short name T199
Test name
Test status
Simulation time 490672126 ps
CPU time 7.97 seconds
Started Aug 01 06:26:06 PM PDT 24
Finished Aug 01 06:26:14 PM PDT 24
Peak memory 237648 kb
Host smart-7d68d8b2-603e-4106-9cd3-fc64d1b21be0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2591722560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.2591722560
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.2629995162
Short name T798
Test name
Test status
Simulation time 6399506 ps
CPU time 1.42 seconds
Started Aug 01 06:26:09 PM PDT 24
Finished Aug 01 06:26:11 PM PDT 24
Peak memory 236828 kb
Host smart-2559bdc4-2e05-40c1-a793-a40043e75c1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2629995162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.2629995162
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.2062806338
Short name T206
Test name
Test status
Simulation time 89624559 ps
CPU time 12.04 seconds
Started Aug 01 06:26:10 PM PDT 24
Finished Aug 01 06:26:22 PM PDT 24
Peak memory 245032 kb
Host smart-03bfc984-ee92-416f-b0b4-5a9f1a4dd150
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2062806338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.2062806338
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.3745695573
Short name T167
Test name
Test status
Simulation time 17473426087 ps
CPU time 358.56 seconds
Started Aug 01 06:26:07 PM PDT 24
Finished Aug 01 06:32:06 PM PDT 24
Peak memory 265796 kb
Host smart-7d84e2c9-3174-4547-9772-aed2097332cf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3745695573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.3745695573
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.3634435082
Short name T739
Test name
Test status
Simulation time 45693345 ps
CPU time 7.73 seconds
Started Aug 01 06:26:07 PM PDT 24
Finished Aug 01 06:26:15 PM PDT 24
Peak memory 253896 kb
Host smart-f9c6f2d9-c25d-4841-bb9e-54c1d4d2cefa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3634435082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.3634435082
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.2239533875
Short name T212
Test name
Test status
Simulation time 60348906 ps
CPU time 3.89 seconds
Started Aug 01 06:26:17 PM PDT 24
Finished Aug 01 06:26:21 PM PDT 24
Peak memory 237672 kb
Host smart-50405d28-c1e9-4ddd-91aa-84a23d098df9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2239533875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.2239533875
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.2493401215
Short name T753
Test name
Test status
Simulation time 18491422048 ps
CPU time 173.86 seconds
Started Aug 01 06:26:11 PM PDT 24
Finished Aug 01 06:29:04 PM PDT 24
Peak memory 241540 kb
Host smart-214266d8-e97f-4057-a484-85bbb2c6799d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2493401215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.2493401215
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.2097834147
Short name T745
Test name
Test status
Simulation time 3335567334 ps
CPU time 182.39 seconds
Started Aug 01 06:26:05 PM PDT 24
Finished Aug 01 06:29:07 PM PDT 24
Peak memory 236864 kb
Host smart-39713f4c-c776-40d6-8d74-35664b7caf95
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2097834147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.2097834147
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.3256104955
Short name T807
Test name
Test status
Simulation time 129841671 ps
CPU time 6.08 seconds
Started Aug 01 06:26:13 PM PDT 24
Finished Aug 01 06:26:19 PM PDT 24
Peak memory 248820 kb
Host smart-fd5cf7c4-abed-4b7e-8e43-beb171f0ba0f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3256104955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.3256104955
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.802822411
Short name T814
Test name
Test status
Simulation time 255921564 ps
CPU time 14.04 seconds
Started Aug 01 06:26:10 PM PDT 24
Finished Aug 01 06:26:24 PM PDT 24
Peak memory 249940 kb
Host smart-be0e5d56-6f22-4252-8e9e-d049a044657e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802822411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 1.alert_handler_csr_mem_rw_with_rand_reset.802822411
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.3817478217
Short name T380
Test name
Test status
Simulation time 179762175 ps
CPU time 5 seconds
Started Aug 01 06:26:10 PM PDT 24
Finished Aug 01 06:26:16 PM PDT 24
Peak memory 237688 kb
Host smart-1a60bc23-3e93-420c-a13e-8c8d26bb6885
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3817478217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.3817478217
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.2955379540
Short name T748
Test name
Test status
Simulation time 20842856 ps
CPU time 1.33 seconds
Started Aug 01 06:26:09 PM PDT 24
Finished Aug 01 06:26:10 PM PDT 24
Peak memory 236784 kb
Host smart-fcf2f779-79e4-4922-945b-b398411fb186
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2955379540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.2955379540
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.1849744081
Short name T765
Test name
Test status
Simulation time 583139572 ps
CPU time 25.31 seconds
Started Aug 01 06:26:11 PM PDT 24
Finished Aug 01 06:26:37 PM PDT 24
Peak memory 248772 kb
Host smart-813aa5cc-eedb-47ae-9ac1-1a1c274bc675
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1849744081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.1849744081
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.1976151276
Short name T148
Test name
Test status
Simulation time 12486964608 ps
CPU time 509.4 seconds
Started Aug 01 06:26:11 PM PDT 24
Finished Aug 01 06:34:41 PM PDT 24
Peak memory 265132 kb
Host smart-2619dcf9-ab12-41d5-8a46-7fb38c390429
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976151276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.1976151276
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.1003226713
Short name T716
Test name
Test status
Simulation time 331753299 ps
CPU time 11.77 seconds
Started Aug 01 06:26:12 PM PDT 24
Finished Aug 01 06:26:24 PM PDT 24
Peak memory 248592 kb
Host smart-07adcec1-ef43-44f7-bc9b-f520d37933c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1003226713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.1003226713
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.4137530670
Short name T187
Test name
Test status
Simulation time 57294532 ps
CPU time 3.85 seconds
Started Aug 01 06:26:09 PM PDT 24
Finished Aug 01 06:26:13 PM PDT 24
Peak memory 237676 kb
Host smart-ff281ebd-f39c-44ed-ab70-a8fcbbc5d4fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4137530670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.4137530670
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.3130084251
Short name T255
Test name
Test status
Simulation time 121202595 ps
CPU time 9.42 seconds
Started Aug 01 06:26:25 PM PDT 24
Finished Aug 01 06:26:35 PM PDT 24
Peak memory 240396 kb
Host smart-088d9b3a-fdf5-4af2-a84c-27837dfb6622
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130084251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.3130084251
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.2793895077
Short name T202
Test name
Test status
Simulation time 338941796 ps
CPU time 4.38 seconds
Started Aug 01 06:26:20 PM PDT 24
Finished Aug 01 06:26:25 PM PDT 24
Peak memory 237900 kb
Host smart-ab59d5ce-ac62-4160-98c8-a8da275a28fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2793895077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.2793895077
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.1142877937
Short name T757
Test name
Test status
Simulation time 8566139 ps
CPU time 1.55 seconds
Started Aug 01 06:26:23 PM PDT 24
Finished Aug 01 06:26:25 PM PDT 24
Peak memory 237092 kb
Host smart-f398ca58-d372-49f2-9561-546927f55181
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1142877937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.1142877937
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.3426312708
Short name T719
Test name
Test status
Simulation time 669160970 ps
CPU time 23.23 seconds
Started Aug 01 06:26:30 PM PDT 24
Finished Aug 01 06:26:53 PM PDT 24
Peak memory 245936 kb
Host smart-3f516148-67c4-400b-8e0a-366739b2ab19
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3426312708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.3426312708
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.3457726989
Short name T159
Test name
Test status
Simulation time 4474941458 ps
CPU time 173.1 seconds
Started Aug 01 06:26:26 PM PDT 24
Finished Aug 01 06:29:20 PM PDT 24
Peak memory 265872 kb
Host smart-4c9e0740-8a89-498a-b5cb-889aa2f132cf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3457726989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.3457726989
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.3388877537
Short name T744
Test name
Test status
Simulation time 709224831 ps
CPU time 14.79 seconds
Started Aug 01 06:26:19 PM PDT 24
Finished Aug 01 06:26:34 PM PDT 24
Peak memory 250100 kb
Host smart-4cfd4d17-e59a-4089-9e37-d1bbf2d8ac4d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3388877537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.3388877537
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.1112786016
Short name T782
Test name
Test status
Simulation time 35797870 ps
CPU time 5.44 seconds
Started Aug 01 06:26:15 PM PDT 24
Finished Aug 01 06:26:20 PM PDT 24
Peak memory 256484 kb
Host smart-26b694b7-efbc-48c0-915f-189d67aaf2b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112786016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.1112786016
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.2484430447
Short name T768
Test name
Test status
Simulation time 990022312 ps
CPU time 9.37 seconds
Started Aug 01 06:26:26 PM PDT 24
Finished Aug 01 06:26:35 PM PDT 24
Peak memory 237680 kb
Host smart-9d91a605-a966-4af5-89d1-4130bd25b5c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2484430447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.2484430447
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.3164976463
Short name T792
Test name
Test status
Simulation time 15749432 ps
CPU time 1.34 seconds
Started Aug 01 06:26:15 PM PDT 24
Finished Aug 01 06:26:16 PM PDT 24
Peak memory 237720 kb
Host smart-be9392eb-75c7-48e8-b8ae-240a2e190935
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3164976463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.3164976463
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.441947387
Short name T774
Test name
Test status
Simulation time 147220357 ps
CPU time 12.69 seconds
Started Aug 01 06:26:19 PM PDT 24
Finished Aug 01 06:26:32 PM PDT 24
Peak memory 240628 kb
Host smart-74c72e58-a4da-4c2e-8bc4-530c5cd77ec7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=441947387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_out
standing.441947387
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.3296509249
Short name T161
Test name
Test status
Simulation time 2165304356 ps
CPU time 146.09 seconds
Started Aug 01 06:26:13 PM PDT 24
Finished Aug 01 06:28:40 PM PDT 24
Peak memory 264984 kb
Host smart-676123ea-50ea-4ab0-baa1-eb8602f76978
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3296509249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.3296509249
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.69908573
Short name T710
Test name
Test status
Simulation time 159373165 ps
CPU time 8.95 seconds
Started Aug 01 06:26:20 PM PDT 24
Finished Aug 01 06:26:29 PM PDT 24
Peak memory 255036 kb
Host smart-9ea93268-7960-458e-b0c1-68f69d287ef0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=69908573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.69908573
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.1134849312
Short name T213
Test name
Test status
Simulation time 312243181 ps
CPU time 7.07 seconds
Started Aug 01 06:26:29 PM PDT 24
Finished Aug 01 06:26:36 PM PDT 24
Peak memory 240860 kb
Host smart-abcfaf21-dba8-4c66-abbd-34139649b519
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134849312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.1134849312
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.1310908677
Short name T379
Test name
Test status
Simulation time 35538586 ps
CPU time 3.13 seconds
Started Aug 01 06:26:26 PM PDT 24
Finished Aug 01 06:26:30 PM PDT 24
Peak memory 236780 kb
Host smart-21d624a8-0701-42a8-af4f-b6008ebda769
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1310908677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.1310908677
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.3365915710
Short name T773
Test name
Test status
Simulation time 12723803 ps
CPU time 1.69 seconds
Started Aug 01 06:26:21 PM PDT 24
Finished Aug 01 06:26:23 PM PDT 24
Peak memory 235704 kb
Host smart-2a3a6300-b7e1-477a-b686-0041a8e0e0cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3365915710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.3365915710
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.2207624944
Short name T802
Test name
Test status
Simulation time 1097211646 ps
CPU time 20.5 seconds
Started Aug 01 06:26:24 PM PDT 24
Finished Aug 01 06:26:45 PM PDT 24
Peak memory 245012 kb
Host smart-a11bc2fc-c720-47fb-9f56-45b974721999
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2207624944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou
tstanding.2207624944
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.3357289524
Short name T162
Test name
Test status
Simulation time 1147160173 ps
CPU time 129.89 seconds
Started Aug 01 06:26:15 PM PDT 24
Finished Aug 01 06:28:25 PM PDT 24
Peak memory 265524 kb
Host smart-a2af71fd-3cef-4c78-8184-41de733ba4a4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3357289524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.3357289524
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.279484767
Short name T136
Test name
Test status
Simulation time 25416522108 ps
CPU time 517.87 seconds
Started Aug 01 06:26:21 PM PDT 24
Finished Aug 01 06:34:59 PM PDT 24
Peak memory 265844 kb
Host smart-2f57383d-6503-41b9-b49d-b37b18b47855
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279484767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.279484767
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.310386199
Short name T256
Test name
Test status
Simulation time 114915839 ps
CPU time 8.71 seconds
Started Aug 01 06:26:15 PM PDT 24
Finished Aug 01 06:26:24 PM PDT 24
Peak memory 251784 kb
Host smart-66b6ecfd-ccc9-42ad-b042-f8990cb70b27
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=310386199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.310386199
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.1796152593
Short name T809
Test name
Test status
Simulation time 62953383 ps
CPU time 4.79 seconds
Started Aug 01 06:26:31 PM PDT 24
Finished Aug 01 06:26:36 PM PDT 24
Peak memory 241104 kb
Host smart-193d81b4-18c1-4c87-a148-b024995dd102
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796152593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.1796152593
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.11877553
Short name T819
Test name
Test status
Simulation time 25948720 ps
CPU time 3.39 seconds
Started Aug 01 06:26:26 PM PDT 24
Finished Aug 01 06:26:29 PM PDT 24
Peak memory 237700 kb
Host smart-ad06972c-9144-4aa6-9f75-d172d69c1a9e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=11877553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.11877553
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.3007132185
Short name T806
Test name
Test status
Simulation time 6378850 ps
CPU time 1.5 seconds
Started Aug 01 06:26:33 PM PDT 24
Finished Aug 01 06:26:35 PM PDT 24
Peak memory 235704 kb
Host smart-1fd616c0-ad08-4953-a922-7b438486b96c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3007132185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.3007132185
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.3387747205
Short name T715
Test name
Test status
Simulation time 519056255 ps
CPU time 18.82 seconds
Started Aug 01 06:26:25 PM PDT 24
Finished Aug 01 06:26:44 PM PDT 24
Peak memory 240640 kb
Host smart-9b7c9b87-8360-49ec-aec1-2195ff1b3669
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3387747205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.3387747205
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.1026379167
Short name T133
Test name
Test status
Simulation time 2129781265 ps
CPU time 134.79 seconds
Started Aug 01 06:26:26 PM PDT 24
Finished Aug 01 06:28:42 PM PDT 24
Peak memory 265524 kb
Host smart-e5526c45-100d-497e-b89d-ac0aa7112e0d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1026379167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.1026379167
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.4288880807
Short name T164
Test name
Test status
Simulation time 13367408177 ps
CPU time 284.12 seconds
Started Aug 01 06:26:35 PM PDT 24
Finished Aug 01 06:31:19 PM PDT 24
Peak memory 265760 kb
Host smart-d3a6b1fe-08a1-474d-82cb-4b5be63230ec
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288880807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.4288880807
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.2538037427
Short name T820
Test name
Test status
Simulation time 1213354683 ps
CPU time 21.92 seconds
Started Aug 01 06:26:25 PM PDT 24
Finished Aug 01 06:26:47 PM PDT 24
Peak memory 248828 kb
Host smart-2ca13e14-ba81-406a-b3d7-1f866d44506e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2538037427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.2538037427
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.2653693439
Short name T750
Test name
Test status
Simulation time 432047350 ps
CPU time 7.87 seconds
Started Aug 01 06:26:29 PM PDT 24
Finished Aug 01 06:26:37 PM PDT 24
Peak memory 240368 kb
Host smart-62bec4bf-34cf-44e2-b7e9-1ebbb01ab4b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653693439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.2653693439
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.2656590716
Short name T743
Test name
Test status
Simulation time 118123945 ps
CPU time 6.22 seconds
Started Aug 01 06:26:16 PM PDT 24
Finished Aug 01 06:26:23 PM PDT 24
Peak memory 237688 kb
Host smart-04977fcd-1f05-4d63-bad0-ce78de962c1b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2656590716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.2656590716
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.2903723533
Short name T738
Test name
Test status
Simulation time 303145251 ps
CPU time 20.12 seconds
Started Aug 01 06:26:18 PM PDT 24
Finished Aug 01 06:26:38 PM PDT 24
Peak memory 245008 kb
Host smart-d84a05c7-7338-410e-b101-8687067d5f8d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2903723533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.2903723533
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.1251185835
Short name T785
Test name
Test status
Simulation time 292564691 ps
CPU time 4.21 seconds
Started Aug 01 06:26:26 PM PDT 24
Finished Aug 01 06:26:31 PM PDT 24
Peak memory 251980 kb
Host smart-9ca4b746-f748-43af-92d7-6ac2c483db03
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1251185835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.1251185835
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.2322030505
Short name T742
Test name
Test status
Simulation time 8871659075 ps
CPU time 41.94 seconds
Started Aug 01 06:26:22 PM PDT 24
Finished Aug 01 06:27:04 PM PDT 24
Peak memory 240724 kb
Host smart-10b967d3-c693-4b33-9f1c-ff611fb8bbf0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2322030505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.2322030505
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.1444206620
Short name T813
Test name
Test status
Simulation time 280092873 ps
CPU time 7.66 seconds
Started Aug 01 06:26:19 PM PDT 24
Finished Aug 01 06:26:27 PM PDT 24
Peak memory 239808 kb
Host smart-dc3cd17e-9f28-41df-be97-3a1bddf71718
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444206620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.1444206620
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.3252924025
Short name T724
Test name
Test status
Simulation time 645803830 ps
CPU time 7.73 seconds
Started Aug 01 06:26:33 PM PDT 24
Finished Aug 01 06:26:41 PM PDT 24
Peak memory 237588 kb
Host smart-522e4a84-ae83-4bd5-a135-b87a426df769
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3252924025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.3252924025
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.4054902414
Short name T791
Test name
Test status
Simulation time 5515695438 ps
CPU time 44.31 seconds
Started Aug 01 06:26:22 PM PDT 24
Finished Aug 01 06:27:11 PM PDT 24
Peak memory 245136 kb
Host smart-f82725ad-c3a2-4775-8b49-3349b2a37314
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4054902414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.4054902414
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.838926592
Short name T152
Test name
Test status
Simulation time 12247889605 ps
CPU time 549.64 seconds
Started Aug 01 06:26:27 PM PDT 24
Finished Aug 01 06:35:37 PM PDT 24
Peak memory 265636 kb
Host smart-78f43acc-1abe-482b-83f5-6ce68eb204d1
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838926592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.838926592
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.321613158
Short name T824
Test name
Test status
Simulation time 51618700 ps
CPU time 7.32 seconds
Started Aug 01 06:26:25 PM PDT 24
Finished Aug 01 06:26:33 PM PDT 24
Peak memory 248500 kb
Host smart-c5cb47b8-6a9d-4e98-9662-5b878707a121
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=321613158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.321613158
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.2452532236
Short name T725
Test name
Test status
Simulation time 815836908 ps
CPU time 8.51 seconds
Started Aug 01 06:26:23 PM PDT 24
Finished Aug 01 06:26:32 PM PDT 24
Peak memory 238276 kb
Host smart-038f2798-f897-4c9f-8391-d8cb0ff0bc3d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452532236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.2452532236
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.1945835627
Short name T754
Test name
Test status
Simulation time 51945713 ps
CPU time 3.96 seconds
Started Aug 01 06:26:24 PM PDT 24
Finished Aug 01 06:26:29 PM PDT 24
Peak memory 237696 kb
Host smart-562ae138-6bec-499e-bcca-b846e437df1d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1945835627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.1945835627
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.3653796682
Short name T374
Test name
Test status
Simulation time 31939212 ps
CPU time 1.29 seconds
Started Aug 01 06:26:29 PM PDT 24
Finished Aug 01 06:26:31 PM PDT 24
Peak memory 237708 kb
Host smart-6286de1f-9fc7-434e-bbf1-2ad9cf233a7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3653796682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.3653796682
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.3932750750
Short name T795
Test name
Test status
Simulation time 1878623228 ps
CPU time 38.06 seconds
Started Aug 01 06:26:26 PM PDT 24
Finished Aug 01 06:27:05 PM PDT 24
Peak memory 245876 kb
Host smart-03ceacb5-c9ba-40ec-a413-0297c2db66d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3932750750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.3932750750
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.2785398216
Short name T151
Test name
Test status
Simulation time 11080682969 ps
CPU time 456.41 seconds
Started Aug 01 06:26:30 PM PDT 24
Finished Aug 01 06:34:07 PM PDT 24
Peak memory 265692 kb
Host smart-85e22096-b053-4d04-a08e-6b85d72fb32b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785398216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.2785398216
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.998045148
Short name T752
Test name
Test status
Simulation time 429479458 ps
CPU time 7.1 seconds
Started Aug 01 06:26:28 PM PDT 24
Finished Aug 01 06:26:36 PM PDT 24
Peak memory 248884 kb
Host smart-0a0f5427-b43e-44f0-828f-4e45a98245f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=998045148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.998045148
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.3035256376
Short name T746
Test name
Test status
Simulation time 140103863 ps
CPU time 5.75 seconds
Started Aug 01 06:26:31 PM PDT 24
Finished Aug 01 06:26:36 PM PDT 24
Peak memory 239912 kb
Host smart-03af76e0-ee4f-4826-ac60-143be80b1075
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035256376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.3035256376
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.2691935966
Short name T804
Test name
Test status
Simulation time 210286185 ps
CPU time 7.42 seconds
Started Aug 01 06:26:30 PM PDT 24
Finished Aug 01 06:26:38 PM PDT 24
Peak memory 240636 kb
Host smart-f27f8502-cd39-4e27-a0f1-126868cc12ba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2691935966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.2691935966
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.2794553508
Short name T718
Test name
Test status
Simulation time 11105035 ps
CPU time 1.68 seconds
Started Aug 01 06:26:24 PM PDT 24
Finished Aug 01 06:26:26 PM PDT 24
Peak memory 237708 kb
Host smart-65f2e501-33c9-4ce8-9ca7-47f9b660800e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2794553508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.2794553508
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.2898613747
Short name T741
Test name
Test status
Simulation time 1216078208 ps
CPU time 17.18 seconds
Started Aug 01 06:26:22 PM PDT 24
Finished Aug 01 06:26:39 PM PDT 24
Peak memory 240652 kb
Host smart-f8632f53-4249-4077-bb30-e5b8ff766ef3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2898613747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.2898613747
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.2546972406
Short name T812
Test name
Test status
Simulation time 737662344 ps
CPU time 11.6 seconds
Started Aug 01 06:26:26 PM PDT 24
Finished Aug 01 06:26:38 PM PDT 24
Peak memory 253564 kb
Host smart-2bd52a57-6712-459d-b80d-05c0b5a41019
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2546972406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.2546972406
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.798574815
Short name T762
Test name
Test status
Simulation time 136014981 ps
CPU time 9.36 seconds
Started Aug 01 06:26:21 PM PDT 24
Finished Aug 01 06:26:31 PM PDT 24
Peak memory 239988 kb
Host smart-8b0c47a9-1828-4749-8a8f-a59a92751e2e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798574815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 18.alert_handler_csr_mem_rw_with_rand_reset.798574815
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.4131976904
Short name T186
Test name
Test status
Simulation time 236765875 ps
CPU time 4.91 seconds
Started Aug 01 06:26:30 PM PDT 24
Finished Aug 01 06:26:35 PM PDT 24
Peak memory 237676 kb
Host smart-31191c39-bd55-4e5d-86d7-56a7b36bc812
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4131976904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.4131976904
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.2353544328
Short name T793
Test name
Test status
Simulation time 7624735 ps
CPU time 1.53 seconds
Started Aug 01 06:26:25 PM PDT 24
Finished Aug 01 06:26:27 PM PDT 24
Peak memory 236784 kb
Host smart-a453a167-5412-4cf9-9d7f-3bfa4eb29e7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2353544328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.2353544328
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.866393271
Short name T805
Test name
Test status
Simulation time 1994492191 ps
CPU time 40.39 seconds
Started Aug 01 06:26:21 PM PDT 24
Finished Aug 01 06:27:02 PM PDT 24
Peak memory 245912 kb
Host smart-725206e4-0e60-4f53-9e7f-246204e0edc9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=866393271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_out
standing.866393271
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.2109388066
Short name T150
Test name
Test status
Simulation time 42164122176 ps
CPU time 542.08 seconds
Started Aug 01 06:26:27 PM PDT 24
Finished Aug 01 06:35:29 PM PDT 24
Peak memory 265616 kb
Host smart-d33042a9-d020-450e-99ea-9c3b6a685a36
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109388066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.2109388066
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.3009134415
Short name T713
Test name
Test status
Simulation time 132506128 ps
CPU time 5.31 seconds
Started Aug 01 06:26:30 PM PDT 24
Finished Aug 01 06:26:36 PM PDT 24
Peak memory 248776 kb
Host smart-a53a2401-1b35-4d4b-8867-10cb7ad748b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3009134415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.3009134415
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.2416151435
Short name T730
Test name
Test status
Simulation time 69110492 ps
CPU time 4.52 seconds
Started Aug 01 06:26:28 PM PDT 24
Finished Aug 01 06:26:33 PM PDT 24
Peak memory 237972 kb
Host smart-59201ee8-5810-44c3-8687-b93d631f4da9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416151435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.2416151435
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.924126284
Short name T200
Test name
Test status
Simulation time 118267990 ps
CPU time 3.67 seconds
Started Aug 01 06:26:20 PM PDT 24
Finished Aug 01 06:26:24 PM PDT 24
Peak memory 237668 kb
Host smart-8174c205-9962-4493-b757-719e2796061e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=924126284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.924126284
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.3190646152
Short name T778
Test name
Test status
Simulation time 18160521 ps
CPU time 1.43 seconds
Started Aug 01 06:26:32 PM PDT 24
Finished Aug 01 06:26:33 PM PDT 24
Peak memory 237708 kb
Host smart-040d5159-d583-4d9a-a944-62c52cf67a03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3190646152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.3190646152
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.1839268363
Short name T185
Test name
Test status
Simulation time 605458542 ps
CPU time 33.83 seconds
Started Aug 01 06:26:19 PM PDT 24
Finished Aug 01 06:26:53 PM PDT 24
Peak memory 248856 kb
Host smart-71639477-687c-43a3-a361-d6226afc5205
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1839268363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.1839268363
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.1911387685
Short name T143
Test name
Test status
Simulation time 1911300074 ps
CPU time 128.21 seconds
Started Aug 01 06:26:24 PM PDT 24
Finished Aug 01 06:28:33 PM PDT 24
Peak memory 264948 kb
Host smart-5aa596aa-117a-4922-928b-d408c6160588
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1911387685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.1911387685
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.634522154
Short name T794
Test name
Test status
Simulation time 95600794 ps
CPU time 7.86 seconds
Started Aug 01 06:26:26 PM PDT 24
Finished Aug 01 06:26:35 PM PDT 24
Peak memory 252400 kb
Host smart-47f8b8e1-5f89-4e58-91da-b713343c2670
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=634522154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.634522154
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.2369281205
Short name T818
Test name
Test status
Simulation time 575230089 ps
CPU time 76.51 seconds
Started Aug 01 06:26:13 PM PDT 24
Finished Aug 01 06:27:29 PM PDT 24
Peak memory 240568 kb
Host smart-cd1159de-f73e-4a53-82bc-5d90ede9106f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2369281205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.2369281205
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.1921326109
Short name T201
Test name
Test status
Simulation time 11909366016 ps
CPU time 431.59 seconds
Started Aug 01 06:26:15 PM PDT 24
Finished Aug 01 06:33:27 PM PDT 24
Peak memory 237792 kb
Host smart-90a879aa-24d7-4bba-8fb1-7b43c0693194
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1921326109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.1921326109
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.1050757721
Short name T769
Test name
Test status
Simulation time 139446786 ps
CPU time 10.52 seconds
Started Aug 01 06:26:18 PM PDT 24
Finished Aug 01 06:26:29 PM PDT 24
Peak memory 240628 kb
Host smart-5f97de89-3cf7-4da2-8a40-b89a311d041f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1050757721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.1050757721
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.639614368
Short name T733
Test name
Test status
Simulation time 49224236 ps
CPU time 4.62 seconds
Started Aug 01 06:26:16 PM PDT 24
Finished Aug 01 06:26:21 PM PDT 24
Peak memory 248980 kb
Host smart-a1036038-5c69-4bbb-a069-02463029e32f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639614368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 2.alert_handler_csr_mem_rw_with_rand_reset.639614368
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.2636113379
Short name T737
Test name
Test status
Simulation time 28682425 ps
CPU time 3.8 seconds
Started Aug 01 06:26:08 PM PDT 24
Finished Aug 01 06:26:12 PM PDT 24
Peak memory 236816 kb
Host smart-5fa2b094-bcce-49ef-a25c-3e7735b9b4e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2636113379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.2636113379
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.3366253538
Short name T717
Test name
Test status
Simulation time 9537578 ps
CPU time 1.61 seconds
Started Aug 01 06:26:23 PM PDT 24
Finished Aug 01 06:26:24 PM PDT 24
Peak memory 236832 kb
Host smart-f4133335-a17e-4737-98b5-c003c0af13a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3366253538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.3366253538
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.3321016004
Short name T803
Test name
Test status
Simulation time 511908661 ps
CPU time 37.04 seconds
Started Aug 01 06:26:10 PM PDT 24
Finished Aug 01 06:26:47 PM PDT 24
Peak memory 245908 kb
Host smart-e601af33-2967-4b48-8be7-a75cd4e705e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3321016004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.3321016004
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.4154448578
Short name T153
Test name
Test status
Simulation time 8573601215 ps
CPU time 378.14 seconds
Started Aug 01 06:26:13 PM PDT 24
Finished Aug 01 06:32:31 PM PDT 24
Peak memory 265612 kb
Host smart-e2cfb4a7-76da-4fef-b671-4fa700b3fabe
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4154448578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.4154448578
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.4127757992
Short name T156
Test name
Test status
Simulation time 8785008800 ps
CPU time 283.97 seconds
Started Aug 01 06:26:17 PM PDT 24
Finished Aug 01 06:31:01 PM PDT 24
Peak memory 273036 kb
Host smart-6b73daf3-de26-42cb-a5ab-46e820aa4d2e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127757992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.4127757992
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.3638419428
Short name T712
Test name
Test status
Simulation time 66238206 ps
CPU time 4.3 seconds
Started Aug 01 06:26:07 PM PDT 24
Finished Aug 01 06:26:12 PM PDT 24
Peak memory 248068 kb
Host smart-aed2fbb1-993d-4c8f-9600-c606530e6cf4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3638419428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.3638419428
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.3571283360
Short name T758
Test name
Test status
Simulation time 158026757 ps
CPU time 21.64 seconds
Started Aug 01 06:26:21 PM PDT 24
Finished Aug 01 06:26:43 PM PDT 24
Peak memory 240540 kb
Host smart-199518f2-f9a0-4f50-af68-cf5851ab6ad4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3571283360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.3571283360
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.3053054072
Short name T763
Test name
Test status
Simulation time 12826044 ps
CPU time 1.38 seconds
Started Aug 01 06:26:39 PM PDT 24
Finished Aug 01 06:26:41 PM PDT 24
Peak memory 236712 kb
Host smart-b596cc8f-f7f6-4915-b8a0-6c0f5a45538a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3053054072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.3053054072
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.746703142
Short name T734
Test name
Test status
Simulation time 20582523 ps
CPU time 1.43 seconds
Started Aug 01 06:26:41 PM PDT 24
Finished Aug 01 06:26:43 PM PDT 24
Peak memory 237712 kb
Host smart-10b0d8ed-7cc3-4826-a579-f444e13e37f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=746703142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.746703142
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.2596657768
Short name T776
Test name
Test status
Simulation time 41564512 ps
CPU time 1.47 seconds
Started Aug 01 06:26:32 PM PDT 24
Finished Aug 01 06:26:34 PM PDT 24
Peak memory 236756 kb
Host smart-a96ac4bb-b754-4f15-a469-41228c61d17b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2596657768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.2596657768
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.131379708
Short name T747
Test name
Test status
Simulation time 9071510 ps
CPU time 1.44 seconds
Started Aug 01 06:26:31 PM PDT 24
Finished Aug 01 06:26:32 PM PDT 24
Peak memory 235648 kb
Host smart-828cbb88-d08a-425b-8a09-1aed125d0193
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=131379708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.131379708
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.329410100
Short name T727
Test name
Test status
Simulation time 7705272 ps
CPU time 1.55 seconds
Started Aug 01 06:26:32 PM PDT 24
Finished Aug 01 06:26:34 PM PDT 24
Peak memory 236748 kb
Host smart-67447c0d-e7bd-4142-aa72-e1dc70b7a009
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=329410100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.329410100
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.2765032830
Short name T726
Test name
Test status
Simulation time 22015461 ps
CPU time 1.52 seconds
Started Aug 01 06:26:27 PM PDT 24
Finished Aug 01 06:26:29 PM PDT 24
Peak memory 236688 kb
Host smart-e21e34db-b441-41d9-8c9e-11d82302d970
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2765032830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.2765032830
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.3187052012
Short name T816
Test name
Test status
Simulation time 34650992 ps
CPU time 1.67 seconds
Started Aug 01 06:26:24 PM PDT 24
Finished Aug 01 06:26:26 PM PDT 24
Peak memory 237680 kb
Host smart-2005df97-46ae-46ef-be7b-c92fe9b6dcbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3187052012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.3187052012
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.2233223634
Short name T373
Test name
Test status
Simulation time 10068913 ps
CPU time 1.28 seconds
Started Aug 01 06:26:27 PM PDT 24
Finished Aug 01 06:26:28 PM PDT 24
Peak memory 236824 kb
Host smart-15057bb8-6079-4cfb-bc3f-fe6cf2b118be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2233223634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.2233223634
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.4191922776
Short name T810
Test name
Test status
Simulation time 10040328 ps
CPU time 1.27 seconds
Started Aug 01 06:26:26 PM PDT 24
Finished Aug 01 06:26:28 PM PDT 24
Peak memory 237704 kb
Host smart-5b6bf56a-d31d-4a19-976e-7a895029804c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4191922776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.4191922776
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.1625772325
Short name T749
Test name
Test status
Simulation time 3332058574 ps
CPU time 219.12 seconds
Started Aug 01 06:26:20 PM PDT 24
Finished Aug 01 06:29:59 PM PDT 24
Peak memory 240708 kb
Host smart-f8e9b92f-f309-4828-87ac-b56ea4331e4f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1625772325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.1625772325
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.1466046334
Short name T783
Test name
Test status
Simulation time 11431896614 ps
CPU time 174.78 seconds
Started Aug 01 06:26:13 PM PDT 24
Finished Aug 01 06:29:08 PM PDT 24
Peak memory 236952 kb
Host smart-4d4bda30-197b-45b5-860c-e8e4ce66d9a7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1466046334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.1466046334
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.968546371
Short name T711
Test name
Test status
Simulation time 73446001 ps
CPU time 6.29 seconds
Started Aug 01 06:26:17 PM PDT 24
Finished Aug 01 06:26:24 PM PDT 24
Peak memory 248844 kb
Host smart-6f4d5e38-a89b-4a1b-9cdb-e10700136715
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=968546371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.968546371
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.3682236315
Short name T736
Test name
Test status
Simulation time 124075179 ps
CPU time 9.97 seconds
Started Aug 01 06:26:21 PM PDT 24
Finished Aug 01 06:26:31 PM PDT 24
Peak memory 251384 kb
Host smart-2e8816cb-6cea-4f2c-b2ad-1ae9b4e3aff7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682236315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.3682236315
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.2698715318
Short name T732
Test name
Test status
Simulation time 49286211 ps
CPU time 4.48 seconds
Started Aug 01 06:26:13 PM PDT 24
Finished Aug 01 06:26:17 PM PDT 24
Peak memory 240608 kb
Host smart-2e3ec0e8-495c-4cd1-9f7a-7af5cf0082a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2698715318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.2698715318
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.1644866040
Short name T740
Test name
Test status
Simulation time 10126095 ps
CPU time 1.57 seconds
Started Aug 01 06:26:12 PM PDT 24
Finished Aug 01 06:26:13 PM PDT 24
Peak memory 237708 kb
Host smart-bf069ebe-25e9-4a6b-8118-b335ffeb71ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1644866040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.1644866040
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.3428366766
Short name T204
Test name
Test status
Simulation time 972612204 ps
CPU time 19.33 seconds
Started Aug 01 06:26:14 PM PDT 24
Finished Aug 01 06:26:33 PM PDT 24
Peak memory 245900 kb
Host smart-04048264-3e5b-4292-98c4-a4f1a253111d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3428366766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.3428366766
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.405006400
Short name T144
Test name
Test status
Simulation time 5903159253 ps
CPU time 384.26 seconds
Started Aug 01 06:26:27 PM PDT 24
Finished Aug 01 06:32:51 PM PDT 24
Peak memory 273816 kb
Host smart-c8f67573-62ef-4db6-a90f-fe366471e0e7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=405006400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_error
s.405006400
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.4155978662
Short name T154
Test name
Test status
Simulation time 25425574341 ps
CPU time 309.89 seconds
Started Aug 01 06:26:14 PM PDT 24
Finished Aug 01 06:31:24 PM PDT 24
Peak memory 268920 kb
Host smart-ad7814c3-958c-4f99-93f9-df107e4c411e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155978662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.4155978662
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.2619247232
Short name T826
Test name
Test status
Simulation time 32466695 ps
CPU time 4.29 seconds
Started Aug 01 06:26:16 PM PDT 24
Finished Aug 01 06:26:21 PM PDT 24
Peak memory 247588 kb
Host smart-2b334734-e11d-4c65-8292-43ec932105a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2619247232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.2619247232
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.4193041794
Short name T372
Test name
Test status
Simulation time 24645864 ps
CPU time 1.43 seconds
Started Aug 01 06:26:37 PM PDT 24
Finished Aug 01 06:26:39 PM PDT 24
Peak memory 236728 kb
Host smart-7984036f-eb7e-463d-87e1-ef4d60d5db5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4193041794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.4193041794
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.2195568727
Short name T172
Test name
Test status
Simulation time 6676207 ps
CPU time 1.42 seconds
Started Aug 01 06:26:31 PM PDT 24
Finished Aug 01 06:26:32 PM PDT 24
Peak memory 237704 kb
Host smart-72dfec8e-02fb-41d1-84e3-39693b23dfb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2195568727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.2195568727
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.1628133162
Short name T821
Test name
Test status
Simulation time 7253977 ps
CPU time 1.41 seconds
Started Aug 01 06:26:22 PM PDT 24
Finished Aug 01 06:26:23 PM PDT 24
Peak memory 237680 kb
Host smart-1dc5c097-26f9-4e6b-9259-5f019157df27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1628133162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.1628133162
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.3600807314
Short name T761
Test name
Test status
Simulation time 13762777 ps
CPU time 1.31 seconds
Started Aug 01 06:26:33 PM PDT 24
Finished Aug 01 06:26:34 PM PDT 24
Peak memory 237720 kb
Host smart-9bf05dc0-ea51-46b5-904a-f21a6f1a5a25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3600807314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.3600807314
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.1534489896
Short name T784
Test name
Test status
Simulation time 14732706 ps
CPU time 1.32 seconds
Started Aug 01 06:26:29 PM PDT 24
Finished Aug 01 06:26:30 PM PDT 24
Peak memory 237724 kb
Host smart-94f494ed-8b9c-4805-9f85-baec2fa7ad08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1534489896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.1534489896
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.3073258264
Short name T371
Test name
Test status
Simulation time 8344678 ps
CPU time 1.55 seconds
Started Aug 01 06:26:28 PM PDT 24
Finished Aug 01 06:26:34 PM PDT 24
Peak memory 237708 kb
Host smart-07c4f8c7-78aa-404d-9e7b-c38a64fd0d9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3073258264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.3073258264
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.461001505
Short name T825
Test name
Test status
Simulation time 11062746 ps
CPU time 1.42 seconds
Started Aug 01 06:26:30 PM PDT 24
Finished Aug 01 06:26:32 PM PDT 24
Peak memory 236816 kb
Host smart-270fd4c2-b6eb-4ff4-bd12-108321eee3fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=461001505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.461001505
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.1682350742
Short name T770
Test name
Test status
Simulation time 9086107 ps
CPU time 1.32 seconds
Started Aug 01 06:26:23 PM PDT 24
Finished Aug 01 06:26:24 PM PDT 24
Peak memory 237712 kb
Host smart-c068e84d-712c-4dde-9626-8504a47a45d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1682350742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.1682350742
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.869844110
Short name T822
Test name
Test status
Simulation time 16454366 ps
CPU time 1.33 seconds
Started Aug 01 06:26:31 PM PDT 24
Finished Aug 01 06:26:33 PM PDT 24
Peak memory 237700 kb
Host smart-d390929c-5396-481f-b4a1-bc7afd9695d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=869844110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.869844110
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.4144769078
Short name T755
Test name
Test status
Simulation time 16916354 ps
CPU time 1.38 seconds
Started Aug 01 06:26:55 PM PDT 24
Finished Aug 01 06:26:57 PM PDT 24
Peak memory 235676 kb
Host smart-220f632e-dc50-4081-a6e8-0e548289ff9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4144769078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.4144769078
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.3444636268
Short name T817
Test name
Test status
Simulation time 14436020091 ps
CPU time 155.05 seconds
Started Aug 01 06:26:17 PM PDT 24
Finished Aug 01 06:28:52 PM PDT 24
Peak memory 240736 kb
Host smart-330439ad-e761-468a-b870-12ad434741e4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3444636268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.3444636268
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.2063940960
Short name T721
Test name
Test status
Simulation time 11380676924 ps
CPU time 212.49 seconds
Started Aug 01 06:26:30 PM PDT 24
Finished Aug 01 06:30:05 PM PDT 24
Peak memory 237844 kb
Host smart-00e02c6b-f3d9-47f1-b1e4-16f1f7168a32
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2063940960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.2063940960
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.2595287326
Short name T723
Test name
Test status
Simulation time 264761122 ps
CPU time 6.02 seconds
Started Aug 01 06:26:12 PM PDT 24
Finished Aug 01 06:26:18 PM PDT 24
Peak memory 248808 kb
Host smart-5d924f21-4fe4-4f0a-b9c5-4371d8fb0a81
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2595287326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.2595287326
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.3630871826
Short name T766
Test name
Test status
Simulation time 57226035 ps
CPU time 5.31 seconds
Started Aug 01 06:26:20 PM PDT 24
Finished Aug 01 06:26:26 PM PDT 24
Peak memory 240584 kb
Host smart-b4cf8b9a-ec85-4280-8e5f-f11a69607d90
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630871826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.3630871826
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.4202500069
Short name T764
Test name
Test status
Simulation time 135664834 ps
CPU time 9.82 seconds
Started Aug 01 06:26:11 PM PDT 24
Finished Aug 01 06:26:21 PM PDT 24
Peak memory 240592 kb
Host smart-590b23ed-5471-482a-8943-b5e34b65aa7e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4202500069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.4202500069
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.3831639008
Short name T779
Test name
Test status
Simulation time 17559147 ps
CPU time 1.43 seconds
Started Aug 01 06:26:17 PM PDT 24
Finished Aug 01 06:26:19 PM PDT 24
Peak memory 236784 kb
Host smart-1de14b32-aaa7-4b6c-88b2-c20cfd46f501
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3831639008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.3831639008
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.2811055614
Short name T756
Test name
Test status
Simulation time 1048154755 ps
CPU time 19.08 seconds
Started Aug 01 06:26:11 PM PDT 24
Finished Aug 01 06:26:31 PM PDT 24
Peak memory 240576 kb
Host smart-409f1b56-1eac-49c1-b694-f43bee2c2ecc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2811055614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.2811055614
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.1033543492
Short name T145
Test name
Test status
Simulation time 1720538486 ps
CPU time 98.96 seconds
Started Aug 01 06:26:15 PM PDT 24
Finished Aug 01 06:27:54 PM PDT 24
Peak memory 266740 kb
Host smart-29050aa4-6e94-456e-963b-bfc347636947
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1033543492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.1033543492
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.1706840837
Short name T141
Test name
Test status
Simulation time 8904920341 ps
CPU time 363.7 seconds
Started Aug 01 06:26:11 PM PDT 24
Finished Aug 01 06:32:15 PM PDT 24
Peak memory 265740 kb
Host smart-d755b2b7-39d8-4283-b165-8e754f1c549c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706840837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.1706840837
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.915512079
Short name T709
Test name
Test status
Simulation time 194719916 ps
CPU time 14.75 seconds
Started Aug 01 06:26:21 PM PDT 24
Finished Aug 01 06:26:36 PM PDT 24
Peak memory 256864 kb
Host smart-f0016b55-689a-462c-b178-7b8d469f0308
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=915512079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.915512079
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.3443836867
Short name T735
Test name
Test status
Simulation time 152642831 ps
CPU time 22.53 seconds
Started Aug 01 06:26:13 PM PDT 24
Finished Aug 01 06:26:36 PM PDT 24
Peak memory 240640 kb
Host smart-dca2bbb7-4d92-4a56-961e-dd07dff5f5d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3443836867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.3443836867
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.2105289591
Short name T780
Test name
Test status
Simulation time 9057820 ps
CPU time 1.46 seconds
Started Aug 01 06:26:58 PM PDT 24
Finished Aug 01 06:26:59 PM PDT 24
Peak memory 237720 kb
Host smart-103bd494-11d4-47ea-a6d5-ba2d48b5a50d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2105289591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.2105289591
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.1215213309
Short name T173
Test name
Test status
Simulation time 6304133 ps
CPU time 1.45 seconds
Started Aug 01 06:26:45 PM PDT 24
Finished Aug 01 06:26:47 PM PDT 24
Peak memory 236840 kb
Host smart-8d08a930-068d-48f2-a5e9-fb54f2e2ee13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1215213309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.1215213309
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.2769509541
Short name T171
Test name
Test status
Simulation time 7990692 ps
CPU time 1.32 seconds
Started Aug 01 06:26:51 PM PDT 24
Finished Aug 01 06:26:52 PM PDT 24
Peak memory 237708 kb
Host smart-d1166428-d0bd-41c3-b78f-fc54a2033205
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2769509541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.2769509541
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.1414643952
Short name T789
Test name
Test status
Simulation time 43988443 ps
CPU time 1.45 seconds
Started Aug 01 06:26:38 PM PDT 24
Finished Aug 01 06:26:40 PM PDT 24
Peak memory 237704 kb
Host smart-3d5ede77-00bb-4ac1-81e3-42e9fb6cd40a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1414643952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.1414643952
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.971798285
Short name T823
Test name
Test status
Simulation time 10781900 ps
CPU time 1.65 seconds
Started Aug 01 06:26:36 PM PDT 24
Finished Aug 01 06:26:37 PM PDT 24
Peak memory 237704 kb
Host smart-79eac9ee-d681-4469-a35e-198c9266f18d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=971798285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.971798285
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.4258123550
Short name T788
Test name
Test status
Simulation time 71105785 ps
CPU time 1.37 seconds
Started Aug 01 06:26:31 PM PDT 24
Finished Aug 01 06:26:32 PM PDT 24
Peak memory 237548 kb
Host smart-bc300b37-5ea8-4269-928f-23a5fc759df7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4258123550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.4258123550
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.2087762521
Short name T771
Test name
Test status
Simulation time 15492558 ps
CPU time 1.32 seconds
Started Aug 01 06:26:34 PM PDT 24
Finished Aug 01 06:26:36 PM PDT 24
Peak memory 236804 kb
Host smart-3e1b40a5-ec0d-4c38-9100-87a59f07eae8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2087762521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.2087762521
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.2144215231
Short name T787
Test name
Test status
Simulation time 47798060 ps
CPU time 1.26 seconds
Started Aug 01 06:26:55 PM PDT 24
Finished Aug 01 06:26:57 PM PDT 24
Peak memory 235704 kb
Host smart-d270eac4-e97e-4827-97f1-d4441b82cd53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2144215231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.2144215231
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.1278145037
Short name T799
Test name
Test status
Simulation time 17108002 ps
CPU time 1.28 seconds
Started Aug 01 06:26:37 PM PDT 24
Finished Aug 01 06:26:38 PM PDT 24
Peak memory 235756 kb
Host smart-a3a874d4-46c8-407d-b116-8ad7405f6816
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1278145037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.1278145037
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.679088040
Short name T378
Test name
Test status
Simulation time 6310128 ps
CPU time 1.5 seconds
Started Aug 01 06:26:37 PM PDT 24
Finished Aug 01 06:26:38 PM PDT 24
Peak memory 235804 kb
Host smart-825bc8fb-3785-4e8e-bdd6-a999f029f06b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=679088040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.679088040
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.2392645888
Short name T796
Test name
Test status
Simulation time 292056073 ps
CPU time 6.26 seconds
Started Aug 01 06:26:14 PM PDT 24
Finished Aug 01 06:26:20 PM PDT 24
Peak memory 240712 kb
Host smart-a42ae2d8-1f7c-44a7-936b-a16a841a9a43
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392645888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.2392645888
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.2566978479
Short name T808
Test name
Test status
Simulation time 62035184 ps
CPU time 5.47 seconds
Started Aug 01 06:26:13 PM PDT 24
Finished Aug 01 06:26:19 PM PDT 24
Peak memory 237664 kb
Host smart-a5bcdc96-a269-429c-9c2d-c0fd327155bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2566978479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.2566978479
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.3546923533
Short name T375
Test name
Test status
Simulation time 6265708 ps
CPU time 1.48 seconds
Started Aug 01 06:26:16 PM PDT 24
Finished Aug 01 06:26:17 PM PDT 24
Peak memory 237720 kb
Host smart-6413a72e-b19e-4f4d-8cf8-ac6941cbf7ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3546923533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.3546923533
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.2184049114
Short name T205
Test name
Test status
Simulation time 168581723 ps
CPU time 20.14 seconds
Started Aug 01 06:26:16 PM PDT 24
Finished Aug 01 06:26:36 PM PDT 24
Peak memory 248836 kb
Host smart-be0ec8de-a8ae-4154-8379-0d9ded074b6b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2184049114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.2184049114
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.2059336543
Short name T158
Test name
Test status
Simulation time 2253593962 ps
CPU time 341.26 seconds
Started Aug 01 06:26:24 PM PDT 24
Finished Aug 01 06:32:06 PM PDT 24
Peak memory 265788 kb
Host smart-2301f11f-3513-4775-897a-8b4f8e8c89fa
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059336543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.2059336543
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.3505711612
Short name T714
Test name
Test status
Simulation time 128031058 ps
CPU time 9.14 seconds
Started Aug 01 06:26:13 PM PDT 24
Finished Aug 01 06:26:22 PM PDT 24
Peak memory 248872 kb
Host smart-2ef874d6-0f85-4a4c-872f-cb286b826f22
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3505711612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.3505711612
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.450209046
Short name T815
Test name
Test status
Simulation time 73280669 ps
CPU time 6.3 seconds
Started Aug 01 06:26:17 PM PDT 24
Finished Aug 01 06:26:24 PM PDT 24
Peak memory 239528 kb
Host smart-ec5ad635-c0f7-4889-b67f-3fe5ec3a24e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450209046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 6.alert_handler_csr_mem_rw_with_rand_reset.450209046
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.3958020320
Short name T760
Test name
Test status
Simulation time 48391896 ps
CPU time 4.67 seconds
Started Aug 01 06:26:23 PM PDT 24
Finished Aug 01 06:26:29 PM PDT 24
Peak memory 240572 kb
Host smart-012cc457-ff56-4d06-acf6-2f46146a1c8a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3958020320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.3958020320
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.2905815683
Short name T797
Test name
Test status
Simulation time 10554910 ps
CPU time 1.21 seconds
Started Aug 01 06:26:14 PM PDT 24
Finished Aug 01 06:26:16 PM PDT 24
Peak memory 236836 kb
Host smart-98277d30-7635-414e-82b8-fa44922922cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2905815683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.2905815683
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.2303157049
Short name T781
Test name
Test status
Simulation time 1440029724 ps
CPU time 23.18 seconds
Started Aug 01 06:26:15 PM PDT 24
Finished Aug 01 06:26:38 PM PDT 24
Peak memory 245920 kb
Host smart-f3e969d4-0ff0-4d68-9206-d0d407fcb885
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2303157049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.2303157049
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.3455701599
Short name T163
Test name
Test status
Simulation time 43952950158 ps
CPU time 162.67 seconds
Started Aug 01 06:26:17 PM PDT 24
Finished Aug 01 06:29:00 PM PDT 24
Peak memory 265604 kb
Host smart-0fc3eed4-d9bb-4865-8762-62454adb4515
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3455701599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.3455701599
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.2713461853
Short name T729
Test name
Test status
Simulation time 140639166 ps
CPU time 6.12 seconds
Started Aug 01 06:26:16 PM PDT 24
Finished Aug 01 06:26:22 PM PDT 24
Peak memory 252904 kb
Host smart-4c015711-97f4-420b-8f60-25753f4f6ccc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2713461853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.2713461853
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.1216169135
Short name T254
Test name
Test status
Simulation time 733883024 ps
CPU time 12.42 seconds
Started Aug 01 06:26:21 PM PDT 24
Finished Aug 01 06:26:34 PM PDT 24
Peak memory 251872 kb
Host smart-8a73bd4e-c042-4cdf-bdea-82041eb91fa1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216169135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.1216169135
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.1173378649
Short name T772
Test name
Test status
Simulation time 37395727 ps
CPU time 3.87 seconds
Started Aug 01 06:26:20 PM PDT 24
Finished Aug 01 06:26:24 PM PDT 24
Peak memory 236804 kb
Host smart-2402c52c-1341-47e4-9b7c-4b6dd922c103
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1173378649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.1173378649
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.3399801216
Short name T777
Test name
Test status
Simulation time 6148646 ps
CPU time 1.5 seconds
Started Aug 01 06:26:23 PM PDT 24
Finished Aug 01 06:26:25 PM PDT 24
Peak memory 236824 kb
Host smart-a0cbfccc-1418-4c9f-b648-7e0692d31be5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3399801216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.3399801216
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.357373800
Short name T728
Test name
Test status
Simulation time 171282556 ps
CPU time 19.93 seconds
Started Aug 01 06:26:20 PM PDT 24
Finished Aug 01 06:26:40 PM PDT 24
Peak memory 245008 kb
Host smart-0c19271d-c2c0-4606-ade4-e12ac8cf5093
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=357373800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_outs
tanding.357373800
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.401161675
Short name T137
Test name
Test status
Simulation time 26366843418 ps
CPU time 488.99 seconds
Started Aug 01 06:26:25 PM PDT 24
Finished Aug 01 06:34:34 PM PDT 24
Peak memory 265576 kb
Host smart-511043d8-a022-4191-ba4f-bcdac9f629cd
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401161675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.401161675
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.2945435647
Short name T801
Test name
Test status
Simulation time 450798393 ps
CPU time 16.19 seconds
Started Aug 01 06:26:23 PM PDT 24
Finished Aug 01 06:26:39 PM PDT 24
Peak memory 254148 kb
Host smart-3dd89350-6be3-4fb6-96e9-bbc35e7f3d58
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2945435647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.2945435647
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.652171252
Short name T214
Test name
Test status
Simulation time 136837413 ps
CPU time 10.43 seconds
Started Aug 01 06:26:21 PM PDT 24
Finished Aug 01 06:26:31 PM PDT 24
Peak memory 240200 kb
Host smart-de09e737-3186-48fe-8411-f662010965db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652171252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 8.alert_handler_csr_mem_rw_with_rand_reset.652171252
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.2638375227
Short name T767
Test name
Test status
Simulation time 91182784 ps
CPU time 3.46 seconds
Started Aug 01 06:26:23 PM PDT 24
Finished Aug 01 06:26:26 PM PDT 24
Peak memory 237668 kb
Host smart-d079b985-89e6-4be6-9d05-17a6f09290ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2638375227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.2638375227
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.1067335235
Short name T720
Test name
Test status
Simulation time 6821585 ps
CPU time 1.46 seconds
Started Aug 01 06:26:19 PM PDT 24
Finished Aug 01 06:26:21 PM PDT 24
Peak memory 236840 kb
Host smart-89154907-9d91-4614-a479-7a950202fb34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1067335235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.1067335235
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.1467388403
Short name T203
Test name
Test status
Simulation time 180040863 ps
CPU time 24.9 seconds
Started Aug 01 06:26:19 PM PDT 24
Finished Aug 01 06:26:44 PM PDT 24
Peak memory 245920 kb
Host smart-82077a7a-cb13-417f-8d8d-02edb052546b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1467388403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.1467388403
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.3115226002
Short name T257
Test name
Test status
Simulation time 764498979 ps
CPU time 12.31 seconds
Started Aug 01 06:26:16 PM PDT 24
Finished Aug 01 06:26:28 PM PDT 24
Peak memory 254108 kb
Host smart-994d1f8c-ef08-4d59-a39d-17a90aa3e42c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3115226002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.3115226002
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.1275701569
Short name T751
Test name
Test status
Simulation time 23306264 ps
CPU time 2.51 seconds
Started Aug 01 06:26:22 PM PDT 24
Finished Aug 01 06:26:25 PM PDT 24
Peak memory 237664 kb
Host smart-f0cb7adb-da85-46e6-b351-7e20617c748c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1275701569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.1275701569
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.292192135
Short name T775
Test name
Test status
Simulation time 189247784 ps
CPU time 13.48 seconds
Started Aug 01 06:26:17 PM PDT 24
Finished Aug 01 06:26:30 PM PDT 24
Peak memory 255292 kb
Host smart-c800ee9b-b29b-460a-98e9-8f4597521858
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292192135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 9.alert_handler_csr_mem_rw_with_rand_reset.292192135
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.3399710918
Short name T759
Test name
Test status
Simulation time 21854414 ps
CPU time 3.54 seconds
Started Aug 01 06:26:26 PM PDT 24
Finished Aug 01 06:26:30 PM PDT 24
Peak memory 237688 kb
Host smart-1c948f25-eaf5-4e85-9c92-1c2c8fed0019
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3399710918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.3399710918
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.527509345
Short name T722
Test name
Test status
Simulation time 10595143 ps
CPU time 1.41 seconds
Started Aug 01 06:26:24 PM PDT 24
Finished Aug 01 06:26:25 PM PDT 24
Peak memory 236796 kb
Host smart-bf08bd8b-91e0-45cb-b4a4-1a4e7394fd07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=527509345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.527509345
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.170329373
Short name T786
Test name
Test status
Simulation time 1908197419 ps
CPU time 46.78 seconds
Started Aug 01 06:26:21 PM PDT 24
Finished Aug 01 06:27:08 PM PDT 24
Peak memory 245920 kb
Host smart-b6197498-8368-45af-9383-0c8eab8fc53f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=170329373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_outs
tanding.170329373
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.3220602906
Short name T147
Test name
Test status
Simulation time 3441813801 ps
CPU time 117.11 seconds
Started Aug 01 06:26:18 PM PDT 24
Finished Aug 01 06:28:16 PM PDT 24
Peak memory 266628 kb
Host smart-e1eb9763-f398-46be-a5fd-4a668e6b2eb5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3220602906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.3220602906
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.1294036932
Short name T138
Test name
Test status
Simulation time 59963200234 ps
CPU time 1040.54 seconds
Started Aug 01 06:26:24 PM PDT 24
Finished Aug 01 06:43:45 PM PDT 24
Peak memory 273732 kb
Host smart-735508e7-30b1-4231-baed-0a7355be7cc9
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294036932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.1294036932
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.3870211583
Short name T708
Test name
Test status
Simulation time 191669343 ps
CPU time 13.49 seconds
Started Aug 01 06:26:18 PM PDT 24
Finished Aug 01 06:26:32 PM PDT 24
Peak memory 248748 kb
Host smart-1dde55e0-750b-44dc-bf75-754ae7807acf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3870211583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.3870211583
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.470766374
Short name T77
Test name
Test status
Simulation time 60504021155 ps
CPU time 1732 seconds
Started Aug 01 05:39:37 PM PDT 24
Finished Aug 01 06:08:29 PM PDT 24
Peak memory 272668 kb
Host smart-4eea0d04-9474-46fd-8b18-53fe598953cb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470766374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.470766374
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.1483644466
Short name T539
Test name
Test status
Simulation time 346707755 ps
CPU time 17.16 seconds
Started Aug 01 05:39:39 PM PDT 24
Finished Aug 01 05:39:56 PM PDT 24
Peak memory 248260 kb
Host smart-addf41f2-8a90-4ebe-93bd-cb876072a64e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1483644466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.1483644466
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.1222761176
Short name T656
Test name
Test status
Simulation time 1251899171 ps
CPU time 38.83 seconds
Started Aug 01 05:39:39 PM PDT 24
Finished Aug 01 05:40:18 PM PDT 24
Peak memory 256008 kb
Host smart-cfa3d0d9-5c9c-4251-af5c-98628a765eea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12227
61176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.1222761176
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.2516028345
Short name T86
Test name
Test status
Simulation time 1757498926 ps
CPU time 53.2 seconds
Started Aug 01 05:39:36 PM PDT 24
Finished Aug 01 05:40:29 PM PDT 24
Peak memory 256200 kb
Host smart-97141365-3b73-453f-a45e-aec537fd1e27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25160
28345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.2516028345
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.1816149166
Short name T208
Test name
Test status
Simulation time 149150349659 ps
CPU time 2287.83 seconds
Started Aug 01 05:39:39 PM PDT 24
Finished Aug 01 06:17:47 PM PDT 24
Peak memory 289124 kb
Host smart-29c18698-64a8-47a3-8cc9-3aec1f3d4732
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816149166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.1816149166
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.4228300936
Short name T677
Test name
Test status
Simulation time 42258526717 ps
CPU time 415.7 seconds
Started Aug 01 05:39:35 PM PDT 24
Finished Aug 01 05:46:31 PM PDT 24
Peak memory 248248 kb
Host smart-51fe3675-f917-4e00-af37-04f0db171832
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228300936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.4228300936
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.3652782554
Short name T455
Test name
Test status
Simulation time 910103904 ps
CPU time 27.49 seconds
Started Aug 01 05:39:37 PM PDT 24
Finished Aug 01 05:40:05 PM PDT 24
Peak memory 255584 kb
Host smart-be751aeb-1555-4cb0-ac37-7362e40f94f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36527
82554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.3652782554
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.4081117417
Short name T282
Test name
Test status
Simulation time 206665381 ps
CPU time 4.75 seconds
Started Aug 01 05:39:39 PM PDT 24
Finished Aug 01 05:39:44 PM PDT 24
Peak memory 239488 kb
Host smart-ee66db5e-28b1-41a0-aa3f-a3222dabbf3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40811
17417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.4081117417
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.1199495458
Short name T448
Test name
Test status
Simulation time 1722533416 ps
CPU time 29.74 seconds
Started Aug 01 05:39:37 PM PDT 24
Finished Aug 01 05:40:07 PM PDT 24
Peak memory 256436 kb
Host smart-bf9e4b6d-b26f-48db-9824-d8fa5407f826
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11994
95458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.1199495458
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.984268367
Short name T647
Test name
Test status
Simulation time 105126130998 ps
CPU time 3066.77 seconds
Started Aug 01 05:39:37 PM PDT 24
Finished Aug 01 06:30:45 PM PDT 24
Peak memory 334340 kb
Host smart-fd729b1e-d1d1-404b-bcdf-89ad2bc15031
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984268367 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.984268367
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.3595784006
Short name T51
Test name
Test status
Simulation time 22895964986 ps
CPU time 1581.82 seconds
Started Aug 01 05:39:37 PM PDT 24
Finished Aug 01 06:05:59 PM PDT 24
Peak memory 272656 kb
Host smart-a3fb2d4f-76a6-4b26-9de6-fe259162090f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595784006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.3595784006
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.3200606298
Short name T478
Test name
Test status
Simulation time 223501784 ps
CPU time 11.46 seconds
Started Aug 01 05:39:53 PM PDT 24
Finished Aug 01 05:40:05 PM PDT 24
Peak memory 248236 kb
Host smart-5b83656a-4228-4f4f-9594-243be6d493da
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3200606298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.3200606298
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.4229707588
Short name T685
Test name
Test status
Simulation time 8017033513 ps
CPU time 165.62 seconds
Started Aug 01 05:39:37 PM PDT 24
Finished Aug 01 05:42:23 PM PDT 24
Peak memory 256068 kb
Host smart-cc4c937b-2833-4fe2-86ec-e61da0450189
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42297
07588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.4229707588
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.286843788
Short name T615
Test name
Test status
Simulation time 1430674593 ps
CPU time 42.23 seconds
Started Aug 01 05:39:37 PM PDT 24
Finished Aug 01 05:40:20 PM PDT 24
Peak memory 256468 kb
Host smart-653149c9-f0dc-4861-bab2-2edb11ce9c7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28684
3788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.286843788
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.2792656140
Short name T189
Test name
Test status
Simulation time 31748260101 ps
CPU time 1942.59 seconds
Started Aug 01 05:39:48 PM PDT 24
Finished Aug 01 06:12:11 PM PDT 24
Peak memory 282408 kb
Host smart-ac21ae54-fa67-4d38-aa50-91e280003715
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792656140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.2792656140
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.422800132
Short name T191
Test name
Test status
Simulation time 29212173414 ps
CPU time 1896.92 seconds
Started Aug 01 05:39:50 PM PDT 24
Finished Aug 01 06:11:28 PM PDT 24
Peak memory 272272 kb
Host smart-499dcf7c-0cb7-4736-bf9f-600fbb9626a3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422800132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.422800132
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.3403113537
Short name T468
Test name
Test status
Simulation time 108317410 ps
CPU time 4.55 seconds
Started Aug 01 05:39:37 PM PDT 24
Finished Aug 01 05:39:42 PM PDT 24
Peak memory 248248 kb
Host smart-e4424da4-96a9-430f-a7c7-75e6dc974a54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34031
13537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.3403113537
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.4209587662
Short name T96
Test name
Test status
Simulation time 614353843 ps
CPU time 23.05 seconds
Started Aug 01 05:39:38 PM PDT 24
Finished Aug 01 05:40:01 PM PDT 24
Peak memory 248060 kb
Host smart-10b277e3-d31b-4814-8b99-a98cc2b62c69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42095
87662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.4209587662
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.56007619
Short name T88
Test name
Test status
Simulation time 1002149661 ps
CPU time 17.67 seconds
Started Aug 01 05:39:38 PM PDT 24
Finished Aug 01 05:39:56 PM PDT 24
Peak memory 248832 kb
Host smart-404687ed-ed03-4967-adc9-edd03196141f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56007
619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.56007619
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.660011106
Short name T698
Test name
Test status
Simulation time 768690400 ps
CPU time 50.62 seconds
Started Aug 01 05:39:39 PM PDT 24
Finished Aug 01 05:40:30 PM PDT 24
Peak memory 255720 kb
Host smart-14be4399-0698-4565-817b-d1706a1c0ea4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66001
1106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.660011106
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.817880735
Short name T43
Test name
Test status
Simulation time 19138145049 ps
CPU time 1744.47 seconds
Started Aug 01 05:39:49 PM PDT 24
Finished Aug 01 06:08:54 PM PDT 24
Peak memory 298100 kb
Host smart-b6b5e809-e7ee-4f07-b2b1-6ed4455443ae
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817880735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_hand
ler_stress_all.817880735
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.3930594990
Short name T533
Test name
Test status
Simulation time 220247643510 ps
CPU time 4591.6 seconds
Started Aug 01 05:39:51 PM PDT 24
Finished Aug 01 06:56:24 PM PDT 24
Peak memory 304404 kb
Host smart-1372a996-2335-4f19-abb5-9a5c8f7c6faa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930594990 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.3930594990
Directory /workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.3901788507
Short name T57
Test name
Test status
Simulation time 98651969449 ps
CPU time 2342.34 seconds
Started Aug 01 05:40:11 PM PDT 24
Finished Aug 01 06:19:14 PM PDT 24
Peak memory 271488 kb
Host smart-3c1aa479-bfd6-48d9-b5a6-843c244fbdee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901788507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.3901788507
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.55436373
Short name T454
Test name
Test status
Simulation time 801023147 ps
CPU time 8.05 seconds
Started Aug 01 05:40:12 PM PDT 24
Finished Aug 01 05:40:20 PM PDT 24
Peak memory 248204 kb
Host smart-b0a72741-f4ad-4ffc-bae5-f4a8e85fb6f0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=55436373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.55436373
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.3262285370
Short name T604
Test name
Test status
Simulation time 19031251454 ps
CPU time 182.82 seconds
Started Aug 01 05:40:06 PM PDT 24
Finished Aug 01 05:43:09 PM PDT 24
Peak memory 256400 kb
Host smart-c80d5f2a-d9c2-4d3e-8188-41f82d669c09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32622
85370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.3262285370
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.2792036314
Short name T90
Test name
Test status
Simulation time 642802238 ps
CPU time 37.85 seconds
Started Aug 01 05:40:08 PM PDT 24
Finished Aug 01 05:40:46 PM PDT 24
Peak memory 248196 kb
Host smart-30762c50-cee9-4daa-a840-a33c16f444ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27920
36314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.2792036314
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.2515554710
Short name T467
Test name
Test status
Simulation time 208947252271 ps
CPU time 1398.66 seconds
Started Aug 01 05:40:12 PM PDT 24
Finished Aug 01 06:03:30 PM PDT 24
Peak memory 288484 kb
Host smart-30b5dbed-4db2-425f-bcce-8afd085d0e34
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515554710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.2515554710
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.334386980
Short name T307
Test name
Test status
Simulation time 3397020653 ps
CPU time 71.71 seconds
Started Aug 01 05:40:08 PM PDT 24
Finished Aug 01 05:41:20 PM PDT 24
Peak memory 248144 kb
Host smart-d63cdecd-0727-4e4a-983a-5bcaebef6d5c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334386980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.334386980
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.3798998737
Short name T545
Test name
Test status
Simulation time 295614821 ps
CPU time 25.2 seconds
Started Aug 01 05:40:04 PM PDT 24
Finished Aug 01 05:40:30 PM PDT 24
Peak memory 248100 kb
Host smart-773e8381-6e15-4076-b9eb-8ba5b5ff794e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37989
98737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.3798998737
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.2796439598
Short name T562
Test name
Test status
Simulation time 643519397 ps
CPU time 39.87 seconds
Started Aug 01 05:40:04 PM PDT 24
Finished Aug 01 05:40:44 PM PDT 24
Peak memory 255996 kb
Host smart-e8f135a8-c127-4e06-a54a-13f3ee024b75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27964
39598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.2796439598
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.4035714502
Short name T470
Test name
Test status
Simulation time 244392882 ps
CPU time 5.97 seconds
Started Aug 01 05:40:05 PM PDT 24
Finished Aug 01 05:40:11 PM PDT 24
Peak memory 239496 kb
Host smart-7c156c67-2864-4adb-8717-2ffd5e854610
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40357
14502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.4035714502
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.3770740467
Short name T476
Test name
Test status
Simulation time 146187547 ps
CPU time 8.47 seconds
Started Aug 01 05:40:06 PM PDT 24
Finished Aug 01 05:40:15 PM PDT 24
Peak memory 254476 kb
Host smart-19c7d997-410e-4b86-a5c6-59edde945f30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37707
40467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.3770740467
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.1449800224
Short name T469
Test name
Test status
Simulation time 21083547104 ps
CPU time 1042.01 seconds
Started Aug 01 05:40:08 PM PDT 24
Finished Aug 01 05:57:31 PM PDT 24
Peak memory 264736 kb
Host smart-289cde98-22af-4ae3-84ba-c9409fcffd02
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449800224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.1449800224
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.2288278511
Short name T218
Test name
Test status
Simulation time 23506016 ps
CPU time 2.48 seconds
Started Aug 01 05:40:20 PM PDT 24
Finished Aug 01 05:40:22 PM PDT 24
Peak memory 248508 kb
Host smart-4ed31dd2-f30c-44a0-b7d3-42c3db2b3968
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2288278511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.2288278511
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.1847966151
Short name T569
Test name
Test status
Simulation time 31330975920 ps
CPU time 1768.96 seconds
Started Aug 01 05:40:19 PM PDT 24
Finished Aug 01 06:09:49 PM PDT 24
Peak memory 272544 kb
Host smart-efcf6b1a-5a39-4ad8-9d6e-1161bbbf7f72
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847966151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.1847966151
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.364100316
Short name T431
Test name
Test status
Simulation time 3362643902 ps
CPU time 38.09 seconds
Started Aug 01 05:40:18 PM PDT 24
Finished Aug 01 05:40:56 PM PDT 24
Peak memory 248320 kb
Host smart-fae11c9f-6741-421c-97cd-11c48b5fc961
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=364100316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.364100316
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.1503973750
Short name T461
Test name
Test status
Simulation time 4124276962 ps
CPU time 105.45 seconds
Started Aug 01 05:40:18 PM PDT 24
Finished Aug 01 05:42:04 PM PDT 24
Peak memory 255956 kb
Host smart-7694902d-2ccb-4973-bfab-35b3e7d6c0f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15039
73750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.1503973750
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.3667699607
Short name T37
Test name
Test status
Simulation time 1332968649 ps
CPU time 29.09 seconds
Started Aug 01 05:40:17 PM PDT 24
Finished Aug 01 05:40:46 PM PDT 24
Peak memory 256424 kb
Host smart-f73bc95b-b5c5-4bc7-b8f7-c2ed0a8e9244
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36676
99607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.3667699607
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.3317691086
Short name T31
Test name
Test status
Simulation time 14966922682 ps
CPU time 1465.51 seconds
Started Aug 01 05:40:20 PM PDT 24
Finished Aug 01 06:04:46 PM PDT 24
Peak memory 289160 kb
Host smart-75640d73-7b84-4460-914e-7db6624b6624
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317691086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.3317691086
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.3978363831
Short name T113
Test name
Test status
Simulation time 34469756712 ps
CPU time 364.33 seconds
Started Aug 01 05:40:17 PM PDT 24
Finished Aug 01 05:46:22 PM PDT 24
Peak memory 254840 kb
Host smart-7d65f92b-0c3b-40df-9a96-ac0366f712bb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978363831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.3978363831
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.1254011871
Short name T207
Test name
Test status
Simulation time 2585765807 ps
CPU time 48.26 seconds
Started Aug 01 05:40:20 PM PDT 24
Finished Aug 01 05:41:08 PM PDT 24
Peak memory 248344 kb
Host smart-5530ae20-701d-4c32-aa74-7ae903158759
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12540
11871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.1254011871
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.3955376443
Short name T103
Test name
Test status
Simulation time 333347295 ps
CPU time 20.39 seconds
Started Aug 01 05:40:20 PM PDT 24
Finished Aug 01 05:40:40 PM PDT 24
Peak memory 255728 kb
Host smart-17c69196-7a2a-4fd7-a2d4-6cec4812bb7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39553
76443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.3955376443
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.3182901975
Short name T553
Test name
Test status
Simulation time 456031502 ps
CPU time 29.32 seconds
Started Aug 01 05:40:19 PM PDT 24
Finished Aug 01 05:40:48 PM PDT 24
Peak memory 255528 kb
Host smart-fc9ea983-69a8-4358-b543-1661accafb08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31829
01975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.3182901975
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.1233805400
Short name T680
Test name
Test status
Simulation time 108301132 ps
CPU time 9.77 seconds
Started Aug 01 05:40:19 PM PDT 24
Finished Aug 01 05:40:29 PM PDT 24
Peak memory 254988 kb
Host smart-4c9af2cf-54a0-466c-84dd-a5df57a2ff36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12338
05400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.1233805400
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.2974378416
Short name T567
Test name
Test status
Simulation time 126632186891 ps
CPU time 2789.88 seconds
Started Aug 01 05:40:17 PM PDT 24
Finished Aug 01 06:26:48 PM PDT 24
Peak memory 287468 kb
Host smart-6443621c-695f-4c2d-9b1f-e46e78492931
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974378416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.2974378416
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.263216105
Short name T224
Test name
Test status
Simulation time 395840934 ps
CPU time 2.89 seconds
Started Aug 01 05:40:18 PM PDT 24
Finished Aug 01 05:40:21 PM PDT 24
Peak memory 248548 kb
Host smart-c3d1007c-7981-42b9-916c-dd91ee10a4b2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=263216105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.263216105
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.2209327584
Short name T274
Test name
Test status
Simulation time 9616886120 ps
CPU time 910.9 seconds
Started Aug 01 05:40:19 PM PDT 24
Finished Aug 01 05:55:31 PM PDT 24
Peak memory 270796 kb
Host smart-cea702b9-c6a4-424a-8eea-869a57691c87
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209327584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.2209327584
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.1894955483
Short name T394
Test name
Test status
Simulation time 4899000696 ps
CPU time 48.43 seconds
Started Aug 01 05:40:19 PM PDT 24
Finished Aug 01 05:41:08 PM PDT 24
Peak memory 248352 kb
Host smart-d46276b5-38c9-424c-8e1e-123301d4e9ad
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1894955483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.1894955483
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.3837063880
Short name T619
Test name
Test status
Simulation time 12048457525 ps
CPU time 235.9 seconds
Started Aug 01 05:40:17 PM PDT 24
Finished Aug 01 05:44:13 PM PDT 24
Peak memory 255628 kb
Host smart-05a16454-1203-4a09-95e0-e1ebb6b62aef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38370
63880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.3837063880
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.2264888460
Short name T556
Test name
Test status
Simulation time 2165289714 ps
CPU time 36.96 seconds
Started Aug 01 05:40:21 PM PDT 24
Finished Aug 01 05:40:58 PM PDT 24
Peak memory 256352 kb
Host smart-723c6751-3ba9-4615-aac9-638a2d9741f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22648
88460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.2264888460
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.2926616615
Short name T348
Test name
Test status
Simulation time 26529438206 ps
CPU time 1153.72 seconds
Started Aug 01 05:40:22 PM PDT 24
Finished Aug 01 05:59:36 PM PDT 24
Peak memory 288156 kb
Host smart-2194db61-9504-4b2e-ac4b-d12567c9469d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926616615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.2926616615
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.1666885505
Short name T639
Test name
Test status
Simulation time 43333904801 ps
CPU time 2247.67 seconds
Started Aug 01 05:40:18 PM PDT 24
Finished Aug 01 06:17:46 PM PDT 24
Peak memory 287208 kb
Host smart-efa20e39-caf7-419d-b2a7-076f70cb9a82
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666885505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.1666885505
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.1357365724
Short name T320
Test name
Test status
Simulation time 12341177192 ps
CPU time 500.57 seconds
Started Aug 01 05:40:18 PM PDT 24
Finished Aug 01 05:48:39 PM PDT 24
Peak memory 248060 kb
Host smart-2cd6a9e9-d94a-4f4b-86b5-c1969a454f14
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357365724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.1357365724
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.2197485067
Short name T384
Test name
Test status
Simulation time 1186347057 ps
CPU time 43.77 seconds
Started Aug 01 05:40:21 PM PDT 24
Finished Aug 01 05:41:05 PM PDT 24
Peak memory 255524 kb
Host smart-7d2173d2-ee00-4a75-923e-a154c316a2ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21974
85067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.2197485067
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.2869745123
Short name T403
Test name
Test status
Simulation time 621999909 ps
CPU time 10.71 seconds
Started Aug 01 05:40:19 PM PDT 24
Finished Aug 01 05:40:30 PM PDT 24
Peak memory 254396 kb
Host smart-e475e939-9feb-4819-accb-12d27517b250
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28697
45123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.2869745123
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.4286988453
Short name T561
Test name
Test status
Simulation time 746784324 ps
CPU time 19.47 seconds
Started Aug 01 05:40:18 PM PDT 24
Finished Aug 01 05:40:38 PM PDT 24
Peak memory 255784 kb
Host smart-d42e9641-fd1f-42ee-963b-d110603a5ded
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42869
88453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.4286988453
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.443491116
Short name T659
Test name
Test status
Simulation time 2316851634 ps
CPU time 37.77 seconds
Started Aug 01 05:40:18 PM PDT 24
Finished Aug 01 05:40:56 PM PDT 24
Peak memory 256192 kb
Host smart-144dc608-69b9-45bc-b314-20b22af234bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44349
1116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.443491116
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.4179155542
Short name T486
Test name
Test status
Simulation time 5702986906 ps
CPU time 395.17 seconds
Started Aug 01 05:40:19 PM PDT 24
Finished Aug 01 05:46:55 PM PDT 24
Peak memory 264536 kb
Host smart-b31ab97c-5389-4924-9d99-5240feb0312b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179155542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.4179155542
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.3546362481
Short name T225
Test name
Test status
Simulation time 58668562 ps
CPU time 4.73 seconds
Started Aug 01 05:40:38 PM PDT 24
Finished Aug 01 05:40:43 PM PDT 24
Peak memory 248528 kb
Host smart-9551888d-8407-4dc2-a317-1766271773c8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3546362481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.3546362481
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.3476659951
Short name T606
Test name
Test status
Simulation time 33147966647 ps
CPU time 2228.98 seconds
Started Aug 01 05:40:38 PM PDT 24
Finished Aug 01 06:17:47 PM PDT 24
Peak memory 286964 kb
Host smart-aeae4638-71a2-4af7-be74-f2f691b10a2b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476659951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.3476659951
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.3568474736
Short name T45
Test name
Test status
Simulation time 147270432 ps
CPU time 9.33 seconds
Started Aug 01 05:40:36 PM PDT 24
Finished Aug 01 05:40:46 PM PDT 24
Peak memory 248280 kb
Host smart-fe3af977-00ff-41d1-84a6-b89cc4a46644
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3568474736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.3568474736
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.1063738377
Short name T665
Test name
Test status
Simulation time 3239604867 ps
CPU time 126.82 seconds
Started Aug 01 05:40:37 PM PDT 24
Finished Aug 01 05:42:44 PM PDT 24
Peak memory 256272 kb
Host smart-ebe2cc3e-beb2-4890-a63d-7b70f296a287
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10637
38377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.1063738377
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.3573816261
Short name T445
Test name
Test status
Simulation time 1321668917 ps
CPU time 38.16 seconds
Started Aug 01 05:40:37 PM PDT 24
Finished Aug 01 05:41:15 PM PDT 24
Peak memory 248252 kb
Host smart-99dbe666-a039-4761-848b-4a00ae38625f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35738
16261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.3573816261
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.67283651
Short name T306
Test name
Test status
Simulation time 24182332789 ps
CPU time 669.22 seconds
Started Aug 01 05:40:37 PM PDT 24
Finished Aug 01 05:51:46 PM PDT 24
Peak memory 271648 kb
Host smart-2ccf5785-eae4-4f5d-a003-cc452694ed40
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67283651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.67283651
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.1222244006
Short name T474
Test name
Test status
Simulation time 199205217533 ps
CPU time 3066.25 seconds
Started Aug 01 05:40:37 PM PDT 24
Finished Aug 01 06:31:44 PM PDT 24
Peak memory 288396 kb
Host smart-6af1c37b-0ea9-4a95-9994-5c54503f39ae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222244006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.1222244006
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.2971372116
Short name T631
Test name
Test status
Simulation time 16523278719 ps
CPU time 631.1 seconds
Started Aug 01 05:40:34 PM PDT 24
Finished Aug 01 05:51:05 PM PDT 24
Peak memory 255028 kb
Host smart-cfffce6a-f0be-4fb4-9896-4d7576617d94
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971372116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.2971372116
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.4052674087
Short name T663
Test name
Test status
Simulation time 67116409 ps
CPU time 6.29 seconds
Started Aug 01 05:40:36 PM PDT 24
Finished Aug 01 05:40:43 PM PDT 24
Peak memory 248200 kb
Host smart-96d59c8d-62b9-42a1-b612-ae6594528440
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40526
74087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.4052674087
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.2570867514
Short name T73
Test name
Test status
Simulation time 197567784 ps
CPU time 15.69 seconds
Started Aug 01 05:40:36 PM PDT 24
Finished Aug 01 05:40:52 PM PDT 24
Peak memory 255952 kb
Host smart-f6d53517-741d-4949-a81f-e6b24965f436
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25708
67514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.2570867514
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.3296550499
Short name T288
Test name
Test status
Simulation time 227766795 ps
CPU time 22.34 seconds
Started Aug 01 05:40:36 PM PDT 24
Finished Aug 01 05:40:59 PM PDT 24
Peak memory 248296 kb
Host smart-4183228b-226e-4a78-b6de-caaa0c29f8fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32965
50499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.3296550499
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.4025949854
Short name T75
Test name
Test status
Simulation time 227453688 ps
CPU time 7.61 seconds
Started Aug 01 05:40:18 PM PDT 24
Finished Aug 01 05:40:26 PM PDT 24
Peak memory 248176 kb
Host smart-8ce2ec7b-e5f2-40fc-9aab-7919002ea263
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40259
49854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.4025949854
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.3167236125
Short name T558
Test name
Test status
Simulation time 15104386276 ps
CPU time 314.71 seconds
Started Aug 01 05:40:35 PM PDT 24
Finished Aug 01 05:45:49 PM PDT 24
Peak memory 264660 kb
Host smart-09921216-597a-4d3b-8a1c-5d789e05d375
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167236125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.3167236125
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.2611210230
Short name T216
Test name
Test status
Simulation time 73237796 ps
CPU time 3.61 seconds
Started Aug 01 05:40:40 PM PDT 24
Finished Aug 01 05:40:44 PM PDT 24
Peak memory 248540 kb
Host smart-5ebafa3c-81b0-4e39-afbd-d4b7e7508d1c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2611210230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.2611210230
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.3441444267
Short name T459
Test name
Test status
Simulation time 500296434 ps
CPU time 20.86 seconds
Started Aug 01 05:40:42 PM PDT 24
Finished Aug 01 05:41:03 PM PDT 24
Peak memory 248244 kb
Host smart-71db4061-d395-4a50-b2f0-80b3ce6d5503
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3441444267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.3441444267
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.2902320870
Short name T399
Test name
Test status
Simulation time 1874390150 ps
CPU time 37.58 seconds
Started Aug 01 05:40:34 PM PDT 24
Finished Aug 01 05:41:12 PM PDT 24
Peak memory 256308 kb
Host smart-f0fcf6a9-b4fe-4037-9714-a5b742890bcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29023
20870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.2902320870
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.3261440635
Short name T508
Test name
Test status
Simulation time 501412564 ps
CPU time 37.67 seconds
Started Aug 01 05:40:36 PM PDT 24
Finished Aug 01 05:41:14 PM PDT 24
Peak memory 255316 kb
Host smart-417e3c2f-98e2-4c0a-b6bf-db4f493a9513
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32614
40635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.3261440635
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.1722310476
Short name T190
Test name
Test status
Simulation time 46940546236 ps
CPU time 1047.14 seconds
Started Aug 01 05:40:37 PM PDT 24
Finished Aug 01 05:58:04 PM PDT 24
Peak memory 272676 kb
Host smart-5b80052b-b06e-4634-a62e-665534ade310
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722310476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.1722310476
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.2636692705
Short name T297
Test name
Test status
Simulation time 26353878021 ps
CPU time 295.43 seconds
Started Aug 01 05:40:36 PM PDT 24
Finished Aug 01 05:45:31 PM PDT 24
Peak memory 248228 kb
Host smart-fac046e1-0e0e-4774-872a-52fcdf6c17d0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636692705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.2636692705
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.693523825
Short name T408
Test name
Test status
Simulation time 447070190 ps
CPU time 6.59 seconds
Started Aug 01 05:40:35 PM PDT 24
Finished Aug 01 05:40:42 PM PDT 24
Peak memory 251992 kb
Host smart-c1d4f1f3-b19c-4df9-add6-0f3c4acb5e51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69352
3825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.693523825
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.1609590803
Short name T117
Test name
Test status
Simulation time 226611419 ps
CPU time 17 seconds
Started Aug 01 05:40:36 PM PDT 24
Finished Aug 01 05:40:53 PM PDT 24
Peak memory 247492 kb
Host smart-496e5095-4e3c-46d7-8752-6ae276afc186
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16095
90803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.1609590803
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.3886478889
Short name T505
Test name
Test status
Simulation time 441236708 ps
CPU time 41 seconds
Started Aug 01 05:40:37 PM PDT 24
Finished Aug 01 05:41:18 PM PDT 24
Peak memory 247688 kb
Host smart-6c71835e-2ad2-4200-84ea-cda07dd0ccfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38864
78889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.3886478889
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.1851875082
Short name T628
Test name
Test status
Simulation time 1091836269 ps
CPU time 37.99 seconds
Started Aug 01 05:40:40 PM PDT 24
Finished Aug 01 05:41:18 PM PDT 24
Peak memory 256400 kb
Host smart-1ad2c159-2089-43e5-8690-bb835f73688f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18518
75082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.1851875082
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.5597989
Short name T228
Test name
Test status
Simulation time 158637790 ps
CPU time 3.95 seconds
Started Aug 01 05:40:45 PM PDT 24
Finished Aug 01 05:40:49 PM PDT 24
Peak memory 248504 kb
Host smart-0191af40-ef6a-4bca-8daa-ab6af160adec
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=5597989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.5597989
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.4140328746
Short name T682
Test name
Test status
Simulation time 69551870192 ps
CPU time 1187.92 seconds
Started Aug 01 05:40:55 PM PDT 24
Finished Aug 01 06:00:44 PM PDT 24
Peak memory 272492 kb
Host smart-45a79156-0a3e-4f9a-8c79-d0958a2e58f6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140328746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.4140328746
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.3160285171
Short name T648
Test name
Test status
Simulation time 1097153874 ps
CPU time 15.41 seconds
Started Aug 01 05:40:43 PM PDT 24
Finished Aug 01 05:40:59 PM PDT 24
Peak memory 248324 kb
Host smart-83ca80dd-df0a-470a-ab85-bee9fa22f51f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3160285171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.3160285171
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.4217505146
Short name T391
Test name
Test status
Simulation time 4711294320 ps
CPU time 79.19 seconds
Started Aug 01 05:40:37 PM PDT 24
Finished Aug 01 05:41:56 PM PDT 24
Peak memory 256416 kb
Host smart-e26a416a-cbf8-4446-879e-e0721747d934
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42175
05146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.4217505146
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.590749333
Short name T502
Test name
Test status
Simulation time 294711353 ps
CPU time 18.8 seconds
Started Aug 01 05:40:35 PM PDT 24
Finished Aug 01 05:40:54 PM PDT 24
Peak memory 247828 kb
Host smart-f781eadb-2f10-41f0-8833-9af078ee0297
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59074
9333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.590749333
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.3283317773
Short name T434
Test name
Test status
Simulation time 11574969170 ps
CPU time 1409.37 seconds
Started Aug 01 05:40:43 PM PDT 24
Finished Aug 01 06:04:12 PM PDT 24
Peak memory 289180 kb
Host smart-cff0dd4b-ad40-4d15-a200-439b01981e17
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283317773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.3283317773
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.333294805
Short name T517
Test name
Test status
Simulation time 70099450 ps
CPU time 5.59 seconds
Started Aug 01 05:40:37 PM PDT 24
Finished Aug 01 05:40:42 PM PDT 24
Peak memory 248196 kb
Host smart-f2901093-a04c-434d-9c46-458b84806095
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33329
4805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.333294805
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.3190089758
Short name T622
Test name
Test status
Simulation time 125990594 ps
CPU time 8.69 seconds
Started Aug 01 05:40:36 PM PDT 24
Finished Aug 01 05:40:45 PM PDT 24
Peak memory 251076 kb
Host smart-f1cd3d6d-2968-44a4-9095-b669cccb3dfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31900
89758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.3190089758
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.3560650519
Short name T280
Test name
Test status
Simulation time 2914470004 ps
CPU time 49.23 seconds
Started Aug 01 05:40:36 PM PDT 24
Finished Aug 01 05:41:25 PM PDT 24
Peak memory 248428 kb
Host smart-43661146-9c67-4caa-8610-a5e58b717383
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35606
50519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.3560650519
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.2962246588
Short name T612
Test name
Test status
Simulation time 465019364 ps
CPU time 39.95 seconds
Started Aug 01 05:40:36 PM PDT 24
Finished Aug 01 05:41:16 PM PDT 24
Peak memory 256356 kb
Host smart-1152447d-5aa3-4522-8256-2166ea3a464d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29622
46588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.2962246588
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.3684720618
Short name T253
Test name
Test status
Simulation time 101504176066 ps
CPU time 686.09 seconds
Started Aug 01 05:40:42 PM PDT 24
Finished Aug 01 05:52:08 PM PDT 24
Peak memory 282576 kb
Host smart-73b6ea38-ab1c-4c7c-9e9f-3c6a776d790a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684720618 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.3684720618
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.1039309566
Short name T231
Test name
Test status
Simulation time 130991782 ps
CPU time 3.28 seconds
Started Aug 01 05:40:48 PM PDT 24
Finished Aug 01 05:40:51 PM PDT 24
Peak memory 248572 kb
Host smart-f17614cf-272e-4b26-a5ae-e38cb84e358c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1039309566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.1039309566
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.1566105544
Short name T603
Test name
Test status
Simulation time 15364919117 ps
CPU time 817.07 seconds
Started Aug 01 05:40:48 PM PDT 24
Finished Aug 01 05:54:25 PM PDT 24
Peak memory 265732 kb
Host smart-9252b136-a198-4edb-8308-675e0b91fa80
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566105544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.1566105544
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.1041453345
Short name T71
Test name
Test status
Simulation time 515736353 ps
CPU time 8.89 seconds
Started Aug 01 05:40:47 PM PDT 24
Finished Aug 01 05:40:56 PM PDT 24
Peak memory 248232 kb
Host smart-84a5e7e1-b30a-4db1-ac85-da93cc080779
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1041453345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.1041453345
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.2233564707
Short name T460
Test name
Test status
Simulation time 175100789 ps
CPU time 5.86 seconds
Started Aug 01 05:40:51 PM PDT 24
Finished Aug 01 05:40:57 PM PDT 24
Peak memory 247540 kb
Host smart-ae0b08ff-e6a7-46ec-853e-53735cbb41fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22335
64707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.2233564707
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.2259578967
Short name T267
Test name
Test status
Simulation time 4233953350 ps
CPU time 71.69 seconds
Started Aug 01 05:40:44 PM PDT 24
Finished Aug 01 05:41:56 PM PDT 24
Peak memory 249336 kb
Host smart-cf00c8b0-c1f5-4ffc-aad2-0714d8c4d26d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22595
78967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.2259578967
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.2041293237
Short name T352
Test name
Test status
Simulation time 39341240579 ps
CPU time 1197.46 seconds
Started Aug 01 05:40:48 PM PDT 24
Finished Aug 01 06:00:46 PM PDT 24
Peak memory 288976 kb
Host smart-547a01a6-76db-4ade-8fc2-652aeeae03f9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041293237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.2041293237
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.2479462561
Short name T548
Test name
Test status
Simulation time 47088662546 ps
CPU time 1646.96 seconds
Started Aug 01 05:40:48 PM PDT 24
Finished Aug 01 06:08:15 PM PDT 24
Peak memory 272968 kb
Host smart-4c9a02de-58f5-407b-b7ba-e40217075c12
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479462561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.2479462561
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.3560488190
Short name T233
Test name
Test status
Simulation time 994459986 ps
CPU time 19.52 seconds
Started Aug 01 05:41:00 PM PDT 24
Finished Aug 01 05:41:20 PM PDT 24
Peak memory 248292 kb
Host smart-d9f39be4-2eab-482c-a07c-3bb6321d4f99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35604
88190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.3560488190
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.1744503342
Short name T643
Test name
Test status
Simulation time 213839113 ps
CPU time 7.25 seconds
Started Aug 01 05:40:44 PM PDT 24
Finished Aug 01 05:40:52 PM PDT 24
Peak memory 247764 kb
Host smart-f40c5fcd-30c9-41b9-aeb3-d5c212dcc0ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17445
03342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.1744503342
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.2099190962
Short name T597
Test name
Test status
Simulation time 50505124 ps
CPU time 6.37 seconds
Started Aug 01 05:40:51 PM PDT 24
Finished Aug 01 05:40:58 PM PDT 24
Peak memory 251860 kb
Host smart-ec73d5da-3171-4b1b-b86f-f40ef8c7be49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20991
90962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.2099190962
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.3440337121
Short name T697
Test name
Test status
Simulation time 79532426 ps
CPU time 4.37 seconds
Started Aug 01 05:40:42 PM PDT 24
Finished Aug 01 05:40:46 PM PDT 24
Peak memory 250232 kb
Host smart-d9090c21-4037-4055-845d-7da53d05c6aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34403
37121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.3440337121
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.4033837116
Short name T78
Test name
Test status
Simulation time 262364405223 ps
CPU time 3336.18 seconds
Started Aug 01 05:40:52 PM PDT 24
Finished Aug 01 06:36:28 PM PDT 24
Peak memory 298424 kb
Host smart-964bae43-e7e9-4c97-97bd-8739397bd58d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033837116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.4033837116
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.339015615
Short name T230
Test name
Test status
Simulation time 36016905 ps
CPU time 3.9 seconds
Started Aug 01 05:40:48 PM PDT 24
Finished Aug 01 05:40:53 PM PDT 24
Peak memory 248524 kb
Host smart-8e758f3f-2898-4aab-b89c-88e7ef00330f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=339015615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.339015615
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.4132317646
Short name T99
Test name
Test status
Simulation time 144400448234 ps
CPU time 1933.87 seconds
Started Aug 01 05:41:02 PM PDT 24
Finished Aug 01 06:13:16 PM PDT 24
Peak memory 282516 kb
Host smart-31462f14-0422-492c-b9fb-8d67733362e4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132317646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.4132317646
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.3011828275
Short name T62
Test name
Test status
Simulation time 465615672 ps
CPU time 7.92 seconds
Started Aug 01 05:41:13 PM PDT 24
Finished Aug 01 05:41:21 PM PDT 24
Peak memory 248256 kb
Host smart-66190921-658f-4d0d-90f3-f11a4fca5dd0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3011828275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.3011828275
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.1078298756
Short name T209
Test name
Test status
Simulation time 6982425122 ps
CPU time 203.58 seconds
Started Aug 01 05:41:03 PM PDT 24
Finished Aug 01 05:44:27 PM PDT 24
Peak memory 250408 kb
Host smart-b5496373-2d9b-4978-89e0-7a23982215b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10782
98756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.1078298756
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.1838103430
Short name T563
Test name
Test status
Simulation time 425329044 ps
CPU time 25.43 seconds
Started Aug 01 05:41:02 PM PDT 24
Finished Aug 01 05:41:28 PM PDT 24
Peak memory 256352 kb
Host smart-fce93865-cf8d-40d2-be79-c53ddc741d83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18381
03430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.1838103430
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.2387053564
Short name T566
Test name
Test status
Simulation time 86730953087 ps
CPU time 1643.17 seconds
Started Aug 01 05:41:01 PM PDT 24
Finished Aug 01 06:08:25 PM PDT 24
Peak memory 267700 kb
Host smart-95cbe0b1-f4a5-43ca-8a8d-69d4e6d06cb2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387053564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.2387053564
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.3448919588
Short name T111
Test name
Test status
Simulation time 47473648322 ps
CPU time 938.86 seconds
Started Aug 01 05:41:00 PM PDT 24
Finished Aug 01 05:56:39 PM PDT 24
Peak memory 272920 kb
Host smart-093d0724-ec7c-4bfe-b4f5-77c72812d41e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448919588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.3448919588
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.378193250
Short name T119
Test name
Test status
Simulation time 294031348 ps
CPU time 22.16 seconds
Started Aug 01 05:40:55 PM PDT 24
Finished Aug 01 05:41:18 PM PDT 24
Peak memory 248232 kb
Host smart-edc41f8d-3057-4b19-bb6e-975686d7eb4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37819
3250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.378193250
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.624865698
Short name T25
Test name
Test status
Simulation time 164348457 ps
CPU time 10.8 seconds
Started Aug 01 05:41:03 PM PDT 24
Finished Aug 01 05:41:14 PM PDT 24
Peak memory 247752 kb
Host smart-8f58b888-7029-4eb4-bde7-831105b69840
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62486
5698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.624865698
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.2826464743
Short name T423
Test name
Test status
Simulation time 737727744 ps
CPU time 22.45 seconds
Started Aug 01 05:41:01 PM PDT 24
Finished Aug 01 05:41:23 PM PDT 24
Peak memory 248280 kb
Host smart-277822fd-f3b2-4e44-bc1b-c79315c93650
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28264
64743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.2826464743
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.3161771513
Short name T192
Test name
Test status
Simulation time 544457469 ps
CPU time 22.03 seconds
Started Aug 01 05:40:57 PM PDT 24
Finished Aug 01 05:41:19 PM PDT 24
Peak memory 255448 kb
Host smart-036cb8b4-4fe8-4f5d-a119-81ab08616f20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31617
71513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.3161771513
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.3560134356
Short name T513
Test name
Test status
Simulation time 211954085407 ps
CPU time 2283.85 seconds
Started Aug 01 05:41:02 PM PDT 24
Finished Aug 01 06:19:06 PM PDT 24
Peak memory 288632 kb
Host smart-b2e18258-30f4-43ff-aab4-ad7b6ede46c3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560134356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.3560134356
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.24175125
Short name T232
Test name
Test status
Simulation time 39648768 ps
CPU time 4.32 seconds
Started Aug 01 05:41:01 PM PDT 24
Finished Aug 01 05:41:06 PM PDT 24
Peak memory 248556 kb
Host smart-c69a4789-e918-4b81-a961-7355ab4c47c5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=24175125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.24175125
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.844374652
Short name T69
Test name
Test status
Simulation time 95599056571 ps
CPU time 1583.02 seconds
Started Aug 01 05:40:47 PM PDT 24
Finished Aug 01 06:07:11 PM PDT 24
Peak memory 268800 kb
Host smart-6062a356-9d77-4525-8e81-a74201971026
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844374652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.844374652
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.4155452631
Short name T686
Test name
Test status
Simulation time 614596117 ps
CPU time 29.04 seconds
Started Aug 01 05:41:01 PM PDT 24
Finished Aug 01 05:41:30 PM PDT 24
Peak memory 248192 kb
Host smart-d46662cf-b5f7-4f68-99dd-b291d5deed1b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4155452631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.4155452631
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.3313306139
Short name T530
Test name
Test status
Simulation time 998666632 ps
CPU time 15.72 seconds
Started Aug 01 05:40:44 PM PDT 24
Finished Aug 01 05:41:00 PM PDT 24
Peak memory 254300 kb
Host smart-04b3f861-bde6-4e0d-ac02-16596298012c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33133
06139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.3313306139
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.2685821462
Short name T323
Test name
Test status
Simulation time 6137200264 ps
CPU time 48.2 seconds
Started Aug 01 05:40:59 PM PDT 24
Finished Aug 01 05:41:48 PM PDT 24
Peak memory 249384 kb
Host smart-ea6737e8-4dd6-454a-a31f-2d354caa8d1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26858
21462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.2685821462
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.3185382541
Short name T523
Test name
Test status
Simulation time 35055279246 ps
CPU time 1465.22 seconds
Started Aug 01 05:40:48 PM PDT 24
Finished Aug 01 06:05:14 PM PDT 24
Peak memory 288556 kb
Host smart-fe5679bc-f6bc-4446-bf42-89ca204427cf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185382541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.3185382541
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.3244125932
Short name T429
Test name
Test status
Simulation time 22253040748 ps
CPU time 1361.98 seconds
Started Aug 01 05:41:02 PM PDT 24
Finished Aug 01 06:03:44 PM PDT 24
Peak memory 288068 kb
Host smart-18c9453e-f7ee-485e-8613-6aef65b1b976
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244125932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.3244125932
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.2399289569
Short name T296
Test name
Test status
Simulation time 3737698966 ps
CPU time 153.51 seconds
Started Aug 01 05:40:48 PM PDT 24
Finished Aug 01 05:43:22 PM PDT 24
Peak memory 254264 kb
Host smart-eea693a4-afff-415c-91cb-8339d5eab19d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399289569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.2399289569
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.956409342
Short name T127
Test name
Test status
Simulation time 424460897 ps
CPU time 13.11 seconds
Started Aug 01 05:41:00 PM PDT 24
Finished Aug 01 05:41:14 PM PDT 24
Peak memory 248200 kb
Host smart-b5df92b7-117f-434f-8c47-b060c113a4b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95640
9342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.956409342
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.2237587571
Short name T637
Test name
Test status
Simulation time 1749522060 ps
CPU time 39.14 seconds
Started Aug 01 05:41:23 PM PDT 24
Finished Aug 01 05:42:03 PM PDT 24
Peak memory 248304 kb
Host smart-e9a2964d-ed9d-4c38-bcc3-2ffd6887be92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22375
87571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.2237587571
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.917225866
Short name T343
Test name
Test status
Simulation time 1610316455 ps
CPU time 25.93 seconds
Started Aug 01 05:41:24 PM PDT 24
Finished Aug 01 05:41:50 PM PDT 24
Peak memory 247724 kb
Host smart-5de6d59c-06c1-4e41-b05d-60d5acafc269
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91722
5866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.917225866
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.3261542527
Short name T446
Test name
Test status
Simulation time 224639924 ps
CPU time 11.24 seconds
Started Aug 01 05:41:14 PM PDT 24
Finished Aug 01 05:41:25 PM PDT 24
Peak memory 256396 kb
Host smart-16f38831-d0be-4980-9cb9-69135a45284d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32615
42527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.3261542527
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.2541701509
Short name T226
Test name
Test status
Simulation time 21590125 ps
CPU time 3.02 seconds
Started Aug 01 05:41:03 PM PDT 24
Finished Aug 01 05:41:06 PM PDT 24
Peak memory 248580 kb
Host smart-7be73455-aac4-40bb-b6c7-b03bd8e951b3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2541701509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.2541701509
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.307073090
Short name T635
Test name
Test status
Simulation time 166769220472 ps
CPU time 2550.05 seconds
Started Aug 01 05:40:58 PM PDT 24
Finished Aug 01 06:23:29 PM PDT 24
Peak memory 288628 kb
Host smart-5140b1c6-24c8-455b-acee-323e7d9184c0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307073090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.307073090
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.3520905000
Short name T243
Test name
Test status
Simulation time 769398468 ps
CPU time 10.58 seconds
Started Aug 01 05:40:56 PM PDT 24
Finished Aug 01 05:41:06 PM PDT 24
Peak memory 248200 kb
Host smart-56f05cda-7fe8-4f50-8fb3-de6e15726d8e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3520905000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.3520905000
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.2908181757
Short name T573
Test name
Test status
Simulation time 28287969225 ps
CPU time 287.72 seconds
Started Aug 01 05:41:02 PM PDT 24
Finished Aug 01 05:45:50 PM PDT 24
Peak memory 251524 kb
Host smart-29fbe00d-bae3-4f36-a695-ac3a0ef7fae9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29081
81757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.2908181757
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.2837780944
Short name T634
Test name
Test status
Simulation time 10631963373 ps
CPU time 56.12 seconds
Started Aug 01 05:41:21 PM PDT 24
Finished Aug 01 05:42:17 PM PDT 24
Peak memory 256176 kb
Host smart-4b2d54f1-aa17-4fed-9d33-b1359e4c832b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28377
80944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.2837780944
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.1129899229
Short name T347
Test name
Test status
Simulation time 10413854492 ps
CPU time 1099.92 seconds
Started Aug 01 05:40:53 PM PDT 24
Finished Aug 01 05:59:13 PM PDT 24
Peak memory 280984 kb
Host smart-24e19b62-b412-470c-9e77-fbec0ec42f3e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129899229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.1129899229
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.2059098480
Short name T312
Test name
Test status
Simulation time 31845119440 ps
CPU time 358.07 seconds
Started Aug 01 05:40:52 PM PDT 24
Finished Aug 01 05:46:50 PM PDT 24
Peak memory 247192 kb
Host smart-a14df619-a079-456b-a1c4-5ddaea03d13e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059098480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.2059098480
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.4168765768
Short name T641
Test name
Test status
Simulation time 933132480 ps
CPU time 55.68 seconds
Started Aug 01 05:41:01 PM PDT 24
Finished Aug 01 05:41:57 PM PDT 24
Peak memory 255512 kb
Host smart-af8bc945-9e51-4b26-b48c-ac26bc4b2dde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41687
65768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.4168765768
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.688893392
Short name T538
Test name
Test status
Simulation time 845667516 ps
CPU time 13.57 seconds
Started Aug 01 05:40:52 PM PDT 24
Finished Aug 01 05:41:06 PM PDT 24
Peak memory 252776 kb
Host smart-721388ab-d285-4c9b-8d4f-e9cbf01ae2e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68889
3392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.688893392
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.117871939
Short name T406
Test name
Test status
Simulation time 634825471 ps
CPU time 33.77 seconds
Started Aug 01 05:40:46 PM PDT 24
Finished Aug 01 05:41:20 PM PDT 24
Peak memory 256444 kb
Host smart-2c2c65d8-6550-4c70-9603-1024c76bafcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11787
1939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.117871939
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.6638872
Short name T196
Test name
Test status
Simulation time 50106178 ps
CPU time 3.93 seconds
Started Aug 01 05:39:54 PM PDT 24
Finished Aug 01 05:39:58 PM PDT 24
Peak memory 248516 kb
Host smart-3ed4c481-e992-47a4-b89f-c9427393b1de
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=6638872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.6638872
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.922291515
Short name T19
Test name
Test status
Simulation time 31097110556 ps
CPU time 1524.07 seconds
Started Aug 01 05:39:51 PM PDT 24
Finished Aug 01 06:05:15 PM PDT 24
Peak memory 271916 kb
Host smart-b9193ad8-831e-4d75-a1e1-40b29e399c46
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922291515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.922291515
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.777271339
Short name T419
Test name
Test status
Simulation time 1728503452 ps
CPU time 10.15 seconds
Started Aug 01 05:39:53 PM PDT 24
Finished Aug 01 05:40:03 PM PDT 24
Peak memory 248236 kb
Host smart-4e71f7af-c11b-4e61-9245-f017af2da5af
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=777271339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.777271339
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.3799060038
Short name T47
Test name
Test status
Simulation time 807891434 ps
CPU time 72.31 seconds
Started Aug 01 05:39:56 PM PDT 24
Finished Aug 01 05:41:08 PM PDT 24
Peak memory 256412 kb
Host smart-7e1dae79-cf5f-4173-b9b2-a1971103e55f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37990
60038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.3799060038
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.1492110194
Short name T673
Test name
Test status
Simulation time 3876652457 ps
CPU time 54.8 seconds
Started Aug 01 05:39:47 PM PDT 24
Finished Aug 01 05:40:42 PM PDT 24
Peak memory 248220 kb
Host smart-0b255d1e-b0d1-4289-bca9-480ae98b4a77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14921
10194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.1492110194
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.3194936818
Short name T357
Test name
Test status
Simulation time 47089670378 ps
CPU time 2507.24 seconds
Started Aug 01 05:39:49 PM PDT 24
Finished Aug 01 06:21:37 PM PDT 24
Peak memory 288336 kb
Host smart-70242759-dc23-4002-9fc2-0cab6ae19711
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194936818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.3194936818
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.2145763142
Short name T70
Test name
Test status
Simulation time 32532809090 ps
CPU time 1767.03 seconds
Started Aug 01 05:39:52 PM PDT 24
Finished Aug 01 06:09:20 PM PDT 24
Peak memory 283492 kb
Host smart-dd30a851-eae9-4a9b-a838-4c3526ecb89b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145763142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.2145763142
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.3234410527
Short name T317
Test name
Test status
Simulation time 14068710514 ps
CPU time 144.83 seconds
Started Aug 01 05:39:50 PM PDT 24
Finished Aug 01 05:42:15 PM PDT 24
Peak memory 248256 kb
Host smart-5696c507-3ee4-42ee-82b0-fc4660ea8e5f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234410527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.3234410527
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.1759002250
Short name T50
Test name
Test status
Simulation time 193290084 ps
CPU time 12.47 seconds
Started Aug 01 05:39:47 PM PDT 24
Finished Aug 01 05:40:00 PM PDT 24
Peak memory 248224 kb
Host smart-633a904c-2c0c-4677-bc2c-f71c34720e26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17590
02250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.1759002250
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.2247784086
Short name T385
Test name
Test status
Simulation time 161571260 ps
CPU time 12.6 seconds
Started Aug 01 05:39:57 PM PDT 24
Finished Aug 01 05:40:10 PM PDT 24
Peak memory 254288 kb
Host smart-1d2594b4-502e-4254-8a25-37bb07ddeeaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22477
84086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.2247784086
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.4029774740
Short name T10
Test name
Test status
Simulation time 1614317316 ps
CPU time 66.37 seconds
Started Aug 01 05:39:51 PM PDT 24
Finished Aug 01 05:40:57 PM PDT 24
Peak memory 277764 kb
Host smart-92066c0f-3e46-48e1-b11f-8ac69396752a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4029774740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.4029774740
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.781226406
Short name T483
Test name
Test status
Simulation time 1707723015 ps
CPU time 65.2 seconds
Started Aug 01 05:39:48 PM PDT 24
Finished Aug 01 05:40:54 PM PDT 24
Peak memory 256452 kb
Host smart-46269032-630e-42bd-b050-49f33ed541ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78122
6406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.781226406
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.2024018157
Short name T568
Test name
Test status
Simulation time 5962304327 ps
CPU time 138.4 seconds
Started Aug 01 05:39:56 PM PDT 24
Finished Aug 01 05:42:15 PM PDT 24
Peak memory 256472 kb
Host smart-d03c9be6-fb72-41d1-ac81-d376acb83ec2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024018157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.2024018157
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.1337566867
Short name T657
Test name
Test status
Simulation time 72935340225 ps
CPU time 1215.06 seconds
Started Aug 01 05:41:32 PM PDT 24
Finished Aug 01 06:01:47 PM PDT 24
Peak memory 264724 kb
Host smart-f919a93d-f0b8-4cbf-8ba5-7e16b87fcabf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337566867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.1337566867
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.4267101415
Short name T490
Test name
Test status
Simulation time 3759952248 ps
CPU time 228.06 seconds
Started Aug 01 05:41:23 PM PDT 24
Finished Aug 01 05:45:12 PM PDT 24
Peak memory 255692 kb
Host smart-93cc2f48-a55e-481d-b7bc-e72cc14fdd7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42671
01415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.4267101415
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.2422394143
Short name T76
Test name
Test status
Simulation time 6300571498 ps
CPU time 22.57 seconds
Started Aug 01 05:41:20 PM PDT 24
Finished Aug 01 05:41:43 PM PDT 24
Peak memory 255732 kb
Host smart-be8bcb2d-5b73-4939-b92b-5ccf1a93a0b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24223
94143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.2422394143
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.1406955538
Short name T594
Test name
Test status
Simulation time 15423562364 ps
CPU time 1271.86 seconds
Started Aug 01 05:41:31 PM PDT 24
Finished Aug 01 06:02:43 PM PDT 24
Peak memory 281460 kb
Host smart-856a609b-a16c-4dd3-bd1a-f22f6c5de51c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406955538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.1406955538
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.291759059
Short name T112
Test name
Test status
Simulation time 19420508058 ps
CPU time 801.09 seconds
Started Aug 01 05:40:55 PM PDT 24
Finished Aug 01 05:54:17 PM PDT 24
Peak memory 272688 kb
Host smart-14545512-eba0-4e87-a2bf-519c1bcfa871
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291759059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.291759059
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.2194772903
Short name T537
Test name
Test status
Simulation time 29993404620 ps
CPU time 328.07 seconds
Started Aug 01 05:41:11 PM PDT 24
Finished Aug 01 05:46:39 PM PDT 24
Peak memory 255056 kb
Host smart-b1e810e5-3888-4f82-a187-a3086adde2a0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194772903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.2194772903
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.4080262793
Short name T381
Test name
Test status
Simulation time 968566742 ps
CPU time 53.09 seconds
Started Aug 01 05:40:54 PM PDT 24
Finished Aug 01 05:41:47 PM PDT 24
Peak memory 256264 kb
Host smart-ebf2e646-313f-4e7a-8199-41e4256a7725
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40802
62793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.4080262793
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.3717351242
Short name T672
Test name
Test status
Simulation time 520914949 ps
CPU time 8.61 seconds
Started Aug 01 05:42:40 PM PDT 24
Finished Aug 01 05:42:48 PM PDT 24
Peak memory 251100 kb
Host smart-5e49fe49-906e-4248-957a-ffa199fc5ad9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37173
51242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.3717351242
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.1407604388
Short name T321
Test name
Test status
Simulation time 687325301 ps
CPU time 13.77 seconds
Started Aug 01 05:41:06 PM PDT 24
Finished Aug 01 05:41:20 PM PDT 24
Peak memory 248204 kb
Host smart-c6f02981-1bf6-44b8-91f2-ea7acce7eecd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14076
04388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.1407604388
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.592334606
Short name T412
Test name
Test status
Simulation time 1317476977 ps
CPU time 15.47 seconds
Started Aug 01 05:40:56 PM PDT 24
Finished Aug 01 05:41:11 PM PDT 24
Peak memory 255892 kb
Host smart-00cac82b-7d71-46a4-8a36-e449a702b65c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59233
4606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.592334606
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.2456264860
Short name T494
Test name
Test status
Simulation time 17471707382 ps
CPU time 1358.19 seconds
Started Aug 01 05:43:33 PM PDT 24
Finished Aug 01 06:06:11 PM PDT 24
Peak memory 289276 kb
Host smart-6daf7bd8-56bf-4afc-b3bb-20b5aa41247a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456264860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.2456264860
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.3037668680
Short name T593
Test name
Test status
Simulation time 3254619750 ps
CPU time 98.72 seconds
Started Aug 01 05:41:33 PM PDT 24
Finished Aug 01 05:43:12 PM PDT 24
Peak memory 255796 kb
Host smart-910f35c3-08dd-4ec7-bf12-1de5b030215b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30376
68680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.3037668680
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.111796610
Short name T427
Test name
Test status
Simulation time 598825714 ps
CPU time 22.44 seconds
Started Aug 01 05:43:34 PM PDT 24
Finished Aug 01 05:43:57 PM PDT 24
Peak memory 247676 kb
Host smart-dbbc050a-02ac-4c0e-b9f7-39fbb37ad03e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11179
6610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.111796610
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.4185158710
Short name T122
Test name
Test status
Simulation time 61329834981 ps
CPU time 1301.55 seconds
Started Aug 01 05:41:20 PM PDT 24
Finished Aug 01 06:03:02 PM PDT 24
Peak memory 281116 kb
Host smart-f0f5951b-b89f-466a-900b-165983e714d2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185158710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.4185158710
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.2994156203
Short name T694
Test name
Test status
Simulation time 275924046087 ps
CPU time 2163.34 seconds
Started Aug 01 05:41:21 PM PDT 24
Finished Aug 01 06:17:25 PM PDT 24
Peak memory 282068 kb
Host smart-49f2c4df-4ef0-416a-8ce9-f28295e7ea34
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994156203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.2994156203
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.2234122472
Short name T642
Test name
Test status
Simulation time 4050146263 ps
CPU time 179.11 seconds
Started Aug 01 05:41:21 PM PDT 24
Finished Aug 01 05:44:21 PM PDT 24
Peak memory 247172 kb
Host smart-02ed0fd5-fbdb-46c1-9c00-d861c17abad5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234122472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.2234122472
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.1181396953
Short name T630
Test name
Test status
Simulation time 563620334 ps
CPU time 14.29 seconds
Started Aug 01 05:41:30 PM PDT 24
Finished Aug 01 05:41:44 PM PDT 24
Peak memory 255080 kb
Host smart-56358a4d-a332-45b3-b65b-1d4dd13ae82a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11813
96953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.1181396953
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.3340761849
Short name T581
Test name
Test status
Simulation time 481109049 ps
CPU time 21.07 seconds
Started Aug 01 05:43:35 PM PDT 24
Finished Aug 01 05:43:56 PM PDT 24
Peak memory 255760 kb
Host smart-de8a23d5-e8af-4271-90e0-4cb718eb0b8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33407
61849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.3340761849
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.699868583
Short name T415
Test name
Test status
Simulation time 294763514 ps
CPU time 8.39 seconds
Started Aug 01 05:41:25 PM PDT 24
Finished Aug 01 05:41:34 PM PDT 24
Peak memory 246996 kb
Host smart-fa998321-5605-4871-833c-e43f6474c12d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69986
8583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.699868583
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.2004974832
Short name T382
Test name
Test status
Simulation time 51179501 ps
CPU time 2.88 seconds
Started Aug 01 05:42:51 PM PDT 24
Finished Aug 01 05:42:54 PM PDT 24
Peak memory 250212 kb
Host smart-131078c1-dde6-4329-9bbe-55c78e8571c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20049
74832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.2004974832
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.3438062943
Short name T61
Test name
Test status
Simulation time 329870164855 ps
CPU time 2366.16 seconds
Started Aug 01 05:41:54 PM PDT 24
Finished Aug 01 06:21:21 PM PDT 24
Peak memory 281056 kb
Host smart-e7aee6ba-4436-4a24-aaf8-9e355d100d65
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438062943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.3438062943
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.3159846042
Short name T12
Test name
Test status
Simulation time 4337544655 ps
CPU time 236.19 seconds
Started Aug 01 05:43:50 PM PDT 24
Finished Aug 01 05:47:46 PM PDT 24
Peak memory 256520 kb
Host smart-d6007cd4-d240-4c7c-a10e-8116418350e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31598
46042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.3159846042
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.4199189232
Short name T600
Test name
Test status
Simulation time 477342093 ps
CPU time 12.28 seconds
Started Aug 01 05:41:05 PM PDT 24
Finished Aug 01 05:41:17 PM PDT 24
Peak memory 247720 kb
Host smart-0f6c93ed-0529-41ec-bee2-9a0f93c6322a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41991
89232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.4199189232
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.422780630
Short name T640
Test name
Test status
Simulation time 22902794354 ps
CPU time 1107.82 seconds
Started Aug 01 05:41:05 PM PDT 24
Finished Aug 01 05:59:33 PM PDT 24
Peak memory 288528 kb
Host smart-e6602e7d-dbb5-4265-9d01-5776ffe1e98c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422780630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.422780630
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.4222979107
Short name T442
Test name
Test status
Simulation time 46774986067 ps
CPU time 960.23 seconds
Started Aug 01 05:41:45 PM PDT 24
Finished Aug 01 05:57:46 PM PDT 24
Peak memory 281532 kb
Host smart-b4b9aee0-3ff9-4144-8c5f-9ddc4bbcc14a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222979107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.4222979107
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.901613247
Short name T510
Test name
Test status
Simulation time 1698257483 ps
CPU time 24.08 seconds
Started Aug 01 05:41:24 PM PDT 24
Finished Aug 01 05:41:48 PM PDT 24
Peak memory 255732 kb
Host smart-2ff7dd66-6195-41cf-86cf-8be0238fb9b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90161
3247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.901613247
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.1455566635
Short name T484
Test name
Test status
Simulation time 1464637191 ps
CPU time 35.29 seconds
Started Aug 01 05:41:04 PM PDT 24
Finished Aug 01 05:41:39 PM PDT 24
Peak memory 256148 kb
Host smart-fbf928f0-c922-48ad-b9cc-2f898301e187
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14555
66635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.1455566635
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.2276238892
Short name T250
Test name
Test status
Simulation time 1160695593 ps
CPU time 31.5 seconds
Started Aug 01 05:42:18 PM PDT 24
Finished Aug 01 05:42:49 PM PDT 24
Peak memory 256384 kb
Host smart-7f1678df-11e5-4cc7-adb6-43930011a955
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22762
38892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.2276238892
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.3820756450
Short name T583
Test name
Test status
Simulation time 1702998820 ps
CPU time 34.62 seconds
Started Aug 01 05:41:58 PM PDT 24
Finished Aug 01 05:42:32 PM PDT 24
Peak memory 256396 kb
Host smart-bb021c24-bd08-4bf2-a5bf-16989ca546a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38207
56450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.3820756450
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all_with_rand_reset.1169139773
Short name T531
Test name
Test status
Simulation time 141458723434 ps
CPU time 5817.6 seconds
Started Aug 01 05:43:34 PM PDT 24
Finished Aug 01 07:20:32 PM PDT 24
Peak memory 319576 kb
Host smart-d66ffeb1-aa31-4d3a-b4b7-ab61ff9a22aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169139773 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.alert_handler_stress_all_with_rand_reset.1169139773
Directory /workspace/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.4145989828
Short name T703
Test name
Test status
Simulation time 16403315629 ps
CPU time 1230.18 seconds
Started Aug 01 05:41:45 PM PDT 24
Finished Aug 01 06:02:15 PM PDT 24
Peak memory 281080 kb
Host smart-07835b5c-27ea-4b5b-a3c4-d5cf927f5e7a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145989828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.4145989828
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.3638759061
Short name T466
Test name
Test status
Simulation time 3057547834 ps
CPU time 94.6 seconds
Started Aug 01 05:41:47 PM PDT 24
Finished Aug 01 05:43:22 PM PDT 24
Peak memory 256532 kb
Host smart-9e5c7132-889a-4d85-b3b8-fe73d337ccf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36387
59061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.3638759061
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.3701842218
Short name T661
Test name
Test status
Simulation time 4205669368 ps
CPU time 67.93 seconds
Started Aug 01 05:43:00 PM PDT 24
Finished Aug 01 05:44:08 PM PDT 24
Peak memory 248276 kb
Host smart-96ac6769-e979-436f-b3fa-3aea35475060
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37018
42218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.3701842218
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.2385620905
Short name T614
Test name
Test status
Simulation time 26531089082 ps
CPU time 1528.11 seconds
Started Aug 01 05:41:37 PM PDT 24
Finished Aug 01 06:07:05 PM PDT 24
Peak memory 268828 kb
Host smart-e4f473ec-883d-4f3f-a62c-ff47bc26d2cc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385620905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.2385620905
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.855796556
Short name T310
Test name
Test status
Simulation time 7663552751 ps
CPU time 301.71 seconds
Started Aug 01 05:42:49 PM PDT 24
Finished Aug 01 05:47:51 PM PDT 24
Peak memory 248308 kb
Host smart-4b090ab5-e887-4daf-88f6-ca26333d8ddc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855796556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.855796556
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.3891049406
Short name T491
Test name
Test status
Simulation time 1425948328 ps
CPU time 15.93 seconds
Started Aug 01 05:43:33 PM PDT 24
Finished Aug 01 05:43:49 PM PDT 24
Peak memory 255668 kb
Host smart-95450612-13d3-4462-87b0-cfeb899e0ab3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38910
49406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.3891049406
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.179708120
Short name T527
Test name
Test status
Simulation time 2175102691 ps
CPU time 29.15 seconds
Started Aug 01 05:41:07 PM PDT 24
Finished Aug 01 05:41:36 PM PDT 24
Peak memory 256512 kb
Host smart-a8d36dd0-75c0-4c98-896d-5290539694f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17970
8120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.179708120
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.396167250
Short name T322
Test name
Test status
Simulation time 264316066 ps
CPU time 9.62 seconds
Started Aug 01 05:43:51 PM PDT 24
Finished Aug 01 05:44:01 PM PDT 24
Peak memory 248812 kb
Host smart-c768d5ca-7c36-424b-ad6d-f13b3e74b0e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39616
7250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.396167250
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.727206247
Short name T46
Test name
Test status
Simulation time 471433967 ps
CPU time 25.43 seconds
Started Aug 01 05:41:54 PM PDT 24
Finished Aug 01 05:42:20 PM PDT 24
Peak memory 255180 kb
Host smart-c2caea2f-9a40-4bed-b84c-5273ece6b1da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72720
6247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.727206247
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.3697802595
Short name T279
Test name
Test status
Simulation time 141584116062 ps
CPU time 2230.1 seconds
Started Aug 01 05:42:28 PM PDT 24
Finished Aug 01 06:19:38 PM PDT 24
Peak memory 272800 kb
Host smart-292627e1-50ef-440b-b128-3005f0ca33f3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697802595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.3697802595
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.2462753529
Short name T268
Test name
Test status
Simulation time 58186217766 ps
CPU time 4516.66 seconds
Started Aug 01 05:41:56 PM PDT 24
Finished Aug 01 06:57:13 PM PDT 24
Peak memory 329984 kb
Host smart-8828953b-db56-4e68-b7f5-2ca44e1dcb78
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462753529 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.2462753529
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.2575633512
Short name T669
Test name
Test status
Simulation time 17358129558 ps
CPU time 918.69 seconds
Started Aug 01 05:41:33 PM PDT 24
Finished Aug 01 05:56:52 PM PDT 24
Peak memory 272548 kb
Host smart-23900e2e-8840-4330-8c58-fd2d34216848
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575633512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.2575633512
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.2398692982
Short name T679
Test name
Test status
Simulation time 267364796 ps
CPU time 14.73 seconds
Started Aug 01 05:42:31 PM PDT 24
Finished Aug 01 05:42:46 PM PDT 24
Peak memory 255792 kb
Host smart-26e84f30-aeae-4cfc-9a87-f73271971117
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23986
92982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.2398692982
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.228627433
Short name T666
Test name
Test status
Simulation time 823159211 ps
CPU time 54.28 seconds
Started Aug 01 05:42:04 PM PDT 24
Finished Aug 01 05:42:59 PM PDT 24
Peak memory 248296 kb
Host smart-a3c91256-9e22-438e-9d1c-73f953a85729
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22862
7433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.228627433
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.489080243
Short name T358
Test name
Test status
Simulation time 11728648996 ps
CPU time 1099.61 seconds
Started Aug 01 05:42:07 PM PDT 24
Finished Aug 01 06:00:27 PM PDT 24
Peak memory 288320 kb
Host smart-af885a4d-6988-4042-9c12-f04c3e0c6d9c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489080243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.489080243
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.528380614
Short name T64
Test name
Test status
Simulation time 8568493118 ps
CPU time 186.76 seconds
Started Aug 01 05:42:11 PM PDT 24
Finished Aug 01 05:45:18 PM PDT 24
Peak memory 247180 kb
Host smart-66a22c14-7ccd-45d3-b431-b63e4fed53d2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528380614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.528380614
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.3079796178
Short name T449
Test name
Test status
Simulation time 21682950 ps
CPU time 3.15 seconds
Started Aug 01 05:42:17 PM PDT 24
Finished Aug 01 05:42:20 PM PDT 24
Peak memory 248232 kb
Host smart-c96c2389-97b4-4484-8ef9-dd85d81fae4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30797
96178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.3079796178
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.2717964940
Short name T601
Test name
Test status
Simulation time 3237681345 ps
CPU time 48.12 seconds
Started Aug 01 05:41:46 PM PDT 24
Finished Aug 01 05:42:35 PM PDT 24
Peak memory 248184 kb
Host smart-83d9f0b8-1a5c-446b-a7b8-1f747f61fc02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27179
64940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.2717964940
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.1915528879
Short name T674
Test name
Test status
Simulation time 2139041118 ps
CPU time 59.29 seconds
Started Aug 01 05:41:45 PM PDT 24
Finished Aug 01 05:42:44 PM PDT 24
Peak memory 256352 kb
Host smart-e416b738-529c-4975-8cc5-105a70afedda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19155
28879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.1915528879
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.2656369027
Short name T579
Test name
Test status
Simulation time 103965944713 ps
CPU time 884.17 seconds
Started Aug 01 05:42:05 PM PDT 24
Finished Aug 01 05:56:50 PM PDT 24
Peak memory 268820 kb
Host smart-0450ac5b-16d9-436c-b278-d3e3d61b694e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656369027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.2656369027
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.3708858782
Short name T125
Test name
Test status
Simulation time 1291927352 ps
CPU time 105.51 seconds
Started Aug 01 05:42:08 PM PDT 24
Finished Aug 01 05:43:53 PM PDT 24
Peak memory 255528 kb
Host smart-4085bf2e-8d67-46c9-803e-7bf6deab3512
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37088
58782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.3708858782
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.2991897195
Short name T422
Test name
Test status
Simulation time 395527520 ps
CPU time 8.65 seconds
Started Aug 01 05:43:22 PM PDT 24
Finished Aug 01 05:43:31 PM PDT 24
Peak memory 253676 kb
Host smart-626a5a6e-974b-47cb-b525-f673b6637a39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29918
97195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.2991897195
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.2775565407
Short name T41
Test name
Test status
Simulation time 42493197752 ps
CPU time 850.77 seconds
Started Aug 01 05:41:47 PM PDT 24
Finished Aug 01 05:55:58 PM PDT 24
Peak memory 272240 kb
Host smart-38c0ca64-bc5d-42e3-9f9f-92bd6a0c274a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775565407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.2775565407
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.3124337596
Short name T457
Test name
Test status
Simulation time 7149901543 ps
CPU time 682.64 seconds
Started Aug 01 05:42:52 PM PDT 24
Finished Aug 01 05:54:15 PM PDT 24
Peak memory 264640 kb
Host smart-bf0ca6ab-5584-40de-b2bc-5d7fc8652ec5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124337596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.3124337596
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.4073169205
Short name T198
Test name
Test status
Simulation time 11875708905 ps
CPU time 499.09 seconds
Started Aug 01 05:41:46 PM PDT 24
Finished Aug 01 05:50:05 PM PDT 24
Peak memory 255324 kb
Host smart-823d1d33-4735-484c-b803-37a9227d4f37
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073169205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.4073169205
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.2162881608
Short name T653
Test name
Test status
Simulation time 359252739 ps
CPU time 18.45 seconds
Started Aug 01 05:42:52 PM PDT 24
Finished Aug 01 05:43:10 PM PDT 24
Peak memory 248188 kb
Host smart-19a9be2b-2947-4bef-9b98-d659b68e70c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21628
81608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.2162881608
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.122707836
Short name T586
Test name
Test status
Simulation time 590024634 ps
CPU time 25.35 seconds
Started Aug 01 05:42:15 PM PDT 24
Finished Aug 01 05:42:41 PM PDT 24
Peak memory 256016 kb
Host smart-6b1df4e5-a587-49cd-a399-d782f3397ef0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12270
7836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.122707836
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.519425318
Short name T234
Test name
Test status
Simulation time 624529058 ps
CPU time 41.95 seconds
Started Aug 01 05:42:16 PM PDT 24
Finished Aug 01 05:42:58 PM PDT 24
Peak memory 247444 kb
Host smart-6ea20984-0e9c-4db3-9e64-56d55f8ae829
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51942
5318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.519425318
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.2591133977
Short name T607
Test name
Test status
Simulation time 980789042 ps
CPU time 15.88 seconds
Started Aug 01 05:41:47 PM PDT 24
Finished Aug 01 05:42:03 PM PDT 24
Peak memory 255004 kb
Host smart-620550c1-ac87-4e64-8d84-48471088047c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25911
33977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.2591133977
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.3911335533
Short name T613
Test name
Test status
Simulation time 160938445 ps
CPU time 15.98 seconds
Started Aug 01 05:41:16 PM PDT 24
Finished Aug 01 05:41:33 PM PDT 24
Peak memory 255236 kb
Host smart-c03bed4e-b611-4230-bc2d-64c4fa8246f4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911335533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.3911335533
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.1982579024
Short name T49
Test name
Test status
Simulation time 139603287946 ps
CPU time 1836.99 seconds
Started Aug 01 05:41:38 PM PDT 24
Finished Aug 01 06:12:15 PM PDT 24
Peak memory 272140 kb
Host smart-a9b1ec4c-f6c6-40f1-85fa-b03e2d4feb49
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982579024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.1982579024
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.2281493421
Short name T390
Test name
Test status
Simulation time 7955171105 ps
CPU time 245.61 seconds
Started Aug 01 05:42:54 PM PDT 24
Finished Aug 01 05:46:59 PM PDT 24
Peak memory 255924 kb
Host smart-9c62b2f3-d457-4c60-a18a-8464396bbfbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22814
93421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.2281493421
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.874660384
Short name T435
Test name
Test status
Simulation time 1961294549 ps
CPU time 41.61 seconds
Started Aug 01 05:41:30 PM PDT 24
Finished Aug 01 05:42:11 PM PDT 24
Peak memory 256004 kb
Host smart-fe881905-3c64-4aa3-9880-47dfba1e92cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87466
0384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.874660384
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.3257383992
Short name T701
Test name
Test status
Simulation time 24173883248 ps
CPU time 1359.88 seconds
Started Aug 01 05:44:36 PM PDT 24
Finished Aug 01 06:07:16 PM PDT 24
Peak memory 272520 kb
Host smart-be944b8b-f092-4639-918c-7cc5834da375
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257383992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.3257383992
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.4039050801
Short name T314
Test name
Test status
Simulation time 15529787465 ps
CPU time 132.95 seconds
Started Aug 01 05:42:56 PM PDT 24
Finished Aug 01 05:45:09 PM PDT 24
Peak memory 248324 kb
Host smart-8a113bc5-5132-47c2-ad0b-93bac380fb2c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039050801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.4039050801
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.2289275262
Short name T387
Test name
Test status
Simulation time 1207327291 ps
CPU time 74.14 seconds
Started Aug 01 05:41:47 PM PDT 24
Finished Aug 01 05:43:01 PM PDT 24
Peak memory 256476 kb
Host smart-9c2fff7f-dd88-4d5c-9cfe-a6a999430daa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22892
75262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.2289275262
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.2360200598
Short name T536
Test name
Test status
Simulation time 213624613 ps
CPU time 13.52 seconds
Started Aug 01 05:41:30 PM PDT 24
Finished Aug 01 05:41:44 PM PDT 24
Peak memory 247512 kb
Host smart-b9726769-899e-4959-8a4e-b9cdb7867cf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23602
00598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.2360200598
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.3098729101
Short name T341
Test name
Test status
Simulation time 2151330426 ps
CPU time 36.32 seconds
Started Aug 01 05:42:53 PM PDT 24
Finished Aug 01 05:43:29 PM PDT 24
Peak memory 248312 kb
Host smart-b1035c35-1807-4574-980b-d089687f828c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30987
29101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.3098729101
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.2613966943
Short name T456
Test name
Test status
Simulation time 269717003 ps
CPU time 20.17 seconds
Started Aug 01 05:42:52 PM PDT 24
Finished Aug 01 05:43:13 PM PDT 24
Peak memory 255884 kb
Host smart-0c31b490-9ef7-4b29-b868-75014468d7f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26139
66943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.2613966943
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.1057512490
Short name T540
Test name
Test status
Simulation time 2062034378 ps
CPU time 172.98 seconds
Started Aug 01 05:42:52 PM PDT 24
Finished Aug 01 05:45:46 PM PDT 24
Peak memory 256532 kb
Host smart-5a632ed0-33ad-4fc8-9611-1b339b5eeed7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057512490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.1057512490
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.3706302219
Short name T40
Test name
Test status
Simulation time 81377835516 ps
CPU time 959.79 seconds
Started Aug 01 05:41:18 PM PDT 24
Finished Aug 01 05:57:18 PM PDT 24
Peak memory 264708 kb
Host smart-d7ee0a11-7611-4cf2-a2d4-d9d509864bf3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706302219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.3706302219
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.3615202362
Short name T430
Test name
Test status
Simulation time 798347616 ps
CPU time 43.96 seconds
Started Aug 01 05:42:53 PM PDT 24
Finished Aug 01 05:43:37 PM PDT 24
Peak memory 249284 kb
Host smart-1b0628a9-6461-4396-89b5-8e6b44cfecb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36152
02362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.3615202362
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.2130453288
Short name T541
Test name
Test status
Simulation time 2097249199 ps
CPU time 36.83 seconds
Started Aug 01 05:42:50 PM PDT 24
Finished Aug 01 05:43:28 PM PDT 24
Peak memory 247920 kb
Host smart-e9ea456f-41b2-4a48-ad3a-f19322232124
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21304
53288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.2130453288
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.438690116
Short name T316
Test name
Test status
Simulation time 37593786147 ps
CPU time 919.12 seconds
Started Aug 01 05:41:37 PM PDT 24
Finished Aug 01 05:56:56 PM PDT 24
Peak memory 288940 kb
Host smart-c78cb106-e7e3-42bf-b899-9681d7e73365
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438690116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.438690116
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.3020525357
Short name T418
Test name
Test status
Simulation time 24022843041 ps
CPU time 1106.32 seconds
Started Aug 01 05:42:52 PM PDT 24
Finished Aug 01 06:01:19 PM PDT 24
Peak memory 288292 kb
Host smart-4814fba6-8e08-4c21-bbc0-81d842fa6c4d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020525357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.3020525357
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.4047852749
Short name T294
Test name
Test status
Simulation time 16721730377 ps
CPU time 344.39 seconds
Started Aug 01 05:42:54 PM PDT 24
Finished Aug 01 05:48:38 PM PDT 24
Peak memory 248272 kb
Host smart-2229f2e9-2c9b-4b07-a93f-e05f0049c550
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047852749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.4047852749
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.1877333071
Short name T425
Test name
Test status
Simulation time 360966722 ps
CPU time 33.35 seconds
Started Aug 01 05:41:59 PM PDT 24
Finished Aug 01 05:42:33 PM PDT 24
Peak memory 256364 kb
Host smart-dc0c55af-2397-494c-a8a4-108a2922cc33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18773
33071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.1877333071
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.736716361
Short name T627
Test name
Test status
Simulation time 280122419 ps
CPU time 19.81 seconds
Started Aug 01 05:42:56 PM PDT 24
Finished Aug 01 05:43:16 PM PDT 24
Peak memory 247540 kb
Host smart-d10486d6-4af7-4842-aa81-2e3ab08a48b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73671
6361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.736716361
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.3662012695
Short name T547
Test name
Test status
Simulation time 345158358 ps
CPU time 15.82 seconds
Started Aug 01 05:45:47 PM PDT 24
Finished Aug 01 05:46:04 PM PDT 24
Peak memory 254152 kb
Host smart-b29e2f1f-b1e3-4b65-a075-05cba01f05f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36620
12695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.3662012695
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.3813528384
Short name T610
Test name
Test status
Simulation time 1318276609 ps
CPU time 23.59 seconds
Started Aug 01 05:42:53 PM PDT 24
Finished Aug 01 05:43:16 PM PDT 24
Peak memory 256388 kb
Host smart-01f7ad1a-cf14-44f5-8b2b-ef8613f9952a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38135
28384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.3813528384
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.439562452
Short name T262
Test name
Test status
Simulation time 2988550064 ps
CPU time 245.7 seconds
Started Aug 01 05:42:55 PM PDT 24
Finished Aug 01 05:47:01 PM PDT 24
Peak memory 256516 kb
Host smart-60a87ef8-4a95-485b-8938-6552bda2382e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439562452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_han
dler_stress_all.439562452
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.347798726
Short name T108
Test name
Test status
Simulation time 259229858133 ps
CPU time 6136.98 seconds
Started Aug 01 05:42:53 PM PDT 24
Finished Aug 01 07:25:10 PM PDT 24
Peak memory 337224 kb
Host smart-03a3d2f7-c55e-4edb-bbcf-ccd2e8d441b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347798726 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.347798726
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.1074942200
Short name T706
Test name
Test status
Simulation time 36972884627 ps
CPU time 2289.3 seconds
Started Aug 01 05:41:42 PM PDT 24
Finished Aug 01 06:19:51 PM PDT 24
Peak memory 289208 kb
Host smart-0fd60383-650f-412c-aa4b-f5fbfd40211a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074942200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.1074942200
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.4206899230
Short name T528
Test name
Test status
Simulation time 2848004883 ps
CPU time 164.89 seconds
Started Aug 01 05:41:41 PM PDT 24
Finished Aug 01 05:44:26 PM PDT 24
Peak memory 256464 kb
Host smart-026bfd37-7768-4746-bc29-fecc36780e0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42068
99230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.4206899230
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.642223612
Short name T452
Test name
Test status
Simulation time 282446037 ps
CPU time 23.03 seconds
Started Aug 01 05:41:41 PM PDT 24
Finished Aug 01 05:42:04 PM PDT 24
Peak memory 248160 kb
Host smart-cad7c90d-1915-4c65-b441-67e903a16645
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64222
3612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.642223612
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.875727506
Short name T366
Test name
Test status
Simulation time 18731769009 ps
CPU time 1112.29 seconds
Started Aug 01 05:41:37 PM PDT 24
Finished Aug 01 06:00:09 PM PDT 24
Peak memory 272764 kb
Host smart-5b74050f-6778-4886-a4c1-bf9a9c6dbfac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875727506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.875727506
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.2253525106
Short name T552
Test name
Test status
Simulation time 36295447881 ps
CPU time 742.89 seconds
Started Aug 01 05:41:37 PM PDT 24
Finished Aug 01 05:54:00 PM PDT 24
Peak memory 288320 kb
Host smart-6d95ba8d-4e35-47c4-8be5-ff6aa901b2d6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253525106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.2253525106
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.1350826594
Short name T290
Test name
Test status
Simulation time 25517108819 ps
CPU time 278.73 seconds
Started Aug 01 05:41:58 PM PDT 24
Finished Aug 01 05:46:36 PM PDT 24
Peak memory 248316 kb
Host smart-bbc5f97e-4b9e-44b8-8511-e873f5ff26b1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350826594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.1350826594
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.2025330269
Short name T44
Test name
Test status
Simulation time 63165960 ps
CPU time 9.52 seconds
Started Aug 01 05:41:42 PM PDT 24
Finished Aug 01 05:41:52 PM PDT 24
Peak memory 248216 kb
Host smart-0ca5db4c-542c-4f19-bfa7-2a6c9b64c9e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20253
30269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.2025330269
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.3734259633
Short name T473
Test name
Test status
Simulation time 231793273 ps
CPU time 23.65 seconds
Started Aug 01 05:41:35 PM PDT 24
Finished Aug 01 05:41:59 PM PDT 24
Peak memory 256376 kb
Host smart-512fc26e-0dc0-4928-8158-6b3dfd2d2ee8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37342
59633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.3734259633
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.3654424842
Short name T344
Test name
Test status
Simulation time 549173423 ps
CPU time 33.61 seconds
Started Aug 01 05:41:34 PM PDT 24
Finished Aug 01 05:42:08 PM PDT 24
Peak memory 248772 kb
Host smart-ae922adb-bc3c-4788-968a-4dc1b7578e92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36544
24842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.3654424842
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.1964585513
Short name T392
Test name
Test status
Simulation time 1456560421 ps
CPU time 21.28 seconds
Started Aug 01 05:42:53 PM PDT 24
Finished Aug 01 05:43:14 PM PDT 24
Peak memory 255624 kb
Host smart-d192c3de-3ab0-4ed4-8501-742e09990d78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19645
85513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.1964585513
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.2859899021
Short name T684
Test name
Test status
Simulation time 173381641425 ps
CPU time 2537.68 seconds
Started Aug 01 05:41:41 PM PDT 24
Finished Aug 01 06:23:59 PM PDT 24
Peak memory 286736 kb
Host smart-4a0af2f8-fd9d-4712-b103-240a7381ea31
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859899021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.2859899021
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.417117536
Short name T260
Test name
Test status
Simulation time 51857214849 ps
CPU time 3824.36 seconds
Started Aug 01 05:41:43 PM PDT 24
Finished Aug 01 06:45:28 PM PDT 24
Peak memory 338048 kb
Host smart-8126f80f-5516-4f34-8472-41b7d132d10f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417117536 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.417117536
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.2174788641
Short name T585
Test name
Test status
Simulation time 50478331106 ps
CPU time 1132.65 seconds
Started Aug 01 05:41:42 PM PDT 24
Finished Aug 01 06:00:35 PM PDT 24
Peak memory 282788 kb
Host smart-db4b0cf2-0bfe-48b1-b1c2-e5343b9ddd62
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174788641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.2174788641
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.4176093770
Short name T194
Test name
Test status
Simulation time 1756935078 ps
CPU time 109.07 seconds
Started Aug 01 05:43:49 PM PDT 24
Finished Aug 01 05:45:38 PM PDT 24
Peak memory 256032 kb
Host smart-37a57eb5-3bdc-4563-9d1b-41486171fdbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41760
93770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.4176093770
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.195838480
Short name T24
Test name
Test status
Simulation time 691311101 ps
CPU time 13.35 seconds
Started Aug 01 05:41:42 PM PDT 24
Finished Aug 01 05:41:56 PM PDT 24
Peak memory 247492 kb
Host smart-d4c84f27-8f59-48ee-9c2b-e399bf4ab9b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19583
8480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.195838480
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.4143738958
Short name T120
Test name
Test status
Simulation time 50602003053 ps
CPU time 1500.65 seconds
Started Aug 01 05:41:38 PM PDT 24
Finished Aug 01 06:06:39 PM PDT 24
Peak memory 272184 kb
Host smart-d6db9e31-4425-4f8f-b192-4ab1a91bf0d1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143738958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.4143738958
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.3297373963
Short name T584
Test name
Test status
Simulation time 576008438147 ps
CPU time 2979.6 seconds
Started Aug 01 05:41:56 PM PDT 24
Finished Aug 01 06:31:36 PM PDT 24
Peak memory 288312 kb
Host smart-be883acf-2e1b-47c2-b619-b09912755e00
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297373963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.3297373963
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.91526182
Short name T14
Test name
Test status
Simulation time 16267634980 ps
CPU time 347.08 seconds
Started Aug 01 05:41:36 PM PDT 24
Finished Aug 01 05:47:23 PM PDT 24
Peak memory 248256 kb
Host smart-975e29f5-4f35-480a-af9a-df113ba6187a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91526182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.91526182
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.483539994
Short name T124
Test name
Test status
Simulation time 1204535825 ps
CPU time 70.48 seconds
Started Aug 01 05:41:43 PM PDT 24
Finished Aug 01 05:42:53 PM PDT 24
Peak memory 256400 kb
Host smart-d4ccbd6b-42c4-430f-9dca-21f52bddbcb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48353
9994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.483539994
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.699409369
Short name T246
Test name
Test status
Simulation time 719585094 ps
CPU time 6.81 seconds
Started Aug 01 05:41:33 PM PDT 24
Finished Aug 01 05:41:40 PM PDT 24
Peak memory 253432 kb
Host smart-a760b755-a617-44d6-b6ef-675a2119a9bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69940
9369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.699409369
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.1190169744
Short name T564
Test name
Test status
Simulation time 187292766 ps
CPU time 17.26 seconds
Started Aug 01 05:41:45 PM PDT 24
Finished Aug 01 05:42:03 PM PDT 24
Peak memory 256432 kb
Host smart-355fba45-efe9-4f64-bd94-616504934c4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11901
69744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.1190169744
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.1932274746
Short name T335
Test name
Test status
Simulation time 9518949159 ps
CPU time 128.67 seconds
Started Aug 01 05:43:34 PM PDT 24
Finished Aug 01 05:45:43 PM PDT 24
Peak memory 256468 kb
Host smart-5bc79f3e-31ea-4b0b-b7e5-3cafa390f891
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932274746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.1932274746
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.2585128011
Short name T632
Test name
Test status
Simulation time 36574286382 ps
CPU time 3080.94 seconds
Started Aug 01 05:41:43 PM PDT 24
Finished Aug 01 06:33:04 PM PDT 24
Peak memory 285328 kb
Host smart-23ae030e-44b4-43f9-a213-4a212a8fa70e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585128011 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.2585128011
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.2831702879
Short name T227
Test name
Test status
Simulation time 184124262 ps
CPU time 3.23 seconds
Started Aug 01 05:39:57 PM PDT 24
Finished Aug 01 05:40:00 PM PDT 24
Peak memory 248520 kb
Host smart-3c20359a-611c-4fde-950a-f961547d564b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2831702879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.2831702879
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.3449113079
Short name T68
Test name
Test status
Simulation time 516972193085 ps
CPU time 2390.92 seconds
Started Aug 01 05:39:47 PM PDT 24
Finished Aug 01 06:19:38 PM PDT 24
Peak memory 283336 kb
Host smart-f9c183f8-010f-4144-9ff2-a162817dffbe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449113079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.3449113079
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.234598587
Short name T252
Test name
Test status
Simulation time 6743220121 ps
CPU time 25.62 seconds
Started Aug 01 05:39:54 PM PDT 24
Finished Aug 01 05:40:19 PM PDT 24
Peak memory 248348 kb
Host smart-64ae7293-706f-4681-9692-30f608fb2014
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=234598587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.234598587
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.955897624
Short name T702
Test name
Test status
Simulation time 3333389544 ps
CPU time 176.67 seconds
Started Aug 01 05:39:54 PM PDT 24
Finished Aug 01 05:42:51 PM PDT 24
Peak memory 256016 kb
Host smart-105d5c86-8cf5-4da3-849a-eea358baca40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95589
7624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.955897624
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.3417017552
Short name T618
Test name
Test status
Simulation time 342352334 ps
CPU time 18.23 seconds
Started Aug 01 05:39:51 PM PDT 24
Finished Aug 01 05:40:10 PM PDT 24
Peak memory 247888 kb
Host smart-f333811e-6cc8-4a86-9039-d2c33ac9d199
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34170
17552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.3417017552
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.1687532115
Short name T349
Test name
Test status
Simulation time 30502709069 ps
CPU time 1598.65 seconds
Started Aug 01 05:39:54 PM PDT 24
Finished Aug 01 06:06:33 PM PDT 24
Peak memory 272904 kb
Host smart-3a58d16c-bea6-46df-8cf3-d5782b15d756
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687532115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.1687532115
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.1677039507
Short name T559
Test name
Test status
Simulation time 76266239263 ps
CPU time 1245.01 seconds
Started Aug 01 05:39:48 PM PDT 24
Finished Aug 01 06:00:34 PM PDT 24
Peak memory 272324 kb
Host smart-a0a46e78-667a-43a3-829b-622816e1befb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677039507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.1677039507
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.2556544981
Short name T671
Test name
Test status
Simulation time 34221569601 ps
CPU time 337.03 seconds
Started Aug 01 05:39:50 PM PDT 24
Finished Aug 01 05:45:27 PM PDT 24
Peak memory 248344 kb
Host smart-ca2fd7ab-4f67-4880-8891-8b38da907d36
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556544981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.2556544981
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.1598987914
Short name T433
Test name
Test status
Simulation time 210387951 ps
CPU time 17.01 seconds
Started Aug 01 05:39:49 PM PDT 24
Finished Aug 01 05:40:06 PM PDT 24
Peak memory 248240 kb
Host smart-74a96daa-1356-4884-8ea5-c4b4d836849f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15989
87914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.1598987914
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.4239018228
Short name T35
Test name
Test status
Simulation time 431081554 ps
CPU time 23.94 seconds
Started Aug 01 05:39:51 PM PDT 24
Finished Aug 01 05:40:15 PM PDT 24
Peak memory 273048 kb
Host smart-e6d7aebc-80a3-40d5-84b0-c21757a197b2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4239018228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.4239018228
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.2475785924
Short name T602
Test name
Test status
Simulation time 873280288 ps
CPU time 22.93 seconds
Started Aug 01 05:39:53 PM PDT 24
Finished Aug 01 05:40:16 PM PDT 24
Peak memory 248212 kb
Host smart-c5c5c103-14db-4e7b-95c5-2575eb5f0a3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24757
85924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.2475785924
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.2424582520
Short name T485
Test name
Test status
Simulation time 2308329023 ps
CPU time 11.4 seconds
Started Aug 01 05:39:48 PM PDT 24
Finished Aug 01 05:40:00 PM PDT 24
Peak memory 254664 kb
Host smart-2fe99144-434b-4f10-840d-69b70f3898ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24245
82520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.2424582520
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.1683794381
Short name T6
Test name
Test status
Simulation time 11783864083 ps
CPU time 213.04 seconds
Started Aug 01 05:39:53 PM PDT 24
Finished Aug 01 05:43:27 PM PDT 24
Peak memory 256444 kb
Host smart-05e2be76-0980-47e6-a5c8-01d918a0a405
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683794381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.1683794381
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.567787106
Short name T193
Test name
Test status
Simulation time 1107805680 ps
CPU time 85.44 seconds
Started Aug 01 05:41:39 PM PDT 24
Finished Aug 01 05:43:05 PM PDT 24
Peak memory 250268 kb
Host smart-8696a014-7705-41f7-8f6d-997730bfd0e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56778
7106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.567787106
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.830363241
Short name T2
Test name
Test status
Simulation time 601325704 ps
CPU time 13.46 seconds
Started Aug 01 05:41:32 PM PDT 24
Finished Aug 01 05:41:45 PM PDT 24
Peak memory 256432 kb
Host smart-38802ac7-27d5-491d-bf8c-d416be047fe3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83036
3241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.830363241
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.135660753
Short name T123
Test name
Test status
Simulation time 13665814605 ps
CPU time 1115.88 seconds
Started Aug 01 05:41:39 PM PDT 24
Finished Aug 01 06:00:15 PM PDT 24
Peak memory 288384 kb
Host smart-1cb63ebe-de45-4b5b-853b-f99c9b56065d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135660753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.135660753
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.4270441339
Short name T691
Test name
Test status
Simulation time 10680221504 ps
CPU time 1166.56 seconds
Started Aug 01 05:41:45 PM PDT 24
Finished Aug 01 06:01:12 PM PDT 24
Peak memory 288952 kb
Host smart-5a449961-cf29-4924-8df0-5f0e938f8df7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270441339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.4270441339
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.3057242782
Short name T441
Test name
Test status
Simulation time 36828704 ps
CPU time 3.04 seconds
Started Aug 01 05:41:32 PM PDT 24
Finished Aug 01 05:41:35 PM PDT 24
Peak memory 248248 kb
Host smart-e2a21025-66a3-44eb-8dec-cdb73f18798c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30572
42782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.3057242782
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.3189481546
Short name T482
Test name
Test status
Simulation time 960874128 ps
CPU time 59.18 seconds
Started Aug 01 05:41:40 PM PDT 24
Finished Aug 01 05:42:39 PM PDT 24
Peak memory 247832 kb
Host smart-e3950226-f915-46dc-a63d-8dccf28a5bb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31894
81546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.3189481546
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.1197570029
Short name T82
Test name
Test status
Simulation time 656155560 ps
CPU time 42.05 seconds
Started Aug 01 05:41:32 PM PDT 24
Finished Aug 01 05:42:15 PM PDT 24
Peak memory 256488 kb
Host smart-01aaf590-54c9-4ddc-9d06-845487e6a388
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11975
70029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.1197570029
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.1027368753
Short name T30
Test name
Test status
Simulation time 355972461 ps
CPU time 39.31 seconds
Started Aug 01 05:41:38 PM PDT 24
Finished Aug 01 05:42:17 PM PDT 24
Peak memory 256080 kb
Host smart-543d05fe-cfec-4da1-9a88-c432eeb75f67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10273
68753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.1027368753
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.3692876240
Short name T87
Test name
Test status
Simulation time 65243875414 ps
CPU time 3627.09 seconds
Started Aug 01 05:43:13 PM PDT 24
Finished Aug 01 06:43:41 PM PDT 24
Peak memory 288944 kb
Host smart-e030f4a5-f643-4557-bf94-0ed7171ee60e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692876240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.3692876240
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.429886537
Short name T333
Test name
Test status
Simulation time 250548173278 ps
CPU time 3093.76 seconds
Started Aug 01 05:43:46 PM PDT 24
Finished Aug 01 06:35:21 PM PDT 24
Peak memory 289432 kb
Host smart-cc6a8360-c227-4fe1-8d02-f9c4f15c21b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429886537 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.429886537
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.1123404102
Short name T236
Test name
Test status
Simulation time 13691482000 ps
CPU time 1417.38 seconds
Started Aug 01 05:41:42 PM PDT 24
Finished Aug 01 06:05:20 PM PDT 24
Peak memory 286756 kb
Host smart-e05864dc-2c9b-4239-b89f-295728a5a685
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123404102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.1123404102
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.4146474154
Short name T516
Test name
Test status
Simulation time 998890589 ps
CPU time 101.83 seconds
Started Aug 01 05:43:35 PM PDT 24
Finished Aug 01 05:45:17 PM PDT 24
Peak memory 256052 kb
Host smart-ecc1798b-768b-4e5e-a9d4-dc3cd2e5f69d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41464
74154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.4146474154
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.4183305782
Short name T477
Test name
Test status
Simulation time 685526554 ps
CPU time 45.21 seconds
Started Aug 01 05:43:45 PM PDT 24
Finished Aug 01 05:44:31 PM PDT 24
Peak memory 248128 kb
Host smart-47139a48-364b-4ce0-a55b-f8067622463d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41833
05782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.4183305782
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.2068501138
Short name T98
Test name
Test status
Simulation time 33557574910 ps
CPU time 2075.39 seconds
Started Aug 01 05:41:42 PM PDT 24
Finished Aug 01 06:16:17 PM PDT 24
Peak memory 289076 kb
Host smart-522995e3-c6d4-4f90-ba22-107a219d261f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068501138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.2068501138
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.1015071637
Short name T242
Test name
Test status
Simulation time 576905068 ps
CPU time 38.23 seconds
Started Aug 01 05:41:43 PM PDT 24
Finished Aug 01 05:42:21 PM PDT 24
Peak memory 255692 kb
Host smart-3fe5ccfa-6347-4b4d-80cb-18d4b93e71dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10150
71637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.1015071637
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.3922829124
Short name T636
Test name
Test status
Simulation time 205057419 ps
CPU time 22.77 seconds
Started Aug 01 05:42:42 PM PDT 24
Finished Aug 01 05:43:05 PM PDT 24
Peak memory 255764 kb
Host smart-4d264b35-63cf-4475-bdae-33c1bd27a3df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39228
29124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.3922829124
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.948588155
Short name T328
Test name
Test status
Simulation time 844971797 ps
CPU time 20.66 seconds
Started Aug 01 05:42:29 PM PDT 24
Finished Aug 01 05:42:49 PM PDT 24
Peak memory 247876 kb
Host smart-4319c5b4-9425-4711-a96d-02caafc4aebe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94858
8155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.948588155
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.1448999254
Short name T676
Test name
Test status
Simulation time 62140131 ps
CPU time 5.16 seconds
Started Aug 01 05:43:10 PM PDT 24
Finished Aug 01 05:43:15 PM PDT 24
Peak memory 250584 kb
Host smart-dd7d4c38-fa62-40cd-b23c-e1ba975ed623
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14489
99254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.1448999254
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.2433593410
Short name T106
Test name
Test status
Simulation time 497645323 ps
CPU time 19.1 seconds
Started Aug 01 05:42:44 PM PDT 24
Finished Aug 01 05:43:03 PM PDT 24
Peak memory 255288 kb
Host smart-9ab1748f-9c90-425f-9499-af70d7ee39c8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433593410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.2433593410
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.1681917366
Short name T565
Test name
Test status
Simulation time 4373513731 ps
CPU time 64.65 seconds
Started Aug 01 05:43:21 PM PDT 24
Finished Aug 01 05:44:25 PM PDT 24
Peak memory 256372 kb
Host smart-f3c303cb-a4b9-453f-99d0-a44db7d92a0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16819
17366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.1681917366
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.2514685626
Short name T417
Test name
Test status
Simulation time 321648708 ps
CPU time 19.78 seconds
Started Aug 01 05:42:43 PM PDT 24
Finished Aug 01 05:43:03 PM PDT 24
Peak memory 247736 kb
Host smart-35de38e6-2d44-4420-845c-33e7249da749
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25146
85626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.2514685626
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.242250266
Short name T355
Test name
Test status
Simulation time 14421385466 ps
CPU time 1054.3 seconds
Started Aug 01 05:43:25 PM PDT 24
Finished Aug 01 06:01:00 PM PDT 24
Peak memory 272276 kb
Host smart-2a55838d-3a9c-470a-8336-9ada980cc3d4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242250266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.242250266
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.233336763
Short name T401
Test name
Test status
Simulation time 43768273905 ps
CPU time 2623.32 seconds
Started Aug 01 05:42:30 PM PDT 24
Finished Aug 01 06:26:13 PM PDT 24
Peak memory 281032 kb
Host smart-5d9f257e-069e-4758-b733-da5d25973afb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233336763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.233336763
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.1813779716
Short name T670
Test name
Test status
Simulation time 3825505821 ps
CPU time 158.01 seconds
Started Aug 01 05:42:18 PM PDT 24
Finished Aug 01 05:44:56 PM PDT 24
Peak memory 248320 kb
Host smart-48593fe9-4b46-4754-a444-2e5ab90c319c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813779716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.1813779716
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.3774840898
Short name T688
Test name
Test status
Simulation time 304862543 ps
CPU time 26.61 seconds
Started Aug 01 05:41:56 PM PDT 24
Finished Aug 01 05:42:23 PM PDT 24
Peak memory 248292 kb
Host smart-8b990bfd-ce2a-488b-9b09-b4b722b13ef8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37748
40898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.3774840898
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.2397613599
Short name T248
Test name
Test status
Simulation time 1196691966 ps
CPU time 34.79 seconds
Started Aug 01 05:43:11 PM PDT 24
Finished Aug 01 05:43:46 PM PDT 24
Peak memory 255940 kb
Host smart-ebc09509-53a5-4a7f-9240-a515697b995c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23976
13599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.2397613599
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.176647723
Short name T334
Test name
Test status
Simulation time 1837199424 ps
CPU time 8.91 seconds
Started Aug 01 05:43:01 PM PDT 24
Finished Aug 01 05:43:10 PM PDT 24
Peak memory 247624 kb
Host smart-089bf9da-738d-43df-8d3a-092daf8b6585
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17664
7723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.176647723
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.2426659109
Short name T416
Test name
Test status
Simulation time 978205464 ps
CPU time 39.25 seconds
Started Aug 01 05:41:54 PM PDT 24
Finished Aug 01 05:42:33 PM PDT 24
Peak memory 256372 kb
Host smart-1e2f83fc-6279-424a-bc96-30f50a978cbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24266
59109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.2426659109
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.2776455665
Short name T542
Test name
Test status
Simulation time 255727254 ps
CPU time 13.65 seconds
Started Aug 01 05:41:43 PM PDT 24
Finished Aug 01 05:41:57 PM PDT 24
Peak memory 255880 kb
Host smart-120e4e59-d145-4840-83a4-5f5c5bd1bf4c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776455665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.2776455665
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.3523927102
Short name T389
Test name
Test status
Simulation time 106696666346 ps
CPU time 1623.07 seconds
Started Aug 01 05:42:00 PM PDT 24
Finished Aug 01 06:09:03 PM PDT 24
Peak memory 288616 kb
Host smart-a14b2ae3-6b58-429d-929a-60a11f2586a8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523927102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.3523927102
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.171831007
Short name T386
Test name
Test status
Simulation time 1108637730 ps
CPU time 102.83 seconds
Started Aug 01 05:43:14 PM PDT 24
Finished Aug 01 05:44:57 PM PDT 24
Peak memory 255744 kb
Host smart-d3198cf8-fc8c-4a4a-adb8-e5351217fc68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17183
1007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.171831007
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.3048188190
Short name T590
Test name
Test status
Simulation time 77922193 ps
CPU time 5.76 seconds
Started Aug 01 05:42:40 PM PDT 24
Finished Aug 01 05:42:46 PM PDT 24
Peak memory 240016 kb
Host smart-bbcfe6db-af0a-429d-8b3f-2dfb9b016c4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30481
88190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.3048188190
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.563349553
Short name T646
Test name
Test status
Simulation time 26594157044 ps
CPU time 1635.23 seconds
Started Aug 01 05:41:53 PM PDT 24
Finished Aug 01 06:09:08 PM PDT 24
Peak memory 272184 kb
Host smart-f2166e85-abae-4c7c-bfcc-059443d37869
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563349553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.563349553
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.3598381211
Short name T704
Test name
Test status
Simulation time 36060036936 ps
CPU time 2127.89 seconds
Started Aug 01 05:42:31 PM PDT 24
Finished Aug 01 06:17:59 PM PDT 24
Peak memory 284440 kb
Host smart-4c491645-9ffd-4fe2-a0a5-97b6ac35b955
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598381211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.3598381211
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.3842214664
Short name T311
Test name
Test status
Simulation time 40862567189 ps
CPU time 597.48 seconds
Started Aug 01 05:43:10 PM PDT 24
Finished Aug 01 05:53:08 PM PDT 24
Peak memory 248136 kb
Host smart-e80d52ba-2040-4eda-aa6e-d6406d9c0d06
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842214664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.3842214664
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.763975693
Short name T471
Test name
Test status
Simulation time 834896852 ps
CPU time 24.05 seconds
Started Aug 01 05:41:52 PM PDT 24
Finished Aug 01 05:42:16 PM PDT 24
Peak memory 248292 kb
Host smart-9226f8bf-97dc-4191-ad62-f397c5282bc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76397
5693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.763975693
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.2673850224
Short name T115
Test name
Test status
Simulation time 1200213971 ps
CPU time 26.27 seconds
Started Aug 01 05:43:46 PM PDT 24
Finished Aug 01 05:44:13 PM PDT 24
Peak memory 248288 kb
Host smart-793545c8-9829-4551-89a6-ce6176212a4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26738
50224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.2673850224
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.284592657
Short name T605
Test name
Test status
Simulation time 112289861 ps
CPU time 11.73 seconds
Started Aug 01 05:41:49 PM PDT 24
Finished Aug 01 05:42:01 PM PDT 24
Peak memory 248276 kb
Host smart-965ac0b7-5fa6-4a77-9a98-70c0453d47aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28459
2657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.284592657
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all_with_rand_reset.1742791156
Short name T188
Test name
Test status
Simulation time 15228649397 ps
CPU time 1455.29 seconds
Started Aug 01 05:43:09 PM PDT 24
Finished Aug 01 06:07:25 PM PDT 24
Peak memory 289428 kb
Host smart-16256432-5571-4a1e-b718-353f67e3e614
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742791156 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.alert_handler_stress_all_with_rand_reset.1742791156
Directory /workspace/33.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.1269572333
Short name T102
Test name
Test status
Simulation time 34174444062 ps
CPU time 760.85 seconds
Started Aug 01 05:43:22 PM PDT 24
Finished Aug 01 05:56:03 PM PDT 24
Peak memory 264708 kb
Host smart-adaab5c4-3919-4052-abbe-93dafbc7f7f7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269572333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.1269572333
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.1894036331
Short name T611
Test name
Test status
Simulation time 4610292696 ps
CPU time 137.09 seconds
Started Aug 01 05:41:55 PM PDT 24
Finished Aug 01 05:44:12 PM PDT 24
Peak memory 256060 kb
Host smart-6dbb56cf-a20b-4588-9cfb-aa6ed4a84acb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18940
36331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.1894036331
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.2728598668
Short name T397
Test name
Test status
Simulation time 1130281666 ps
CPU time 19.13 seconds
Started Aug 01 05:42:24 PM PDT 24
Finished Aug 01 05:42:43 PM PDT 24
Peak memory 254644 kb
Host smart-9eb54477-ee1b-4bc2-9e05-e20173700394
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27285
98668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.2728598668
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.2960908879
Short name T370
Test name
Test status
Simulation time 53066772263 ps
CPU time 1230.61 seconds
Started Aug 01 05:42:25 PM PDT 24
Finished Aug 01 06:02:56 PM PDT 24
Peak memory 285704 kb
Host smart-f7d54e42-10c6-4639-913f-94f8dc434155
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960908879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.2960908879
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.3864717354
Short name T623
Test name
Test status
Simulation time 33272264982 ps
CPU time 864.32 seconds
Started Aug 01 05:41:57 PM PDT 24
Finished Aug 01 05:56:21 PM PDT 24
Peak memory 272388 kb
Host smart-cc1466c1-e012-4452-8654-69723f02e117
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864717354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.3864717354
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.1344799221
Short name T304
Test name
Test status
Simulation time 11264267422 ps
CPU time 449.38 seconds
Started Aug 01 05:43:22 PM PDT 24
Finished Aug 01 05:50:52 PM PDT 24
Peak memory 248316 kb
Host smart-97768a05-3921-4643-be5f-21d64681cdf5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344799221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.1344799221
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.3149001667
Short name T432
Test name
Test status
Simulation time 4839141259 ps
CPU time 34.83 seconds
Started Aug 01 05:42:14 PM PDT 24
Finished Aug 01 05:42:49 PM PDT 24
Peak memory 256496 kb
Host smart-0128b2ad-9653-4718-a259-a6e2e155d3ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31490
01667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.3149001667
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.1668713682
Short name T28
Test name
Test status
Simulation time 335965416 ps
CPU time 7.58 seconds
Started Aug 01 05:41:59 PM PDT 24
Finished Aug 01 05:42:06 PM PDT 24
Peak memory 253236 kb
Host smart-da64ffcc-1eaf-4664-8d81-83dae2744794
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16687
13682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.1668713682
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.2228707935
Short name T289
Test name
Test status
Simulation time 56953031 ps
CPU time 4.9 seconds
Started Aug 01 05:43:22 PM PDT 24
Finished Aug 01 05:43:27 PM PDT 24
Peak memory 247820 kb
Host smart-05958732-1dbd-429f-af9c-87a0b02c3a69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22287
07935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.2228707935
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.4258320021
Short name T453
Test name
Test status
Simulation time 733999663 ps
CPU time 30.01 seconds
Started Aug 01 05:42:13 PM PDT 24
Finished Aug 01 05:42:43 PM PDT 24
Peak memory 255484 kb
Host smart-1a8a6e2a-5668-45cc-856e-47d3d1b50dd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42583
20021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.4258320021
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.1771787200
Short name T94
Test name
Test status
Simulation time 95146113 ps
CPU time 9.34 seconds
Started Aug 01 05:42:18 PM PDT 24
Finished Aug 01 05:42:27 PM PDT 24
Peak memory 255144 kb
Host smart-3620d0e7-bd5e-4480-ac26-d35b7250ded0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771787200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.1771787200
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.2562874277
Short name T95
Test name
Test status
Simulation time 19523535966 ps
CPU time 804.94 seconds
Started Aug 01 05:42:12 PM PDT 24
Finished Aug 01 05:55:37 PM PDT 24
Peak memory 272636 kb
Host smart-43c2a239-cf2c-409b-9bd3-3ef6e7e17036
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562874277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.2562874277
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.1267976689
Short name T275
Test name
Test status
Simulation time 3489134391 ps
CPU time 131.89 seconds
Started Aug 01 05:41:54 PM PDT 24
Finished Aug 01 05:44:06 PM PDT 24
Peak memory 255688 kb
Host smart-07626bbf-699a-42eb-a749-f0031b9c1b6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12679
76689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.1267976689
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.3520356774
Short name T496
Test name
Test status
Simulation time 388851805 ps
CPU time 32.85 seconds
Started Aug 01 05:41:58 PM PDT 24
Finished Aug 01 05:42:31 PM PDT 24
Peak memory 256468 kb
Host smart-52e74095-a469-44a7-a6fa-e3d0dfeceaf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35203
56774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.3520356774
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.1800508111
Short name T361
Test name
Test status
Simulation time 33996250655 ps
CPU time 681.18 seconds
Started Aug 01 05:42:03 PM PDT 24
Finished Aug 01 05:53:25 PM PDT 24
Peak memory 263888 kb
Host smart-39205d8a-154a-4488-92d2-11284cdf1a53
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800508111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.1800508111
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.130317572
Short name T13
Test name
Test status
Simulation time 16194839994 ps
CPU time 916.05 seconds
Started Aug 01 05:43:18 PM PDT 24
Finished Aug 01 05:58:35 PM PDT 24
Peak memory 264688 kb
Host smart-18529ae8-7ca1-429e-8dae-b0abb63e8bf7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130317572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.130317572
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.2764692275
Short name T621
Test name
Test status
Simulation time 31344497164 ps
CPU time 489.29 seconds
Started Aug 01 05:42:15 PM PDT 24
Finished Aug 01 05:50:25 PM PDT 24
Peak memory 248228 kb
Host smart-bc22c9a7-ad34-401a-9cc3-40f9ee901c7d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764692275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.2764692275
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.1694369491
Short name T398
Test name
Test status
Simulation time 1069284768 ps
CPU time 17.89 seconds
Started Aug 01 05:42:15 PM PDT 24
Finished Aug 01 05:42:33 PM PDT 24
Peak memory 248264 kb
Host smart-92a09dd9-b85f-4b12-8ee2-daecfed4b8a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16943
69491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.1694369491
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.1519905786
Short name T438
Test name
Test status
Simulation time 303281890 ps
CPU time 11.42 seconds
Started Aug 01 05:42:14 PM PDT 24
Finished Aug 01 05:42:26 PM PDT 24
Peak memory 247852 kb
Host smart-8b87b461-3773-45fa-a3e0-0c8881618617
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15199
05786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.1519905786
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.1934065439
Short name T278
Test name
Test status
Simulation time 2113543174 ps
CPU time 36.59 seconds
Started Aug 01 05:42:24 PM PDT 24
Finished Aug 01 05:43:01 PM PDT 24
Peak memory 255640 kb
Host smart-0e627829-a3c4-475c-8209-f041e885c3ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19340
65439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.1934065439
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.1682517648
Short name T247
Test name
Test status
Simulation time 1416150123 ps
CPU time 35.32 seconds
Started Aug 01 05:42:44 PM PDT 24
Finished Aug 01 05:43:20 PM PDT 24
Peak memory 248292 kb
Host smart-652a9c6e-6918-4d7e-b35c-2a040e20fd8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16825
17648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.1682517648
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.3440663133
Short name T273
Test name
Test status
Simulation time 170266529260 ps
CPU time 2530.22 seconds
Started Aug 01 05:43:21 PM PDT 24
Finished Aug 01 06:25:32 PM PDT 24
Peak memory 288548 kb
Host smart-a6a0bcf8-6f81-4cef-887d-76163cba7686
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440663133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.3440663133
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.1611898645
Short name T18
Test name
Test status
Simulation time 33133112336 ps
CPU time 2193.18 seconds
Started Aug 01 05:42:12 PM PDT 24
Finished Aug 01 06:18:45 PM PDT 24
Peak memory 288576 kb
Host smart-180e66df-e7e4-412a-8550-001684948794
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611898645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.1611898645
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.465120415
Short name T258
Test name
Test status
Simulation time 1799301424 ps
CPU time 63.59 seconds
Started Aug 01 05:42:26 PM PDT 24
Finished Aug 01 05:43:29 PM PDT 24
Peak memory 255944 kb
Host smart-0303ce29-f281-4183-ba32-64c44cf44d36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46512
0415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.465120415
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.1545254506
Short name T414
Test name
Test status
Simulation time 131786644 ps
CPU time 3.42 seconds
Started Aug 01 05:42:08 PM PDT 24
Finished Aug 01 05:42:11 PM PDT 24
Peak memory 239896 kb
Host smart-5f20d0f4-527f-418f-9e83-68daefc78575
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15452
54506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.1545254506
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.2423022489
Short name T299
Test name
Test status
Simulation time 108478551725 ps
CPU time 1654.01 seconds
Started Aug 01 05:42:05 PM PDT 24
Finished Aug 01 06:09:39 PM PDT 24
Peak memory 272048 kb
Host smart-8727e75a-9bb7-46b7-ab5e-80914cf44f7c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423022489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.2423022489
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.1322402761
Short name T522
Test name
Test status
Simulation time 36922214241 ps
CPU time 2198.71 seconds
Started Aug 01 05:42:10 PM PDT 24
Finished Aug 01 06:18:49 PM PDT 24
Peak memory 280280 kb
Host smart-ba28e6d0-376b-42e0-b871-916327a2f82b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322402761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.1322402761
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.3373964593
Short name T303
Test name
Test status
Simulation time 25166675330 ps
CPU time 267.26 seconds
Started Aug 01 05:42:10 PM PDT 24
Finished Aug 01 05:46:37 PM PDT 24
Peak memory 255052 kb
Host smart-d40e545a-213c-4626-8489-71a59129efec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373964593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.3373964593
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.3485004458
Short name T512
Test name
Test status
Simulation time 866420205 ps
CPU time 41.32 seconds
Started Aug 01 05:43:27 PM PDT 24
Finished Aug 01 05:44:08 PM PDT 24
Peak memory 256136 kb
Host smart-837f0d39-b4c6-4264-8d83-ac9401faee2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34850
04458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.3485004458
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.2436652925
Short name T535
Test name
Test status
Simulation time 937107310 ps
CPU time 24.21 seconds
Started Aug 01 05:42:24 PM PDT 24
Finished Aug 01 05:42:48 PM PDT 24
Peak memory 248032 kb
Host smart-2b98817c-ce98-4607-b13d-ee71f7db1078
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24366
52925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.2436652925
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.3906088924
Short name T331
Test name
Test status
Simulation time 51938421 ps
CPU time 7.23 seconds
Started Aug 01 05:43:27 PM PDT 24
Finished Aug 01 05:43:34 PM PDT 24
Peak memory 253384 kb
Host smart-b005245d-412f-4b91-a875-4a27ca9810d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39060
88924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.3906088924
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.567033625
Short name T411
Test name
Test status
Simulation time 169132406 ps
CPU time 16.51 seconds
Started Aug 01 05:42:34 PM PDT 24
Finished Aug 01 05:42:51 PM PDT 24
Peak memory 255632 kb
Host smart-e2ad1e47-5db5-4df4-9fb4-41f876cdd12f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56703
3625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.567033625
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.717368344
Short name T60
Test name
Test status
Simulation time 61177232942 ps
CPU time 5363.38 seconds
Started Aug 01 05:42:32 PM PDT 24
Finished Aug 01 07:11:55 PM PDT 24
Peak memory 330344 kb
Host smart-4b6cecf1-8805-431a-9842-0c73c55471f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717368344 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.717368344
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.3015565176
Short name T281
Test name
Test status
Simulation time 32502400459 ps
CPU time 2030.6 seconds
Started Aug 01 05:43:45 PM PDT 24
Finished Aug 01 06:17:36 PM PDT 24
Peak memory 281840 kb
Host smart-851aa958-9f52-41f5-9a94-c6fce4e2eb0d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015565176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.3015565176
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.1176850404
Short name T464
Test name
Test status
Simulation time 18393726298 ps
CPU time 265.35 seconds
Started Aug 01 05:42:23 PM PDT 24
Finished Aug 01 05:46:48 PM PDT 24
Peak memory 256408 kb
Host smart-7c5d9c5c-1ee6-4d95-b9fd-825fa98f9a1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11768
50404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.1176850404
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.3710000451
Short name T91
Test name
Test status
Simulation time 1538269190 ps
CPU time 9.62 seconds
Started Aug 01 05:42:12 PM PDT 24
Finished Aug 01 05:42:22 PM PDT 24
Peak memory 247636 kb
Host smart-a6f13334-c043-4dfb-8c6b-4e1e56ce3a5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37100
00451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.3710000451
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.3558260649
Short name T362
Test name
Test status
Simulation time 86580491236 ps
CPU time 1362.82 seconds
Started Aug 01 05:42:13 PM PDT 24
Finished Aug 01 06:04:56 PM PDT 24
Peak memory 272676 kb
Host smart-4964a624-cbcf-4c49-a107-45321bde513c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558260649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.3558260649
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.1417138075
Short name T571
Test name
Test status
Simulation time 139042919278 ps
CPU time 2010.44 seconds
Started Aug 01 05:42:34 PM PDT 24
Finished Aug 01 06:16:05 PM PDT 24
Peak memory 282720 kb
Host smart-5208cede-1bfb-4bbb-8e2a-9788cad80d89
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417138075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.1417138075
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.2928688108
Short name T651
Test name
Test status
Simulation time 1983288227 ps
CPU time 46.94 seconds
Started Aug 01 05:42:08 PM PDT 24
Finished Aug 01 05:42:55 PM PDT 24
Peak memory 248212 kb
Host smart-bb617111-3e42-47cd-8450-6298d6b8b690
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29286
88108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.2928688108
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.4058419260
Short name T475
Test name
Test status
Simulation time 3501027673 ps
CPU time 52.55 seconds
Started Aug 01 05:42:29 PM PDT 24
Finished Aug 01 05:43:22 PM PDT 24
Peak memory 255948 kb
Host smart-fb96949a-eea1-456f-91e3-e1e590bfeb3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40584
19260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.4058419260
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.2531304537
Short name T329
Test name
Test status
Simulation time 363232704 ps
CPU time 26.21 seconds
Started Aug 01 05:44:29 PM PDT 24
Finished Aug 01 05:44:55 PM PDT 24
Peak memory 247912 kb
Host smart-b9e3d919-ddc8-46b2-83d8-044a5b2d4c94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25313
04537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.2531304537
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.333909732
Short name T447
Test name
Test status
Simulation time 11117083291 ps
CPU time 37.11 seconds
Started Aug 01 05:43:45 PM PDT 24
Finished Aug 01 05:44:22 PM PDT 24
Peak memory 256240 kb
Host smart-d0a52b98-e6f3-4afe-a423-31ac121f8f8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33390
9732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.333909732
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.4294710030
Short name T261
Test name
Test status
Simulation time 103536991467 ps
CPU time 2923.1 seconds
Started Aug 01 05:43:29 PM PDT 24
Finished Aug 01 06:32:13 PM PDT 24
Peak memory 304936 kb
Host smart-7e1bfe63-8295-4628-a873-39ad88a30e56
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294710030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.4294710030
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all_with_rand_reset.2159151723
Short name T276
Test name
Test status
Simulation time 33777717378 ps
CPU time 3805.23 seconds
Started Aug 01 05:42:06 PM PDT 24
Finished Aug 01 06:45:32 PM PDT 24
Peak memory 337424 kb
Host smart-b0aee26e-b753-4523-9005-2d7ad7fce265
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159151723 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.alert_handler_stress_all_with_rand_reset.2159151723
Directory /workspace/37.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.1297186771
Short name T472
Test name
Test status
Simulation time 2670919176 ps
CPU time 71.97 seconds
Started Aug 01 05:42:26 PM PDT 24
Finished Aug 01 05:43:38 PM PDT 24
Peak memory 256064 kb
Host smart-f39ea34d-2135-4ddd-bf88-dfe6dc8be609
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12971
86771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.1297186771
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.977526261
Short name T549
Test name
Test status
Simulation time 1246439382 ps
CPU time 17.5 seconds
Started Aug 01 05:42:36 PM PDT 24
Finished Aug 01 05:42:54 PM PDT 24
Peak memory 247868 kb
Host smart-e7c06457-e8e9-4d3b-afdf-065b179fe533
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97752
6261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.977526261
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.2809305345
Short name T287
Test name
Test status
Simulation time 11087159209 ps
CPU time 768.94 seconds
Started Aug 01 05:42:17 PM PDT 24
Finished Aug 01 05:55:06 PM PDT 24
Peak memory 272860 kb
Host smart-7d7fc24f-9c75-49ba-8777-8c98aa228561
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809305345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.2809305345
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.694130253
Short name T519
Test name
Test status
Simulation time 9920807615 ps
CPU time 857.59 seconds
Started Aug 01 05:42:32 PM PDT 24
Finished Aug 01 05:56:50 PM PDT 24
Peak memory 266876 kb
Host smart-dd9c5526-536a-4f5d-a117-96a086da0427
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694130253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.694130253
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.1340784480
Short name T509
Test name
Test status
Simulation time 1758181850 ps
CPU time 28.73 seconds
Started Aug 01 05:42:36 PM PDT 24
Finished Aug 01 05:43:05 PM PDT 24
Peak memory 256340 kb
Host smart-8a9164b7-e0ae-458c-9e6a-61783a342be6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13407
84480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.1340784480
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.156973563
Short name T633
Test name
Test status
Simulation time 1590636220 ps
CPU time 19.79 seconds
Started Aug 01 05:43:24 PM PDT 24
Finished Aug 01 05:43:44 PM PDT 24
Peak memory 255592 kb
Host smart-03d505c0-3c47-469e-b3d0-c79c8b0c3c45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15697
3563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.156973563
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.2644104458
Short name T598
Test name
Test status
Simulation time 1471182022 ps
CPU time 33.77 seconds
Started Aug 01 05:42:36 PM PDT 24
Finished Aug 01 05:43:10 PM PDT 24
Peak memory 247636 kb
Host smart-492e1cb1-de72-4758-b0b6-5a9540b609f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26441
04458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.2644104458
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.2669821470
Short name T587
Test name
Test status
Simulation time 1106064825 ps
CPU time 33.23 seconds
Started Aug 01 05:44:29 PM PDT 24
Finished Aug 01 05:45:02 PM PDT 24
Peak memory 256236 kb
Host smart-81851b85-39b9-410c-a008-4c97e0b7a2f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26698
21470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.2669821470
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.1164464160
Short name T72
Test name
Test status
Simulation time 17733198966 ps
CPU time 1809.04 seconds
Started Aug 01 05:42:20 PM PDT 24
Finished Aug 01 06:12:29 PM PDT 24
Peak memory 305488 kb
Host smart-d98c21e6-10bd-4435-b290-46a6c2e41c07
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164464160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.1164464160
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.2532735182
Short name T336
Test name
Test status
Simulation time 43434347308 ps
CPU time 3092.37 seconds
Started Aug 01 05:43:46 PM PDT 24
Finished Aug 01 06:35:19 PM PDT 24
Peak memory 297560 kb
Host smart-51722b38-1409-4a51-bbe0-0e7984b942f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532735182 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.2532735182
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.4042633894
Short name T59
Test name
Test status
Simulation time 49165397177 ps
CPU time 2849.69 seconds
Started Aug 01 05:42:31 PM PDT 24
Finished Aug 01 06:30:01 PM PDT 24
Peak memory 288980 kb
Host smart-1b90c523-513c-4784-b38f-cbe4d1d84dca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042633894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.4042633894
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.210354435
Short name T462
Test name
Test status
Simulation time 32251853720 ps
CPU time 182.17 seconds
Started Aug 01 05:42:32 PM PDT 24
Finished Aug 01 05:45:34 PM PDT 24
Peak memory 256504 kb
Host smart-2482465d-1b80-4174-a279-3a1557447e27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21035
4435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.210354435
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.565526330
Short name T396
Test name
Test status
Simulation time 156009929 ps
CPU time 6.07 seconds
Started Aug 01 05:43:58 PM PDT 24
Finished Aug 01 05:44:04 PM PDT 24
Peak memory 247768 kb
Host smart-00f9493e-1887-469a-a912-8981a1cb9bcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56552
6330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.565526330
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.3477438388
Short name T356
Test name
Test status
Simulation time 10012762431 ps
CPU time 1171.72 seconds
Started Aug 01 05:42:32 PM PDT 24
Finished Aug 01 06:02:04 PM PDT 24
Peak memory 281088 kb
Host smart-e23d0e01-3c97-4307-84bb-ef9e261f0fbd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477438388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.3477438388
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.357954746
Short name T63
Test name
Test status
Simulation time 121176652991 ps
CPU time 1507.82 seconds
Started Aug 01 05:42:31 PM PDT 24
Finished Aug 01 06:07:39 PM PDT 24
Peak memory 272324 kb
Host smart-a196a586-fec1-47ab-8356-91858c0cbf2a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357954746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.357954746
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.2883049866
Short name T695
Test name
Test status
Simulation time 16672233473 ps
CPU time 172.29 seconds
Started Aug 01 05:42:30 PM PDT 24
Finished Aug 01 05:45:23 PM PDT 24
Peak memory 248364 kb
Host smart-61541dd6-9355-4190-ae9b-1ecca13740bd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883049866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.2883049866
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.1200010748
Short name T444
Test name
Test status
Simulation time 195075325 ps
CPU time 11.45 seconds
Started Aug 01 05:42:18 PM PDT 24
Finished Aug 01 05:42:29 PM PDT 24
Peak memory 254960 kb
Host smart-58bdb16b-ede0-473d-a7ae-f7cf88f9cfa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12000
10748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.1200010748
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.2476559345
Short name T692
Test name
Test status
Simulation time 801465687 ps
CPU time 53.5 seconds
Started Aug 01 05:44:16 PM PDT 24
Finished Aug 01 05:45:10 PM PDT 24
Peak memory 256040 kb
Host smart-47c4d123-b7f6-4137-8430-0d0ab9438c33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24765
59345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.2476559345
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.3915185163
Short name T501
Test name
Test status
Simulation time 326917448 ps
CPU time 23.99 seconds
Started Aug 01 05:44:05 PM PDT 24
Finished Aug 01 05:44:29 PM PDT 24
Peak memory 256432 kb
Host smart-d0e49adb-045b-4720-9324-de2dd28698dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39151
85163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.3915185163
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.3715862110
Short name T439
Test name
Test status
Simulation time 946431795 ps
CPU time 49.63 seconds
Started Aug 01 05:42:30 PM PDT 24
Finished Aug 01 05:43:19 PM PDT 24
Peak memory 256472 kb
Host smart-a4101e7c-84e5-4c5f-a9de-56dbc107affc
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715862110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.3715862110
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.1375020647
Short name T219
Test name
Test status
Simulation time 52357538 ps
CPU time 2.96 seconds
Started Aug 01 05:39:56 PM PDT 24
Finished Aug 01 05:39:59 PM PDT 24
Peak memory 248532 kb
Host smart-2755045d-51bb-43c7-82c8-b2ac7569219e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1375020647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.1375020647
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.2048019540
Short name T588
Test name
Test status
Simulation time 504685895534 ps
CPU time 1805.6 seconds
Started Aug 01 05:39:50 PM PDT 24
Finished Aug 01 06:09:56 PM PDT 24
Peak memory 286376 kb
Host smart-27a09999-0eb1-46be-b432-a9165d95e322
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048019540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.2048019540
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.3430885332
Short name T493
Test name
Test status
Simulation time 4539365280 ps
CPU time 42.06 seconds
Started Aug 01 05:39:49 PM PDT 24
Finished Aug 01 05:40:31 PM PDT 24
Peak memory 248324 kb
Host smart-11c8d817-cb09-4531-a702-eac0b8708279
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3430885332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.3430885332
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.683245400
Short name T241
Test name
Test status
Simulation time 5502145540 ps
CPU time 158.99 seconds
Started Aug 01 05:39:49 PM PDT 24
Finished Aug 01 05:42:28 PM PDT 24
Peak memory 255968 kb
Host smart-b9f3ec63-4f85-41a1-88b7-9c809a7273e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68324
5400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.683245400
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.44956800
Short name T572
Test name
Test status
Simulation time 1007093395 ps
CPU time 19.53 seconds
Started Aug 01 05:39:55 PM PDT 24
Finished Aug 01 05:40:15 PM PDT 24
Peak memory 248176 kb
Host smart-b26dfd4c-dc82-4d17-adb6-b4c509f73e7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44956
800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.44956800
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.1901798062
Short name T591
Test name
Test status
Simulation time 20126406984 ps
CPU time 584.06 seconds
Started Aug 01 05:39:51 PM PDT 24
Finished Aug 01 05:49:35 PM PDT 24
Peak memory 271324 kb
Host smart-161b7900-0c7f-4009-ab45-023549a2bbd8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901798062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.1901798062
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.987087612
Short name T658
Test name
Test status
Simulation time 58868775102 ps
CPU time 669.02 seconds
Started Aug 01 05:39:56 PM PDT 24
Finished Aug 01 05:51:05 PM PDT 24
Peak memory 248252 kb
Host smart-479a1d7d-fb4f-40b0-9c14-ec71d018b28e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987087612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.987087612
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.875289983
Short name T114
Test name
Test status
Simulation time 3112381968 ps
CPU time 45.14 seconds
Started Aug 01 05:39:50 PM PDT 24
Finished Aug 01 05:40:36 PM PDT 24
Peak memory 247760 kb
Host smart-cd8c1857-802e-477a-b33e-e6faaded9bff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87528
9983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.875289983
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.1324594871
Short name T36
Test name
Test status
Simulation time 3406884335 ps
CPU time 20.61 seconds
Started Aug 01 05:39:52 PM PDT 24
Finished Aug 01 05:40:13 PM PDT 24
Peak memory 270692 kb
Host smart-586f2996-f3f8-4802-b3ab-f6b4ccc9f549
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1324594871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.1324594871
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.3690020035
Short name T395
Test name
Test status
Simulation time 773567423 ps
CPU time 44.96 seconds
Started Aug 01 05:39:52 PM PDT 24
Finished Aug 01 05:40:37 PM PDT 24
Peak memory 255732 kb
Host smart-0e5633e0-9057-4734-8502-2be97853b7a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36900
20035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.3690020035
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.1197544885
Short name T595
Test name
Test status
Simulation time 109121701 ps
CPU time 4.06 seconds
Started Aug 01 05:39:48 PM PDT 24
Finished Aug 01 05:39:52 PM PDT 24
Peak memory 250284 kb
Host smart-89a8a2e9-b083-45bd-85ba-9f737b20b37f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11975
44885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.1197544885
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.2127274991
Short name T277
Test name
Test status
Simulation time 439451306863 ps
CPU time 3190.58 seconds
Started Aug 01 05:39:53 PM PDT 24
Finished Aug 01 06:33:04 PM PDT 24
Peak memory 288684 kb
Host smart-9ac715e2-aca6-41d0-ae06-b218c259a5df
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127274991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.2127274991
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.1857416149
Short name T413
Test name
Test status
Simulation time 164325944971 ps
CPU time 2355.68 seconds
Started Aug 01 05:42:40 PM PDT 24
Finished Aug 01 06:21:56 PM PDT 24
Peak memory 284664 kb
Host smart-3b16e1d6-0ac6-413f-ac22-4d68652a5db6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857416149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.1857416149
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.110789271
Short name T489
Test name
Test status
Simulation time 2852808679 ps
CPU time 152.77 seconds
Started Aug 01 05:42:32 PM PDT 24
Finished Aug 01 05:45:05 PM PDT 24
Peak memory 255840 kb
Host smart-1d4bcaa3-cbf8-4581-aa8c-7b332d6b0181
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11078
9271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.110789271
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.2745533934
Short name T596
Test name
Test status
Simulation time 772708159 ps
CPU time 20.7 seconds
Started Aug 01 05:43:24 PM PDT 24
Finished Aug 01 05:43:45 PM PDT 24
Peak memory 256252 kb
Host smart-9e3984be-425e-441e-b791-118039c0f08b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27455
33934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.2745533934
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.1115250439
Short name T354
Test name
Test status
Simulation time 30196619387 ps
CPU time 1745.42 seconds
Started Aug 01 05:42:39 PM PDT 24
Finished Aug 01 06:11:45 PM PDT 24
Peak memory 272212 kb
Host smart-1ea38ab0-0f30-4a30-899c-3e09db4afbef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115250439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.1115250439
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.420900130
Short name T7
Test name
Test status
Simulation time 100873509543 ps
CPU time 2808.16 seconds
Started Aug 01 05:42:40 PM PDT 24
Finished Aug 01 06:29:29 PM PDT 24
Peak memory 288192 kb
Host smart-d47028a3-55a6-4105-b543-27bdb35200d8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420900130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.420900130
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.12280836
Short name T239
Test name
Test status
Simulation time 9144189169 ps
CPU time 363.97 seconds
Started Aug 01 05:42:46 PM PDT 24
Finished Aug 01 05:48:50 PM PDT 24
Peak memory 248096 kb
Host smart-5fb95f75-b99a-433a-bf92-76be32b0b10f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12280836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.12280836
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.3032263127
Short name T675
Test name
Test status
Simulation time 171128326 ps
CPU time 8.37 seconds
Started Aug 01 05:42:29 PM PDT 24
Finished Aug 01 05:42:37 PM PDT 24
Peak memory 253644 kb
Host smart-330c93da-a0d3-4184-8efc-dd4d32b20867
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30322
63127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.3032263127
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.1029090984
Short name T577
Test name
Test status
Simulation time 376512088 ps
CPU time 34.41 seconds
Started Aug 01 05:43:23 PM PDT 24
Finished Aug 01 05:43:58 PM PDT 24
Peak memory 256472 kb
Host smart-a257a617-ff7d-4a1f-b765-94a606fd68b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10290
90984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.1029090984
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.2962582445
Short name T104
Test name
Test status
Simulation time 2082459507 ps
CPU time 66.97 seconds
Started Aug 01 05:42:31 PM PDT 24
Finished Aug 01 05:43:38 PM PDT 24
Peak memory 249208 kb
Host smart-891eb8c2-df4f-4663-969f-e5820b58e68b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29625
82445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.2962582445
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.2791788899
Short name T195
Test name
Test status
Simulation time 100842591 ps
CPU time 7.73 seconds
Started Aug 01 05:42:29 PM PDT 24
Finished Aug 01 05:42:37 PM PDT 24
Peak memory 251356 kb
Host smart-da3e9750-0382-4767-b039-16f6919bcaf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27917
88899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.2791788899
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.2999515959
Short name T480
Test name
Test status
Simulation time 51230120994 ps
CPU time 1363.81 seconds
Started Aug 01 05:42:41 PM PDT 24
Finished Aug 01 06:05:25 PM PDT 24
Peak memory 289128 kb
Host smart-305ff480-5280-4cc5-8ea3-982479ec8199
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999515959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.2999515959
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.2659720752
Short name T265
Test name
Test status
Simulation time 86326062834 ps
CPU time 1173.25 seconds
Started Aug 01 05:42:47 PM PDT 24
Finished Aug 01 06:02:21 PM PDT 24
Peak memory 264696 kb
Host smart-70e8137a-c05d-4161-a2e7-9928ad9b0643
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659720752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.2659720752
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.1709288205
Short name T443
Test name
Test status
Simulation time 119307775 ps
CPU time 12.91 seconds
Started Aug 01 05:42:55 PM PDT 24
Finished Aug 01 05:43:08 PM PDT 24
Peak memory 255972 kb
Host smart-1d366b18-11b0-4318-b24a-5265df9135ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17092
88205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.1709288205
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.1985508795
Short name T109
Test name
Test status
Simulation time 1089081984 ps
CPU time 20.07 seconds
Started Aug 01 05:42:43 PM PDT 24
Finished Aug 01 05:43:03 PM PDT 24
Peak memory 253660 kb
Host smart-99a506b5-b440-4591-83d8-af8f062ff1f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19855
08795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.1985508795
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.2783807939
Short name T365
Test name
Test status
Simulation time 107850105880 ps
CPU time 1539.65 seconds
Started Aug 01 05:42:40 PM PDT 24
Finished Aug 01 06:08:20 PM PDT 24
Peak memory 272244 kb
Host smart-ed3b05dc-2077-471d-8eaf-d84c895b0637
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783807939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.2783807939
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.3747152720
Short name T624
Test name
Test status
Simulation time 54947391208 ps
CPU time 3009.52 seconds
Started Aug 01 05:42:47 PM PDT 24
Finished Aug 01 06:32:57 PM PDT 24
Peak memory 288484 kb
Host smart-cce47304-d6a7-4613-a952-0d63f4cb8885
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747152720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.3747152720
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.1813703720
Short name T245
Test name
Test status
Simulation time 20634320223 ps
CPU time 404.94 seconds
Started Aug 01 05:42:40 PM PDT 24
Finished Aug 01 05:49:25 PM PDT 24
Peak memory 248188 kb
Host smart-df78306b-fa28-4d99-b1e5-8e315350e49a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813703720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.1813703720
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.802680098
Short name T407
Test name
Test status
Simulation time 4188350634 ps
CPU time 58.29 seconds
Started Aug 01 05:42:44 PM PDT 24
Finished Aug 01 05:43:43 PM PDT 24
Peak memory 255620 kb
Host smart-5f35b330-a0b9-4991-886b-ad1e8b0cbdb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80268
0098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.802680098
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.545805686
Short name T506
Test name
Test status
Simulation time 760413636 ps
CPU time 13.9 seconds
Started Aug 01 05:42:42 PM PDT 24
Finished Aug 01 05:42:56 PM PDT 24
Peak memory 254464 kb
Host smart-d40047fa-7547-4a8d-a0b9-70e37ed56f25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54580
5686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.545805686
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.714183217
Short name T259
Test name
Test status
Simulation time 136470544 ps
CPU time 13.35 seconds
Started Aug 01 05:42:41 PM PDT 24
Finished Aug 01 05:42:55 PM PDT 24
Peak memory 255488 kb
Host smart-fd480b16-1fa4-41b8-8142-e2949d8dfdd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71418
3217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.714183217
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.584008737
Short name T393
Test name
Test status
Simulation time 1023946994 ps
CPU time 17.32 seconds
Started Aug 01 05:42:44 PM PDT 24
Finished Aug 01 05:43:01 PM PDT 24
Peak memory 248148 kb
Host smart-b19376d2-d07c-44aa-be52-04a9aed5e834
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58400
8737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.584008737
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.457484155
Short name T197
Test name
Test status
Simulation time 21055478469 ps
CPU time 62.34 seconds
Started Aug 01 05:42:42 PM PDT 24
Finished Aug 01 05:43:45 PM PDT 24
Peak memory 256376 kb
Host smart-f7941bd5-d5ec-46d3-aadd-566d1538891c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457484155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_han
dler_stress_all.457484155
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all_with_rand_reset.2817727838
Short name T330
Test name
Test status
Simulation time 49468508651 ps
CPU time 4290.91 seconds
Started Aug 01 05:42:47 PM PDT 24
Finished Aug 01 06:54:19 PM PDT 24
Peak memory 304936 kb
Host smart-90c89c25-1155-4e45-9459-386a8bb8700b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817727838 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.alert_handler_stress_all_with_rand_reset.2817727838
Directory /workspace/41.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.2159206163
Short name T525
Test name
Test status
Simulation time 17584070824 ps
CPU time 258.11 seconds
Started Aug 01 05:43:01 PM PDT 24
Finished Aug 01 05:47:19 PM PDT 24
Peak memory 256556 kb
Host smart-56a74e84-d2ae-48f6-8346-cbf6a0f0371f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21592
06163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.2159206163
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.2040216598
Short name T479
Test name
Test status
Simulation time 4762083714 ps
CPU time 55.92 seconds
Started Aug 01 05:43:02 PM PDT 24
Finished Aug 01 05:43:58 PM PDT 24
Peak memory 248056 kb
Host smart-9cf52956-5761-451b-be9d-d849d809ff5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20402
16598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.2040216598
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.1587526087
Short name T359
Test name
Test status
Simulation time 10651112161 ps
CPU time 1064.5 seconds
Started Aug 01 05:43:00 PM PDT 24
Finished Aug 01 06:00:44 PM PDT 24
Peak memory 272336 kb
Host smart-6b0e57cf-ec56-44c0-8a92-b81a117ac6db
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587526087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.1587526087
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.1138781095
Short name T629
Test name
Test status
Simulation time 106371759598 ps
CPU time 1725.55 seconds
Started Aug 01 05:43:01 PM PDT 24
Finished Aug 01 06:11:46 PM PDT 24
Peak memory 272900 kb
Host smart-7c312040-8950-4763-affc-defdf9286faf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138781095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.1138781095
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.3939129242
Short name T578
Test name
Test status
Simulation time 107827952 ps
CPU time 7.34 seconds
Started Aug 01 05:42:46 PM PDT 24
Finished Aug 01 05:42:53 PM PDT 24
Peak memory 248276 kb
Host smart-b26b384c-2c5e-4d70-850a-c54325c4c9eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39391
29242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.3939129242
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.3385922373
Short name T409
Test name
Test status
Simulation time 777415852 ps
CPU time 19.9 seconds
Started Aug 01 05:42:57 PM PDT 24
Finished Aug 01 05:43:17 PM PDT 24
Peak memory 248268 kb
Host smart-7ed7abf3-9600-4c26-9181-b517c8df4dd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33859
22373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.3385922373
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.83130158
Short name T487
Test name
Test status
Simulation time 475120666 ps
CPU time 24.94 seconds
Started Aug 01 05:42:59 PM PDT 24
Finished Aug 01 05:43:24 PM PDT 24
Peak memory 248632 kb
Host smart-28a64035-7868-4107-a29b-0f5359934597
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83130
158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.83130158
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.2951047137
Short name T625
Test name
Test status
Simulation time 83109786 ps
CPU time 4.43 seconds
Started Aug 01 05:42:41 PM PDT 24
Finished Aug 01 05:42:46 PM PDT 24
Peak memory 248208 kb
Host smart-3bf23796-594b-4cc5-822b-9b01f3d3b2ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29510
47137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.2951047137
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all_with_rand_reset.950132959
Short name T32
Test name
Test status
Simulation time 160285705372 ps
CPU time 5240.91 seconds
Started Aug 01 05:42:59 PM PDT 24
Finished Aug 01 07:10:21 PM PDT 24
Peak memory 322060 kb
Host smart-03e387b1-1b74-4a77-b034-a06fb0c630e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950132959 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 42.alert_handler_stress_all_with_rand_reset.950132959
Directory /workspace/42.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.701747075
Short name T503
Test name
Test status
Simulation time 79732094210 ps
CPU time 2508.85 seconds
Started Aug 01 05:43:00 PM PDT 24
Finished Aug 01 06:24:50 PM PDT 24
Peak memory 288544 kb
Host smart-b274066d-6f24-4cc5-93de-8787d9545d87
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701747075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.701747075
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.3198022476
Short name T405
Test name
Test status
Simulation time 4253673487 ps
CPU time 102.76 seconds
Started Aug 01 05:43:01 PM PDT 24
Finished Aug 01 05:44:44 PM PDT 24
Peak memory 249384 kb
Host smart-e57c94ef-4914-49e0-a282-8f608722619a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31980
22476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.3198022476
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.213352129
Short name T664
Test name
Test status
Simulation time 1562862815 ps
CPU time 24.99 seconds
Started Aug 01 05:43:01 PM PDT 24
Finished Aug 01 05:43:26 PM PDT 24
Peak memory 247724 kb
Host smart-e0a67638-0e29-4d5a-8360-ba66303144eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21335
2129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.213352129
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.3908571430
Short name T550
Test name
Test status
Simulation time 23125606588 ps
CPU time 1485.12 seconds
Started Aug 01 05:43:00 PM PDT 24
Finished Aug 01 06:07:45 PM PDT 24
Peak memory 272052 kb
Host smart-d9122311-3572-4bc6-a69c-0a98493a2b76
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908571430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.3908571430
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.3860399847
Short name T570
Test name
Test status
Simulation time 37181431381 ps
CPU time 838.02 seconds
Started Aug 01 05:43:08 PM PDT 24
Finished Aug 01 05:57:06 PM PDT 24
Peak memory 267748 kb
Host smart-56f4b535-c563-4d79-841a-730ea1be9f86
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860399847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.3860399847
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.1424763017
Short name T313
Test name
Test status
Simulation time 9940805954 ps
CPU time 378.23 seconds
Started Aug 01 05:43:00 PM PDT 24
Finished Aug 01 05:49:18 PM PDT 24
Peak memory 255104 kb
Host smart-901a5dd1-de9d-4fda-b3b2-b5a5be0a2aba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424763017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.1424763017
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.2905637757
Short name T544
Test name
Test status
Simulation time 678158279 ps
CPU time 13.99 seconds
Started Aug 01 05:43:02 PM PDT 24
Finished Aug 01 05:43:16 PM PDT 24
Peak memory 248192 kb
Host smart-b67ce3dc-dc2c-43dd-8fce-d299e18e04c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29056
37757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.2905637757
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.3641259322
Short name T424
Test name
Test status
Simulation time 53595142 ps
CPU time 4.9 seconds
Started Aug 01 05:42:58 PM PDT 24
Finished Aug 01 05:43:03 PM PDT 24
Peak memory 239272 kb
Host smart-9f64413e-b2b8-4d91-9137-a64c4bf75041
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36412
59322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.3641259322
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.4248267569
Short name T340
Test name
Test status
Simulation time 404845217 ps
CPU time 43.57 seconds
Started Aug 01 05:42:59 PM PDT 24
Finished Aug 01 05:43:42 PM PDT 24
Peak memory 256068 kb
Host smart-e206b207-e5b6-4e25-9058-729e7d9159ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42482
67569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.4248267569
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.3364915481
Short name T74
Test name
Test status
Simulation time 1450287098 ps
CPU time 49.14 seconds
Started Aug 01 05:43:00 PM PDT 24
Finished Aug 01 05:43:50 PM PDT 24
Peak memory 256372 kb
Host smart-850f504f-b131-45f9-9ea6-548d8cbaeb9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33649
15481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.3364915481
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.654571412
Short name T66
Test name
Test status
Simulation time 45659093886 ps
CPU time 2952.14 seconds
Started Aug 01 05:43:14 PM PDT 24
Finished Aug 01 06:32:27 PM PDT 24
Peak memory 299792 kb
Host smart-cfb793cb-605f-4aed-ac88-0195c8fc4f34
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654571412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_han
dler_stress_all.654571412
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.631954524
Short name T458
Test name
Test status
Simulation time 9888127425 ps
CPU time 963.33 seconds
Started Aug 01 05:43:09 PM PDT 24
Finished Aug 01 05:59:13 PM PDT 24
Peak memory 272788 kb
Host smart-9b21a58f-d633-4345-9ab1-86627a68a8b4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631954524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.631954524
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.3841583221
Short name T521
Test name
Test status
Simulation time 4509466215 ps
CPU time 119.16 seconds
Started Aug 01 05:43:13 PM PDT 24
Finished Aug 01 05:45:12 PM PDT 24
Peak memory 255992 kb
Host smart-b81b0313-47ab-460f-ad0d-06ed162dc18d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38415
83221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.3841583221
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.2285665723
Short name T560
Test name
Test status
Simulation time 371006655 ps
CPU time 13.48 seconds
Started Aug 01 05:44:16 PM PDT 24
Finished Aug 01 05:44:29 PM PDT 24
Peak memory 248180 kb
Host smart-3876f454-ffdf-4f79-b557-fecc57acea18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22856
65723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.2285665723
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.3730290732
Short name T286
Test name
Test status
Simulation time 39015998269 ps
CPU time 1007.17 seconds
Started Aug 01 05:43:10 PM PDT 24
Finished Aug 01 05:59:57 PM PDT 24
Peak memory 282392 kb
Host smart-9a3c11c5-86fa-4aea-bcb5-c676e871e1aa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730290732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.3730290732
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.2681739549
Short name T609
Test name
Test status
Simulation time 157681341764 ps
CPU time 2485.82 seconds
Started Aug 01 05:43:11 PM PDT 24
Finished Aug 01 06:24:37 PM PDT 24
Peak memory 288960 kb
Host smart-97aaac99-542c-4585-9115-862893e701dc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681739549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.2681739549
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.627763891
Short name T292
Test name
Test status
Simulation time 10486919971 ps
CPU time 218.65 seconds
Started Aug 01 05:43:07 PM PDT 24
Finished Aug 01 05:46:46 PM PDT 24
Peak memory 248260 kb
Host smart-88eedd6e-c8e8-4549-8946-a7a03e7d628a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627763891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.627763891
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.3104798040
Short name T589
Test name
Test status
Simulation time 487585546 ps
CPU time 8.9 seconds
Started Aug 01 05:43:06 PM PDT 24
Finished Aug 01 05:43:15 PM PDT 24
Peak memory 248220 kb
Host smart-6dcd5d15-a1b3-4b77-8b92-fb212658e438
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31047
98040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.3104798040
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.302687730
Short name T526
Test name
Test status
Simulation time 177904783 ps
CPU time 20.81 seconds
Started Aug 01 05:43:14 PM PDT 24
Finished Aug 01 05:43:35 PM PDT 24
Peak memory 248128 kb
Host smart-3e554ff9-047c-45c4-aa27-a4f5c507ba0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30268
7730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.302687730
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.2555655393
Short name T383
Test name
Test status
Simulation time 223048692 ps
CPU time 5.81 seconds
Started Aug 01 05:43:45 PM PDT 24
Finished Aug 01 05:43:51 PM PDT 24
Peak memory 250240 kb
Host smart-95b13bce-4c90-456a-a0cb-9746626adc04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25556
55393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.2555655393
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.1533035722
Short name T338
Test name
Test status
Simulation time 43673756875 ps
CPU time 2037.4 seconds
Started Aug 01 05:43:15 PM PDT 24
Finished Aug 01 06:17:13 PM PDT 24
Peak memory 299156 kb
Host smart-bc91085f-2352-4527-9a82-69712f0ed8c9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533035722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.1533035722
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.115392330
Short name T105
Test name
Test status
Simulation time 33781771984 ps
CPU time 1733.23 seconds
Started Aug 01 05:43:12 PM PDT 24
Finished Aug 01 06:12:06 PM PDT 24
Peak memory 303364 kb
Host smart-81479bdc-7e9c-4ff3-9cfb-d38017eb4a1a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115392330 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.115392330
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.3542977946
Short name T500
Test name
Test status
Simulation time 12713255796 ps
CPU time 1426.6 seconds
Started Aug 01 05:43:04 PM PDT 24
Finished Aug 01 06:06:51 PM PDT 24
Peak memory 288904 kb
Host smart-b95027cc-13aa-44cf-b890-6217d7203937
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542977946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.3542977946
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.3206612081
Short name T121
Test name
Test status
Simulation time 2702594605 ps
CPU time 108.42 seconds
Started Aug 01 05:43:07 PM PDT 24
Finished Aug 01 05:44:56 PM PDT 24
Peak memory 256052 kb
Host smart-8bfd4e72-eb03-4d1a-afc0-b7d8e8267dce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32066
12081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.3206612081
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.119656577
Short name T699
Test name
Test status
Simulation time 203197607 ps
CPU time 23.93 seconds
Started Aug 01 05:43:08 PM PDT 24
Finished Aug 01 05:43:32 PM PDT 24
Peak memory 256360 kb
Host smart-13591430-6c8e-48dc-be83-9d5e824964b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11965
6577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.119656577
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.325902262
Short name T367
Test name
Test status
Simulation time 9122077492 ps
CPU time 751.39 seconds
Started Aug 01 05:43:14 PM PDT 24
Finished Aug 01 05:55:45 PM PDT 24
Peak memory 264592 kb
Host smart-73df3577-1fc8-48d4-91e3-df993706c27e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325902262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.325902262
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.1302725911
Short name T645
Test name
Test status
Simulation time 84135578352 ps
CPU time 1222.54 seconds
Started Aug 01 05:43:05 PM PDT 24
Finished Aug 01 06:03:28 PM PDT 24
Peak memory 265748 kb
Host smart-8acd350f-730b-4090-ae4e-8a2771d74767
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302725911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.1302725911
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.1982684560
Short name T524
Test name
Test status
Simulation time 4681986616 ps
CPU time 189.11 seconds
Started Aug 01 05:44:18 PM PDT 24
Finished Aug 01 05:47:27 PM PDT 24
Peak memory 247284 kb
Host smart-3383055d-0a43-45ce-a789-85ba64d123ba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982684560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.1982684560
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.3807236198
Short name T616
Test name
Test status
Simulation time 4581156079 ps
CPU time 29.8 seconds
Started Aug 01 05:43:06 PM PDT 24
Finished Aug 01 05:43:36 PM PDT 24
Peak memory 255684 kb
Host smart-426d331d-a881-4d6a-88dd-561cfb7d45a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38072
36198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.3807236198
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.3954596993
Short name T402
Test name
Test status
Simulation time 168204351 ps
CPU time 11.75 seconds
Started Aug 01 05:43:13 PM PDT 24
Finished Aug 01 05:43:25 PM PDT 24
Peak memory 255632 kb
Host smart-bf8fb63f-4fee-4ec4-a73a-96e184c66f31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39545
96993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.3954596993
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.1969842925
Short name T678
Test name
Test status
Simulation time 1192208481 ps
CPU time 43.29 seconds
Started Aug 01 05:43:13 PM PDT 24
Finished Aug 01 05:43:57 PM PDT 24
Peak memory 255832 kb
Host smart-681edb48-3435-49d0-9a60-2305c5c15fa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19698
42925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.1969842925
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.2254557851
Short name T20
Test name
Test status
Simulation time 876182919 ps
CPU time 16.78 seconds
Started Aug 01 05:44:17 PM PDT 24
Finished Aug 01 05:44:34 PM PDT 24
Peak memory 256152 kb
Host smart-deb891d9-1add-4a5e-a3b3-71dc5149764d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22545
57851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.2254557851
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.2706434347
Short name T492
Test name
Test status
Simulation time 233196631810 ps
CPU time 3086.2 seconds
Started Aug 01 05:43:12 PM PDT 24
Finished Aug 01 06:34:39 PM PDT 24
Peak memory 289044 kb
Host smart-1f57fa49-8ad2-4ec7-8eb4-5c78a1bd6b92
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706434347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.2706434347
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.1176363178
Short name T576
Test name
Test status
Simulation time 6225637170 ps
CPU time 766.53 seconds
Started Aug 01 05:43:16 PM PDT 24
Finished Aug 01 05:56:03 PM PDT 24
Peak memory 272672 kb
Host smart-a20906a1-5e6c-43c3-9861-06cbd5b66789
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176363178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.1176363178
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.2346628658
Short name T426
Test name
Test status
Simulation time 5684919427 ps
CPU time 81.52 seconds
Started Aug 01 05:43:15 PM PDT 24
Finished Aug 01 05:44:36 PM PDT 24
Peak memory 256280 kb
Host smart-11606f01-43a5-46c9-ae56-ff196b819aed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23466
28658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.2346628658
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.3603590564
Short name T437
Test name
Test status
Simulation time 143231083 ps
CPU time 16.4 seconds
Started Aug 01 05:43:19 PM PDT 24
Finished Aug 01 05:43:35 PM PDT 24
Peak memory 248216 kb
Host smart-3689758b-8a4e-43f2-a583-7184eb29d2e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36035
90564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.3603590564
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.1655447934
Short name T575
Test name
Test status
Simulation time 21587940642 ps
CPU time 1270.62 seconds
Started Aug 01 05:43:19 PM PDT 24
Finished Aug 01 06:04:30 PM PDT 24
Peak memory 266820 kb
Host smart-9bba0174-1bfc-4e1a-98fd-85eb3e53a0c7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655447934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.1655447934
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.1302629182
Short name T237
Test name
Test status
Simulation time 6356219776 ps
CPU time 55.05 seconds
Started Aug 01 05:43:15 PM PDT 24
Finished Aug 01 05:44:10 PM PDT 24
Peak memory 255704 kb
Host smart-3bf4d571-af46-4f5b-bdc3-0814bd463897
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13026
29182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.1302629182
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.2958046212
Short name T520
Test name
Test status
Simulation time 440853032 ps
CPU time 22.72 seconds
Started Aug 01 05:43:16 PM PDT 24
Finished Aug 01 05:43:39 PM PDT 24
Peak memory 248248 kb
Host smart-fc9cc7f3-4077-4537-8417-bab1b5aab125
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29580
46212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.2958046212
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.1728054635
Short name T283
Test name
Test status
Simulation time 62295845 ps
CPU time 5.1 seconds
Started Aug 01 05:43:17 PM PDT 24
Finished Aug 01 05:43:22 PM PDT 24
Peak memory 239324 kb
Host smart-7d028fa8-80c9-423a-a323-02404012bfd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17280
54635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.1728054635
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.2917847777
Short name T668
Test name
Test status
Simulation time 2328901318 ps
CPU time 37.1 seconds
Started Aug 01 05:44:16 PM PDT 24
Finished Aug 01 05:44:53 PM PDT 24
Peak memory 255628 kb
Host smart-cd1ee9dd-06b3-43c6-bf91-26a451183b6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29178
47777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.2917847777
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.3187615489
Short name T574
Test name
Test status
Simulation time 31450442382 ps
CPU time 1125.2 seconds
Started Aug 01 05:43:13 PM PDT 24
Finished Aug 01 06:01:59 PM PDT 24
Peak memory 282048 kb
Host smart-ef38c872-7f93-4c80-8658-465c45a59499
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187615489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.3187615489
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.562910811
Short name T27
Test name
Test status
Simulation time 72797146600 ps
CPU time 1111.89 seconds
Started Aug 01 05:43:29 PM PDT 24
Finished Aug 01 06:02:01 PM PDT 24
Peak memory 271888 kb
Host smart-3bfc8b4b-5249-4f8d-ab9f-beef25cd7e9b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562910811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.562910811
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.3913394664
Short name T689
Test name
Test status
Simulation time 547685373 ps
CPU time 12.63 seconds
Started Aug 01 05:43:31 PM PDT 24
Finished Aug 01 05:43:44 PM PDT 24
Peak memory 254448 kb
Host smart-605a4ba7-1eb5-4f8d-84b5-77de8f6ec2cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39133
94664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.3913394664
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.2855614628
Short name T400
Test name
Test status
Simulation time 920063165 ps
CPU time 11.49 seconds
Started Aug 01 05:43:28 PM PDT 24
Finished Aug 01 05:43:39 PM PDT 24
Peak memory 252720 kb
Host smart-63fd6a1e-88de-487f-9d3f-0b6d56b2fa23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28556
14628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.2855614628
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.2120438466
Short name T690
Test name
Test status
Simulation time 153974485272 ps
CPU time 1305.14 seconds
Started Aug 01 05:43:31 PM PDT 24
Finished Aug 01 06:05:17 PM PDT 24
Peak memory 288708 kb
Host smart-260f24e0-9167-4ea8-98a0-0ef09e3a2ffc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120438466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.2120438466
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.4084243934
Short name T667
Test name
Test status
Simulation time 57148980914 ps
CPU time 1041.7 seconds
Started Aug 01 05:43:29 PM PDT 24
Finished Aug 01 06:00:51 PM PDT 24
Peak memory 289096 kb
Host smart-acc749c1-e54b-4813-b99a-cdd6c0fada21
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084243934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.4084243934
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.1216474270
Short name T16
Test name
Test status
Simulation time 41377222089 ps
CPU time 228.89 seconds
Started Aug 01 05:43:31 PM PDT 24
Finished Aug 01 05:47:20 PM PDT 24
Peak memory 248040 kb
Host smart-1bc463c6-93f4-404d-90f8-51f63db63df4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216474270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.1216474270
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.3166224108
Short name T38
Test name
Test status
Simulation time 8902176642 ps
CPU time 63.78 seconds
Started Aug 01 05:43:15 PM PDT 24
Finished Aug 01 05:44:19 PM PDT 24
Peak memory 255692 kb
Host smart-f43f04ab-72ae-48b5-843a-0c735bd94396
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31662
24108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.3166224108
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.1788501921
Short name T660
Test name
Test status
Simulation time 680957401 ps
CPU time 15.15 seconds
Started Aug 01 05:43:18 PM PDT 24
Finished Aug 01 05:43:34 PM PDT 24
Peak memory 247852 kb
Host smart-f35b4a20-23ca-474b-8008-6481dc7a6d90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17885
01921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.1788501921
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.232378701
Short name T210
Test name
Test status
Simulation time 543951399 ps
CPU time 23.47 seconds
Started Aug 01 05:43:29 PM PDT 24
Finished Aug 01 05:43:52 PM PDT 24
Peak memory 247540 kb
Host smart-3826c65f-f710-467b-bade-0bb00a901dbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23237
8701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.232378701
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.2189080030
Short name T683
Test name
Test status
Simulation time 2296117930 ps
CPU time 40.07 seconds
Started Aug 01 05:43:15 PM PDT 24
Finished Aug 01 05:43:55 PM PDT 24
Peak memory 256504 kb
Host smart-280593cb-b436-4b7e-805f-c4ffc4d9c43d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21890
80030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.2189080030
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.2971626350
Short name T327
Test name
Test status
Simulation time 216147069473 ps
CPU time 1834.17 seconds
Started Aug 01 05:43:32 PM PDT 24
Finished Aug 01 06:14:07 PM PDT 24
Peak memory 296720 kb
Host smart-8a3f01f0-8ec9-4669-934f-290c3f90d32d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971626350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.2971626350
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.464033751
Short name T56
Test name
Test status
Simulation time 58323505383 ps
CPU time 3762.96 seconds
Started Aug 01 05:43:30 PM PDT 24
Finished Aug 01 06:46:13 PM PDT 24
Peak memory 305732 kb
Host smart-d6b7c05e-7412-484c-9658-7476f896ba42
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464033751 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.464033751
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.2019650200
Short name T687
Test name
Test status
Simulation time 210669250686 ps
CPU time 2899.99 seconds
Started Aug 01 05:43:45 PM PDT 24
Finished Aug 01 06:32:06 PM PDT 24
Peak memory 289272 kb
Host smart-b7c9ac0d-04ba-489c-9e4f-8cfa6ee96d42
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019650200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.2019650200
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.605948118
Short name T465
Test name
Test status
Simulation time 1032738229 ps
CPU time 59.58 seconds
Started Aug 01 05:43:28 PM PDT 24
Finished Aug 01 05:44:28 PM PDT 24
Peak memory 255900 kb
Host smart-73cd156a-f595-481a-a6bd-dfb46536ff22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60594
8118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.605948118
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.1846421187
Short name T514
Test name
Test status
Simulation time 2189933828 ps
CPU time 34.41 seconds
Started Aug 01 05:43:30 PM PDT 24
Finished Aug 01 05:44:04 PM PDT 24
Peak memory 248276 kb
Host smart-3fd60358-61d5-4843-9824-0dcfbc36fa34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18464
21187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.1846421187
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.1739871031
Short name T308
Test name
Test status
Simulation time 42799430967 ps
CPU time 2335.73 seconds
Started Aug 01 05:43:45 PM PDT 24
Finished Aug 01 06:22:42 PM PDT 24
Peak memory 280968 kb
Host smart-bb72a603-8dc7-4194-b7d0-0c7979bb777e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739871031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.1739871031
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.2118761819
Short name T404
Test name
Test status
Simulation time 8332064388 ps
CPU time 773.49 seconds
Started Aug 01 05:43:45 PM PDT 24
Finished Aug 01 05:56:39 PM PDT 24
Peak memory 272528 kb
Host smart-d2a5255b-2563-436d-a087-4eaa79d020d7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118761819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.2118761819
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.63390024
Short name T620
Test name
Test status
Simulation time 4114461520 ps
CPU time 156.4 seconds
Started Aug 01 05:43:44 PM PDT 24
Finished Aug 01 05:46:21 PM PDT 24
Peak memory 248356 kb
Host smart-7b5da157-1cc8-4513-b2d4-28c9c80a1bc2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63390024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.63390024
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.2396651351
Short name T652
Test name
Test status
Simulation time 2601145706 ps
CPU time 48.31 seconds
Started Aug 01 05:43:31 PM PDT 24
Finished Aug 01 05:44:19 PM PDT 24
Peak memory 255512 kb
Host smart-34411ca1-e79a-4b7d-a78c-3b04293232a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23966
51351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.2396651351
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.3401052913
Short name T39
Test name
Test status
Simulation time 1636541518 ps
CPU time 36.73 seconds
Started Aug 01 05:43:30 PM PDT 24
Finished Aug 01 05:44:06 PM PDT 24
Peak memory 255748 kb
Host smart-fd4eb930-04fc-4dae-b4f2-658a88d145dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34010
52913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.3401052913
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.4270467471
Short name T238
Test name
Test status
Simulation time 2897503000 ps
CPU time 42.16 seconds
Started Aug 01 05:43:29 PM PDT 24
Finished Aug 01 05:44:12 PM PDT 24
Peak memory 247740 kb
Host smart-6beb1fea-46fc-4dd7-be94-d0928a5d6d40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42704
67471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.4270467471
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.390436817
Short name T497
Test name
Test status
Simulation time 534846582 ps
CPU time 10.41 seconds
Started Aug 01 05:43:33 PM PDT 24
Finished Aug 01 05:43:44 PM PDT 24
Peak memory 254408 kb
Host smart-a32cbb6e-62f5-4dcc-8c1d-8ce9a204252d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39043
6817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.390436817
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.1618053195
Short name T546
Test name
Test status
Simulation time 393577323 ps
CPU time 31.67 seconds
Started Aug 01 05:43:46 PM PDT 24
Finished Aug 01 05:44:18 PM PDT 24
Peak memory 256452 kb
Host smart-d403be41-ffb1-449e-8457-9adecfa6cbc2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618053195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.1618053195
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all_with_rand_reset.846704926
Short name T89
Test name
Test status
Simulation time 397809392658 ps
CPU time 6323.98 seconds
Started Aug 01 05:43:44 PM PDT 24
Finished Aug 01 07:29:09 PM PDT 24
Peak memory 322212 kb
Host smart-6bed7088-ac0d-4462-9729-dc04ce5b3841
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846704926 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 48.alert_handler_stress_all_with_rand_reset.846704926
Directory /workspace/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.3950264954
Short name T499
Test name
Test status
Simulation time 4647980845 ps
CPU time 72.21 seconds
Started Aug 01 05:43:45 PM PDT 24
Finished Aug 01 05:44:57 PM PDT 24
Peak memory 256016 kb
Host smart-569d93f9-5275-44b2-8791-795b948c76cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39502
64954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.3950264954
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.1386482758
Short name T507
Test name
Test status
Simulation time 2613406131 ps
CPU time 82.13 seconds
Started Aug 01 05:43:43 PM PDT 24
Finished Aug 01 05:45:06 PM PDT 24
Peak memory 255284 kb
Host smart-944935a8-2be3-463e-9aea-07346c40feaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13864
82758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.1386482758
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.1661303722
Short name T368
Test name
Test status
Simulation time 33249526059 ps
CPU time 1901.85 seconds
Started Aug 01 05:43:45 PM PDT 24
Finished Aug 01 06:15:27 PM PDT 24
Peak memory 281100 kb
Host smart-4b3741b5-091a-4bb6-87fe-80375b7a248a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661303722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.1661303722
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.2133201629
Short name T608
Test name
Test status
Simulation time 27238157190 ps
CPU time 1703.41 seconds
Started Aug 01 05:43:42 PM PDT 24
Finished Aug 01 06:12:06 PM PDT 24
Peak memory 272404 kb
Host smart-6003c652-38b5-4dbb-8a25-9c93932c6a8c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133201629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.2133201629
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.2841194583
Short name T302
Test name
Test status
Simulation time 135578865842 ps
CPU time 280.42 seconds
Started Aug 01 05:43:46 PM PDT 24
Finished Aug 01 05:48:27 PM PDT 24
Peak memory 248280 kb
Host smart-ee3ff86c-f541-4e6e-a900-7293058761a1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841194583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.2841194583
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.1593724613
Short name T48
Test name
Test status
Simulation time 1438827581 ps
CPU time 47.43 seconds
Started Aug 01 05:43:44 PM PDT 24
Finished Aug 01 05:44:32 PM PDT 24
Peak memory 255496 kb
Host smart-d8202b71-4bef-40d7-afb9-f9f3ff8cacb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15937
24613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.1593724613
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.1575576403
Short name T518
Test name
Test status
Simulation time 601567966 ps
CPU time 15.2 seconds
Started Aug 01 05:43:47 PM PDT 24
Finished Aug 01 05:44:02 PM PDT 24
Peak memory 248200 kb
Host smart-3a0a1f75-5d8f-4399-9d0a-820739a19b90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15755
76403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.1575576403
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.1986074074
Short name T557
Test name
Test status
Simulation time 695111116 ps
CPU time 41.48 seconds
Started Aug 01 05:43:45 PM PDT 24
Finished Aug 01 05:44:27 PM PDT 24
Peak memory 255720 kb
Host smart-3d5126f0-5ce2-4943-8067-1b27c56dd050
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19860
74074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.1986074074
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.1626769255
Short name T543
Test name
Test status
Simulation time 83499068 ps
CPU time 7.64 seconds
Started Aug 01 05:43:43 PM PDT 24
Finished Aug 01 05:43:51 PM PDT 24
Peak memory 251284 kb
Host smart-bf00c646-376d-4043-a149-2d05aa1a1ad9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16267
69255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.1626769255
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.2185453361
Short name T481
Test name
Test status
Simulation time 5316271156 ps
CPU time 224.15 seconds
Started Aug 01 05:43:47 PM PDT 24
Finished Aug 01 05:47:31 PM PDT 24
Peak memory 256472 kb
Host smart-bac855d2-d7bb-4c51-9740-5ce16c65c2f3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185453361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.2185453361
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.2537894857
Short name T655
Test name
Test status
Simulation time 45818661374 ps
CPU time 2530.01 seconds
Started Aug 01 05:43:44 PM PDT 24
Finished Aug 01 06:25:54 PM PDT 24
Peak memory 304792 kb
Host smart-690c3cc0-9df8-4c40-8107-cc3031a224cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537894857 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.2537894857
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.3596188429
Short name T693
Test name
Test status
Simulation time 8913762140 ps
CPU time 946.38 seconds
Started Aug 01 05:39:54 PM PDT 24
Finished Aug 01 05:55:40 PM PDT 24
Peak memory 272804 kb
Host smart-ecdad6cb-2c51-4218-8599-da00ce1aca30
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596188429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.3596188429
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.1643394983
Short name T705
Test name
Test status
Simulation time 413741908 ps
CPU time 12.59 seconds
Started Aug 01 05:39:52 PM PDT 24
Finished Aug 01 05:40:05 PM PDT 24
Peak memory 248256 kb
Host smart-af5b945f-194e-4b78-a19f-3aa389a8e77c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1643394983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.1643394983
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.2645437780
Short name T580
Test name
Test status
Simulation time 1887090996 ps
CPU time 141.85 seconds
Started Aug 01 05:39:51 PM PDT 24
Finished Aug 01 05:42:13 PM PDT 24
Peak memory 256436 kb
Host smart-3f7269b5-29fa-4989-adf6-6192ef8d48cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26454
37780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.2645437780
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.629360231
Short name T488
Test name
Test status
Simulation time 1966714418 ps
CPU time 27.53 seconds
Started Aug 01 05:39:57 PM PDT 24
Finished Aug 01 05:40:24 PM PDT 24
Peak memory 255928 kb
Host smart-04d74f80-79ae-4f54-9c1f-3ab0fa1b6162
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62936
0231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.629360231
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.989960922
Short name T654
Test name
Test status
Simulation time 89018021849 ps
CPU time 801.62 seconds
Started Aug 01 05:39:56 PM PDT 24
Finished Aug 01 05:53:18 PM PDT 24
Peak memory 272496 kb
Host smart-6aa292b2-b505-46a1-a1f5-760c158464e9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989960922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.989960922
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.897914531
Short name T1
Test name
Test status
Simulation time 42149962044 ps
CPU time 2463.49 seconds
Started Aug 01 05:39:56 PM PDT 24
Finished Aug 01 06:21:00 PM PDT 24
Peak memory 283104 kb
Host smart-8ed66e96-a014-4720-8c7f-7a4d91622baa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897914531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.897914531
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.352836286
Short name T700
Test name
Test status
Simulation time 5747787491 ps
CPU time 242.6 seconds
Started Aug 01 05:39:50 PM PDT 24
Finished Aug 01 05:43:53 PM PDT 24
Peak memory 248296 kb
Host smart-99c29035-846c-48fb-8a0b-dc69df3dbe10
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352836286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.352836286
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.1766787519
Short name T420
Test name
Test status
Simulation time 903874879 ps
CPU time 13 seconds
Started Aug 01 05:39:54 PM PDT 24
Finished Aug 01 05:40:07 PM PDT 24
Peak memory 248216 kb
Host smart-58476652-49d6-48d2-818e-86c67b1a9443
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17667
87519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.1766787519
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.2361814195
Short name T681
Test name
Test status
Simulation time 1961900372 ps
CPU time 34.32 seconds
Started Aug 01 05:39:50 PM PDT 24
Finished Aug 01 05:40:24 PM PDT 24
Peak memory 248060 kb
Host smart-d2b41417-1ba8-4d5e-b44c-d0cbd53b1476
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23618
14195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.2361814195
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.3875378522
Short name T58
Test name
Test status
Simulation time 271481984 ps
CPU time 30.74 seconds
Started Aug 01 05:39:52 PM PDT 24
Finished Aug 01 05:40:22 PM PDT 24
Peak memory 248344 kb
Host smart-b7f5876c-8763-4bf1-ade7-14dac00dd407
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38753
78522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.3875378522
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.2251544316
Short name T554
Test name
Test status
Simulation time 2154567659 ps
CPU time 33.03 seconds
Started Aug 01 05:39:56 PM PDT 24
Finished Aug 01 05:40:29 PM PDT 24
Peak memory 248528 kb
Host smart-b60ee09f-413d-4c21-831a-3d577f2510e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22515
44316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.2251544316
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.3711834774
Short name T107
Test name
Test status
Simulation time 72377391031 ps
CPU time 1111.74 seconds
Started Aug 01 05:39:55 PM PDT 24
Finished Aug 01 05:58:27 PM PDT 24
Peak memory 280664 kb
Host smart-049b324a-b7b3-4e4c-974f-1ddf129e4c2f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711834774 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.3711834774
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.1026750398
Short name T217
Test name
Test status
Simulation time 14302815 ps
CPU time 2.33 seconds
Started Aug 01 05:40:14 PM PDT 24
Finished Aug 01 05:40:16 PM PDT 24
Peak memory 248532 kb
Host smart-d57cce6e-0989-4646-a486-43856b96edbe
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1026750398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.1026750398
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.4251930468
Short name T532
Test name
Test status
Simulation time 71517154546 ps
CPU time 908.28 seconds
Started Aug 01 05:39:57 PM PDT 24
Finished Aug 01 05:55:05 PM PDT 24
Peak memory 272540 kb
Host smart-6597519f-5e07-4aa5-b7c6-928c5e7dd4b9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251930468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.4251930468
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.333495542
Short name T495
Test name
Test status
Simulation time 588853349 ps
CPU time 12.56 seconds
Started Aug 01 05:39:57 PM PDT 24
Finished Aug 01 05:40:09 PM PDT 24
Peak memory 248272 kb
Host smart-fd254b52-ef5c-4949-b16c-443c851482a2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=333495542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.333495542
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.1541429764
Short name T26
Test name
Test status
Simulation time 2510798894 ps
CPU time 157.54 seconds
Started Aug 01 05:40:00 PM PDT 24
Finished Aug 01 05:42:37 PM PDT 24
Peak memory 256068 kb
Host smart-b97872d5-9c12-4ee9-8ddb-cf321f3b93f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15414
29764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.1541429764
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.1920422913
Short name T337
Test name
Test status
Simulation time 3850874894 ps
CPU time 60.73 seconds
Started Aug 01 05:40:01 PM PDT 24
Finished Aug 01 05:41:02 PM PDT 24
Peak memory 256148 kb
Host smart-6120231e-eecd-4edb-b748-d8f4b1121f63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19204
22913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.1920422913
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.799612659
Short name T309
Test name
Test status
Simulation time 164767634586 ps
CPU time 2434.09 seconds
Started Aug 01 05:40:14 PM PDT 24
Finished Aug 01 06:20:48 PM PDT 24
Peak memory 281560 kb
Host smart-0d8009b0-41de-46a9-a047-8f6c931a3a04
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799612659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.799612659
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.3692517397
Short name T650
Test name
Test status
Simulation time 36409181786 ps
CPU time 1180.14 seconds
Started Aug 01 05:39:58 PM PDT 24
Finished Aug 01 05:59:39 PM PDT 24
Peak memory 272884 kb
Host smart-39c9400b-34b4-4779-ad72-7b9f8a642f45
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692517397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.3692517397
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.110408153
Short name T293
Test name
Test status
Simulation time 10034091861 ps
CPU time 391.58 seconds
Started Aug 01 05:40:13 PM PDT 24
Finished Aug 01 05:46:45 PM PDT 24
Peak memory 248368 kb
Host smart-1ded443d-157d-4e87-9f9d-6fee14352d11
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110408153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.110408153
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.3452823864
Short name T388
Test name
Test status
Simulation time 192754810 ps
CPU time 17.28 seconds
Started Aug 01 05:40:14 PM PDT 24
Finished Aug 01 05:40:31 PM PDT 24
Peak memory 255532 kb
Host smart-1f1f3a9e-89a8-4a81-8d07-673fe2b87e0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34528
23864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.3452823864
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.2169480742
Short name T638
Test name
Test status
Simulation time 442348559 ps
CPU time 27.66 seconds
Started Aug 01 05:39:56 PM PDT 24
Finished Aug 01 05:40:24 PM PDT 24
Peak memory 256408 kb
Host smart-68591137-7d1a-4dbd-889f-d976b4d8b5a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21694
80742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.2169480742
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.1269440744
Short name T84
Test name
Test status
Simulation time 1510085955 ps
CPU time 13.99 seconds
Started Aug 01 05:40:04 PM PDT 24
Finished Aug 01 05:40:18 PM PDT 24
Peak memory 247600 kb
Host smart-d2b78684-e3b5-4683-b55c-493d1f3fc07b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12694
40744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.1269440744
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.2504172248
Short name T644
Test name
Test status
Simulation time 350473018 ps
CPU time 30.47 seconds
Started Aug 01 05:40:04 PM PDT 24
Finished Aug 01 05:40:35 PM PDT 24
Peak memory 248280 kb
Host smart-37db99f3-d34b-4330-b354-f8750bc8df92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25041
72248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.2504172248
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.2578780554
Short name T325
Test name
Test status
Simulation time 64512064074 ps
CPU time 1568.86 seconds
Started Aug 01 05:40:08 PM PDT 24
Finished Aug 01 06:06:18 PM PDT 24
Peak memory 288540 kb
Host smart-9df9e07f-0b64-4f91-97b6-c9e9c69b2a70
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578780554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.2578780554
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.613939972
Short name T101
Test name
Test status
Simulation time 40905484226 ps
CPU time 3540.54 seconds
Started Aug 01 05:39:58 PM PDT 24
Finished Aug 01 06:38:59 PM PDT 24
Peak memory 322136 kb
Host smart-f8500805-1e4d-4315-8530-41bb5b9cf1c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613939972 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.613939972
Directory /workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.1431042960
Short name T220
Test name
Test status
Simulation time 45371337 ps
CPU time 4.38 seconds
Started Aug 01 05:40:14 PM PDT 24
Finished Aug 01 05:40:18 PM PDT 24
Peak memory 248628 kb
Host smart-8bab39f2-d467-4078-8682-56d355fd090a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1431042960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.1431042960
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.3259743924
Short name T450
Test name
Test status
Simulation time 53705700252 ps
CPU time 3097.21 seconds
Started Aug 01 05:40:03 PM PDT 24
Finished Aug 01 06:31:41 PM PDT 24
Peak memory 289008 kb
Host smart-fc4fb81a-36eb-4587-97f0-e08675cfb768
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259743924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.3259743924
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.4056852025
Short name T551
Test name
Test status
Simulation time 167334392 ps
CPU time 11.1 seconds
Started Aug 01 05:40:02 PM PDT 24
Finished Aug 01 05:40:13 PM PDT 24
Peak memory 248168 kb
Host smart-18243d5b-7e80-4a9e-939b-58adb2a95ec2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4056852025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.4056852025
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.3340625107
Short name T649
Test name
Test status
Simulation time 10229278366 ps
CPU time 134.45 seconds
Started Aug 01 05:39:58 PM PDT 24
Finished Aug 01 05:42:12 PM PDT 24
Peak memory 255592 kb
Host smart-b82a1818-3857-431d-9560-07b117d6e246
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33406
25107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.3340625107
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.2312166006
Short name T599
Test name
Test status
Simulation time 378974371 ps
CPU time 26.05 seconds
Started Aug 01 05:40:04 PM PDT 24
Finished Aug 01 05:40:30 PM PDT 24
Peak memory 255972 kb
Host smart-a179c885-9d81-4c15-ad4b-9cdf8c72af38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23121
66006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.2312166006
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.1904651740
Short name T315
Test name
Test status
Simulation time 486271302927 ps
CPU time 1806.81 seconds
Started Aug 01 05:40:13 PM PDT 24
Finished Aug 01 06:10:21 PM PDT 24
Peak memory 282252 kb
Host smart-9ae843d4-2985-4eba-bfb1-fb9643df0c76
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904651740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.1904651740
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.567630541
Short name T504
Test name
Test status
Simulation time 10655957239 ps
CPU time 1120.57 seconds
Started Aug 01 05:40:02 PM PDT 24
Finished Aug 01 05:58:42 PM PDT 24
Peak memory 270932 kb
Host smart-79dded06-4f56-4bd5-8a86-9ce09f92fa6b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567630541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.567630541
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.229755029
Short name T269
Test name
Test status
Simulation time 23652608309 ps
CPU time 498.19 seconds
Started Aug 01 05:39:56 PM PDT 24
Finished Aug 01 05:48:14 PM PDT 24
Peak memory 248316 kb
Host smart-514cd175-e3be-4d3d-8bd2-b51b3466fda8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229755029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.229755029
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.301094315
Short name T463
Test name
Test status
Simulation time 141837762 ps
CPU time 12.86 seconds
Started Aug 01 05:39:57 PM PDT 24
Finished Aug 01 05:40:10 PM PDT 24
Peak memory 248296 kb
Host smart-71f2683d-4474-4894-9389-3eb10b35a5c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30109
4315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.301094315
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.2923997049
Short name T696
Test name
Test status
Simulation time 95642722 ps
CPU time 8.46 seconds
Started Aug 01 05:40:14 PM PDT 24
Finished Aug 01 05:40:22 PM PDT 24
Peak memory 247860 kb
Host smart-1bd5e639-8289-4812-a4b7-d1989348b968
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29239
97049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.2923997049
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.2554291259
Short name T421
Test name
Test status
Simulation time 712278621 ps
CPU time 19.76 seconds
Started Aug 01 05:40:04 PM PDT 24
Finished Aug 01 05:40:24 PM PDT 24
Peak memory 248216 kb
Host smart-691eeb39-b1b4-4be2-abb8-576b6fbae8e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25542
91259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.2554291259
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.984304285
Short name T511
Test name
Test status
Simulation time 475241746 ps
CPU time 16.88 seconds
Started Aug 01 05:39:55 PM PDT 24
Finished Aug 01 05:40:12 PM PDT 24
Peak memory 256420 kb
Host smart-4ceed904-3372-4e76-ab88-0c9a14ce7d40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98430
4285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.984304285
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.3543500657
Short name T529
Test name
Test status
Simulation time 43874751491 ps
CPU time 2435.21 seconds
Started Aug 01 05:39:58 PM PDT 24
Finished Aug 01 06:20:33 PM PDT 24
Peak memory 288252 kb
Host smart-e9b7b9d5-39ca-4ea9-adb5-12d10fb1e1de
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543500657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.3543500657
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.3700782279
Short name T126
Test name
Test status
Simulation time 37114492 ps
CPU time 3.94 seconds
Started Aug 01 05:40:13 PM PDT 24
Finished Aug 01 05:40:17 PM PDT 24
Peak memory 248512 kb
Host smart-649646ed-3452-4364-b53b-7fd965ad94fe
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3700782279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.3700782279
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.1733506527
Short name T707
Test name
Test status
Simulation time 154899572933 ps
CPU time 2480.28 seconds
Started Aug 01 05:40:05 PM PDT 24
Finished Aug 01 06:21:25 PM PDT 24
Peak memory 288264 kb
Host smart-1a713f35-62cd-40fb-ab3f-f9a252d4420c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733506527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.1733506527
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.1047577410
Short name T626
Test name
Test status
Simulation time 488920089 ps
CPU time 19.03 seconds
Started Aug 01 05:40:06 PM PDT 24
Finished Aug 01 05:40:25 PM PDT 24
Peak memory 248264 kb
Host smart-0afeaeb6-d216-497b-9740-9905cd2f1a98
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1047577410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.1047577410
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.693493355
Short name T428
Test name
Test status
Simulation time 1736584957 ps
CPU time 92.78 seconds
Started Aug 01 05:40:05 PM PDT 24
Finished Aug 01 05:41:38 PM PDT 24
Peak memory 256464 kb
Host smart-2c603da7-a2a0-4692-8432-050447b4aeac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69349
3355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.693493355
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.1305098072
Short name T451
Test name
Test status
Simulation time 588147886 ps
CPU time 19.72 seconds
Started Aug 01 05:40:05 PM PDT 24
Finished Aug 01 05:40:25 PM PDT 24
Peak memory 256344 kb
Host smart-a095b1d8-ba7a-4ddc-8356-810a3bca9b31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13050
98072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.1305098072
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.1570481204
Short name T363
Test name
Test status
Simulation time 30754204348 ps
CPU time 842.6 seconds
Started Aug 01 05:40:08 PM PDT 24
Finished Aug 01 05:54:11 PM PDT 24
Peak memory 272792 kb
Host smart-44b0d9be-4d59-4c35-8850-e26bede3c117
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570481204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.1570481204
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.2255162189
Short name T592
Test name
Test status
Simulation time 77846900218 ps
CPU time 2139.73 seconds
Started Aug 01 05:40:05 PM PDT 24
Finished Aug 01 06:15:45 PM PDT 24
Peak memory 281068 kb
Host smart-438e2ffd-1cb1-4cc5-965c-c20024008254
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255162189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.2255162189
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.1217087869
Short name T300
Test name
Test status
Simulation time 5518699265 ps
CPU time 166.55 seconds
Started Aug 01 05:40:08 PM PDT 24
Finished Aug 01 05:42:55 PM PDT 24
Peak memory 254764 kb
Host smart-18230061-7aef-4730-9717-e200c8b522cd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217087869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.1217087869
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.3172597163
Short name T534
Test name
Test status
Simulation time 1031018045 ps
CPU time 23.55 seconds
Started Aug 01 05:40:14 PM PDT 24
Finished Aug 01 05:40:37 PM PDT 24
Peak memory 248348 kb
Host smart-96962bb6-e547-4823-aa2b-370e16a88bfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31725
97163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.3172597163
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.1353942636
Short name T662
Test name
Test status
Simulation time 474335446 ps
CPU time 28.46 seconds
Started Aug 01 05:40:07 PM PDT 24
Finished Aug 01 05:40:35 PM PDT 24
Peak memory 248092 kb
Host smart-7ed38d38-1809-41fc-88ae-be5c2cd2df25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13539
42636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.1353942636
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.4101658503
Short name T345
Test name
Test status
Simulation time 686202416 ps
CPU time 41.75 seconds
Started Aug 01 05:40:06 PM PDT 24
Finished Aug 01 05:40:48 PM PDT 24
Peak memory 255812 kb
Host smart-9a1e0584-6c9e-401c-829a-c2bcb2ef98c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41016
58503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.4101658503
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.1928892124
Short name T436
Test name
Test status
Simulation time 4763419236 ps
CPU time 29.58 seconds
Started Aug 01 05:39:58 PM PDT 24
Finished Aug 01 05:40:28 PM PDT 24
Peak memory 255968 kb
Host smart-b6e15761-dd0b-44d8-83c7-b646035030af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19288
92124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.1928892124
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.3952758146
Short name T5
Test name
Test status
Simulation time 66784533483 ps
CPU time 1564.88 seconds
Started Aug 01 05:40:07 PM PDT 24
Finished Aug 01 06:06:12 PM PDT 24
Peak memory 298764 kb
Host smart-960670f9-db85-4ab7-b3ff-65a39e35b9b6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952758146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.3952758146
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.88785068
Short name T222
Test name
Test status
Simulation time 18183743 ps
CPU time 2.92 seconds
Started Aug 01 05:40:09 PM PDT 24
Finished Aug 01 05:40:12 PM PDT 24
Peak memory 248568 kb
Host smart-5a3636c1-c7ed-4b72-a928-4fec9697d2b1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=88785068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.88785068
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.1051775354
Short name T440
Test name
Test status
Simulation time 29759336698 ps
CPU time 1900.85 seconds
Started Aug 01 05:40:12 PM PDT 24
Finished Aug 01 06:11:53 PM PDT 24
Peak memory 281876 kb
Host smart-2fa19b1b-0c53-40d2-8c35-d5eff83f213e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051775354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.1051775354
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.3766530189
Short name T42
Test name
Test status
Simulation time 239213220 ps
CPU time 12.44 seconds
Started Aug 01 05:40:06 PM PDT 24
Finished Aug 01 05:40:19 PM PDT 24
Peak memory 248172 kb
Host smart-677d7b0c-4309-4081-8b5c-09f983b26867
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3766530189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.3766530189
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.3218232160
Short name T498
Test name
Test status
Simulation time 8375965917 ps
CPU time 88.63 seconds
Started Aug 01 05:40:05 PM PDT 24
Finished Aug 01 05:41:34 PM PDT 24
Peak memory 256304 kb
Host smart-5349f977-7662-4226-80ea-cb32161bf841
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32182
32160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.3218232160
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.2979556107
Short name T235
Test name
Test status
Simulation time 1328443988 ps
CPU time 41.2 seconds
Started Aug 01 05:40:09 PM PDT 24
Finished Aug 01 05:40:50 PM PDT 24
Peak memory 247824 kb
Host smart-ebd92208-d3ef-411c-9d67-e8577ce8cdd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29795
56107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.2979556107
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.3557551666
Short name T582
Test name
Test status
Simulation time 124300041857 ps
CPU time 1310.67 seconds
Started Aug 01 05:40:07 PM PDT 24
Finished Aug 01 06:01:58 PM PDT 24
Peak memory 285476 kb
Host smart-476094e4-c1a0-4b79-8464-6e37ec1ec94e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557551666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.3557551666
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.2854685303
Short name T244
Test name
Test status
Simulation time 233695249705 ps
CPU time 1736.93 seconds
Started Aug 01 05:40:06 PM PDT 24
Finished Aug 01 06:09:03 PM PDT 24
Peak memory 272796 kb
Host smart-02a3862e-c85e-4326-9182-f903ac73174f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854685303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.2854685303
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.2479279597
Short name T617
Test name
Test status
Simulation time 20043874966 ps
CPU time 433.25 seconds
Started Aug 01 05:40:07 PM PDT 24
Finished Aug 01 05:47:21 PM PDT 24
Peak memory 248256 kb
Host smart-c0ea1c0c-dd93-46c1-a3f1-80176b6c3823
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479279597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.2479279597
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.137815732
Short name T270
Test name
Test status
Simulation time 906835545 ps
CPU time 54.81 seconds
Started Aug 01 05:40:07 PM PDT 24
Finished Aug 01 05:41:02 PM PDT 24
Peak memory 255836 kb
Host smart-12f5eb16-1f81-4313-beef-9a4e668c7ea1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13781
5732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.137815732
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.2912613652
Short name T410
Test name
Test status
Simulation time 499139929 ps
CPU time 10.63 seconds
Started Aug 01 05:40:07 PM PDT 24
Finished Aug 01 05:40:18 PM PDT 24
Peak memory 254504 kb
Host smart-c55e4b52-8c8e-4a22-86fe-7c285fdc0fb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29126
13652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.2912613652
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.318980940
Short name T81
Test name
Test status
Simulation time 1462598068 ps
CPU time 53.22 seconds
Started Aug 01 05:40:05 PM PDT 24
Finished Aug 01 05:40:58 PM PDT 24
Peak memory 247828 kb
Host smart-fdb97de0-ee16-48d0-a820-35630d070e36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31898
0940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.318980940
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.2421523318
Short name T515
Test name
Test status
Simulation time 543072350 ps
CPU time 27.72 seconds
Started Aug 01 05:40:08 PM PDT 24
Finished Aug 01 05:40:36 PM PDT 24
Peak memory 256408 kb
Host smart-22965107-9ff0-4873-be28-03c15afc26df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24215
23318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.2421523318
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.1140176899
Short name T116
Test name
Test status
Simulation time 5354770457 ps
CPU time 337.47 seconds
Started Aug 01 05:40:08 PM PDT 24
Finished Aug 01 05:45:46 PM PDT 24
Peak memory 256460 kb
Host smart-dcdea3f3-a738-4580-b22f-55441fdcba1d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140176899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.1140176899
Directory /workspace/9.alert_handler_stress_all/latest
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