Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	87673	1			T3	2741		T12	1		T24	451
class_i[0x1]	70830	1			T10	3729		T24	692		T96	80
class_i[0x2]	50725	1			T3	1		T10	5		T24	1
class_i[0x3]	66497	1			T12	2		T17	5003		T14	7

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	71212	1			T3	676		T10	882		T17	1208
alert[0x1]	68316	1			T3	640		T10	955		T12	3
alert[0x2]	68177	1			T3	717		T10	997		T17	1239
alert[0x3]	68020	1			T3	709		T10	900		T17	1293

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

275439

1

T3

2742

T10

3734

T12

2

esc_ping_fail

286

1

T12

1

T14

7

T15

1

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	71129	1			T3	676		T10	882		T17	1208
esc_integrity_fail	alert[0x1]	68241	1			T3	640		T10	955		T12	2
esc_integrity_fail	alert[0x2]	68111	1			T3	717		T10	997		T17	1239
esc_integrity_fail	alert[0x3]	67958	1			T3	709		T10	900		T17	1293
esc_ping_fail	alert[0x0]	83	1			T14	2		T106	1		T256	2
esc_ping_fail	alert[0x1]	75	1			T12	1		T14	1		T15	1
esc_ping_fail	alert[0x2]	66	1			T14	2		T106	1		T293	1
esc_ping_fail	alert[0x3]	62	1			T14	2		T256	1		T293	1

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	87585	1			T3	2741		T24	451		T5	3037
esc_integrity_fail	class_i[0x1]	70775	1			T10	3729		T24	692		T96	80
esc_integrity_fail	class_i[0x2]	50657	1			T3	1		T10	5		T24	1
esc_integrity_fail	class_i[0x3]	66422	1			T12	2		T17	5003		T14	7
esc_ping_fail	class_i[0x0]	88	1			T12	1		T14	6		T293	1
esc_ping_fail	class_i[0x1]	55	1			T256	4		T293	1		T323	6
esc_ping_fail	class_i[0x2]	68	1			T14	1		T15	1		T293	2
esc_ping_fail	class_i[0x3]	75	1			T106	4		T314	9		T324	7