Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	704141077	0	0	624
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	704141077	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	704141077	704010667	0	0
tb.dut.CheckAccuCntDw	0	0	624	624	0	0
tb.dut.CheckEscCntDw	0	0	624	624	0	0
tb.dut.CheckNAlerts	0	0	624	624	0	0
tb.dut.CheckNClasses	0	0	624	624	0	0
tb.dut.CheckNEscSev	0	0	624	624	0	0
tb.dut.CrashdumpKnownO_A	0	0	704141077	704010667	0	0
tb.dut.EdnKnownO_A	0	0	704141077	704010667	0	0
tb.dut.EscPKnownO_A	0	0	704141077	704010667	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	704141077	50	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	704141077	50	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	704141077	50	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	704141077	50	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	704141077	50	0	0
tb.dut.IrqAKnownO_A	0	0	704141077	704010667	0	0
tb.dut.IrqBKnownO_A	0	0	704141077	704010667	0	0
tb.dut.IrqCKnownO_A	0	0	704141077	704010667	0	0
tb.dut.IrqDKnownO_A	0	0	704141077	704010667	0	0
tb.dut.TlAReadyKnownO_A	0	0	704141077	704010667	0	0
tb.dut.TlDValidKnownO_A	0	0	704141077	704010667	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	727679643	2976825	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	727679643	13211	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	727679643	13193	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	727679643	13123	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	727679643	13158	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	727679643	13142	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	727679643	13309	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	727679643	13432	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	727679643	13291	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	727679643	12905	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	727679643	13104	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	727679643	12828	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	727679643	13082	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	727679643	12960	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	727679643	12989	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	727679643	13061	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	727679643	13132	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	727679643	13341	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	727679643	13034	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	727679643	13114	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	727679643	13316	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	727679643	13119	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	727679643	12976	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	727679643	13120	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	727679643	13209	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	727679643	13112	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	727679643	13142	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	727679643	13119	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	727679643	13473	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	727679643	12991	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	727679643	13048	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	727679643	13065	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	727679643	13097	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	727679643	12908	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	727679643	13327	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	727679643	12864	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	727679643	12777	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	727679643	13207	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	727679643	12898	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	727679643	13380	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	727679643	13176	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	727679643	12963	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	727679643	13011	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	727679643	12925	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	727679643	13105	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	727679643	13191	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	727679643	13227	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	727679643	13105	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	727679643	12724	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	727679643	12884	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	727679643	13032	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	727679643	13294	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	727679643	13120	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	727679643	12866	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	727679643	13710	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	727679643	13017	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	727679643	13140	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	727679643	12971	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	727679643	13168	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	727679643	13272	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	727679643	13318	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	727679643	13004	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	727679643	13306	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	727679643	13093	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	727679643	13418	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	727679643	13097	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	727679643	13293	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	727679643	12935	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	727679643	13122	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	727679643	13320	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	727679643	25686	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	727679643	13168	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	727679643	12848	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	727679643	12987	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	727679643	12716	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	727679643	13131	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	727679643	13478	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	727679643	13363	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	727679643	12782	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	704141077	50	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	704141077	50	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	704141077	50	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	704141077	1943	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	704141077	224684	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	704141077	348640924	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	704141077	133	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	704141077	833	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	704141077	52	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	704141077	443	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	703954084	256297391	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	704141077	935	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	704141077	922	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	704141077	899	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	704141077	871	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	704141077	2340	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	704141077	219815	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	704141077	2215	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	704141077	70	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	704141077	834	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	704141077	684	0	0
tb.dut.gen_classes[0].u_esc_timer.EscStateOut_A	0	0	703951978	703885357	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	624	624	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	704141077	704010667	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	704141077	50	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	704141077	50	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	704141077	50	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	704141077	1952	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	704141077	195087	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	704141077	363171647	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	704141077	162	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	704141077	495	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	704141077	21	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	704141077	227	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	703954084	291933276	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	704141077	577	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	704141077	574	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	704141077	566	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	704141077	557	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	704141077	963	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	704141077	110107	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	704141077	868	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	704141077	69	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	704141077	825	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	704141077	675	0	0
tb.dut.gen_classes[1].u_esc_timer.EscStateOut_A	0	0	703951978	703885357	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	624	624	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	704141077	704010667	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	704141077	50	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	704141077	50	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	704141077	50	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	704141077	6164	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	704141077	193853	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	704141077	399891682	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	704141077	188	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	704141077	481	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	704141077	18	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	704141077	197	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	703954084	291122884	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	704141077	540	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	704141077	530	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	704141077	523	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	704141077	516	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	704141077	1531	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	704141077	147991	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	704141077	1462	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	704141077	50	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	704141077	835	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	704141077	685	0	0
tb.dut.gen_classes[2].u_esc_timer.EscStateOut_A	0	0	703951978	703885357	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	624	624	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	704141077	704010667	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	704141077	50	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	704141077	50	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	704141077	50	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	704141077	3194	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	704141077	223648	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	704141077	422162757	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	704141077	152	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	704141077	544	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	704141077	27	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	704141077	262	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	703954084	318780528	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	704141077	590	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	704141077	577	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	704141077	570	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	704141077	562	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	704141077	2202	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	704141077	206160	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	704141077	2140	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	704141077	32	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	704141077	826	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	704141077	676	0	0
tb.dut.gen_classes[3].u_esc_timer.EscStateOut_A	0	0	703951978	703885357	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	624	624	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	704141077	704010667	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	727679643	134753619	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	727679643	727070402	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	727679643	727070402	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	727679643	189403224	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	727679643	727070402	0	0
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