Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.61	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	44	2	42	95.45

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_sig_index_cp	4	0	4	100.00	100	1	1	0
esc_sig_len_cp	11	0	11	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
len_per_esc_sig	44	2	42	95.45	100	1	1	0

Summary for Variable esc_sig_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_sig_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	179	1			T2	1		T13	1		T50	1
index[0x1]	173	1			T1	1		T10	2		T71	1
index[0x2]	179	1			T1	1		T3	1		T10	1
index[0x3]	150	1			T20	1		T48	1		T27	1

---

Summary for Variable esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for esc_sig_len_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lens_less_than_1000[0]	189	1			T3	1		T27	1		T5	1
lens_less_than_1000[1]	124	1			T20	1		T24	1		T50	1
lens_less_than_1000[2]	89	1			T2	1		T10	1		T25	1
lens_less_than_1000[3]	85	1			T10	2		T48	1		T70	1
lens_less_than_1000[4]	65	1			T1	1		T71	1		T110	1
lens_less_than_1000[5]	43	1			T13	1		T5	1		T29	1
lens_less_than_1000[6]	27	1			T71	1		T29	1		T97	1
lens_less_than_1000[7]	26	1			T1	1		T53	1		T244	1
lens_less_than_1000[8]	23	1			T203	1		T290	1		T137	1
lens_less_than_1000[9]	3	1			T75	1		T56	1		T258	1
len_2	7	1			T96	2		T109	1		T267	1

---

Summary for Cross len_per_esc_sig

Samples crossed: esc_sig_index_cp esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	44	2	42	95.45	2

Automatically Generated Cross Bins for len_per_esc_sig

Uncovered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	NUMBER	STATUS
[index[0x0]]	[len_2]	0	1	1
[index[0x1]]	[lens_less_than_1000[9]]	0	1	1

Covered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	lens_less_than_1000[0]	53	1			T91	1		T242	1		T77	1
index[0x0]	lens_less_than_1000[1]	31	1			T82	1		T88	1		T30	1
index[0x0]	lens_less_than_1000[2]	30	1			T2	1		T86	1		T109	1
index[0x0]	lens_less_than_1000[3]	17	1			T50	1		T87	1		T291	1
index[0x0]	lens_less_than_1000[4]	11	1			T81	1		T292	1		T131	1
index[0x0]	lens_less_than_1000[5]	10	1			T13	1		T293	1		T141	1
index[0x0]	lens_less_than_1000[6]	10	1			T112	7		T131	1		T294	1
index[0x0]	lens_less_than_1000[7]	5	1			T131	3		T295	1		T296	1
index[0x0]	lens_less_than_1000[8]	11	1			T297	1		T298	1		T299	1
index[0x0]	lens_less_than_1000[9]	1	1			T75	1		-	-		-	-
index[0x1]	lens_less_than_1000[0]	53	1			T29	1		T84	1		T88	1
index[0x1]	lens_less_than_1000[1]	25	1			T50	1		T34	1		T136	2
index[0x1]	lens_less_than_1000[2]	25	1			T10	1		T29	1		T84	1
index[0x1]	lens_less_than_1000[3]	20	1			T10	1		T56	1		T30	2
index[0x1]	lens_less_than_1000[4]	17	1			T98	2		T80	1		T60	1
index[0x1]	lens_less_than_1000[5]	15	1			T29	1		T203	1		T300	1
index[0x1]	lens_less_than_1000[6]	6	1			T71	1		T29	1		T103	1
index[0x1]	lens_less_than_1000[7]	4	1			T1	1		T244	1		T301	1
index[0x1]	lens_less_than_1000[8]	6	1			T290	1		T137	1		T62	1
index[0x1]	len_2	2	1			T96	1		T302	1		-	-
index[0x2]	lens_less_than_1000[0]	49	1			T3	1		T5	1		T83	1
index[0x2]	lens_less_than_1000[1]	31	1			T303	1		T98	1		T34	1
index[0x2]	lens_less_than_1000[2]	20	1			T25	1		T53	1		T100	1
index[0x2]	lens_less_than_1000[3]	25	1			T10	1		T70	1		T98	2
index[0x2]	lens_less_than_1000[4]	19	1			T1	1		T71	1		T58	1
index[0x2]	lens_less_than_1000[5]	9	1			T31	1		T131	1		T64	1
index[0x2]	lens_less_than_1000[6]	5	1			T280	1		T59	1		T63	1
index[0x2]	lens_less_than_1000[7]	13	1			T124	2		T304	1		T305	1
index[0x2]	lens_less_than_1000[8]	3	1			T62	1		T306	1		T307	1
index[0x2]	lens_less_than_1000[9]	1	1			T56	1		-	-		-	-
index[0x2]	len_2	4	1			T96	1		T109	1		T128	1
index[0x3]	lens_less_than_1000[0]	34	1			T27	1		T14	1		T6	2
index[0x3]	lens_less_than_1000[1]	37	1			T20	1		T24	1		T86	1
index[0x3]	lens_less_than_1000[2]	14	1			T88	1		T291	1		T31	1
index[0x3]	lens_less_than_1000[3]	23	1			T48	1		T75	1		T56	1
index[0x3]	lens_less_than_1000[4]	18	1			T110	1		T31	1		T137	1
index[0x3]	lens_less_than_1000[5]	9	1			T5	1		T32	1		T61	1
index[0x3]	lens_less_than_1000[6]	6	1			T97	1		T308	1		T263	1
index[0x3]	lens_less_than_1000[7]	4	1			T53	1		T102	1		T300	1
index[0x3]	lens_less_than_1000[8]	3	1			T203	1		T309	1		T310	1
index[0x3]	lens_less_than_1000[9]	1	1			T258	1		-	-		-	-
index[0x3]	len_2	1	1			T267	1		-	-		-	-