Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.59	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	4	36	90.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	4	36	90.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	70	1			T24	1		T25	1		T6	1
class_index[0x1]	70	1			T25	1		T5	2		T91	1
class_index[0x2]	50	1			T50	1		T89	1		T99	2
class_index[0x3]	32	1			T24	1		T25	1		T6	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	88	1			T24	1		T25	1		T5	2
intr_timeout_cnt[1]	41	1			T24	1		T25	1		T50	1
intr_timeout_cnt[2]	19	1			T25	1		T100	1		T60	1
intr_timeout_cnt[3]	19	1			T6	1		T89	1		T56	1
intr_timeout_cnt[4]	5	1			T86	1		T262	1		T269	1
intr_timeout_cnt[5]	10	1			T86	1		T89	1		T118	1
intr_timeout_cnt[6]	17	1			T50	1		T95	1		T89	1
intr_timeout_cnt[7]	8	1			T102	1		T61	1		T143	1
intr_timeout_cnt[8]	12	1			T80	1		T270	1		T262	1
intr_timeout_cnt[9]	3	1			T271	1		T272	1		T273	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	4	36	90.00	4

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[8]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[4] , intr_timeout_cnt[5]]	--	--	2
[class_index[0x3]]	[intr_timeout_cnt[9]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	31	1			T24	1		T6	1		T98	1
class_index[0x0]	intr_timeout_cnt[1]	7	1			T94	1		T35	1		T102	1
class_index[0x0]	intr_timeout_cnt[2]	7	1			T25	1		T100	1		T274	1
class_index[0x0]	intr_timeout_cnt[3]	6	1			T80	1		T216	1		T275	1
class_index[0x0]	intr_timeout_cnt[4]	1	1			T262	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[5]	6	1			T86	1		T89	1		T118	1
class_index[0x0]	intr_timeout_cnt[6]	9	1			T50	1		T89	1		T276	4
class_index[0x0]	intr_timeout_cnt[7]	2	1			T143	1		T277	1		-	-
class_index[0x0]	intr_timeout_cnt[9]	1	1			T273	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[0]	31	1			T5	2		T91	1		T99	1
class_index[0x1]	intr_timeout_cnt[1]	15	1			T25	1		T100	1		T80	1
class_index[0x1]	intr_timeout_cnt[2]	5	1			T60	1		T278	1		T279	1
class_index[0x1]	intr_timeout_cnt[3]	3	1			T280	1		T262	1		T113	1
class_index[0x1]	intr_timeout_cnt[4]	3	1			T86	1		T269	1		T128	1
class_index[0x1]	intr_timeout_cnt[5]	2	1			T128	1		T281	1		-	-
class_index[0x1]	intr_timeout_cnt[6]	5	1			T95	1		T141	1		T136	1
class_index[0x1]	intr_timeout_cnt[7]	2	1			T61	1		T282	1		-	-
class_index[0x1]	intr_timeout_cnt[8]	3	1			T263	1		T275	1		T283	1
class_index[0x1]	intr_timeout_cnt[9]	1	1			T272	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[0]	17	1			T99	1		T101	1		T75	1
class_index[0x2]	intr_timeout_cnt[1]	11	1			T50	1		T99	1		T75	1
class_index[0x2]	intr_timeout_cnt[2]	1	1			T284	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[3]	5	1			T89	1		T285	1		T274	1
class_index[0x2]	intr_timeout_cnt[4]	1	1			T286	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[5]	2	1			T258	1		T130	1		-	-
class_index[0x2]	intr_timeout_cnt[6]	1	1			T287	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[7]	3	1			T102	1		T287	1		T277	1
class_index[0x2]	intr_timeout_cnt[8]	8	1			T80	1		T270	1		T262	1
class_index[0x2]	intr_timeout_cnt[9]	1	1			T271	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[0]	9	1			T25	1		T56	1		T141	2
class_index[0x3]	intr_timeout_cnt[1]	8	1			T24	1		T94	1		T103	1
class_index[0x3]	intr_timeout_cnt[2]	6	1			T118	1		T274	1		T113	1
class_index[0x3]	intr_timeout_cnt[3]	5	1			T6	1		T56	1		T126	1
class_index[0x3]	intr_timeout_cnt[6]	2	1			T263	1		T288	1		-	-
class_index[0x3]	intr_timeout_cnt[7]	1	1			T286	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[8]	1	1			T289	1		-	-		-	-