Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	358995	1			T1	1345		T2	1365		T3	1035
all_values[1]	358995	1			T1	1345		T2	1365		T3	1035
all_values[2]	358995	1			T1	1345		T2	1365		T3	1035
all_values[3]	358995	1			T1	1345		T2	1365		T3	1035

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

713211

1

T1

2754

T2

2745

T3

2070

auto[1]

722769

1

T1

2626

T2

2715

T3

2070

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

849343

1

T1

2717

T2

2760

T3

2094

auto[1]

586637

1

T1

2663

T2

2700

T3

2046

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	102586	1			T1	329		T2	356		T3	249
all_values[0]	auto[0]	auto[1]	75381	1			T1	328		T2	352		T3	247
all_values[0]	auto[1]	auto[0]	104860	1			T1	344		T2	329		T3	271
all_values[0]	auto[1]	auto[1]	76168	1			T1	344		T2	328		T3	268
all_values[1]	auto[0]	auto[0]	105667	1			T1	367		T2	332		T3	254
all_values[1]	auto[0]	auto[1]	72587	1			T1	367		T2	326		T3	253
all_values[1]	auto[1]	auto[0]	107465	1			T1	306		T2	355		T3	264
all_values[1]	auto[1]	auto[1]	73276	1			T1	305		T2	352		T3	264
all_values[2]	auto[0]	auto[0]	106278	1			T1	350		T2	345		T3	296
all_values[2]	auto[0]	auto[1]	71995	1			T1	347		T2	328		T3	273
all_values[2]	auto[1]	auto[0]	107802	1			T1	326		T2	357		T3	237
all_values[2]	auto[1]	auto[1]	72920	1			T1	322		T2	335		T3	229
all_values[3]	auto[0]	auto[0]	106519	1			T1	348		T2	355		T3	252
all_values[3]	auto[0]	auto[1]	72198	1			T1	318		T2	351		T3	246
all_values[3]	auto[1]	auto[0]	108166	1			T1	347		T2	331		T3	271
all_values[3]	auto[1]	auto[1]	72112	1			T1	332		T2	328		T3	266