Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	358995	1			T1	1345		T2	1365		T3	1035
all_pins[1]	358995	1			T1	1345		T2	1365		T3	1035
all_pins[2]	358995	1			T1	1345		T2	1365		T3	1035
all_pins[3]	358995	1			T1	1345		T2	1365		T3	1035

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1141504	1			T1	4077		T2	4117		T3	3113
values[0x1]	294476	1			T1	1303		T2	1343		T3	1027
transitions[0x0=>0x1]	194370	1			T1	843		T2	853		T3	670
transitions[0x1=>0x0]	194642	1			T1	844		T2	853		T3	670

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	282827	1			T1	1001		T2	1037		T3	767
all_pins[0]	values[0x1]	76168	1			T1	344		T2	328		T3	268
all_pins[0]	transitions[0x0=>0x1]	75477	1			T1	343		T2	328		T3	268
all_pins[0]	transitions[0x1=>0x0]	71693	1			T1	332		T2	328		T3	266
all_pins[1]	values[0x0]	285719	1			T1	1040		T2	1013		T3	771
all_pins[1]	values[0x1]	73276	1			T1	305		T2	352		T3	264
all_pins[1]	transitions[0x0=>0x1]	39949	1			T1	152		T2	194		T3	135
all_pins[1]	transitions[0x1=>0x0]	42841	1			T1	191		T2	170		T3	139
all_pins[2]	values[0x0]	286075	1			T1	1023		T2	1030		T3	806
all_pins[2]	values[0x1]	72920	1			T1	322		T2	335		T3	229
all_pins[2]	transitions[0x0=>0x1]	39744	1			T1	179		T2	167		T3	118
all_pins[2]	transitions[0x1=>0x0]	40100	1			T1	162		T2	184		T3	153
all_pins[3]	values[0x0]	286883	1			T1	1013		T2	1037		T3	769
all_pins[3]	values[0x1]	72112	1			T1	332		T2	328		T3	266
all_pins[3]	transitions[0x0=>0x1]	39200	1			T1	169		T2	164		T3	149
all_pins[3]	transitions[0x1=>0x0]	40008	1			T1	159		T2	171		T3	112