Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	278	1			T183	7		T185	4		T251	4
all_values[1]	278	1			T183	7		T185	4		T251	4
all_values[2]	278	1			T183	7		T185	4		T251	4
all_values[3]	278	1			T183	7		T185	4		T251	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

619

1

T183

15

T185

12

T251

10

auto[1]

493

1

T183

13

T185

4

T251

6

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

405

1

T183

6

T185

3

T251

8

auto[1]

707

1

T183

22

T185

13

T251

8

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

637

1

T183

13

T185

8

T251

11

auto[1]

475

1

T183

15

T185

8

T251

5

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	24	0	24	100.00
Automatically Generated Cross Bins	24	0	24	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

58

1

T183

1

T185

1

T252

2

all_values[0]

auto[0]

auto[0]

auto[1]

27

1

T183

2

T185

1

T251

2

all_values[0]

auto[0]

auto[1]

auto[0]

36

1

T183

2

T260

1

T360

1

all_values[0]

auto[0]

auto[1]

auto[1]

30

1

T361

2

T360

2

T362

1

all_values[0]

auto[1]

auto[0]

auto[1]

65

1

T183

1

T185

2

T251

2

all_values[0]

auto[1]

auto[1]

auto[1]

62

1

T183

1

T361

2

T260

1

all_values[1]

auto[0]

auto[0]

auto[0]

64

1

T251

1

T361

1

T260

2

all_values[1]

auto[0]

auto[0]

auto[1]

27

1

T183

2

T185

1

T361

2

all_values[1]

auto[0]

auto[1]

auto[0]

59

1

T183

1

T251

3

T252

2

all_values[1]

auto[0]

auto[1]

auto[1]

18

1

T185

1

T363

1

T364

2

all_values[1]

auto[1]

auto[0]

auto[1]

60

1

T183

3

T185

2

T252

1

all_values[1]

auto[1]

auto[1]

auto[1]

50

1

T183

1

T252

1

T361

1

all_values[2]

auto[0]

auto[0]

auto[0]

54

1

T183

2

T185

1

T251

1

all_values[2]

auto[0]

auto[0]

auto[1]

35

1

T185

1

T252

1

T260

1

all_values[2]

auto[0]

auto[1]

auto[0]

37

1

T185

1

T251

2

T361

3

all_values[2]

auto[0]

auto[1]

auto[1]

34

1

T183

1

T365

2

T362

1

all_values[2]

auto[1]

auto[0]

auto[1]

63

1

T252

1

T260

2

T365

2

all_values[2]

auto[1]

auto[1]

auto[1]

55

1

T183

4

T185

1

T251

1

all_values[3]

auto[0]

auto[0]

auto[0]

60

1

T251

1

T361

3

T365

1

all_values[3]

auto[0]

auto[0]

auto[1]

41

1

T183

2

T185

1

T251

1

all_values[3]

auto[0]

auto[1]

auto[0]

37

1

T252

2

T260

1

T365

1

all_values[3]

auto[0]

auto[1]

auto[1]

20

1

T360

1

T366

1

T367

1

all_values[3]

auto[1]

auto[0]

auto[1]

65

1

T183

2

T185

2

T251

2

all_values[3]

auto[1]

auto[1]

auto[1]

55

1

T183

3

T185

1

T252

1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal