Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	98819	1			T1	975		T2	1431		T10	445
accum_cnt_1000	234818	1			T1	887		T2	1457		T10	345
accum_cnt_100	26444	1			T1	61		T2	78		T10	16
accum_cnt_50	79976	1			T1	37		T2	64		T3	762
accum_cnt_10	174759	1			T1	1017		T2	22		T3	794
accum_cnt_0	398713	1			T1	1011		T2	1029		T3	1548

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	265394	1			T1	1009		T2	1027		T3	776
class_index[0x1]	265394	1			T1	1009		T2	1027		T3	776
class_index[0x2]	265394	1			T1	1009		T2	1027		T3	776
class_index[0x3]	265394	1			T1	1009		T2	1027		T3	776

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	25773	1			T2	504		T5	268		T29	478
class_index[0x0]	accum_cnt_1000	60585	1			T2	466		T24	8		T5	1177
class_index[0x0]	accum_cnt_100	6361	1			T2	26		T20	3		T48	10
class_index[0x0]	accum_cnt_50	15503	1			T2	23		T20	16		T48	13
class_index[0x0]	accum_cnt_10	51999	1			T1	1		T2	6		T3	776
class_index[0x0]	accum_cnt_0	92468	1			T1	1008		T2	2		T10	1112
class_index[0x1]	accum_cnt_2000	28386	1			T1	474		T2	514		T5	86
class_index[0x1]	accum_cnt_1000	66945	1			T1	480		T2	434		T28	31
class_index[0x1]	accum_cnt_100	6760	1			T1	30		T2	23		T28	26
class_index[0x1]	accum_cnt_50	15107	1			T1	20		T2	20		T28	21
class_index[0x1]	accum_cnt_10	38206	1			T1	5		T2	8		T3	3
class_index[0x1]	accum_cnt_0	98580	1			T2	1		T3	773		T10	1111
class_index[0x2]	accum_cnt_2000	26208	1			T1	501		T5	180		T6	247
class_index[0x2]	accum_cnt_1000	55192	1			T1	407		T28	48		T5	701
class_index[0x2]	accum_cnt_100	5919	1			T1	31		T28	19		T5	56
class_index[0x2]	accum_cnt_50	24803	1			T1	17		T3	762		T28	17
class_index[0x2]	accum_cnt_10	44279	1			T1	5		T2	3		T3	12
class_index[0x2]	accum_cnt_0	99614	1			T2	1024		T3	2		T10	1111
class_index[0x3]	accum_cnt_2000	18452	1			T2	413		T10	445		T17	130
class_index[0x3]	accum_cnt_1000	52096	1			T2	557		T10	345		T16	523
class_index[0x3]	accum_cnt_100	7404	1			T2	29		T10	16		T16	161
class_index[0x3]	accum_cnt_50	24563	1			T2	21		T10	27		T16	116
class_index[0x3]	accum_cnt_10	40275	1			T1	1006		T2	5		T3	3
class_index[0x3]	accum_cnt_0	108051	1			T1	3		T2	2		T3	773