Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	14267	1			T17	865		T49	1		T50	73
alert[0x1]	3217	1			T10	38		T17	191		T6	1
alert[0x2]	4131	1			T3	15		T17	422		T98	7
alert[0x3]	4609	1			T3	4		T10	850		T17	1048
alert[0x4]	4222	1			T17	50		T5	29		T82	43
alert[0x5]	2666	1			T3	46		T5	73		T82	15
alert[0x6]	11393	1			T3	79		T17	138		T71	3
alert[0x7]	7515	1			T3	153		T17	416		T6	1
alert[0x8]	10889	1			T3	27		T17	68		T71	1
alert[0x9]	7388	1			T3	498		T17	97		T5	44
alert[0xa]	3265	1			T17	110		T14	1		T29	6
alert[0xb]	13315	1			T10	1		T17	36		T5	560
alert[0xc]	5859	1			T6	31		T51	17		T96	3
alert[0xd]	3207	1			T3	129		T10	15		T96	1
alert[0xe]	8575	1			T3	1808		T29	28		T82	30
alert[0xf]	9430	1			T6	1		T29	30		T83	2
alert[0x10]	13089	1			T6	158		T82	265		T81	58
alert[0x11]	3672	1			T3	64		T10	269		T5	1048
alert[0x12]	6457	1			T17	24		T5	15		T14	1
alert[0x13]	7889	1			T11	1		T17	1614		T29	7
alert[0x14]	9371	1			T3	3039		T17	195		T24	1
alert[0x15]	7933	1			T3	12		T106	1		T36	1
alert[0x16]	4556	1			T3	25		T82	15		T51	3
alert[0x17]	4382	1			T10	194		T17	40		T51	89
alert[0x18]	9821	1			T3	9		T17	5223		T5	436
alert[0x19]	4315	1			T3	123		T14	1		T50	53
alert[0x1a]	4802	1			T10	585		T15	1		T29	5
alert[0x1b]	4125	1			T17	170		T82	936		T256	1
alert[0x1c]	6689	1			T10	26		T24	1		T50	21
alert[0x1d]	3304	1			T3	241		T5	43		T6	2
alert[0x1e]	14199	1			T17	27		T51	598		T36	5
alert[0x1f]	4084	1			T3	140		T17	65		T13	1
alert[0x20]	3067	1			T3	43		T17	47		T82	122
alert[0x21]	7693	1			T3	130		T6	7		T82	173
alert[0x22]	5281	1			T3	602		T10	51		T11	1
alert[0x23]	8365	1			T10	24		T17	492		T82	25
alert[0x24]	9664	1			T12	1		T17	607		T51	97
alert[0x25]	5628	1			T17	181		T15	1		T29	313
alert[0x26]	7963	1			T3	49		T10	23		T17	562
alert[0x27]	4490	1			T3	332		T14	1		T6	19
alert[0x28]	8102	1			T82	1		T106	1		T254	34
alert[0x29]	3578	1			T3	289		T17	85		T29	7
alert[0x2a]	5365	1			T5	82		T6	8		T71	4
alert[0x2b]	5624	1			T3	1477		T29	43		T82	14
alert[0x2c]	13014	1			T3	44		T17	406		T5	12
alert[0x2d]	9881	1			T14	1		T36	1		T256	1
alert[0x2e]	7850	1			T3	23		T12	1		T14	1
alert[0x2f]	8818	1			T82	10		T33	2		T254	88
alert[0x30]	5678	1			T51	26		T106	1		T96	6
alert[0x31]	11246	1			T10	172		T12	1		T14	2
alert[0x32]	3962	1			T17	313		T29	51		T82	64
alert[0x33]	12661	1			T10	1		T17	568		T51	232
alert[0x34]	10010	1			T50	29		T96	3		T98	4
alert[0x35]	6321	1			T3	78		T82	23		T36	209
alert[0x36]	4284	1			T3	68		T6	6		T15	1
alert[0x37]	10018	1			T10	22		T5	1520		T6	7
alert[0x38]	10280	1			T3	1425		T12	1		T17	378
alert[0x39]	8085	1			T96	1		T293	1		T254	1
alert[0x3a]	12674	1			T24	2		T5	30		T14	2
alert[0x3b]	11675	1			T3	47		T5	16		T106	1
alert[0x3c]	6509	1			T10	55		T6	1		T29	3
alert[0x3d]	2089	1			T82	18		T51	108		T106	1
alert[0x3e]	7040	1			T17	561		T5	103		T50	1
alert[0x3f]	3750	1			T3	336		T10	20		T17	36
alert[0x40]	3540	1			T6	8		T82	8		T96	2

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	49472	1			T3	12		T11	2		T12	1
class_i[0x1]	83977	1			T3	11338		T12	3		T14	8
class_i[0x2]	125639	1			T3	5		T5	4112		T6	4
class_i[0x3]	207753	1			T10	2346		T17	15050		T24	3

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

466133

1

T3

11355

T10

2346

T17

15050

alert_ping_fail

708

1

T11

2

T12

4

T13

1

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	14259	1			T17	865		T49	1		T50	73
alert_integrity_fail	alert[0x1]	3207	1			T10	38		T17	191		T6	1
alert_integrity_fail	alert[0x2]	4124	1			T3	15		T17	422		T98	7
alert_integrity_fail	alert[0x3]	4601	1			T3	4		T10	850		T17	1048
alert_integrity_fail	alert[0x4]	4210	1			T17	50		T5	29		T82	43
alert_integrity_fail	alert[0x5]	2655	1			T3	46		T5	73		T82	15
alert_integrity_fail	alert[0x6]	11379	1			T3	79		T17	138		T71	3
alert_integrity_fail	alert[0x7]	7509	1			T3	153		T17	416		T6	1
alert_integrity_fail	alert[0x8]	10885	1			T3	27		T17	68		T71	1
alert_integrity_fail	alert[0x9]	7377	1			T3	498		T17	97		T5	44
alert_integrity_fail	alert[0xa]	3251	1			T17	110		T29	6		T86	7
alert_integrity_fail	alert[0xb]	13306	1			T10	1		T17	36		T5	560
alert_integrity_fail	alert[0xc]	5852	1			T6	31		T51	17		T96	3
alert_integrity_fail	alert[0xd]	3197	1			T3	129		T10	15		T96	1
alert_integrity_fail	alert[0xe]	8564	1			T3	1808		T29	28		T82	30
alert_integrity_fail	alert[0xf]	9419	1			T6	1		T29	30		T83	2
alert_integrity_fail	alert[0x10]	13077	1			T6	158		T82	265		T81	58
alert_integrity_fail	alert[0x11]	3664	1			T3	64		T10	269		T5	1048
alert_integrity_fail	alert[0x12]	6445	1			T17	24		T5	15		T82	7
alert_integrity_fail	alert[0x13]	7873	1			T17	1614		T29	7		T82	59
alert_integrity_fail	alert[0x14]	9354	1			T3	3039		T17	195		T24	1
alert_integrity_fail	alert[0x15]	7919	1			T3	12		T36	1		T100	4
alert_integrity_fail	alert[0x16]	4541	1			T3	25		T82	15		T51	3
alert_integrity_fail	alert[0x17]	4371	1			T10	194		T17	40		T51	89
alert_integrity_fail	alert[0x18]	9814	1			T3	9		T17	5223		T5	436
alert_integrity_fail	alert[0x19]	4304	1			T3	123		T50	53		T82	22
alert_integrity_fail	alert[0x1a]	4790	1			T10	585		T29	5		T82	10
alert_integrity_fail	alert[0x1b]	4115	1			T17	170		T82	936		T254	24
alert_integrity_fail	alert[0x1c]	6679	1			T10	26		T24	1		T50	21
alert_integrity_fail	alert[0x1d]	3293	1			T3	241		T5	43		T6	2
alert_integrity_fail	alert[0x1e]	14191	1			T17	27		T51	598		T36	5
alert_integrity_fail	alert[0x1f]	4066	1			T3	140		T17	65		T6	4
alert_integrity_fail	alert[0x20]	3058	1			T3	43		T17	47		T82	122
alert_integrity_fail	alert[0x21]	7689	1			T3	130		T6	7		T82	173
alert_integrity_fail	alert[0x22]	5264	1			T3	602		T10	51		T17	15
alert_integrity_fail	alert[0x23]	8358	1			T10	24		T17	492		T82	25
alert_integrity_fail	alert[0x24]	9656	1			T17	607		T51	97		T36	32
alert_integrity_fail	alert[0x25]	5613	1			T17	181		T29	313		T51	11
alert_integrity_fail	alert[0x26]	7946	1			T3	49		T10	23		T17	562
alert_integrity_fail	alert[0x27]	4476	1			T3	332		T6	19		T50	7
alert_integrity_fail	alert[0x28]	8090	1			T82	1		T254	34		T100	9
alert_integrity_fail	alert[0x29]	3566	1			T3	289		T17	85		T29	7
alert_integrity_fail	alert[0x2a]	5354	1			T5	82		T6	8		T71	4
alert_integrity_fail	alert[0x2b]	5614	1			T3	1477		T29	43		T82	14
alert_integrity_fail	alert[0x2c]	12997	1			T3	44		T17	406		T5	12
alert_integrity_fail	alert[0x2d]	9870	1			T36	1		T56	4		T80	4
alert_integrity_fail	alert[0x2e]	7838	1			T3	23		T6	5		T71	4
alert_integrity_fail	alert[0x2f]	8807	1			T82	10		T33	2		T254	88
alert_integrity_fail	alert[0x30]	5666	1			T51	26		T96	6		T36	428
alert_integrity_fail	alert[0x31]	11232	1			T10	172		T82	112		T51	9
alert_integrity_fail	alert[0x32]	3952	1			T17	313		T29	51		T82	64
alert_integrity_fail	alert[0x33]	12646	1			T10	1		T17	568		T51	232
alert_integrity_fail	alert[0x34]	9999	1			T50	29		T96	3		T98	4
alert_integrity_fail	alert[0x35]	6316	1			T3	78		T82	23		T36	209
alert_integrity_fail	alert[0x36]	4272	1			T3	68		T6	6		T82	20
alert_integrity_fail	alert[0x37]	10006	1			T10	22		T5	1520		T6	7
alert_integrity_fail	alert[0x38]	10267	1			T3	1425		T17	378		T49	4
alert_integrity_fail	alert[0x39]	8072	1			T96	1		T254	1		T81	562
alert_integrity_fail	alert[0x3a]	12665	1			T24	2		T5	30		T82	685
alert_integrity_fail	alert[0x3b]	11663	1			T3	47		T5	16		T36	24
alert_integrity_fail	alert[0x3c]	6502	1			T10	55		T6	1		T29	3
alert_integrity_fail	alert[0x3d]	2077	1			T82	18		T51	108		T36	19
alert_integrity_fail	alert[0x3e]	7032	1			T17	561		T5	103		T50	1
alert_integrity_fail	alert[0x3f]	3742	1			T3	336		T10	20		T17	36
alert_integrity_fail	alert[0x40]	3537	1			T6	8		T82	8		T96	2
alert_ping_fail	alert[0x0]	8	1			T314	2		T315	1		T316	2
alert_ping_fail	alert[0x1]	10	1			T293	1		T314	1		T317	1
alert_ping_fail	alert[0x2]	7	1			T318	1		T319	1		T320	1
alert_ping_fail	alert[0x3]	8	1			T256	1		T321	1		T322	2
alert_ping_fail	alert[0x4]	12	1			T323	1		T324	1		T325	1
alert_ping_fail	alert[0x5]	11	1			T106	1		T326	1		T321	2
alert_ping_fail	alert[0x6]	14	1			T327	1		T328	1		T318	1
alert_ping_fail	alert[0x7]	6	1			T329	1		T330	1		T331	1
alert_ping_fail	alert[0x8]	4	1			T332	1		T333	1		T334	2
alert_ping_fail	alert[0x9]	11	1			T335	1		T336	1		T318	1
alert_ping_fail	alert[0xa]	14	1			T14	1		T323	1		T337	1
alert_ping_fail	alert[0xb]	9	1			T256	1		T293	1		T321	1
alert_ping_fail	alert[0xc]	7	1			T338	1		T324	1		T315	1
alert_ping_fail	alert[0xd]	10	1			T318	1		T325	1		T339	1
alert_ping_fail	alert[0xe]	11	1			T106	1		T324	1		T340	1
alert_ping_fail	alert[0xf]	11	1			T256	1		T323	1		T328	1
alert_ping_fail	alert[0x10]	12	1			T327	1		T318	1		T314	2
alert_ping_fail	alert[0x11]	8	1			T106	1		T324	1		T317	1
alert_ping_fail	alert[0x12]	12	1			T14	1		T256	1		T323	1
alert_ping_fail	alert[0x13]	16	1			T11	1		T327	1		T301	1
alert_ping_fail	alert[0x14]	17	1			T106	1		T85	1		T256	1
alert_ping_fail	alert[0x15]	14	1			T106	1		T312	1		T340	1
alert_ping_fail	alert[0x16]	15	1			T106	2		T323	2		T328	1
alert_ping_fail	alert[0x17]	11	1			T327	1		T335	1		T314	1
alert_ping_fail	alert[0x18]	7	1			T341	1		T319	1		T342	1
alert_ping_fail	alert[0x19]	11	1			T14	1		T256	1		T321	1
alert_ping_fail	alert[0x1a]	12	1			T15	1		T106	1		T328	1
alert_ping_fail	alert[0x1b]	10	1			T256	1		T323	1		T327	1
alert_ping_fail	alert[0x1c]	10	1			T328	1		T318	1		T314	1
alert_ping_fail	alert[0x1d]	11	1			T301	1		T329	1		T340	2
alert_ping_fail	alert[0x1e]	8	1			T338	2		T324	1		T341	1
alert_ping_fail	alert[0x1f]	18	1			T13	1		T106	1		T325	1
alert_ping_fail	alert[0x20]	9	1			T338	1		T314	1		T343	1
alert_ping_fail	alert[0x21]	4	1			T106	1		T314	1		T344	1
alert_ping_fail	alert[0x22]	17	1			T11	1		T326	1		T329	1
alert_ping_fail	alert[0x23]	7	1			T106	1		T341	1		T319	1
alert_ping_fail	alert[0x24]	8	1			T12	1		T106	1		T328	1
alert_ping_fail	alert[0x25]	15	1			T15	1		T323	2		T338	1
alert_ping_fail	alert[0x26]	17	1			T14	2		T323	1		T327	1
alert_ping_fail	alert[0x27]	14	1			T14	1		T256	3		T327	1
alert_ping_fail	alert[0x28]	12	1			T106	1		T249	1		T324	2
alert_ping_fail	alert[0x29]	12	1			T256	2		T338	1		T318	1
alert_ping_fail	alert[0x2a]	11	1			T343	1		T321	1		T339	1
alert_ping_fail	alert[0x2b]	10	1			T313	1		T338	1		T314	1
alert_ping_fail	alert[0x2c]	17	1			T312	1		T250	2		T314	1
alert_ping_fail	alert[0x2d]	11	1			T14	1		T256	1		T335	1
alert_ping_fail	alert[0x2e]	12	1			T12	1		T14	1		T256	1
alert_ping_fail	alert[0x2f]	11	1			T315	2		T321	1		T317	1
alert_ping_fail	alert[0x30]	12	1			T106	1		T338	1		T318	1
alert_ping_fail	alert[0x31]	14	1			T12	1		T14	2		T15	1
alert_ping_fail	alert[0x32]	10	1			T314	2		T317	1		T345	1
alert_ping_fail	alert[0x33]	15	1			T327	1		T328	1		T318	2
alert_ping_fail	alert[0x34]	11	1			T338	1		T314	1		T329	2
alert_ping_fail	alert[0x35]	5	1			T328	1		T320	1		T346	2
alert_ping_fail	alert[0x36]	12	1			T15	1		T106	1		T323	2
alert_ping_fail	alert[0x37]	12	1			T293	1		T325	1		T339	1
alert_ping_fail	alert[0x38]	13	1			T12	1		T327	1		T335	1
alert_ping_fail	alert[0x39]	13	1			T293	1		T323	1		T338	1
alert_ping_fail	alert[0x3a]	9	1			T14	2		T256	1		T338	1
alert_ping_fail	alert[0x3b]	12	1			T106	1		T329	1		T324	1
alert_ping_fail	alert[0x3c]	7	1			T314	1		T341	1		T320	2
alert_ping_fail	alert[0x3d]	12	1			T106	1		T318	1		T329	1
alert_ping_fail	alert[0x3e]	8	1			T338	1		T318	1		T339	1
alert_ping_fail	alert[0x3f]	8	1			T338	1		T314	1		T324	1
alert_ping_fail	alert[0x40]	3	1			T318	1		T324	1		T334	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	49271	1			T3	12		T24	1		T6	119
alert_integrity_fail	class_i[0x1]	83804	1			T3	11338		T6	3		T71	7
alert_integrity_fail	class_i[0x2]	125454	1			T3	5		T5	4112		T6	4
alert_integrity_fail	class_i[0x3]	207604	1			T10	2346		T17	15050		T24	3
alert_ping_fail	class_i[0x0]	201	1			T11	2		T12	1		T13	1
alert_ping_fail	class_i[0x1]	173	1			T12	3		T14	8		T106	11
alert_ping_fail	class_i[0x2]	185	1			T15	4		T327	1		T328	10
alert_ping_fail	class_i[0x3]	149	1			T14	2		T106	3		T293	1