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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.24 99.99 98.73 97.09 100.00 100.00 99.38 99.52


Total test records in report: 829
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T196 /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.2724897670 Aug 02 05:39:01 PM PDT 24 Aug 02 05:39:05 PM PDT 24 90680621 ps
T768 /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.1373090795 Aug 02 05:39:28 PM PDT 24 Aug 02 05:39:34 PM PDT 24 34611357 ps
T769 /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.1310520748 Aug 02 05:39:19 PM PDT 24 Aug 02 05:39:28 PM PDT 24 81781813 ps
T194 /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.3760526207 Aug 02 05:38:44 PM PDT 24 Aug 02 05:39:26 PM PDT 24 1126855578 ps
T770 /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.2383338391 Aug 02 05:38:55 PM PDT 24 Aug 02 05:39:08 PM PDT 24 331001550 ps
T771 /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.455173137 Aug 02 05:38:58 PM PDT 24 Aug 02 05:39:03 PM PDT 24 309048958 ps
T772 /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.3511425402 Aug 02 05:39:16 PM PDT 24 Aug 02 05:39:33 PM PDT 24 2330929437 ps
T773 /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.208457714 Aug 02 05:39:26 PM PDT 24 Aug 02 05:39:27 PM PDT 24 10808438 ps
T175 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.2692548195 Aug 02 05:39:27 PM PDT 24 Aug 02 05:49:37 PM PDT 24 32895045404 ps
T774 /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.3282892910 Aug 02 05:39:28 PM PDT 24 Aug 02 05:39:34 PM PDT 24 142424521 ps
T775 /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.1898592025 Aug 02 05:38:53 PM PDT 24 Aug 02 05:39:14 PM PDT 24 268605888 ps
T174 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.148916650 Aug 02 05:39:01 PM PDT 24 Aug 02 05:58:08 PM PDT 24 59464939882 ps
T172 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.3552092362 Aug 02 05:39:08 PM PDT 24 Aug 02 05:41:42 PM PDT 24 2145238994 ps
T776 /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.1260365620 Aug 02 05:39:16 PM PDT 24 Aug 02 05:39:24 PM PDT 24 54070150 ps
T777 /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.3957289540 Aug 02 05:39:02 PM PDT 24 Aug 02 05:39:18 PM PDT 24 2172195000 ps
T193 /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.3734932807 Aug 02 05:38:57 PM PDT 24 Aug 02 05:39:44 PM PDT 24 1312013495 ps
T778 /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.2023121131 Aug 02 05:39:27 PM PDT 24 Aug 02 05:39:32 PM PDT 24 220198803 ps
T779 /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.3951458826 Aug 02 05:39:10 PM PDT 24 Aug 02 05:39:12 PM PDT 24 6451414 ps
T166 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.2539374995 Aug 02 05:39:16 PM PDT 24 Aug 02 05:40:49 PM PDT 24 1473418237 ps
T780 /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.1782084731 Aug 02 05:39:08 PM PDT 24 Aug 02 05:39:18 PM PDT 24 1374634260 ps
T781 /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.3985182946 Aug 02 05:38:59 PM PDT 24 Aug 02 05:39:00 PM PDT 24 11639933 ps
T782 /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.883995394 Aug 02 05:39:00 PM PDT 24 Aug 02 05:39:08 PM PDT 24 201938221 ps
T783 /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.638887520 Aug 02 05:38:42 PM PDT 24 Aug 02 05:38:54 PM PDT 24 375604391 ps
T784 /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.2887065177 Aug 02 05:39:26 PM PDT 24 Aug 02 05:39:50 PM PDT 24 443518946 ps
T785 /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.2251555866 Aug 02 05:38:53 PM PDT 24 Aug 02 05:38:59 PM PDT 24 326587066 ps
T786 /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.312721231 Aug 02 05:39:27 PM PDT 24 Aug 02 05:39:29 PM PDT 24 9437660 ps
T787 /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.4114892935 Aug 02 05:38:40 PM PDT 24 Aug 02 05:38:44 PM PDT 24 150264202 ps
T788 /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.2149706477 Aug 02 05:39:41 PM PDT 24 Aug 02 05:39:42 PM PDT 24 10771015 ps
T789 /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.3431610403 Aug 02 05:38:54 PM PDT 24 Aug 02 05:45:41 PM PDT 24 11422863708 ps
T790 /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.2015295460 Aug 02 05:39:19 PM PDT 24 Aug 02 05:39:26 PM PDT 24 54126757 ps
T791 /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.725938335 Aug 02 05:39:10 PM PDT 24 Aug 02 05:39:17 PM PDT 24 61184067 ps
T792 /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.3702106298 Aug 02 05:38:44 PM PDT 24 Aug 02 05:40:56 PM PDT 24 32402885982 ps
T202 /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.4083105290 Aug 02 05:39:26 PM PDT 24 Aug 02 05:39:28 PM PDT 24 22801748 ps
T190 /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.4188006489 Aug 02 05:39:17 PM PDT 24 Aug 02 05:39:41 PM PDT 24 192025368 ps
T368 /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.3915340932 Aug 02 05:38:36 PM PDT 24 Aug 02 05:55:20 PM PDT 24 49523671571 ps
T793 /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.4096077330 Aug 02 05:39:28 PM PDT 24 Aug 02 05:39:30 PM PDT 24 11743602 ps
T164 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.3211258231 Aug 02 05:39:17 PM PDT 24 Aug 02 05:42:30 PM PDT 24 3263520822 ps
T794 /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.3840747899 Aug 02 05:38:54 PM PDT 24 Aug 02 05:42:24 PM PDT 24 3889795581 ps
T795 /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.3267991722 Aug 02 05:39:10 PM PDT 24 Aug 02 05:39:28 PM PDT 24 1798218414 ps
T796 /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.3421833048 Aug 02 05:39:17 PM PDT 24 Aug 02 05:39:27 PM PDT 24 61496088 ps
T186 /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.2275536810 Aug 02 05:39:01 PM PDT 24 Aug 02 05:39:05 PM PDT 24 46406545 ps
T797 /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.23601179 Aug 02 05:39:27 PM PDT 24 Aug 02 05:39:38 PM PDT 24 87351358 ps
T798 /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.2119279474 Aug 02 05:39:07 PM PDT 24 Aug 02 05:39:15 PM PDT 24 357169437 ps
T799 /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.793897752 Aug 02 05:39:25 PM PDT 24 Aug 02 05:39:27 PM PDT 24 19624156 ps
T800 /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.2400001587 Aug 02 05:38:59 PM PDT 24 Aug 02 05:39:04 PM PDT 24 54698127 ps
T801 /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.794922006 Aug 02 05:38:59 PM PDT 24 Aug 02 05:39:01 PM PDT 24 19214191 ps
T157 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.809178499 Aug 02 05:39:08 PM PDT 24 Aug 02 05:49:22 PM PDT 24 4609594246 ps
T802 /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.1282381949 Aug 02 05:38:56 PM PDT 24 Aug 02 05:39:05 PM PDT 24 338655735 ps
T803 /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.2440326532 Aug 02 05:39:18 PM PDT 24 Aug 02 05:39:20 PM PDT 24 21649765 ps
T804 /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.3737048012 Aug 02 05:39:28 PM PDT 24 Aug 02 05:39:35 PM PDT 24 304074250 ps
T805 /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.1454189098 Aug 02 05:39:09 PM PDT 24 Aug 02 05:39:31 PM PDT 24 352736011 ps
T806 /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.4219750149 Aug 02 05:39:07 PM PDT 24 Aug 02 05:39:30 PM PDT 24 172406250 ps
T807 /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.1179439385 Aug 02 05:39:08 PM PDT 24 Aug 02 05:39:23 PM PDT 24 207311273 ps
T808 /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.3630206008 Aug 02 05:38:54 PM PDT 24 Aug 02 05:39:03 PM PDT 24 251044012 ps
T809 /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.1953754013 Aug 02 05:38:54 PM PDT 24 Aug 02 05:39:00 PM PDT 24 77612178 ps
T179 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.558027316 Aug 02 05:39:16 PM PDT 24 Aug 02 05:47:31 PM PDT 24 42866165502 ps
T810 /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.242939096 Aug 02 05:39:05 PM PDT 24 Aug 02 05:39:26 PM PDT 24 1162190056 ps
T811 /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.3107895567 Aug 02 05:39:00 PM PDT 24 Aug 02 05:39:21 PM PDT 24 890394533 ps
T178 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.1276616565 Aug 02 05:38:53 PM PDT 24 Aug 02 05:42:20 PM PDT 24 1545446868 ps
T812 /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.3864696115 Aug 02 05:39:28 PM PDT 24 Aug 02 05:39:34 PM PDT 24 36974784 ps
T813 /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.4256737793 Aug 02 05:39:44 PM PDT 24 Aug 02 05:39:45 PM PDT 24 19208259 ps
T814 /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.3416157905 Aug 02 05:38:55 PM PDT 24 Aug 02 05:48:07 PM PDT 24 9105907993 ps
T177 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.3289098175 Aug 02 05:38:55 PM PDT 24 Aug 02 05:45:03 PM PDT 24 2525237455 ps
T815 /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.3435987220 Aug 02 05:39:42 PM PDT 24 Aug 02 05:39:43 PM PDT 24 9443122 ps
T816 /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.2607600577 Aug 02 05:38:55 PM PDT 24 Aug 02 05:40:55 PM PDT 24 6746633686 ps
T173 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.3153189412 Aug 02 05:38:53 PM PDT 24 Aug 02 05:41:45 PM PDT 24 4970428369 ps
T817 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.3094361383 Aug 02 05:38:56 PM PDT 24 Aug 02 05:44:22 PM PDT 24 4747995932 ps
T818 /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.1950172390 Aug 02 05:39:27 PM PDT 24 Aug 02 05:39:29 PM PDT 24 21449702 ps
T819 /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.1972742945 Aug 02 05:39:10 PM PDT 24 Aug 02 05:39:11 PM PDT 24 15419186 ps
T820 /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.610372783 Aug 02 05:39:01 PM PDT 24 Aug 02 05:39:10 PM PDT 24 513882708 ps
T821 /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.2271223106 Aug 02 05:39:10 PM PDT 24 Aug 02 05:39:16 PM PDT 24 89532464 ps
T822 /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.2047378135 Aug 02 05:38:59 PM PDT 24 Aug 02 05:39:04 PM PDT 24 32273480 ps
T823 /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.3505895017 Aug 02 05:38:36 PM PDT 24 Aug 02 05:40:50 PM PDT 24 7450898519 ps
T824 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.2727219937 Aug 02 05:38:53 PM PDT 24 Aug 02 05:44:45 PM PDT 24 2204243528 ps
T825 /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.485180054 Aug 02 05:39:21 PM PDT 24 Aug 02 05:39:24 PM PDT 24 31330526 ps
T826 /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.1876035727 Aug 02 05:39:11 PM PDT 24 Aug 02 05:39:19 PM PDT 24 214265743 ps
T827 /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.4214397308 Aug 02 05:38:53 PM PDT 24 Aug 02 05:38:58 PM PDT 24 60292870 ps
T828 /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.3842585562 Aug 02 05:39:18 PM PDT 24 Aug 02 05:39:20 PM PDT 24 9038973 ps
T829 /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.3547572046 Aug 02 05:39:00 PM PDT 24 Aug 02 05:39:06 PM PDT 24 70444367 ps

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.3041965740
Short name T1
Test name
Test status
Simulation time 62107518603 ps
CPU time 1866.13 seconds
Started Aug 02 05:41:04 PM PDT 24
Finished Aug 02 06:12:11 PM PDT 24
Peak memory 281776 kb
Host smart-f3013555-9e10-4f9f-8c55-bedaec42e752
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041965740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.3041965740
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all_with_rand_reset.2457692247
Short name T5
Test name
Test status
Simulation time 32466388174 ps
CPU time 3961.61 seconds
Started Aug 02 05:40:39 PM PDT 24
Finished Aug 02 06:46:42 PM PDT 24
Peak memory 338712 kb
Host smart-912f3884-6563-4c74-9558-a1749eec7d7b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457692247 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.alert_handler_stress_all_with_rand_reset.2457692247
Directory /workspace/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.106377671
Short name T7
Test name
Test status
Simulation time 175502899 ps
CPU time 10.8 seconds
Started Aug 02 05:39:46 PM PDT 24
Finished Aug 02 05:39:57 PM PDT 24
Peak memory 269852 kb
Host smart-895831c6-d760-4a80-81da-a7ca26294de8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=106377671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.106377671
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.276989849
Short name T181
Test name
Test status
Simulation time 4928924837 ps
CPU time 85.72 seconds
Started Aug 02 05:39:07 PM PDT 24
Finished Aug 02 05:40:33 PM PDT 24
Peak memory 239088 kb
Host smart-5d4b3270-b05c-4af7-af0a-db8a51aaa222
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=276989849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.276989849
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.3106803998
Short name T17
Test name
Test status
Simulation time 85627420506 ps
CPU time 1806.98 seconds
Started Aug 02 05:39:46 PM PDT 24
Finished Aug 02 06:09:53 PM PDT 24
Peak memory 289400 kb
Host smart-183be79a-99f0-470a-b2aa-a34efa4e2954
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106803998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.3106803998
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.4279027832
Short name T29
Test name
Test status
Simulation time 57069244033 ps
CPU time 4574.94 seconds
Started Aug 02 05:39:45 PM PDT 24
Finished Aug 02 06:56:00 PM PDT 24
Peak memory 305352 kb
Host smart-df42d29c-3d05-4bfa-a275-fd7de795b819
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279027832 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.4279027832
Directory /workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.1100269033
Short name T30
Test name
Test status
Simulation time 84392162973 ps
CPU time 2962.99 seconds
Started Aug 02 05:40:58 PM PDT 24
Finished Aug 02 06:30:22 PM PDT 24
Peak memory 289132 kb
Host smart-6ca9fa9f-fb66-42b6-9af8-61af1c691cda
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100269033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.1100269033
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.2891556502
Short name T56
Test name
Test status
Simulation time 16509762373 ps
CPU time 1727.27 seconds
Started Aug 02 05:42:26 PM PDT 24
Finished Aug 02 06:11:14 PM PDT 24
Peak memory 289196 kb
Host smart-097f7572-8ee1-497d-a286-bf8f486e1439
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891556502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.2891556502
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.1835413096
Short name T253
Test name
Test status
Simulation time 413617502 ps
CPU time 7.74 seconds
Started Aug 02 05:39:55 PM PDT 24
Finished Aug 02 05:40:03 PM PDT 24
Peak memory 248392 kb
Host smart-4c047a10-a13e-470a-b865-5219c2e20e4a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1835413096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.1835413096
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.488707594
Short name T145
Test name
Test status
Simulation time 14016419231 ps
CPU time 1080.03 seconds
Started Aug 02 05:38:55 PM PDT 24
Finished Aug 02 05:56:55 PM PDT 24
Peak memory 265688 kb
Host smart-b4ddff4d-7821-4935-87bc-0f6a6c4099cb
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488707594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.488707594
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.1606309315
Short name T13
Test name
Test status
Simulation time 151131363115 ps
CPU time 1972.62 seconds
Started Aug 02 05:40:02 PM PDT 24
Finished Aug 02 06:12:55 PM PDT 24
Peak memory 284848 kb
Host smart-65b04352-e4b3-4219-94f7-2558f9991630
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606309315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.1606309315
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.1587610068
Short name T158
Test name
Test status
Simulation time 1536473223 ps
CPU time 176.14 seconds
Started Aug 02 05:39:28 PM PDT 24
Finished Aug 02 05:42:24 PM PDT 24
Peak memory 272888 kb
Host smart-a4bc458c-f0eb-4675-9833-85870c17be80
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1587610068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.1587610068
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.4030957806
Short name T111
Test name
Test status
Simulation time 79752712592 ps
CPU time 1832.16 seconds
Started Aug 02 05:40:18 PM PDT 24
Finished Aug 02 06:10:50 PM PDT 24
Peak memory 288996 kb
Host smart-09908d7e-5c05-4275-a7a0-24ac4b0c289e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030957806 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.4030957806
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.231683257
Short name T31
Test name
Test status
Simulation time 174765815611 ps
CPU time 1412.94 seconds
Started Aug 02 05:40:47 PM PDT 24
Finished Aug 02 06:04:20 PM PDT 24
Peak memory 272336 kb
Host smart-94736c12-70be-481e-b76b-9cceecca5dde
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231683257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.231683257
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.2279255504
Short name T149
Test name
Test status
Simulation time 6698964226 ps
CPU time 388.59 seconds
Started Aug 02 05:39:18 PM PDT 24
Finished Aug 02 05:45:47 PM PDT 24
Peak memory 273668 kb
Host smart-56cf9f91-f66f-4dcc-a2cc-57ef913951dc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2279255504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.2279255504
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all_with_rand_reset.1070103927
Short name T121
Test name
Test status
Simulation time 60654804060 ps
CPU time 4203.26 seconds
Started Aug 02 05:39:46 PM PDT 24
Finished Aug 02 06:49:50 PM PDT 24
Peak memory 297492 kb
Host smart-67e0df65-c068-4303-b8ce-3fbed0477a08
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070103927 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.alert_handler_stress_all_with_rand_reset.1070103927
Directory /workspace/3.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.73949921
Short name T3
Test name
Test status
Simulation time 104824388473 ps
CPU time 1904.26 seconds
Started Aug 02 05:42:33 PM PDT 24
Finished Aug 02 06:14:17 PM PDT 24
Peak memory 272968 kb
Host smart-299af394-98db-435e-af0a-0828e87e8e04
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73949921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.73949921
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.1465331070
Short name T250
Test name
Test status
Simulation time 77363852617 ps
CPU time 2470.13 seconds
Started Aug 02 05:40:12 PM PDT 24
Finished Aug 02 06:21:22 PM PDT 24
Peak memory 287076 kb
Host smart-32c490fa-bd2e-4bab-9c74-a56a434cb2c2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465331070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.1465331070
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.1978531016
Short name T155
Test name
Test status
Simulation time 4189059124 ps
CPU time 640.35 seconds
Started Aug 02 05:39:19 PM PDT 24
Finished Aug 02 05:50:00 PM PDT 24
Peak memory 273696 kb
Host smart-37a7f469-1315-4f39-a186-aa835ce14557
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978531016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.1978531016
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.3449717807
Short name T365
Test name
Test status
Simulation time 14625775 ps
CPU time 1.53 seconds
Started Aug 02 05:39:28 PM PDT 24
Finished Aug 02 05:39:30 PM PDT 24
Peak memory 236912 kb
Host smart-2cca4f07-69ce-4ab8-a109-5c6f23ff7442
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3449717807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.3449717807
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.148916650
Short name T174
Test name
Test status
Simulation time 59464939882 ps
CPU time 1147.38 seconds
Started Aug 02 05:39:01 PM PDT 24
Finished Aug 02 05:58:08 PM PDT 24
Peak memory 265664 kb
Host smart-e49b27a3-1813-4dd0-b2ee-41c5becfe132
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148916650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.148916650
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.3538438526
Short name T106
Test name
Test status
Simulation time 18947513200 ps
CPU time 403.6 seconds
Started Aug 02 05:40:43 PM PDT 24
Finished Aug 02 05:47:26 PM PDT 24
Peak memory 254956 kb
Host smart-654c4d3d-fdc5-4408-ad57-7881b0fe4229
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538438526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.3538438526
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.2822908957
Short name T6
Test name
Test status
Simulation time 83139985814 ps
CPU time 2112.37 seconds
Started Aug 02 05:40:54 PM PDT 24
Finished Aug 02 06:16:07 PM PDT 24
Peak memory 289052 kb
Host smart-0305c21c-fc42-421c-94be-9a35fddaca68
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822908957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.2822908957
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.2834405776
Short name T313
Test name
Test status
Simulation time 35649046583 ps
CPU time 2116.15 seconds
Started Aug 02 05:41:16 PM PDT 24
Finished Aug 02 06:16:32 PM PDT 24
Peak memory 282740 kb
Host smart-cd28d35a-34c2-4075-a30f-8a8c80811571
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834405776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.2834405776
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.4238111304
Short name T318
Test name
Test status
Simulation time 25207959220 ps
CPU time 501.88 seconds
Started Aug 02 05:42:31 PM PDT 24
Finished Aug 02 05:50:53 PM PDT 24
Peak memory 256320 kb
Host smart-60c56be6-58f4-4bb6-b6fd-38d2466bd346
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238111304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.4238111304
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.1190156033
Short name T144
Test name
Test status
Simulation time 17743527207 ps
CPU time 549.68 seconds
Started Aug 02 05:39:16 PM PDT 24
Finished Aug 02 05:48:26 PM PDT 24
Peak memory 265660 kb
Host smart-2e193a8f-da8a-411e-af20-fca895546537
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190156033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.1190156033
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.736840187
Short name T86
Test name
Test status
Simulation time 1967255312 ps
CPU time 33.89 seconds
Started Aug 02 05:40:42 PM PDT 24
Finished Aug 02 05:41:16 PM PDT 24
Peak memory 248324 kb
Host smart-97916278-be5c-4bac-9ce0-98e2d3dc9fb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73684
0187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.736840187
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.4060031689
Short name T341
Test name
Test status
Simulation time 22670303545 ps
CPU time 508.04 seconds
Started Aug 02 05:40:10 PM PDT 24
Finished Aug 02 05:48:38 PM PDT 24
Peak memory 248304 kb
Host smart-acfaa6eb-c7bc-46b0-b763-31d9a1fbb4c5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060031689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.4060031689
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.3356697289
Short name T290
Test name
Test status
Simulation time 16696765709 ps
CPU time 1269.9 seconds
Started Aug 02 05:41:38 PM PDT 24
Finished Aug 02 06:02:49 PM PDT 24
Peak memory 281204 kb
Host smart-474710dd-4d28-4389-bbdd-c226342f90d8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356697289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.3356697289
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.1976147398
Short name T160
Test name
Test status
Simulation time 4024289438 ps
CPU time 146.38 seconds
Started Aug 02 05:38:59 PM PDT 24
Finished Aug 02 05:41:26 PM PDT 24
Peak memory 265612 kb
Host smart-3bbb5938-7d19-4c07-aed4-6d16b4dca392
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1976147398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.1976147398
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.3153189412
Short name T173
Test name
Test status
Simulation time 4970428369 ps
CPU time 171.7 seconds
Started Aug 02 05:38:53 PM PDT 24
Finished Aug 02 05:41:45 PM PDT 24
Peak memory 265676 kb
Host smart-3dd923ab-9cac-4f31-8801-2735f8f26d8e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3153189412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.3153189412
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.4125577512
Short name T608
Test name
Test status
Simulation time 9073481235 ps
CPU time 386.41 seconds
Started Aug 02 05:40:27 PM PDT 24
Finished Aug 02 05:46:54 PM PDT 24
Peak memory 248276 kb
Host smart-abb4823c-cac3-46c6-89ab-da067903d924
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125577512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.4125577512
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.2443665482
Short name T150
Test name
Test status
Simulation time 90442834458 ps
CPU time 1253.71 seconds
Started Aug 02 05:39:22 PM PDT 24
Finished Aug 02 06:00:16 PM PDT 24
Peak memory 265872 kb
Host smart-26c4eaa7-79d1-4cba-a661-046f5290e056
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443665482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.2443665482
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.1819887023
Short name T136
Test name
Test status
Simulation time 22058683894 ps
CPU time 1887.93 seconds
Started Aug 02 05:41:26 PM PDT 24
Finished Aug 02 06:12:55 PM PDT 24
Peak memory 289412 kb
Host smart-016d1a20-5469-4efc-a815-0c0bdc4f4555
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819887023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.1819887023
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.1474005864
Short name T352
Test name
Test status
Simulation time 86040770754 ps
CPU time 2786.55 seconds
Started Aug 02 05:41:14 PM PDT 24
Finished Aug 02 06:27:41 PM PDT 24
Peak memory 288632 kb
Host smart-b059f616-32aa-42c4-bfa8-2d927aae8b77
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474005864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.1474005864
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.2963717502
Short name T263
Test name
Test status
Simulation time 123735109307 ps
CPU time 2836.58 seconds
Started Aug 02 05:42:41 PM PDT 24
Finished Aug 02 06:29:58 PM PDT 24
Peak memory 288856 kb
Host smart-920022c6-6da3-4d6c-afa3-6750ac04d13c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963717502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.2963717502
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.4128167046
Short name T367
Test name
Test status
Simulation time 14188709 ps
CPU time 1.42 seconds
Started Aug 02 05:38:58 PM PDT 24
Finished Aug 02 05:39:00 PM PDT 24
Peak memory 236812 kb
Host smart-c5502003-1948-4aa5-87f9-6c064f603fa0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4128167046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.4128167046
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.1788005041
Short name T339
Test name
Test status
Simulation time 12276207749 ps
CPU time 517.54 seconds
Started Aug 02 05:41:05 PM PDT 24
Finished Aug 02 05:49:43 PM PDT 24
Peak memory 247256 kb
Host smart-adde1f27-74e1-433e-936f-f1d2ae2aa326
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788005041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.1788005041
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.2783651001
Short name T287
Test name
Test status
Simulation time 114536293318 ps
CPU time 4359.75 seconds
Started Aug 02 05:41:47 PM PDT 24
Finished Aug 02 06:54:28 PM PDT 24
Peak memory 322220 kb
Host smart-75c5dc6f-84af-4908-8d2a-c613d4754373
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783651001 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.2783651001
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.4116728159
Short name T96
Test name
Test status
Simulation time 866949389 ps
CPU time 40.81 seconds
Started Aug 02 05:39:59 PM PDT 24
Finished Aug 02 05:40:40 PM PDT 24
Peak memory 256532 kb
Host smart-72967e46-01e2-48d1-b197-4f3b1e55b7af
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116728159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.4116728159
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.1797365159
Short name T326
Test name
Test status
Simulation time 55804904745 ps
CPU time 2841.97 seconds
Started Aug 02 05:42:42 PM PDT 24
Finished Aug 02 06:30:04 PM PDT 24
Peak memory 289116 kb
Host smart-b5944bd7-a08b-4429-913b-677d3dbf7b98
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797365159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.1797365159
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.1033537368
Short name T10
Test name
Test status
Simulation time 85303445222 ps
CPU time 2449.3 seconds
Started Aug 02 05:40:10 PM PDT 24
Finished Aug 02 06:20:59 PM PDT 24
Peak memory 284176 kb
Host smart-1d728739-1538-44ef-baf1-65b031550591
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033537368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.1033537368
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.1850864975
Short name T156
Test name
Test status
Simulation time 3350763589 ps
CPU time 293.88 seconds
Started Aug 02 05:39:12 PM PDT 24
Finished Aug 02 05:44:06 PM PDT 24
Peak memory 265616 kb
Host smart-4ea220c9-0391-4f52-b6b9-823d31669c5a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1850864975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.1850864975
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.118032781
Short name T333
Test name
Test status
Simulation time 13029139219 ps
CPU time 137.25 seconds
Started Aug 02 05:40:27 PM PDT 24
Finished Aug 02 05:42:45 PM PDT 24
Peak memory 247376 kb
Host smart-5f6513fd-c34d-499f-8e23-df8c39e3da25
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118032781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.118032781
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.212619387
Short name T60
Test name
Test status
Simulation time 111325165205 ps
CPU time 2594.6 seconds
Started Aug 02 05:41:26 PM PDT 24
Finished Aug 02 06:24:41 PM PDT 24
Peak memory 305024 kb
Host smart-497b5aea-f336-45c7-a5b7-6ed50a8e3925
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212619387 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.212619387
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.3625244864
Short name T165
Test name
Test status
Simulation time 4316909361 ps
CPU time 695.56 seconds
Started Aug 02 05:38:59 PM PDT 24
Finished Aug 02 05:50:35 PM PDT 24
Peak memory 266628 kb
Host smart-0a1df02c-2633-4b48-860d-291c241d3824
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625244864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.3625244864
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.724523725
Short name T128
Test name
Test status
Simulation time 151595127080 ps
CPU time 2184.12 seconds
Started Aug 02 05:40:08 PM PDT 24
Finished Aug 02 06:16:32 PM PDT 24
Peak memory 288736 kb
Host smart-e030850e-2483-4bd6-82ef-43c318eac986
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724523725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_han
dler_stress_all.724523725
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.2219293910
Short name T320
Test name
Test status
Simulation time 15104558572 ps
CPU time 605.15 seconds
Started Aug 02 05:40:41 PM PDT 24
Finished Aug 02 05:50:47 PM PDT 24
Peak memory 247244 kb
Host smart-72631691-3027-4de1-ba89-bf39c5639494
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219293910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.2219293910
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.3251719096
Short name T51
Test name
Test status
Simulation time 38790423462 ps
CPU time 2460.72 seconds
Started Aug 02 05:41:41 PM PDT 24
Finished Aug 02 06:22:42 PM PDT 24
Peak memory 280696 kb
Host smart-3d680423-7f7a-4fb4-b8e9-d4e55cf5452a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251719096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.3251719096
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.494410879
Short name T197
Test name
Test status
Simulation time 61304169 ps
CPU time 2.74 seconds
Started Aug 02 05:39:07 PM PDT 24
Finished Aug 02 05:39:10 PM PDT 24
Peak memory 237740 kb
Host smart-4dcd0bc2-03e6-41ff-855c-1bde9572051e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=494410879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.494410879
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.2516738080
Short name T153
Test name
Test status
Simulation time 1644166947 ps
CPU time 102.69 seconds
Started Aug 02 05:38:54 PM PDT 24
Finished Aug 02 05:40:37 PM PDT 24
Peak memory 265484 kb
Host smart-278d75e6-7db4-4b6f-9870-7f6533cb75b9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2516738080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.2516738080
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.809178499
Short name T157
Test name
Test status
Simulation time 4609594246 ps
CPU time 613.94 seconds
Started Aug 02 05:39:08 PM PDT 24
Finished Aug 02 05:49:22 PM PDT 24
Peak memory 265692 kb
Host smart-a10dc255-46f8-4eac-bc85-4c64384eae8e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809178499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.809178499
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.4028665258
Short name T225
Test name
Test status
Simulation time 35999793 ps
CPU time 3.42 seconds
Started Aug 02 05:39:37 PM PDT 24
Finished Aug 02 05:39:41 PM PDT 24
Peak memory 248664 kb
Host smart-73024168-1ab2-41ff-abba-073b7aad7ccc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4028665258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.4028665258
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.1477375063
Short name T228
Test name
Test status
Simulation time 14935720 ps
CPU time 2.38 seconds
Started Aug 02 05:39:34 PM PDT 24
Finished Aug 02 05:39:36 PM PDT 24
Peak memory 248572 kb
Host smart-1e6f0f14-0f5c-44d4-bf4e-4bee3b7b8821
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1477375063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.1477375063
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.928699445
Short name T230
Test name
Test status
Simulation time 41291971 ps
CPU time 2.45 seconds
Started Aug 02 05:40:08 PM PDT 24
Finished Aug 02 05:40:11 PM PDT 24
Peak memory 248704 kb
Host smart-fef759fc-b826-4123-9db3-9c8f16a0e229
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=928699445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.928699445
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.324389255
Short name T240
Test name
Test status
Simulation time 576948497 ps
CPU time 3.86 seconds
Started Aug 02 05:40:39 PM PDT 24
Finished Aug 02 05:40:43 PM PDT 24
Peak memory 248656 kb
Host smart-ec8ee392-0fcc-4dc1-a1c2-df50c2eb8189
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=324389255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.324389255
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.4248013219
Short name T100
Test name
Test status
Simulation time 457645870500 ps
CPU time 3510.95 seconds
Started Aug 02 05:39:37 PM PDT 24
Finished Aug 02 06:38:09 PM PDT 24
Peak memory 297056 kb
Host smart-a3e859c7-b49d-45fc-86f9-38b2e33d1ac8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248013219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.4248013219
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.900460786
Short name T702
Test name
Test status
Simulation time 45824905683 ps
CPU time 2129.76 seconds
Started Aug 02 05:40:18 PM PDT 24
Finished Aug 02 06:15:48 PM PDT 24
Peak memory 286440 kb
Host smart-43384ded-b799-4050-af18-3de36e49b3f2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900460786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_han
dler_stress_all.900460786
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.889741506
Short name T272
Test name
Test status
Simulation time 268850190 ps
CPU time 29.47 seconds
Started Aug 02 05:40:57 PM PDT 24
Finished Aug 02 05:41:26 PM PDT 24
Peak memory 248956 kb
Host smart-0fcd75d9-0806-4887-8089-b19cbe2da863
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88974
1506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.889741506
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.3616982319
Short name T131
Test name
Test status
Simulation time 76782014128 ps
CPU time 395.56 seconds
Started Aug 02 05:40:57 PM PDT 24
Finished Aug 02 05:47:33 PM PDT 24
Peak memory 256632 kb
Host smart-c82b0041-0b4a-4069-bcdb-a279a3db78d1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616982319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.3616982319
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all_with_rand_reset.1838022929
Short name T258
Test name
Test status
Simulation time 317612222977 ps
CPU time 3768.88 seconds
Started Aug 02 05:40:55 PM PDT 24
Finished Aug 02 06:43:45 PM PDT 24
Peak memory 305916 kb
Host smart-a3ab6eb5-417f-416e-9003-5c3d2e12ba23
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838022929 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.alert_handler_stress_all_with_rand_reset.1838022929
Directory /workspace/25.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.1216074744
Short name T286
Test name
Test status
Simulation time 3490207891 ps
CPU time 60.34 seconds
Started Aug 02 05:41:05 PM PDT 24
Finished Aug 02 05:42:05 PM PDT 24
Peak memory 248152 kb
Host smart-28c6af94-da02-4d5c-8ee2-7d857cdcbe9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12160
74744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.1216074744
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.2172867711
Short name T355
Test name
Test status
Simulation time 84342477416 ps
CPU time 1656.76 seconds
Started Aug 02 05:41:34 PM PDT 24
Finished Aug 02 06:09:11 PM PDT 24
Peak memory 289284 kb
Host smart-21feddc4-a5ef-41ae-b2fe-20040874ddb0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172867711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.2172867711
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.4246511283
Short name T280
Test name
Test status
Simulation time 571696392 ps
CPU time 28.03 seconds
Started Aug 02 05:41:39 PM PDT 24
Finished Aug 02 05:42:07 PM PDT 24
Peak memory 255608 kb
Host smart-3a41287f-ac40-484f-8324-c6d8feb2b218
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42465
11283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.4246511283
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.2651115563
Short name T351
Test name
Test status
Simulation time 62659705036 ps
CPU time 1289.45 seconds
Started Aug 02 05:42:32 PM PDT 24
Finished Aug 02 06:04:01 PM PDT 24
Peak memory 281168 kb
Host smart-5c1bab71-95bc-4d35-aca4-95840b932123
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651115563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.2651115563
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.4063828143
Short name T337
Test name
Test status
Simulation time 121914740138 ps
CPU time 2144.59 seconds
Started Aug 02 05:40:01 PM PDT 24
Finished Aug 02 06:15:46 PM PDT 24
Peak memory 289416 kb
Host smart-0236de6c-fe99-4280-b5b5-557f8e03be85
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063828143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.4063828143
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.2124017203
Short name T146
Test name
Test status
Simulation time 839051824 ps
CPU time 105.34 seconds
Started Aug 02 05:38:59 PM PDT 24
Finished Aug 02 05:40:45 PM PDT 24
Peak memory 265524 kb
Host smart-5c46c680-6c9e-47fd-a761-dafe237fdba3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2124017203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.2124017203
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.1988233451
Short name T191
Test name
Test status
Simulation time 4928913965 ps
CPU time 79.07 seconds
Started Aug 02 05:38:58 PM PDT 24
Finished Aug 02 05:40:17 PM PDT 24
Peak memory 240824 kb
Host smart-8dda8afc-0be2-4e18-9f23-0649d4272f69
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1988233451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.1988233451
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.2599238017
Short name T252
Test name
Test status
Simulation time 17546704 ps
CPU time 1.32 seconds
Started Aug 02 05:38:43 PM PDT 24
Finished Aug 02 05:38:44 PM PDT 24
Peak memory 235720 kb
Host smart-14aa0cf9-0a18-484d-bc9f-08493d7957fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2599238017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.2599238017
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.4017240231
Short name T277
Test name
Test status
Simulation time 691781782 ps
CPU time 45.81 seconds
Started Aug 02 05:40:10 PM PDT 24
Finished Aug 02 05:40:56 PM PDT 24
Peak memory 255800 kb
Host smart-92c9f8a6-4e1c-44d8-ab7b-ecb70473f52d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40172
40231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.4017240231
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.2587245760
Short name T267
Test name
Test status
Simulation time 40225270439 ps
CPU time 1731.7 seconds
Started Aug 02 05:40:09 PM PDT 24
Finished Aug 02 06:09:01 PM PDT 24
Peak memory 288712 kb
Host smart-5e3e384b-e9fe-439b-88e9-fd8bdbc6ffd3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587245760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.2587245760
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.2977069284
Short name T329
Test name
Test status
Simulation time 28130250509 ps
CPU time 239.49 seconds
Started Aug 02 05:40:10 PM PDT 24
Finished Aug 02 05:44:09 PM PDT 24
Peak memory 248408 kb
Host smart-2df9d8b6-e8b8-435c-9018-86c9b2c1b458
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977069284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.2977069284
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.2426639882
Short name T566
Test name
Test status
Simulation time 14877544666 ps
CPU time 1646.43 seconds
Started Aug 02 05:40:15 PM PDT 24
Finished Aug 02 06:07:42 PM PDT 24
Peak memory 289044 kb
Host smart-36c5fc9e-8672-45d9-b9f4-9d79a34e4c91
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426639882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.2426639882
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.3142172760
Short name T307
Test name
Test status
Simulation time 46212746150 ps
CPU time 2788.52 seconds
Started Aug 02 05:40:17 PM PDT 24
Finished Aug 02 06:26:46 PM PDT 24
Peak memory 304848 kb
Host smart-c51a385f-54e1-4bab-bce2-01efea5e5afc
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142172760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.3142172760
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.2378390101
Short name T310
Test name
Test status
Simulation time 521375450 ps
CPU time 23.93 seconds
Started Aug 02 05:40:16 PM PDT 24
Finished Aug 02 05:40:40 PM PDT 24
Peak memory 256432 kb
Host smart-42e45dc1-50e6-4ef6-997a-57977bfdddad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23783
90101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.2378390101
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.1770522953
Short name T289
Test name
Test status
Simulation time 4073455892 ps
CPU time 62.33 seconds
Started Aug 02 05:39:45 PM PDT 24
Finished Aug 02 05:40:47 PM PDT 24
Peak memory 248124 kb
Host smart-68e7fc0f-945e-4cca-a881-985dc840acb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17705
22953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.1770522953
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.3723744425
Short name T282
Test name
Test status
Simulation time 2503888474 ps
CPU time 39.69 seconds
Started Aug 02 05:41:06 PM PDT 24
Finished Aug 02 05:41:46 PM PDT 24
Peak memory 247968 kb
Host smart-42ea058e-4cad-44e0-9ad9-d8b479ef0004
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37237
44425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.3723744425
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.3025620349
Short name T284
Test name
Test status
Simulation time 2262041428 ps
CPU time 45.4 seconds
Started Aug 02 05:41:21 PM PDT 24
Finished Aug 02 05:42:06 PM PDT 24
Peak memory 249752 kb
Host smart-8d9a32f7-69fa-4a83-a11e-0bdb4c9e4cc6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025620349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.3025620349
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.2154925859
Short name T271
Test name
Test status
Simulation time 30717633220 ps
CPU time 1758.05 seconds
Started Aug 02 05:41:38 PM PDT 24
Finished Aug 02 06:10:56 PM PDT 24
Peak memory 285676 kb
Host smart-d03c81d8-67c9-408f-8a73-b199a0b2bd67
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154925859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.2154925859
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.2679184162
Short name T75
Test name
Test status
Simulation time 14855139772 ps
CPU time 925.21 seconds
Started Aug 02 05:42:03 PM PDT 24
Finished Aug 02 05:57:28 PM PDT 24
Peak memory 266032 kb
Host smart-fb67b2b6-d290-4637-a082-e857ce6a2e97
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679184162 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.2679184162
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.2293558191
Short name T273
Test name
Test status
Simulation time 537608049 ps
CPU time 40.71 seconds
Started Aug 02 05:40:01 PM PDT 24
Finished Aug 02 05:40:42 PM PDT 24
Peak memory 247928 kb
Host smart-b3032e33-c9d3-4417-91df-c221b8060252
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22935
58191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.2293558191
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.217402620
Short name T262
Test name
Test status
Simulation time 61924610337 ps
CPU time 6157.73 seconds
Started Aug 02 05:39:51 PM PDT 24
Finished Aug 02 07:22:30 PM PDT 24
Peak memory 338668 kb
Host smart-f02c31ec-a684-42b1-b786-a0f383a447dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217402620 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.217402620
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.3552092362
Short name T172
Test name
Test status
Simulation time 2145238994 ps
CPU time 154.13 seconds
Started Aug 02 05:39:08 PM PDT 24
Finished Aug 02 05:41:42 PM PDT 24
Peak memory 265492 kb
Host smart-2b8741ca-2bf4-47ac-9042-0de13254af38
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3552092362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.3552092362
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.3734932807
Short name T193
Test name
Test status
Simulation time 1312013495 ps
CPU time 47.27 seconds
Started Aug 02 05:38:57 PM PDT 24
Finished Aug 02 05:39:44 PM PDT 24
Peak memory 240616 kb
Host smart-301d4f68-788b-49a4-a388-a80d0e3491eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3734932807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.3734932807
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.3659183594
Short name T187
Test name
Test status
Simulation time 14818893817 ps
CPU time 78.52 seconds
Started Aug 02 05:38:56 PM PDT 24
Finished Aug 02 05:40:14 PM PDT 24
Peak memory 240800 kb
Host smart-58c5ffc7-73d3-456f-b943-5cc3418592b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3659183594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.3659183594
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.2916716011
Short name T199
Test name
Test status
Simulation time 1037847923 ps
CPU time 41.4 seconds
Started Aug 02 05:38:44 PM PDT 24
Finished Aug 02 05:39:25 PM PDT 24
Peak memory 248848 kb
Host smart-68342539-829d-43b9-ba2b-297de184b336
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2916716011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.2916716011
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.500593641
Short name T192
Test name
Test status
Simulation time 1161150250 ps
CPU time 35.9 seconds
Started Aug 02 05:38:46 PM PDT 24
Finished Aug 02 05:39:21 PM PDT 24
Peak memory 240656 kb
Host smart-743cb902-f92f-46f8-a7a3-5eaa8b22afa0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=500593641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.500593641
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.2275536810
Short name T186
Test name
Test status
Simulation time 46406545 ps
CPU time 3.22 seconds
Started Aug 02 05:39:01 PM PDT 24
Finished Aug 02 05:39:05 PM PDT 24
Peak memory 238024 kb
Host smart-7ad505fa-6138-4732-9747-23c45afe617b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2275536810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.2275536810
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.3760526207
Short name T194
Test name
Test status
Simulation time 1126855578 ps
CPU time 41.86 seconds
Started Aug 02 05:38:44 PM PDT 24
Finished Aug 02 05:39:26 PM PDT 24
Peak memory 240676 kb
Host smart-485d4b67-52c3-4a94-ba8a-e1ab2c71f460
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3760526207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.3760526207
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.784613800
Short name T154
Test name
Test status
Simulation time 7192453839 ps
CPU time 218.75 seconds
Started Aug 02 05:38:44 PM PDT 24
Finished Aug 02 05:42:23 PM PDT 24
Peak memory 265680 kb
Host smart-cb72a1a9-f197-4833-b7ed-d3aa65ff2a56
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=784613800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_error
s.784613800
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.3540317449
Short name T189
Test name
Test status
Simulation time 172706918 ps
CPU time 8.27 seconds
Started Aug 02 05:39:15 PM PDT 24
Finished Aug 02 05:39:24 PM PDT 24
Peak memory 238764 kb
Host smart-3e810b0d-1ada-4e40-aaad-a263603271a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3540317449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.3540317449
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.2973815047
Short name T200
Test name
Test status
Simulation time 564710134 ps
CPU time 34.76 seconds
Started Aug 02 05:39:19 PM PDT 24
Finished Aug 02 05:39:53 PM PDT 24
Peak memory 248872 kb
Host smart-5d62bf63-f078-43c2-acc7-6674cae20dba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2973815047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.2973815047
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.3779281479
Short name T170
Test name
Test status
Simulation time 4455646667 ps
CPU time 183.99 seconds
Started Aug 02 05:39:28 PM PDT 24
Finished Aug 02 05:42:32 PM PDT 24
Peak memory 257488 kb
Host smart-a19a1a39-8bf6-4948-8890-90a16739263f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3779281479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.3779281479
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.3014970906
Short name T182
Test name
Test status
Simulation time 1042193126 ps
CPU time 58.64 seconds
Started Aug 02 05:39:25 PM PDT 24
Finished Aug 02 05:40:24 PM PDT 24
Peak memory 240680 kb
Host smart-fcb65f52-edcf-4e92-80ed-e08775c3b6cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3014970906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.3014970906
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.1297547728
Short name T180
Test name
Test status
Simulation time 1831529307 ps
CPU time 67.04 seconds
Started Aug 02 05:38:43 PM PDT 24
Finished Aug 02 05:39:50 PM PDT 24
Peak memory 240584 kb
Host smart-085bf4d6-895f-4dd6-a032-7357fa7f3239
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1297547728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.1297547728
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.849439273
Short name T188
Test name
Test status
Simulation time 59840170 ps
CPU time 3.86 seconds
Started Aug 02 05:38:58 PM PDT 24
Finished Aug 02 05:39:02 PM PDT 24
Peak memory 237724 kb
Host smart-fbd04cb1-2cee-48b1-87ac-612145937c74
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=849439273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.849439273
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.1975472012
Short name T18
Test name
Test status
Simulation time 501638926 ps
CPU time 5.68 seconds
Started Aug 02 05:39:35 PM PDT 24
Finished Aug 02 05:39:41 PM PDT 24
Peak memory 254552 kb
Host smart-e46f3500-4da6-41e0-b891-6559b29b10c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19754
72012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.1975472012
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.4188006489
Short name T190
Test name
Test status
Simulation time 192025368 ps
CPU time 23.32 seconds
Started Aug 02 05:39:17 PM PDT 24
Finished Aug 02 05:39:41 PM PDT 24
Peak memory 240624 kb
Host smart-1171b140-4770-4509-9ea6-38d0ab16d3c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4188006489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.4188006489
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.4083105290
Short name T202
Test name
Test status
Simulation time 22801748 ps
CPU time 2.38 seconds
Started Aug 02 05:39:26 PM PDT 24
Finished Aug 02 05:39:28 PM PDT 24
Peak memory 237524 kb
Host smart-09921e59-1564-4af5-9d8d-30a318253364
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4083105290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.4083105290
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.2724897670
Short name T196
Test name
Test status
Simulation time 90680621 ps
CPU time 3.86 seconds
Started Aug 02 05:39:01 PM PDT 24
Finished Aug 02 05:39:05 PM PDT 24
Peak memory 237960 kb
Host smart-ce67c491-e92c-48de-a421-8b323e9583c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2724897670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.2724897670
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.2734952102
Short name T195
Test name
Test status
Simulation time 46595506 ps
CPU time 3.03 seconds
Started Aug 02 05:39:00 PM PDT 24
Finished Aug 02 05:39:03 PM PDT 24
Peak memory 237684 kb
Host smart-1af595d5-edbd-4dbc-ad32-348c06d811be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2734952102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.2734952102
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.3702106298
Short name T792
Test name
Test status
Simulation time 32402885982 ps
CPU time 131.88 seconds
Started Aug 02 05:38:44 PM PDT 24
Finished Aug 02 05:40:56 PM PDT 24
Peak memory 240808 kb
Host smart-98a13c1e-34ea-4c85-8d2e-c1d840f75bd6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3702106298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.3702106298
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.2329271430
Short name T718
Test name
Test status
Simulation time 15496736779 ps
CPU time 213.78 seconds
Started Aug 02 05:38:44 PM PDT 24
Finished Aug 02 05:42:18 PM PDT 24
Peak memory 240780 kb
Host smart-1d4382e7-a06a-45fc-b115-85842fc853f7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2329271430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.2329271430
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.1252252770
Short name T184
Test name
Test status
Simulation time 195992681 ps
CPU time 4.69 seconds
Started Aug 02 05:38:44 PM PDT 24
Finished Aug 02 05:38:49 PM PDT 24
Peak memory 240628 kb
Host smart-2f32b716-92c8-4303-8b10-c6db1e6a9f1f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1252252770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.1252252770
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.1742494299
Short name T766
Test name
Test status
Simulation time 757723851 ps
CPU time 13.84 seconds
Started Aug 02 05:38:54 PM PDT 24
Finished Aug 02 05:39:08 PM PDT 24
Peak memory 255932 kb
Host smart-c3d51c34-4214-4e0a-bae4-b9cb0575dc46
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742494299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.1742494299
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.916294754
Short name T739
Test name
Test status
Simulation time 95636718 ps
CPU time 7.93 seconds
Started Aug 02 05:38:44 PM PDT 24
Finished Aug 02 05:38:52 PM PDT 24
Peak memory 240700 kb
Host smart-504919fe-4727-406a-b71e-2eb00371fbd6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=916294754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.916294754
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.3461446940
Short name T728
Test name
Test status
Simulation time 538349677 ps
CPU time 38.6 seconds
Started Aug 02 05:38:54 PM PDT 24
Finished Aug 02 05:39:33 PM PDT 24
Peak memory 245816 kb
Host smart-bd51232c-93b4-4f16-90c1-b18083a9d6af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3461446940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.3461446940
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.3505895017
Short name T823
Test name
Test status
Simulation time 7450898519 ps
CPU time 133.25 seconds
Started Aug 02 05:38:36 PM PDT 24
Finished Aug 02 05:40:50 PM PDT 24
Peak memory 257452 kb
Host smart-f301e5eb-3e1c-43ec-8d09-fb9208115057
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3505895017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.3505895017
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.3915340932
Short name T368
Test name
Test status
Simulation time 49523671571 ps
CPU time 1003.88 seconds
Started Aug 02 05:38:36 PM PDT 24
Finished Aug 02 05:55:20 PM PDT 24
Peak memory 273844 kb
Host smart-7edfe55c-6490-460f-9709-a71b46c1d827
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915340932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.3915340932
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.4114892935
Short name T787
Test name
Test status
Simulation time 150264202 ps
CPU time 3.98 seconds
Started Aug 02 05:38:40 PM PDT 24
Finished Aug 02 05:38:44 PM PDT 24
Peak memory 247764 kb
Host smart-4ebcc1ed-e81f-4f92-9c7e-5caabdeb2e88
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4114892935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.4114892935
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.1325461857
Short name T713
Test name
Test status
Simulation time 9374751500 ps
CPU time 251.88 seconds
Started Aug 02 05:38:46 PM PDT 24
Finished Aug 02 05:42:58 PM PDT 24
Peak memory 240760 kb
Host smart-cda2f074-8988-4f57-ab56-51dd8e19d746
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1325461857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.1325461857
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.3840747899
Short name T794
Test name
Test status
Simulation time 3889795581 ps
CPU time 209.94 seconds
Started Aug 02 05:38:54 PM PDT 24
Finished Aug 02 05:42:24 PM PDT 24
Peak memory 236820 kb
Host smart-c1afb610-fc43-419b-bc55-ee71e3a601b4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3840747899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.3840747899
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.3962382896
Short name T715
Test name
Test status
Simulation time 514244567 ps
CPU time 10.73 seconds
Started Aug 02 05:38:47 PM PDT 24
Finished Aug 02 05:38:58 PM PDT 24
Peak memory 240644 kb
Host smart-02e74ceb-29cf-4f2d-aad6-de7e39b09850
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3962382896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.3962382896
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.1953754013
Short name T809
Test name
Test status
Simulation time 77612178 ps
CPU time 5.74 seconds
Started Aug 02 05:38:54 PM PDT 24
Finished Aug 02 05:39:00 PM PDT 24
Peak memory 240704 kb
Host smart-740859bb-5308-4d89-bf3f-d2a154d8eb97
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953754013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.1953754013
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.3029168635
Short name T726
Test name
Test status
Simulation time 512918964 ps
CPU time 7.83 seconds
Started Aug 02 05:38:45 PM PDT 24
Finished Aug 02 05:38:53 PM PDT 24
Peak memory 240668 kb
Host smart-27e5ade6-5e5e-4b92-b40b-200984c39811
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3029168635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.3029168635
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.3288009022
Short name T722
Test name
Test status
Simulation time 8195571 ps
CPU time 1.39 seconds
Started Aug 02 05:38:43 PM PDT 24
Finished Aug 02 05:38:45 PM PDT 24
Peak memory 236932 kb
Host smart-0632f267-2208-42dd-8482-2d9dbc804f4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3288009022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.3288009022
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.1344534394
Short name T734
Test name
Test status
Simulation time 532673586 ps
CPU time 38.79 seconds
Started Aug 02 05:38:46 PM PDT 24
Finished Aug 02 05:39:25 PM PDT 24
Peak memory 245968 kb
Host smart-7b5a9d04-25af-4799-a0ed-c85ef5f0c60b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1344534394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.1344534394
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.4291077670
Short name T152
Test name
Test status
Simulation time 32852552748 ps
CPU time 663.39 seconds
Started Aug 02 05:38:43 PM PDT 24
Finished Aug 02 05:49:47 PM PDT 24
Peak memory 265788 kb
Host smart-9f1a0144-6347-4fb0-b870-ecd2eb3df14d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291077670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.4291077670
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.2541478260
Short name T711
Test name
Test status
Simulation time 269370897 ps
CPU time 11.72 seconds
Started Aug 02 05:38:54 PM PDT 24
Finished Aug 02 05:39:05 PM PDT 24
Peak memory 248896 kb
Host smart-7d6fc34e-8687-4bcf-a62e-1c2eaf5d821e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2541478260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.2541478260
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.1179439385
Short name T807
Test name
Test status
Simulation time 207311273 ps
CPU time 14.07 seconds
Started Aug 02 05:39:08 PM PDT 24
Finished Aug 02 05:39:23 PM PDT 24
Peak memory 252504 kb
Host smart-c4ff54b4-0e1f-4087-9af2-e771730a4757
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179439385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.1179439385
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.3324790551
Short name T748
Test name
Test status
Simulation time 567429176 ps
CPU time 7.37 seconds
Started Aug 02 05:39:10 PM PDT 24
Finished Aug 02 05:39:17 PM PDT 24
Peak memory 237700 kb
Host smart-892c8961-0e26-4474-835b-5a4f0d294ca1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3324790551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.3324790551
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.3951458826
Short name T779
Test name
Test status
Simulation time 6451414 ps
CPU time 1.48 seconds
Started Aug 02 05:39:10 PM PDT 24
Finished Aug 02 05:39:12 PM PDT 24
Peak memory 237716 kb
Host smart-067ffc68-d50d-417e-ad9c-fe6642c1c8ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3951458826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.3951458826
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.3267991722
Short name T795
Test name
Test status
Simulation time 1798218414 ps
CPU time 18.01 seconds
Started Aug 02 05:39:10 PM PDT 24
Finished Aug 02 05:39:28 PM PDT 24
Peak memory 245924 kb
Host smart-efdc10d7-11db-47ac-8e48-f8f1ed55b4df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3267991722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.3267991722
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.2893050264
Short name T148
Test name
Test status
Simulation time 24728910973 ps
CPU time 530.96 seconds
Started Aug 02 05:38:58 PM PDT 24
Finished Aug 02 05:47:50 PM PDT 24
Peak memory 265684 kb
Host smart-494416c6-d0ca-4348-ac27-e7979181fe0b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893050264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.2893050264
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.568284354
Short name T725
Test name
Test status
Simulation time 1298812163 ps
CPU time 20.55 seconds
Started Aug 02 05:39:01 PM PDT 24
Finished Aug 02 05:39:21 PM PDT 24
Peak memory 248740 kb
Host smart-3813bacf-48cb-4f7c-b2d3-b215a11bce35
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=568284354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.568284354
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.2658560597
Short name T727
Test name
Test status
Simulation time 338517986 ps
CPU time 11.18 seconds
Started Aug 02 05:39:08 PM PDT 24
Finished Aug 02 05:39:20 PM PDT 24
Peak memory 256088 kb
Host smart-a654b8b7-ee8a-423c-91fe-a3e1b46e0928
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658560597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.2658560597
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.3222244518
Short name T207
Test name
Test status
Simulation time 187942235 ps
CPU time 4.89 seconds
Started Aug 02 05:39:12 PM PDT 24
Finished Aug 02 05:39:17 PM PDT 24
Peak memory 237704 kb
Host smart-40079398-2480-480d-ad72-e4c4defc8d97
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3222244518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.3222244518
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.4248901451
Short name T721
Test name
Test status
Simulation time 7019756 ps
CPU time 1.38 seconds
Started Aug 02 05:39:10 PM PDT 24
Finished Aug 02 05:39:11 PM PDT 24
Peak memory 236844 kb
Host smart-806e0fe1-31ae-438d-83c3-9d2867d7c389
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4248901451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.4248901451
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.1454189098
Short name T805
Test name
Test status
Simulation time 352736011 ps
CPU time 22.45 seconds
Started Aug 02 05:39:09 PM PDT 24
Finished Aug 02 05:39:31 PM PDT 24
Peak memory 245904 kb
Host smart-a25dc371-ff6d-47d1-b0b5-238a76c8dd56
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1454189098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.1454189098
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.2853924291
Short name T168
Test name
Test status
Simulation time 9531251808 ps
CPU time 294.37 seconds
Started Aug 02 05:39:09 PM PDT 24
Finished Aug 02 05:44:03 PM PDT 24
Peak memory 269328 kb
Host smart-d9620abf-0ab7-40fa-aeed-294bbfba0cad
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853924291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.2853924291
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.1876035727
Short name T826
Test name
Test status
Simulation time 214265743 ps
CPU time 7.73 seconds
Started Aug 02 05:39:11 PM PDT 24
Finished Aug 02 05:39:19 PM PDT 24
Peak memory 253484 kb
Host smart-a265ca20-928e-403b-9a2a-e7e559e31783
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1876035727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.1876035727
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.242939096
Short name T810
Test name
Test status
Simulation time 1162190056 ps
CPU time 20.82 seconds
Started Aug 02 05:39:05 PM PDT 24
Finished Aug 02 05:39:26 PM PDT 24
Peak memory 240568 kb
Host smart-3148d121-c4f4-4d34-8c9d-2942a59d7624
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=242939096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.242939096
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.3789238441
Short name T738
Test name
Test status
Simulation time 57443855 ps
CPU time 7.6 seconds
Started Aug 02 05:39:12 PM PDT 24
Finished Aug 02 05:39:19 PM PDT 24
Peak memory 253896 kb
Host smart-8b30e265-016b-46b1-9631-4c515c99251d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789238441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.3789238441
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.2658530584
Short name T724
Test name
Test status
Simulation time 20038195 ps
CPU time 3.21 seconds
Started Aug 02 05:39:09 PM PDT 24
Finished Aug 02 05:39:12 PM PDT 24
Peak memory 236792 kb
Host smart-fc14ad62-31a7-4981-ab85-25ce7b85a95b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2658530584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.2658530584
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.1972742945
Short name T819
Test name
Test status
Simulation time 15419186 ps
CPU time 1.35 seconds
Started Aug 02 05:39:10 PM PDT 24
Finished Aug 02 05:39:11 PM PDT 24
Peak memory 237740 kb
Host smart-f088c21e-cf9b-4410-97e5-bb6d085445f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1972742945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.1972742945
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.4219750149
Short name T806
Test name
Test status
Simulation time 172406250 ps
CPU time 23.44 seconds
Started Aug 02 05:39:07 PM PDT 24
Finished Aug 02 05:39:30 PM PDT 24
Peak memory 245868 kb
Host smart-5bd18a14-4b88-4602-9afa-c2cca35f4b82
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4219750149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou
tstanding.4219750149
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.1913606629
Short name T159
Test name
Test status
Simulation time 85882642410 ps
CPU time 1291.59 seconds
Started Aug 02 05:39:09 PM PDT 24
Finished Aug 02 06:00:41 PM PDT 24
Peak memory 265520 kb
Host smart-d993567d-f77f-4802-9ddf-ce5941415900
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913606629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.1913606629
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.1782084731
Short name T780
Test name
Test status
Simulation time 1374634260 ps
CPU time 9.95 seconds
Started Aug 02 05:39:08 PM PDT 24
Finished Aug 02 05:39:18 PM PDT 24
Peak memory 254736 kb
Host smart-0cf33bd2-c22f-4265-afab-f990c79a2889
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1782084731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.1782084731
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.2325029147
Short name T736
Test name
Test status
Simulation time 173364845 ps
CPU time 12.05 seconds
Started Aug 02 05:39:09 PM PDT 24
Finished Aug 02 05:39:21 PM PDT 24
Peak memory 251136 kb
Host smart-928ed8c3-ac39-4ca7-9dca-03e2c60a1249
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325029147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.2325029147
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.2119279474
Short name T798
Test name
Test status
Simulation time 357169437 ps
CPU time 8.32 seconds
Started Aug 02 05:39:07 PM PDT 24
Finished Aug 02 05:39:15 PM PDT 24
Peak memory 237732 kb
Host smart-3f1b8dd5-7070-4063-9a9d-1bbc0e4bdda0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2119279474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.2119279474
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.51682171
Short name T756
Test name
Test status
Simulation time 9427478 ps
CPU time 1.38 seconds
Started Aug 02 05:39:11 PM PDT 24
Finished Aug 02 05:39:12 PM PDT 24
Peak memory 235844 kb
Host smart-84256a55-50bd-43b0-835a-1c4c586dd637
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=51682171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.51682171
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.3484752685
Short name T747
Test name
Test status
Simulation time 178478124 ps
CPU time 24.87 seconds
Started Aug 02 05:39:10 PM PDT 24
Finished Aug 02 05:39:35 PM PDT 24
Peak memory 248704 kb
Host smart-0dbe801e-f239-45b8-a337-9f115658451c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3484752685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.3484752685
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.3883526608
Short name T147
Test name
Test status
Simulation time 6120695698 ps
CPU time 101.1 seconds
Started Aug 02 05:39:08 PM PDT 24
Finished Aug 02 05:40:49 PM PDT 24
Peak memory 265616 kb
Host smart-8a816a74-2b7f-4d53-a59d-d11714ab0bc1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3883526608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.3883526608
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.1323856089
Short name T706
Test name
Test status
Simulation time 860611989 ps
CPU time 9.18 seconds
Started Aug 02 05:39:07 PM PDT 24
Finished Aug 02 05:39:16 PM PDT 24
Peak memory 253792 kb
Host smart-c13b3ba7-2883-4833-b4bc-4e20e855a6de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1323856089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.1323856089
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.2803043829
Short name T742
Test name
Test status
Simulation time 186157826 ps
CPU time 6.28 seconds
Started Aug 02 05:39:17 PM PDT 24
Finished Aug 02 05:39:24 PM PDT 24
Peak memory 244036 kb
Host smart-78c1a164-8254-48e3-b065-cd5a502ebb75
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803043829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.2803043829
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.3245362959
Short name T744
Test name
Test status
Simulation time 33944907 ps
CPU time 4.58 seconds
Started Aug 02 05:39:16 PM PDT 24
Finished Aug 02 05:39:21 PM PDT 24
Peak memory 236820 kb
Host smart-3b7939bb-f2fd-4f55-8bc4-4d25447234e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3245362959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.3245362959
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.2440326532
Short name T803
Test name
Test status
Simulation time 21649765 ps
CPU time 1.41 seconds
Started Aug 02 05:39:18 PM PDT 24
Finished Aug 02 05:39:20 PM PDT 24
Peak memory 236864 kb
Host smart-92df8124-f346-4a0b-b816-7fc4fc82609d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2440326532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.2440326532
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.81105664
Short name T198
Test name
Test status
Simulation time 676578875 ps
CPU time 22.57 seconds
Started Aug 02 05:39:18 PM PDT 24
Finished Aug 02 05:39:41 PM PDT 24
Peak memory 248908 kb
Host smart-90e64126-ab5b-456b-9fc6-8803dd460f3c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=81105664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_outs
tanding.81105664
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.3211258231
Short name T164
Test name
Test status
Simulation time 3263520822 ps
CPU time 193.56 seconds
Started Aug 02 05:39:17 PM PDT 24
Finished Aug 02 05:42:30 PM PDT 24
Peak memory 266476 kb
Host smart-c4032e9b-91ce-406a-96fb-f5d0c35f80e5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3211258231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.3211258231
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.3511425402
Short name T772
Test name
Test status
Simulation time 2330929437 ps
CPU time 17.08 seconds
Started Aug 02 05:39:16 PM PDT 24
Finished Aug 02 05:39:33 PM PDT 24
Peak memory 256984 kb
Host smart-e86acbaf-2995-4170-9bda-26b863008c18
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3511425402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.3511425402
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.1260365620
Short name T776
Test name
Test status
Simulation time 54070150 ps
CPU time 8.34 seconds
Started Aug 02 05:39:16 PM PDT 24
Finished Aug 02 05:39:24 PM PDT 24
Peak memory 252204 kb
Host smart-a27bf514-f84d-4e37-b721-eef7c0b31436
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260365620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.1260365620
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.299743137
Short name T755
Test name
Test status
Simulation time 69863962 ps
CPU time 6.01 seconds
Started Aug 02 05:39:18 PM PDT 24
Finished Aug 02 05:39:24 PM PDT 24
Peak memory 240652 kb
Host smart-9b831bd1-2b3a-4683-970f-6d21e71a402f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=299743137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.299743137
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.3842585562
Short name T828
Test name
Test status
Simulation time 9038973 ps
CPU time 1.59 seconds
Started Aug 02 05:39:18 PM PDT 24
Finished Aug 02 05:39:20 PM PDT 24
Peak memory 237720 kb
Host smart-45c4b31a-04c8-48fd-9aad-9c4ad3c6f0eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3842585562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.3842585562
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.92894458
Short name T762
Test name
Test status
Simulation time 161410333 ps
CPU time 12.85 seconds
Started Aug 02 05:39:17 PM PDT 24
Finished Aug 02 05:39:30 PM PDT 24
Peak memory 245968 kb
Host smart-e6508aba-de71-4d99-b8e4-f3db34bfb32b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=92894458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_outs
tanding.92894458
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.520579959
Short name T169
Test name
Test status
Simulation time 3251364349 ps
CPU time 90.22 seconds
Started Aug 02 05:39:18 PM PDT 24
Finished Aug 02 05:40:48 PM PDT 24
Peak memory 265588 kb
Host smart-a7daf15a-5a49-496c-98e5-9cda31a242f5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=520579959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_erro
rs.520579959
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.1310520748
Short name T769
Test name
Test status
Simulation time 81781813 ps
CPU time 9.25 seconds
Started Aug 02 05:39:19 PM PDT 24
Finished Aug 02 05:39:28 PM PDT 24
Peak memory 248792 kb
Host smart-7cdc6c0f-b967-4cb4-9152-c620307c062e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1310520748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.1310520748
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.485180054
Short name T825
Test name
Test status
Simulation time 31330526 ps
CPU time 2.85 seconds
Started Aug 02 05:39:21 PM PDT 24
Finished Aug 02 05:39:24 PM PDT 24
Peak memory 238000 kb
Host smart-c4aceb1f-15da-41b6-8de4-abfc0ec8e0da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=485180054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.485180054
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.1772749227
Short name T223
Test name
Test status
Simulation time 280353651 ps
CPU time 7.87 seconds
Started Aug 02 05:39:15 PM PDT 24
Finished Aug 02 05:39:23 PM PDT 24
Peak memory 240928 kb
Host smart-2228b30a-8de3-4368-9def-f4dee2b4d5ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772749227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.1772749227
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.393552542
Short name T224
Test name
Test status
Simulation time 780540438 ps
CPU time 8.59 seconds
Started Aug 02 05:39:20 PM PDT 24
Finished Aug 02 05:39:29 PM PDT 24
Peak memory 237736 kb
Host smart-5acffa13-e54b-475d-9832-a71cf9b95011
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=393552542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.393552542
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.4175231543
Short name T183
Test name
Test status
Simulation time 22446960 ps
CPU time 1.49 seconds
Started Aug 02 05:39:18 PM PDT 24
Finished Aug 02 05:39:20 PM PDT 24
Peak memory 236876 kb
Host smart-2041677a-ea5d-456e-bd2e-c28422e4d804
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4175231543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.4175231543
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.1983699141
Short name T201
Test name
Test status
Simulation time 2287354832 ps
CPU time 36.68 seconds
Started Aug 02 05:39:17 PM PDT 24
Finished Aug 02 05:39:54 PM PDT 24
Peak memory 245132 kb
Host smart-5404abba-151d-480d-bbcf-b6eca83e75eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1983699141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.1983699141
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.558027316
Short name T179
Test name
Test status
Simulation time 42866165502 ps
CPU time 494.51 seconds
Started Aug 02 05:39:16 PM PDT 24
Finished Aug 02 05:47:31 PM PDT 24
Peak memory 265792 kb
Host smart-617415fe-3817-43a5-9182-7673a7fc188e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558027316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.558027316
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.2015295460
Short name T790
Test name
Test status
Simulation time 54126757 ps
CPU time 7.25 seconds
Started Aug 02 05:39:19 PM PDT 24
Finished Aug 02 05:39:26 PM PDT 24
Peak memory 248936 kb
Host smart-511bd466-8e2f-41de-936b-c6a131643ed7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2015295460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.2015295460
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.3737048012
Short name T804
Test name
Test status
Simulation time 304074250 ps
CPU time 6.57 seconds
Started Aug 02 05:39:28 PM PDT 24
Finished Aug 02 05:39:35 PM PDT 24
Peak memory 240360 kb
Host smart-f2784a8b-e9de-498a-bcfc-81c84283ecc6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737048012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.3737048012
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.958688857
Short name T765
Test name
Test status
Simulation time 465768359 ps
CPU time 7.95 seconds
Started Aug 02 05:39:26 PM PDT 24
Finished Aug 02 05:39:34 PM PDT 24
Peak memory 237636 kb
Host smart-975849d0-ba13-4af6-b5f6-c19e384dff52
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=958688857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.958688857
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.1514208527
Short name T185
Test name
Test status
Simulation time 7415241 ps
CPU time 1.4 seconds
Started Aug 02 05:39:17 PM PDT 24
Finished Aug 02 05:39:18 PM PDT 24
Peak memory 237724 kb
Host smart-faa2e33d-8f5d-4ce6-8cf7-299459f899fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1514208527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.1514208527
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.23601179
Short name T797
Test name
Test status
Simulation time 87351358 ps
CPU time 10.5 seconds
Started Aug 02 05:39:27 PM PDT 24
Finished Aug 02 05:39:38 PM PDT 24
Peak memory 244988 kb
Host smart-ea72ec39-2515-4a70-9e4a-c85f005e4daa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=23601179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_outs
tanding.23601179
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.2539374995
Short name T166
Test name
Test status
Simulation time 1473418237 ps
CPU time 92.93 seconds
Started Aug 02 05:39:16 PM PDT 24
Finished Aug 02 05:40:49 PM PDT 24
Peak memory 265548 kb
Host smart-9528c983-5800-43cf-ba3f-ed9496467b16
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2539374995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.2539374995
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.3421833048
Short name T796
Test name
Test status
Simulation time 61496088 ps
CPU time 9.98 seconds
Started Aug 02 05:39:17 PM PDT 24
Finished Aug 02 05:39:27 PM PDT 24
Peak memory 248928 kb
Host smart-bad197e3-d5bd-4c1e-acc2-ebb91d5a3adf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3421833048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.3421833048
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.3282892910
Short name T774
Test name
Test status
Simulation time 142424521 ps
CPU time 5.92 seconds
Started Aug 02 05:39:28 PM PDT 24
Finished Aug 02 05:39:34 PM PDT 24
Peak memory 248880 kb
Host smart-adc8b682-75ff-47c0-bcac-dd4981237744
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282892910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.3282892910
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.1373090795
Short name T768
Test name
Test status
Simulation time 34611357 ps
CPU time 4.96 seconds
Started Aug 02 05:39:28 PM PDT 24
Finished Aug 02 05:39:34 PM PDT 24
Peak memory 236844 kb
Host smart-77f12182-2319-48ef-b7d1-a1add6d2e985
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1373090795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.1373090795
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.282658170
Short name T260
Test name
Test status
Simulation time 9040826 ps
CPU time 1.53 seconds
Started Aug 02 05:39:29 PM PDT 24
Finished Aug 02 05:39:30 PM PDT 24
Peak memory 235852 kb
Host smart-071d1f98-9e09-4eef-9f49-2cdabb737296
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=282658170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.282658170
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.2887065177
Short name T784
Test name
Test status
Simulation time 443518946 ps
CPU time 24.27 seconds
Started Aug 02 05:39:26 PM PDT 24
Finished Aug 02 05:39:50 PM PDT 24
Peak memory 245972 kb
Host smart-26e8c15f-9565-430e-a1fa-11fcb4588fe6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2887065177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.2887065177
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.1689787567
Short name T162
Test name
Test status
Simulation time 12281955282 ps
CPU time 928.45 seconds
Started Aug 02 05:39:28 PM PDT 24
Finished Aug 02 05:54:57 PM PDT 24
Peak memory 273860 kb
Host smart-45905d97-150e-4a02-b80b-b03062255320
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689787567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.1689787567
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.4132077624
Short name T708
Test name
Test status
Simulation time 147238476 ps
CPU time 10.35 seconds
Started Aug 02 05:39:28 PM PDT 24
Finished Aug 02 05:39:39 PM PDT 24
Peak memory 248556 kb
Host smart-feca9f2a-3e45-4eb7-af1f-edace1ce138c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4132077624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.4132077624
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.3864696115
Short name T812
Test name
Test status
Simulation time 36974784 ps
CPU time 5.89 seconds
Started Aug 02 05:39:28 PM PDT 24
Finished Aug 02 05:39:34 PM PDT 24
Peak memory 254112 kb
Host smart-2e70f214-b29b-4220-ade8-c7b7449b0862
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864696115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.3864696115
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.2023121131
Short name T778
Test name
Test status
Simulation time 220198803 ps
CPU time 4.75 seconds
Started Aug 02 05:39:27 PM PDT 24
Finished Aug 02 05:39:32 PM PDT 24
Peak memory 239548 kb
Host smart-23412a9d-dac7-4dae-82e3-59c220b713da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2023121131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.2023121131
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.473634225
Short name T753
Test name
Test status
Simulation time 8652069 ps
CPU time 1.56 seconds
Started Aug 02 05:39:28 PM PDT 24
Finished Aug 02 05:39:30 PM PDT 24
Peak memory 237704 kb
Host smart-f21f3c47-cde2-426e-af61-1fb68ea9c0da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=473634225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.473634225
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.4144351715
Short name T767
Test name
Test status
Simulation time 679759264 ps
CPU time 26.26 seconds
Started Aug 02 05:39:29 PM PDT 24
Finished Aug 02 05:39:56 PM PDT 24
Peak memory 245920 kb
Host smart-37bd03d9-5bc3-4949-9e53-94d9a697f3d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4144351715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.4144351715
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.2692548195
Short name T175
Test name
Test status
Simulation time 32895045404 ps
CPU time 608.93 seconds
Started Aug 02 05:39:27 PM PDT 24
Finished Aug 02 05:49:37 PM PDT 24
Peak memory 265656 kb
Host smart-8d1c1ec2-5cad-46e9-b526-4aa22c516f9e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692548195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.2692548195
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.2722776618
Short name T751
Test name
Test status
Simulation time 386876705 ps
CPU time 16.42 seconds
Started Aug 02 05:39:29 PM PDT 24
Finished Aug 02 05:39:45 PM PDT 24
Peak memory 247980 kb
Host smart-57883037-cae9-430d-b8f4-c48419d39892
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2722776618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.2722776618
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.3084190071
Short name T211
Test name
Test status
Simulation time 1698066889 ps
CPU time 110.91 seconds
Started Aug 02 05:38:45 PM PDT 24
Finished Aug 02 05:40:36 PM PDT 24
Peak memory 240644 kb
Host smart-9111e482-eb48-4949-9d3b-22de54e2da98
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3084190071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.3084190071
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.1079118540
Short name T737
Test name
Test status
Simulation time 6806083134 ps
CPU time 181.41 seconds
Started Aug 02 05:38:45 PM PDT 24
Finished Aug 02 05:41:46 PM PDT 24
Peak memory 240804 kb
Host smart-fbb73068-494b-4b77-9da3-60d1422aa2b8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1079118540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.1079118540
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.1435501319
Short name T206
Test name
Test status
Simulation time 136904899 ps
CPU time 11.32 seconds
Started Aug 02 05:38:46 PM PDT 24
Finished Aug 02 05:38:58 PM PDT 24
Peak memory 240708 kb
Host smart-e33a2e00-c990-41a9-b300-015d897852ce
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1435501319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.1435501319
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.1992272867
Short name T720
Test name
Test status
Simulation time 148482314 ps
CPU time 11.52 seconds
Started Aug 02 05:38:45 PM PDT 24
Finished Aug 02 05:38:56 PM PDT 24
Peak memory 244612 kb
Host smart-1b2e71fe-1c90-4cb1-b557-a845a7a7195f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992272867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.1992272867
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.1776196337
Short name T209
Test name
Test status
Simulation time 454814037 ps
CPU time 8.01 seconds
Started Aug 02 05:38:44 PM PDT 24
Finished Aug 02 05:38:52 PM PDT 24
Peak memory 236812 kb
Host smart-ecddf632-1f64-40e3-88e3-7fa88933beed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1776196337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.1776196337
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.3290552320
Short name T741
Test name
Test status
Simulation time 7588605 ps
CPU time 1.3 seconds
Started Aug 02 05:38:44 PM PDT 24
Finished Aug 02 05:38:45 PM PDT 24
Peak memory 237748 kb
Host smart-6b0e9b11-0cae-4566-b1d5-cac6043f00db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3290552320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.3290552320
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.4285877762
Short name T761
Test name
Test status
Simulation time 344723700 ps
CPU time 29.39 seconds
Started Aug 02 05:38:54 PM PDT 24
Finished Aug 02 05:39:23 PM PDT 24
Peak memory 245900 kb
Host smart-efaa68dc-b05d-4655-9f4e-df9d6eb6113c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4285877762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.4285877762
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.2457118006
Short name T176
Test name
Test status
Simulation time 9619446400 ps
CPU time 363.78 seconds
Started Aug 02 05:38:54 PM PDT 24
Finished Aug 02 05:44:58 PM PDT 24
Peak memory 265780 kb
Host smart-34b3b500-7595-4391-9e1d-51e43621272d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457118006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.2457118006
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.638887520
Short name T783
Test name
Test status
Simulation time 375604391 ps
CPU time 11.67 seconds
Started Aug 02 05:38:42 PM PDT 24
Finished Aug 02 05:38:54 PM PDT 24
Peak memory 248956 kb
Host smart-6fdb345f-e3d9-4e15-a2b4-25ce81bc1f24
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=638887520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.638887520
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.467834241
Short name T731
Test name
Test status
Simulation time 18919105 ps
CPU time 1.36 seconds
Started Aug 02 05:39:29 PM PDT 24
Finished Aug 02 05:39:31 PM PDT 24
Peak memory 237764 kb
Host smart-32f834a9-653a-4331-b496-cb762866e7c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=467834241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.467834241
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.1965360583
Short name T730
Test name
Test status
Simulation time 14408176 ps
CPU time 1.77 seconds
Started Aug 02 05:39:27 PM PDT 24
Finished Aug 02 05:39:29 PM PDT 24
Peak memory 235772 kb
Host smart-da9100d2-7fec-4dd0-aeb9-17c67244d01c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1965360583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.1965360583
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.3609461546
Short name T733
Test name
Test status
Simulation time 25456234 ps
CPU time 1.29 seconds
Started Aug 02 05:39:29 PM PDT 24
Finished Aug 02 05:39:31 PM PDT 24
Peak memory 237772 kb
Host smart-d3c5d2cf-70aa-4108-b4e3-26981e336cea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3609461546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.3609461546
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.208457714
Short name T773
Test name
Test status
Simulation time 10808438 ps
CPU time 1.24 seconds
Started Aug 02 05:39:26 PM PDT 24
Finished Aug 02 05:39:27 PM PDT 24
Peak memory 236844 kb
Host smart-8a0824a7-f918-4038-8eb5-b708850cce85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=208457714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.208457714
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.773044847
Short name T714
Test name
Test status
Simulation time 6734102 ps
CPU time 1.46 seconds
Started Aug 02 05:39:28 PM PDT 24
Finished Aug 02 05:39:30 PM PDT 24
Peak memory 236800 kb
Host smart-79e72e03-536b-4e34-8c04-1d95a53776b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=773044847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.773044847
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.4257762932
Short name T363
Test name
Test status
Simulation time 13234819 ps
CPU time 1.48 seconds
Started Aug 02 05:39:28 PM PDT 24
Finished Aug 02 05:39:29 PM PDT 24
Peak memory 236780 kb
Host smart-44aa5190-289a-45fe-9b45-51bca5da8d88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4257762932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.4257762932
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.2804026533
Short name T709
Test name
Test status
Simulation time 9314800 ps
CPU time 1.46 seconds
Started Aug 02 05:39:28 PM PDT 24
Finished Aug 02 05:39:30 PM PDT 24
Peak memory 237724 kb
Host smart-ddd63407-f1eb-4d8b-8b50-863d355f9419
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2804026533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.2804026533
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.557866368
Short name T360
Test name
Test status
Simulation time 7916798 ps
CPU time 1.31 seconds
Started Aug 02 05:39:27 PM PDT 24
Finished Aug 02 05:39:29 PM PDT 24
Peak memory 236864 kb
Host smart-6d0eab2c-76c7-4789-9917-b9f714126fc9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=557866368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.557866368
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.3584248151
Short name T754
Test name
Test status
Simulation time 9975046 ps
CPU time 1.57 seconds
Started Aug 02 05:39:29 PM PDT 24
Finished Aug 02 05:39:30 PM PDT 24
Peak memory 236804 kb
Host smart-4539ebaa-6443-4d55-a2ca-450029f03e9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3584248151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.3584248151
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.2999426552
Short name T735
Test name
Test status
Simulation time 3323415652 ps
CPU time 119.85 seconds
Started Aug 02 05:38:54 PM PDT 24
Finished Aug 02 05:40:54 PM PDT 24
Peak memory 240704 kb
Host smart-94f9efa6-fec2-4114-868b-06273dde5f18
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2999426552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.2999426552
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.3416157905
Short name T814
Test name
Test status
Simulation time 9105907993 ps
CPU time 551.63 seconds
Started Aug 02 05:38:55 PM PDT 24
Finished Aug 02 05:48:07 PM PDT 24
Peak memory 237852 kb
Host smart-4e9ed542-dec3-4bd6-8359-8cd783c7bbeb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3416157905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.3416157905
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.944362229
Short name T723
Test name
Test status
Simulation time 24078056 ps
CPU time 3.82 seconds
Started Aug 02 05:38:44 PM PDT 24
Finished Aug 02 05:38:48 PM PDT 24
Peak memory 248796 kb
Host smart-75bcc7af-35a5-4a95-86a9-a8dfbd834164
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=944362229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.944362229
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.4244083039
Short name T222
Test name
Test status
Simulation time 57384327 ps
CPU time 7.83 seconds
Started Aug 02 05:38:54 PM PDT 24
Finished Aug 02 05:39:02 PM PDT 24
Peak memory 257088 kb
Host smart-6df8aa3f-ae8c-4958-89c3-fdcd4ac7ceb4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244083039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.4244083039
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.3630206008
Short name T808
Test name
Test status
Simulation time 251044012 ps
CPU time 9.05 seconds
Started Aug 02 05:38:54 PM PDT 24
Finished Aug 02 05:39:03 PM PDT 24
Peak memory 240668 kb
Host smart-c16ddc26-f952-4a6c-b8b9-3f3571a61e62
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3630206008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.3630206008
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.3541581163
Short name T757
Test name
Test status
Simulation time 8041366 ps
CPU time 1.38 seconds
Started Aug 02 05:38:44 PM PDT 24
Finished Aug 02 05:38:45 PM PDT 24
Peak memory 237740 kb
Host smart-1cdd5d0a-fb20-405f-8472-4c7aa573c471
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3541581163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.3541581163
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.1898592025
Short name T775
Test name
Test status
Simulation time 268605888 ps
CPU time 20.86 seconds
Started Aug 02 05:38:53 PM PDT 24
Finished Aug 02 05:39:14 PM PDT 24
Peak memory 240644 kb
Host smart-746cdac9-09d1-476d-b85a-1b96f7215998
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1898592025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.1898592025
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.4211615516
Short name T163
Test name
Test status
Simulation time 15082545908 ps
CPU time 288.43 seconds
Started Aug 02 05:38:48 PM PDT 24
Finished Aug 02 05:43:37 PM PDT 24
Peak memory 265652 kb
Host smart-0989c7c9-3fa7-4e27-883e-b8005f133026
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4211615516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.4211615516
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.2727219937
Short name T824
Test name
Test status
Simulation time 2204243528 ps
CPU time 352.39 seconds
Started Aug 02 05:38:53 PM PDT 24
Finished Aug 02 05:44:45 PM PDT 24
Peak memory 270868 kb
Host smart-c1ea732f-d78c-45bf-b023-7bc782570c45
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727219937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.2727219937
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.154846786
Short name T705
Test name
Test status
Simulation time 297813854 ps
CPU time 21.04 seconds
Started Aug 02 05:38:44 PM PDT 24
Finished Aug 02 05:39:05 PM PDT 24
Peak memory 248792 kb
Host smart-8d05eb2f-ef50-4c37-b760-239546611ec0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=154846786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.154846786
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.2222833379
Short name T729
Test name
Test status
Simulation time 9621306 ps
CPU time 1.56 seconds
Started Aug 02 05:39:25 PM PDT 24
Finished Aug 02 05:39:27 PM PDT 24
Peak memory 236728 kb
Host smart-bf7a84e4-c786-49a2-9c9f-c53ebd0ccbff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2222833379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.2222833379
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.2196697829
Short name T750
Test name
Test status
Simulation time 22324425 ps
CPU time 1.47 seconds
Started Aug 02 05:39:29 PM PDT 24
Finished Aug 02 05:39:31 PM PDT 24
Peak memory 237692 kb
Host smart-816f8b25-9441-4890-a21d-15112f4560da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2196697829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.2196697829
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.287383631
Short name T752
Test name
Test status
Simulation time 6769883 ps
CPU time 1.43 seconds
Started Aug 02 05:39:28 PM PDT 24
Finished Aug 02 05:39:30 PM PDT 24
Peak memory 236868 kb
Host smart-47e7ac4e-b4d2-487d-8376-8faf5cf9d1cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=287383631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.287383631
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.1111084800
Short name T362
Test name
Test status
Simulation time 8696091 ps
CPU time 1.32 seconds
Started Aug 02 05:39:27 PM PDT 24
Finished Aug 02 05:39:29 PM PDT 24
Peak memory 237692 kb
Host smart-6ef8959c-22f2-436a-ad36-ca178b8d1d2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1111084800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.1111084800
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.522738826
Short name T749
Test name
Test status
Simulation time 12076968 ps
CPU time 1.29 seconds
Started Aug 02 05:39:27 PM PDT 24
Finished Aug 02 05:39:29 PM PDT 24
Peak memory 236784 kb
Host smart-431b9228-bc62-46c0-893c-040b8c65189e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=522738826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.522738826
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.1950172390
Short name T818
Test name
Test status
Simulation time 21449702 ps
CPU time 1.36 seconds
Started Aug 02 05:39:27 PM PDT 24
Finished Aug 02 05:39:29 PM PDT 24
Peak memory 237692 kb
Host smart-4f969317-6d96-4bbd-b60d-0c465ba2247a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1950172390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.1950172390
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.2815571868
Short name T763
Test name
Test status
Simulation time 11411553 ps
CPU time 1.63 seconds
Started Aug 02 05:39:28 PM PDT 24
Finished Aug 02 05:39:30 PM PDT 24
Peak memory 236876 kb
Host smart-e22a2e1f-c561-4042-a89d-d66d005b7232
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2815571868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.2815571868
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.312721231
Short name T786
Test name
Test status
Simulation time 9437660 ps
CPU time 1.26 seconds
Started Aug 02 05:39:27 PM PDT 24
Finished Aug 02 05:39:29 PM PDT 24
Peak memory 235784 kb
Host smart-e808c79c-4f9f-4a4c-9434-ce92801e5dfa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=312721231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.312721231
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.3847018944
Short name T364
Test name
Test status
Simulation time 34795067 ps
CPU time 2.42 seconds
Started Aug 02 05:39:28 PM PDT 24
Finished Aug 02 05:39:31 PM PDT 24
Peak memory 237580 kb
Host smart-2767b014-e16a-44a7-9695-035a45f6a6e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3847018944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.3847018944
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.793897752
Short name T799
Test name
Test status
Simulation time 19624156 ps
CPU time 1.42 seconds
Started Aug 02 05:39:25 PM PDT 24
Finished Aug 02 05:39:27 PM PDT 24
Peak memory 237700 kb
Host smart-c21fa738-5489-483c-aba4-42ddffc9b2b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=793897752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.793897752
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.2607600577
Short name T816
Test name
Test status
Simulation time 6746633686 ps
CPU time 119.64 seconds
Started Aug 02 05:38:55 PM PDT 24
Finished Aug 02 05:40:55 PM PDT 24
Peak memory 239960 kb
Host smart-926657fe-b5db-4a37-97d3-0335cd8466c4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2607600577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.2607600577
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.3431610403
Short name T789
Test name
Test status
Simulation time 11422863708 ps
CPU time 406.23 seconds
Started Aug 02 05:38:54 PM PDT 24
Finished Aug 02 05:45:41 PM PDT 24
Peak memory 240768 kb
Host smart-f59cad08-d351-4da5-9267-8917173b2eb8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3431610403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.3431610403
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.2757441234
Short name T717
Test name
Test status
Simulation time 22319095 ps
CPU time 3.47 seconds
Started Aug 02 05:38:56 PM PDT 24
Finished Aug 02 05:38:59 PM PDT 24
Peak memory 248828 kb
Host smart-f3338010-a617-45b8-9a64-d3f1e57c29e0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2757441234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.2757441234
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.4214397308
Short name T827
Test name
Test status
Simulation time 60292870 ps
CPU time 4.88 seconds
Started Aug 02 05:38:53 PM PDT 24
Finished Aug 02 05:38:58 PM PDT 24
Peak memory 240972 kb
Host smart-7792cf30-4fc5-4dec-a53a-dd062ec00cf8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214397308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.4214397308
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.2733439706
Short name T210
Test name
Test status
Simulation time 119066652 ps
CPU time 5.23 seconds
Started Aug 02 05:38:54 PM PDT 24
Finished Aug 02 05:39:00 PM PDT 24
Peak memory 237560 kb
Host smart-6db2ff18-b5f6-48ba-9f8f-5910f179b62e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2733439706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.2733439706
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.2296101765
Short name T716
Test name
Test status
Simulation time 17218493 ps
CPU time 1.29 seconds
Started Aug 02 05:38:52 PM PDT 24
Finished Aug 02 05:38:54 PM PDT 24
Peak memory 235836 kb
Host smart-8e71226a-8fda-4c1c-af43-3cf545ea7fb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2296101765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.2296101765
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.2383338391
Short name T770
Test name
Test status
Simulation time 331001550 ps
CPU time 13.03 seconds
Started Aug 02 05:38:55 PM PDT 24
Finished Aug 02 05:39:08 PM PDT 24
Peak memory 245908 kb
Host smart-351a677d-67b7-4ebf-b108-803fb84b6fd2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2383338391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.2383338391
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.3289098175
Short name T177
Test name
Test status
Simulation time 2525237455 ps
CPU time 367.54 seconds
Started Aug 02 05:38:55 PM PDT 24
Finished Aug 02 05:45:03 PM PDT 24
Peak memory 265844 kb
Host smart-4ae166e6-2aee-4c0f-969e-11d75b335609
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289098175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.3289098175
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.2832186071
Short name T707
Test name
Test status
Simulation time 537450710 ps
CPU time 6.78 seconds
Started Aug 02 05:38:54 PM PDT 24
Finished Aug 02 05:39:00 PM PDT 24
Peak memory 248004 kb
Host smart-ffc94e65-bc9f-40d5-b43b-8c297d5cd73b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2832186071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.2832186071
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.2429014492
Short name T764
Test name
Test status
Simulation time 10331956 ps
CPU time 1.29 seconds
Started Aug 02 05:39:28 PM PDT 24
Finished Aug 02 05:39:29 PM PDT 24
Peak memory 237660 kb
Host smart-b3634132-e054-4511-bcc7-23aa185def6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2429014492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.2429014492
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.3636208149
Short name T710
Test name
Test status
Simulation time 10323123 ps
CPU time 1.32 seconds
Started Aug 02 05:39:27 PM PDT 24
Finished Aug 02 05:39:29 PM PDT 24
Peak memory 236896 kb
Host smart-9b394237-9a80-4c06-bf60-31eccc0fe98a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3636208149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.3636208149
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.1046055817
Short name T759
Test name
Test status
Simulation time 11768267 ps
CPU time 1.61 seconds
Started Aug 02 05:39:27 PM PDT 24
Finished Aug 02 05:39:29 PM PDT 24
Peak memory 237724 kb
Host smart-e087fae7-31f8-4a59-a921-d0bc82dd38e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1046055817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.1046055817
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.1589024224
Short name T251
Test name
Test status
Simulation time 9385598 ps
CPU time 1.48 seconds
Started Aug 02 05:39:29 PM PDT 24
Finished Aug 02 05:39:30 PM PDT 24
Peak memory 237692 kb
Host smart-ab7baa89-f497-45be-82a6-0d2e788ec393
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1589024224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.1589024224
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.4096077330
Short name T793
Test name
Test status
Simulation time 11743602 ps
CPU time 1.61 seconds
Started Aug 02 05:39:28 PM PDT 24
Finished Aug 02 05:39:30 PM PDT 24
Peak memory 237716 kb
Host smart-39b1d179-cab6-4f31-b118-ece6d2b5f970
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4096077330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.4096077330
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.324370572
Short name T712
Test name
Test status
Simulation time 8937783 ps
CPU time 1.27 seconds
Started Aug 02 05:39:29 PM PDT 24
Finished Aug 02 05:39:31 PM PDT 24
Peak memory 237684 kb
Host smart-c20b79b4-fecf-4f11-b7cc-fbeaeeda4b80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=324370572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.324370572
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.3435987220
Short name T815
Test name
Test status
Simulation time 9443122 ps
CPU time 1.27 seconds
Started Aug 02 05:39:42 PM PDT 24
Finished Aug 02 05:39:43 PM PDT 24
Peak memory 235812 kb
Host smart-eb6ac984-6395-46a7-87e1-a8a1f65cff80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3435987220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.3435987220
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.4256737793
Short name T813
Test name
Test status
Simulation time 19208259 ps
CPU time 1.56 seconds
Started Aug 02 05:39:44 PM PDT 24
Finished Aug 02 05:39:45 PM PDT 24
Peak memory 237692 kb
Host smart-294a24c5-cffe-4a4a-a3e1-c548ff46fa7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4256737793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.4256737793
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.2149706477
Short name T788
Test name
Test status
Simulation time 10771015 ps
CPU time 1.45 seconds
Started Aug 02 05:39:41 PM PDT 24
Finished Aug 02 05:39:42 PM PDT 24
Peak memory 237776 kb
Host smart-58d2df77-d8f8-4dc9-badc-47f64a72ac0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2149706477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.2149706477
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.2437748771
Short name T361
Test name
Test status
Simulation time 6488418 ps
CPU time 1.45 seconds
Started Aug 02 05:39:42 PM PDT 24
Finished Aug 02 05:39:43 PM PDT 24
Peak memory 236824 kb
Host smart-15834b41-79c2-4732-b775-b946c4b6cc77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2437748771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.2437748771
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.2251555866
Short name T785
Test name
Test status
Simulation time 326587066 ps
CPU time 6.38 seconds
Started Aug 02 05:38:53 PM PDT 24
Finished Aug 02 05:38:59 PM PDT 24
Peak memory 241380 kb
Host smart-8b46f7b0-900e-4580-9ab6-84b2025e0c2f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251555866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.2251555866
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.1282381949
Short name T802
Test name
Test status
Simulation time 338655735 ps
CPU time 8.59 seconds
Started Aug 02 05:38:56 PM PDT 24
Finished Aug 02 05:39:05 PM PDT 24
Peak memory 240664 kb
Host smart-c9f17d53-34d7-4e13-b042-98f19fea42b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1282381949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.1282381949
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.4099886418
Short name T732
Test name
Test status
Simulation time 6823800 ps
CPU time 1.47 seconds
Started Aug 02 05:38:55 PM PDT 24
Finished Aug 02 05:38:56 PM PDT 24
Peak memory 237704 kb
Host smart-5977592c-bdb2-404d-b36a-d2a11f2b02bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4099886418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.4099886418
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.2986875131
Short name T743
Test name
Test status
Simulation time 510802662 ps
CPU time 41.42 seconds
Started Aug 02 05:38:57 PM PDT 24
Finished Aug 02 05:39:38 PM PDT 24
Peak memory 248836 kb
Host smart-cc8eb3c9-03e3-48bd-9433-ebd99ead232b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2986875131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.2986875131
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.1753890615
Short name T151
Test name
Test status
Simulation time 4900159771 ps
CPU time 179.75 seconds
Started Aug 02 05:38:54 PM PDT 24
Finished Aug 02 05:41:54 PM PDT 24
Peak memory 265720 kb
Host smart-bbaf8bce-3b2a-4b4e-82e8-d11e3865a80f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1753890615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.1753890615
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.3094361383
Short name T817
Test name
Test status
Simulation time 4747995932 ps
CPU time 325.87 seconds
Started Aug 02 05:38:56 PM PDT 24
Finished Aug 02 05:44:22 PM PDT 24
Peak memory 265648 kb
Host smart-9d837a2c-2257-48ce-937e-80425bc4aca0
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094361383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.3094361383
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.1569450166
Short name T760
Test name
Test status
Simulation time 85795744 ps
CPU time 10.8 seconds
Started Aug 02 05:38:54 PM PDT 24
Finished Aug 02 05:39:05 PM PDT 24
Peak memory 248948 kb
Host smart-673762c8-a6e7-457a-8695-66f00398d757
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1569450166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.1569450166
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.3547572046
Short name T829
Test name
Test status
Simulation time 70444367 ps
CPU time 5.25 seconds
Started Aug 02 05:39:00 PM PDT 24
Finished Aug 02 05:39:06 PM PDT 24
Peak memory 237788 kb
Host smart-6dcc582d-7242-43df-8c5c-eb980fc55daf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547572046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.3547572046
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.2400001587
Short name T800
Test name
Test status
Simulation time 54698127 ps
CPU time 4.72 seconds
Started Aug 02 05:38:59 PM PDT 24
Finished Aug 02 05:39:04 PM PDT 24
Peak memory 240652 kb
Host smart-47357927-c1eb-416d-863c-899b0adf7c5e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2400001587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.2400001587
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.3985182946
Short name T781
Test name
Test status
Simulation time 11639933 ps
CPU time 1.28 seconds
Started Aug 02 05:38:59 PM PDT 24
Finished Aug 02 05:39:00 PM PDT 24
Peak memory 236840 kb
Host smart-6e860109-3d53-4e13-9a29-520e9ecd2123
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3985182946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.3985182946
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.3107895567
Short name T811
Test name
Test status
Simulation time 890394533 ps
CPU time 21.03 seconds
Started Aug 02 05:39:00 PM PDT 24
Finished Aug 02 05:39:21 PM PDT 24
Peak memory 248852 kb
Host smart-7458ca98-ef36-47be-92e0-e0167f7d43cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3107895567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.3107895567
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.1276616565
Short name T178
Test name
Test status
Simulation time 1545446868 ps
CPU time 205.86 seconds
Started Aug 02 05:38:53 PM PDT 24
Finished Aug 02 05:42:20 PM PDT 24
Peak memory 273348 kb
Host smart-df774506-6494-4c0a-a612-6bdf966bb0dc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1276616565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.1276616565
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.3856161488
Short name T745
Test name
Test status
Simulation time 22348867 ps
CPU time 3.84 seconds
Started Aug 02 05:38:55 PM PDT 24
Finished Aug 02 05:38:59 PM PDT 24
Peak memory 251592 kb
Host smart-e80bcfcf-ff2d-4f69-8075-aec713038851
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3856161488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.3856161488
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.610372783
Short name T820
Test name
Test status
Simulation time 513882708 ps
CPU time 9.47 seconds
Started Aug 02 05:39:01 PM PDT 24
Finished Aug 02 05:39:10 PM PDT 24
Peak memory 238748 kb
Host smart-850232e0-7ce6-4bc9-ab58-12064e991517
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610372783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 7.alert_handler_csr_mem_rw_with_rand_reset.610372783
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.751823454
Short name T740
Test name
Test status
Simulation time 114260218 ps
CPU time 4.65 seconds
Started Aug 02 05:38:58 PM PDT 24
Finished Aug 02 05:39:03 PM PDT 24
Peak memory 236840 kb
Host smart-acccb74a-4cf1-4a8a-ad23-43f93c15ea59
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=751823454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.751823454
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.1124917069
Short name T208
Test name
Test status
Simulation time 490482523 ps
CPU time 32.95 seconds
Started Aug 02 05:39:10 PM PDT 24
Finished Aug 02 05:39:43 PM PDT 24
Peak memory 248816 kb
Host smart-7e6438f0-d4bb-4fa6-b8f7-6efa8c65d6a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1124917069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.1124917069
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.221177719
Short name T171
Test name
Test status
Simulation time 1049188178 ps
CPU time 92.4 seconds
Started Aug 02 05:39:01 PM PDT 24
Finished Aug 02 05:40:34 PM PDT 24
Peak memory 257492 kb
Host smart-516d0209-3fd1-4e5a-93cf-4071a51057da
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=221177719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_error
s.221177719
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.3957289540
Short name T777
Test name
Test status
Simulation time 2172195000 ps
CPU time 16.3 seconds
Started Aug 02 05:39:02 PM PDT 24
Finished Aug 02 05:39:18 PM PDT 24
Peak memory 248724 kb
Host smart-1ce397cf-14a0-4d6f-9d0f-b680f8cca46c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3957289540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.3957289540
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.883995394
Short name T782
Test name
Test status
Simulation time 201938221 ps
CPU time 7.49 seconds
Started Aug 02 05:39:00 PM PDT 24
Finished Aug 02 05:39:08 PM PDT 24
Peak memory 241188 kb
Host smart-29a579ae-83ee-4a8b-b6c7-d741ab06ba5c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883995394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 8.alert_handler_csr_mem_rw_with_rand_reset.883995394
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.2271223106
Short name T821
Test name
Test status
Simulation time 89532464 ps
CPU time 5.89 seconds
Started Aug 02 05:39:10 PM PDT 24
Finished Aug 02 05:39:16 PM PDT 24
Peak memory 237708 kb
Host smart-e3c911fd-c9e5-4b0b-8e57-492c8d587eca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2271223106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.2271223106
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.2855151579
Short name T366
Test name
Test status
Simulation time 9665177 ps
CPU time 1.61 seconds
Started Aug 02 05:39:10 PM PDT 24
Finished Aug 02 05:39:12 PM PDT 24
Peak memory 236728 kb
Host smart-5c28eb78-316b-4760-8837-d3e5d61ed9bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2855151579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.2855151579
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.1117942087
Short name T758
Test name
Test status
Simulation time 1595699901 ps
CPU time 20.37 seconds
Started Aug 02 05:39:09 PM PDT 24
Finished Aug 02 05:39:30 PM PDT 24
Peak memory 248848 kb
Host smart-a854e05d-d9d2-4280-9a91-21f34dd78c59
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1117942087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.1117942087
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.3400074835
Short name T167
Test name
Test status
Simulation time 16479538455 ps
CPU time 587.65 seconds
Started Aug 02 05:38:58 PM PDT 24
Finished Aug 02 05:48:46 PM PDT 24
Peak memory 270260 kb
Host smart-523c09b3-2144-4353-a8f2-a161929cee23
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400074835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.3400074835
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.2319735086
Short name T719
Test name
Test status
Simulation time 66985841 ps
CPU time 5.37 seconds
Started Aug 02 05:38:57 PM PDT 24
Finished Aug 02 05:39:03 PM PDT 24
Peak memory 248976 kb
Host smart-0a63ad64-ee86-45af-b280-461caa542575
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2319735086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.2319735086
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.2047378135
Short name T822
Test name
Test status
Simulation time 32273480 ps
CPU time 5.13 seconds
Started Aug 02 05:38:59 PM PDT 24
Finished Aug 02 05:39:04 PM PDT 24
Peak memory 249024 kb
Host smart-a006face-d2e7-40bf-b542-dccf962b5183
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047378135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.2047378135
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.455173137
Short name T771
Test name
Test status
Simulation time 309048958 ps
CPU time 4.45 seconds
Started Aug 02 05:38:58 PM PDT 24
Finished Aug 02 05:39:03 PM PDT 24
Peak memory 240632 kb
Host smart-3a42aee0-d675-456a-8229-0605da9941d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=455173137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.455173137
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.794922006
Short name T801
Test name
Test status
Simulation time 19214191 ps
CPU time 1.85 seconds
Started Aug 02 05:38:59 PM PDT 24
Finished Aug 02 05:39:01 PM PDT 24
Peak memory 237740 kb
Host smart-32f9196d-ce66-41d7-b8f5-0e4ecce0e85b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=794922006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.794922006
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.1221381084
Short name T746
Test name
Test status
Simulation time 91360385 ps
CPU time 11.73 seconds
Started Aug 02 05:39:00 PM PDT 24
Finished Aug 02 05:39:12 PM PDT 24
Peak memory 245048 kb
Host smart-022d8d85-b919-4b10-8083-17d3d4031f04
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1221381084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.1221381084
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.2690184897
Short name T161
Test name
Test status
Simulation time 683998525 ps
CPU time 78.17 seconds
Started Aug 02 05:38:58 PM PDT 24
Finished Aug 02 05:40:16 PM PDT 24
Peak memory 266080 kb
Host smart-5ca08957-7a87-45b2-b64f-3173eadabbd9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2690184897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.2690184897
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.725938335
Short name T791
Test name
Test status
Simulation time 61184067 ps
CPU time 7.32 seconds
Started Aug 02 05:39:10 PM PDT 24
Finished Aug 02 05:39:17 PM PDT 24
Peak memory 248972 kb
Host smart-b1955121-d90f-4f63-beec-41673f7b1156
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=725938335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.725938335
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.4223384077
Short name T451
Test name
Test status
Simulation time 11551531836 ps
CPU time 824.32 seconds
Started Aug 02 05:39:42 PM PDT 24
Finished Aug 02 05:53:26 PM PDT 24
Peak memory 272984 kb
Host smart-41fd63fa-6f9c-4512-93d9-4cb607572f4a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223384077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.4223384077
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.1585845058
Short name T482
Test name
Test status
Simulation time 2754065900 ps
CPU time 22.71 seconds
Started Aug 02 05:39:43 PM PDT 24
Finished Aug 02 05:40:06 PM PDT 24
Peak memory 248380 kb
Host smart-c920494d-1d10-4afd-8780-d200df6625fb
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1585845058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.1585845058
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.2811403940
Short name T28
Test name
Test status
Simulation time 5825187091 ps
CPU time 313.11 seconds
Started Aug 02 05:39:36 PM PDT 24
Finished Aug 02 05:44:49 PM PDT 24
Peak memory 256564 kb
Host smart-24e0b3b6-414d-414e-8db6-27e9d16653fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28114
03940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.2811403940
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.1937828593
Short name T590
Test name
Test status
Simulation time 1266719530 ps
CPU time 54 seconds
Started Aug 02 05:39:35 PM PDT 24
Finished Aug 02 05:40:29 PM PDT 24
Peak memory 256088 kb
Host smart-a9ecd6c3-e168-4c2a-ac17-dfa7e0f6b6ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19378
28593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.1937828593
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.60244904
Short name T332
Test name
Test status
Simulation time 169776994984 ps
CPU time 2691.57 seconds
Started Aug 02 05:39:34 PM PDT 24
Finished Aug 02 06:24:26 PM PDT 24
Peak memory 282588 kb
Host smart-b3abbb33-87af-4e18-a244-122f56d40fab
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60244904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.60244904
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.3073445917
Short name T426
Test name
Test status
Simulation time 39750882562 ps
CPU time 1313.28 seconds
Started Aug 02 05:39:42 PM PDT 24
Finished Aug 02 06:01:35 PM PDT 24
Peak memory 272956 kb
Host smart-1f41f004-8feb-4e59-974c-2f2776f66af9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073445917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.3073445917
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.2172925686
Short name T338
Test name
Test status
Simulation time 10252407818 ps
CPU time 441.02 seconds
Started Aug 02 05:39:40 PM PDT 24
Finished Aug 02 05:47:02 PM PDT 24
Peak memory 248440 kb
Host smart-d2c024cf-49e5-4a71-84bf-c490417bdc7b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172925686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.2172925686
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.624830686
Short name T548
Test name
Test status
Simulation time 874580732 ps
CPU time 12.64 seconds
Started Aug 02 05:39:35 PM PDT 24
Finished Aug 02 05:39:48 PM PDT 24
Peak memory 255044 kb
Host smart-f1b32f7b-b832-4573-84d1-1be12c6937de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62483
0686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.624830686
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.3610001596
Short name T295
Test name
Test status
Simulation time 543958458 ps
CPU time 17.58 seconds
Started Aug 02 05:39:43 PM PDT 24
Finished Aug 02 05:40:00 PM PDT 24
Peak memory 247852 kb
Host smart-eef5f061-88f6-483a-9cf1-da07f2802cb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36100
01596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.3610001596
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.2360744628
Short name T8
Test name
Test status
Simulation time 579540181 ps
CPU time 10.56 seconds
Started Aug 02 05:39:34 PM PDT 24
Finished Aug 02 05:39:45 PM PDT 24
Peak memory 273324 kb
Host smart-50fd23c9-435b-4058-a4cf-0638f06ec7d6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2360744628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.2360744628
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.685464844
Short name T135
Test name
Test status
Simulation time 246449807 ps
CPU time 7.79 seconds
Started Aug 02 05:39:42 PM PDT 24
Finished Aug 02 05:39:50 PM PDT 24
Peak memory 254800 kb
Host smart-3a8fcea6-5374-4bf9-99d8-ab750751f7f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68546
4844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.685464844
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.1208717411
Short name T247
Test name
Test status
Simulation time 208104269 ps
CPU time 20.07 seconds
Started Aug 02 05:39:34 PM PDT 24
Finished Aug 02 05:39:55 PM PDT 24
Peak memory 248412 kb
Host smart-1f6ccad7-c37a-47b4-b61e-f9fd2f36be27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12087
17411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.1208717411
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.2279885210
Short name T66
Test name
Test status
Simulation time 808670807 ps
CPU time 85.72 seconds
Started Aug 02 05:39:35 PM PDT 24
Finished Aug 02 05:41:01 PM PDT 24
Peak memory 250916 kb
Host smart-54289a8e-b0e3-48d2-a665-55a354201b99
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279885210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.2279885210
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.297791927
Short name T134
Test name
Test status
Simulation time 81213350543 ps
CPU time 1457.35 seconds
Started Aug 02 05:39:36 PM PDT 24
Finished Aug 02 06:03:54 PM PDT 24
Peak memory 288132 kb
Host smart-9fdbfa9b-f24e-46ab-b149-3c6bc692455b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297791927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.297791927
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.1601417495
Short name T553
Test name
Test status
Simulation time 176812284 ps
CPU time 10.02 seconds
Started Aug 02 05:39:35 PM PDT 24
Finished Aug 02 05:39:45 PM PDT 24
Peak memory 248268 kb
Host smart-ecbea48b-69db-4c3e-9db7-462b4e08ed2b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1601417495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.1601417495
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.2486434113
Short name T634
Test name
Test status
Simulation time 50860016592 ps
CPU time 273.73 seconds
Started Aug 02 05:39:33 PM PDT 24
Finished Aug 02 05:44:07 PM PDT 24
Peak memory 255980 kb
Host smart-5543b0a4-5eac-4cc5-9f6b-b00eb25560dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24864
34113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.2486434113
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.2537100426
Short name T549
Test name
Test status
Simulation time 934928429 ps
CPU time 57.56 seconds
Started Aug 02 05:39:36 PM PDT 24
Finished Aug 02 05:40:34 PM PDT 24
Peak memory 248400 kb
Host smart-924bdf06-168a-4edf-b669-ea7bb6dcb646
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25371
00426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.2537100426
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.3320526087
Short name T74
Test name
Test status
Simulation time 98406465618 ps
CPU time 1644.85 seconds
Started Aug 02 05:39:40 PM PDT 24
Finished Aug 02 06:07:06 PM PDT 24
Peak memory 273000 kb
Host smart-d8511169-b465-44cc-b6cb-c64aa5e4a6e6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320526087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.3320526087
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.856443189
Short name T379
Test name
Test status
Simulation time 626819564074 ps
CPU time 3286.6 seconds
Started Aug 02 05:39:36 PM PDT 24
Finished Aug 02 06:34:23 PM PDT 24
Peak memory 288888 kb
Host smart-46dd4445-47b1-48b7-b4a3-3ec5c6e58d85
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856443189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.856443189
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.581565031
Short name T621
Test name
Test status
Simulation time 8837902288 ps
CPU time 374.89 seconds
Started Aug 02 05:39:37 PM PDT 24
Finished Aug 02 05:45:52 PM PDT 24
Peak memory 247276 kb
Host smart-a892679d-a6f9-44ec-bdce-5bde34136519
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581565031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.581565031
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.2041207679
Short name T107
Test name
Test status
Simulation time 257871497 ps
CPU time 8.55 seconds
Started Aug 02 05:39:35 PM PDT 24
Finished Aug 02 05:39:44 PM PDT 24
Peak memory 248364 kb
Host smart-9268bec7-ab0d-4d24-984d-2463ceeebc28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20412
07679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.2041207679
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.1871835627
Short name T616
Test name
Test status
Simulation time 479018178 ps
CPU time 29.6 seconds
Started Aug 02 05:39:34 PM PDT 24
Finished Aug 02 05:40:04 PM PDT 24
Peak memory 247832 kb
Host smart-a6be723a-ffd2-4315-8cb4-8ba8c54cd537
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18718
35627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.1871835627
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.4211017571
Short name T37
Test name
Test status
Simulation time 183115224 ps
CPU time 11.53 seconds
Started Aug 02 05:39:36 PM PDT 24
Finished Aug 02 05:39:48 PM PDT 24
Peak memory 269424 kb
Host smart-a1f60b37-448a-4eaa-8786-76c542ae615f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4211017571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.4211017571
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.2469583685
Short name T517
Test name
Test status
Simulation time 238688512 ps
CPU time 16.23 seconds
Started Aug 02 05:39:35 PM PDT 24
Finished Aug 02 05:39:52 PM PDT 24
Peak memory 256108 kb
Host smart-1b4f3149-16e4-4f20-ae5d-0dd08a1b42b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24695
83685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.2469583685
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.3692402697
Short name T413
Test name
Test status
Simulation time 733470386 ps
CPU time 41.67 seconds
Started Aug 02 05:39:33 PM PDT 24
Finished Aug 02 05:40:14 PM PDT 24
Peak memory 256544 kb
Host smart-e3528714-d624-4eb5-9b00-290093da039b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36924
02697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.3692402697
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.493048044
Short name T666
Test name
Test status
Simulation time 110937454765 ps
CPU time 10391.2 seconds
Started Aug 02 05:39:35 PM PDT 24
Finished Aug 02 08:32:47 PM PDT 24
Peak memory 452236 kb
Host smart-98c6415d-bc44-41bc-b021-f4214c23f249
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493048044 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.493048044
Directory /workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.940950134
Short name T669
Test name
Test status
Simulation time 1215207433 ps
CPU time 12.83 seconds
Started Aug 02 05:40:10 PM PDT 24
Finished Aug 02 05:40:23 PM PDT 24
Peak memory 248380 kb
Host smart-a26ea649-07e3-44f8-9780-c31698faf9b2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=940950134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.940950134
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.588105332
Short name T452
Test name
Test status
Simulation time 853611012 ps
CPU time 19.7 seconds
Started Aug 02 05:40:12 PM PDT 24
Finished Aug 02 05:40:31 PM PDT 24
Peak memory 256136 kb
Host smart-b4a0fb02-3181-4818-975e-1621de14eaa8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58810
5332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.588105332
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.1692226239
Short name T684
Test name
Test status
Simulation time 398415497 ps
CPU time 29.74 seconds
Started Aug 02 05:40:10 PM PDT 24
Finished Aug 02 05:40:40 PM PDT 24
Peak memory 255676 kb
Host smart-3423f7e9-71c4-4422-8203-280afbec8294
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16922
26239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.1692226239
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.3891846607
Short name T301
Test name
Test status
Simulation time 154874204273 ps
CPU time 1975.93 seconds
Started Aug 02 05:40:17 PM PDT 24
Finished Aug 02 06:13:13 PM PDT 24
Peak memory 272252 kb
Host smart-5434234c-a28f-49cd-8840-2a0e6dd42038
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891846607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.3891846607
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.2330008965
Short name T583
Test name
Test status
Simulation time 163596944090 ps
CPU time 2380.1 seconds
Started Aug 02 05:40:10 PM PDT 24
Finished Aug 02 06:19:51 PM PDT 24
Peak memory 281956 kb
Host smart-a1d8cf48-c529-444a-b0dd-5adf6870a28e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330008965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.2330008965
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.2883640601
Short name T342
Test name
Test status
Simulation time 11116884478 ps
CPU time 242.57 seconds
Started Aug 02 05:40:12 PM PDT 24
Finished Aug 02 05:44:15 PM PDT 24
Peak memory 255016 kb
Host smart-9f407337-18f8-4b19-8ade-3ec5a992e405
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883640601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.2883640601
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.1551933895
Short name T20
Test name
Test status
Simulation time 2282045754 ps
CPU time 37.02 seconds
Started Aug 02 05:40:09 PM PDT 24
Finished Aug 02 05:40:46 PM PDT 24
Peak memory 255932 kb
Host smart-5799b00f-edc3-499a-af13-9e6ac05e194f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15519
33895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.1551933895
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.1715411184
Short name T523
Test name
Test status
Simulation time 4214814329 ps
CPU time 66.1 seconds
Started Aug 02 05:40:07 PM PDT 24
Finished Aug 02 05:41:13 PM PDT 24
Peak memory 256388 kb
Host smart-8ac7de8e-8be3-4e63-a3ae-c2ee5dffa811
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17154
11184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.1715411184
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.1598816310
Short name T72
Test name
Test status
Simulation time 357455957 ps
CPU time 29.67 seconds
Started Aug 02 05:40:00 PM PDT 24
Finished Aug 02 05:40:30 PM PDT 24
Peak memory 256508 kb
Host smart-88b5af16-5c21-46bb-a7cb-617741532389
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15988
16310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.1598816310
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.3108351324
Short name T19
Test name
Test status
Simulation time 125864448 ps
CPU time 3.36 seconds
Started Aug 02 05:40:11 PM PDT 24
Finished Aug 02 05:40:15 PM PDT 24
Peak memory 248564 kb
Host smart-63689509-48ff-4746-8096-d29584777299
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3108351324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.3108351324
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.40561771
Short name T49
Test name
Test status
Simulation time 8400629123 ps
CPU time 807.83 seconds
Started Aug 02 05:40:12 PM PDT 24
Finished Aug 02 05:53:40 PM PDT 24
Peak memory 272600 kb
Host smart-97e565eb-a975-48d4-9967-351f34f25f61
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40561771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.40561771
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.3927152813
Short name T415
Test name
Test status
Simulation time 3206364871 ps
CPU time 17.85 seconds
Started Aug 02 05:40:08 PM PDT 24
Finished Aug 02 05:40:26 PM PDT 24
Peak memory 248400 kb
Host smart-1ce891fd-7566-4ec8-9747-1a879086c5d1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3927152813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.3927152813
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.1681130281
Short name T265
Test name
Test status
Simulation time 2146651712 ps
CPU time 111.14 seconds
Started Aug 02 05:40:09 PM PDT 24
Finished Aug 02 05:42:00 PM PDT 24
Peak memory 256480 kb
Host smart-0bc86cf2-5267-4199-8412-5995dbe0e2cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16811
30281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.1681130281
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.2921159708
Short name T419
Test name
Test status
Simulation time 289818756 ps
CPU time 3.76 seconds
Started Aug 02 05:40:14 PM PDT 24
Finished Aug 02 05:40:18 PM PDT 24
Peak memory 239668 kb
Host smart-22585374-355f-4103-bfb8-55509743b9b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29211
59708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.2921159708
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.30307865
Short name T213
Test name
Test status
Simulation time 42849283483 ps
CPU time 2738.53 seconds
Started Aug 02 05:40:13 PM PDT 24
Finished Aug 02 06:25:52 PM PDT 24
Peak memory 285996 kb
Host smart-9c161e49-68aa-4ba9-af33-43c3599f48d9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30307865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.30307865
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.1412351130
Short name T491
Test name
Test status
Simulation time 489733718 ps
CPU time 4.7 seconds
Started Aug 02 05:40:09 PM PDT 24
Finished Aug 02 05:40:14 PM PDT 24
Peak memory 251112 kb
Host smart-cf976184-47e8-4c01-a15e-b885d505649f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14123
51130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.1412351130
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.650663248
Short name T127
Test name
Test status
Simulation time 457708580 ps
CPU time 18.26 seconds
Started Aug 02 05:40:08 PM PDT 24
Finished Aug 02 05:40:27 PM PDT 24
Peak memory 247668 kb
Host smart-bd814eec-dc7a-45be-b39a-936cc3ffc274
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65066
3248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.650663248
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.1785277455
Short name T679
Test name
Test status
Simulation time 1232600974 ps
CPU time 19.07 seconds
Started Aug 02 05:40:11 PM PDT 24
Finished Aug 02 05:40:30 PM PDT 24
Peak memory 255716 kb
Host smart-5bb4478c-c2d5-4f67-8153-a5232d973a03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17852
77455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.1785277455
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.637425449
Short name T457
Test name
Test status
Simulation time 389806546 ps
CPU time 25.11 seconds
Started Aug 02 05:40:11 PM PDT 24
Finished Aug 02 05:40:36 PM PDT 24
Peak memory 256436 kb
Host smart-fdf26ba2-4160-413d-9044-6fe75a2a8794
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63742
5449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.637425449
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.3816405472
Short name T236
Test name
Test status
Simulation time 13585119 ps
CPU time 2.61 seconds
Started Aug 02 05:40:07 PM PDT 24
Finished Aug 02 05:40:10 PM PDT 24
Peak memory 248636 kb
Host smart-639f0779-9b68-4876-ba1e-db27c257497f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3816405472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.3816405472
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.1459289461
Short name T110
Test name
Test status
Simulation time 160023369134 ps
CPU time 1265.88 seconds
Started Aug 02 05:40:08 PM PDT 24
Finished Aug 02 06:01:14 PM PDT 24
Peak memory 265800 kb
Host smart-27e14cfe-a413-4fb0-bb98-b1be64c8b0b5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459289461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.1459289461
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.1602471074
Short name T543
Test name
Test status
Simulation time 8115444791 ps
CPU time 38.72 seconds
Started Aug 02 05:40:14 PM PDT 24
Finished Aug 02 05:40:53 PM PDT 24
Peak memory 248332 kb
Host smart-ca5316cf-2b78-4038-b3a9-4a5971c3f523
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1602471074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.1602471074
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.3895310851
Short name T219
Test name
Test status
Simulation time 4444045923 ps
CPU time 162.92 seconds
Started Aug 02 05:40:14 PM PDT 24
Finished Aug 02 05:42:57 PM PDT 24
Peak memory 256108 kb
Host smart-a682278b-b3fe-4fbe-8c31-bdf300eb0f09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38953
10851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.3895310851
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.304383596
Short name T678
Test name
Test status
Simulation time 12805521618 ps
CPU time 46.82 seconds
Started Aug 02 05:40:11 PM PDT 24
Finished Aug 02 05:40:58 PM PDT 24
Peak memory 256492 kb
Host smart-8dc6b982-ea87-4251-8f9e-1cd58856debe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30438
3596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.304383596
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.2091457137
Short name T598
Test name
Test status
Simulation time 841062450787 ps
CPU time 2993.41 seconds
Started Aug 02 05:40:09 PM PDT 24
Finished Aug 02 06:30:02 PM PDT 24
Peak memory 287040 kb
Host smart-ccda874d-9087-49aa-bb0e-9115917ad9f0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091457137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.2091457137
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.415807818
Short name T636
Test name
Test status
Simulation time 40379564533 ps
CPU time 1338.98 seconds
Started Aug 02 05:40:11 PM PDT 24
Finished Aug 02 06:02:31 PM PDT 24
Peak memory 272824 kb
Host smart-6927958d-6ed9-4f00-ac0d-a0d2b36b711c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415807818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.415807818
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.917299344
Short name T692
Test name
Test status
Simulation time 26739589058 ps
CPU time 580.39 seconds
Started Aug 02 05:40:11 PM PDT 24
Finished Aug 02 05:49:52 PM PDT 24
Peak memory 248288 kb
Host smart-03c1429a-5ecf-47c0-85ad-b3860e81e62b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917299344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.917299344
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.1850754059
Short name T246
Test name
Test status
Simulation time 720307914 ps
CPU time 45.44 seconds
Started Aug 02 05:40:10 PM PDT 24
Finished Aug 02 05:40:55 PM PDT 24
Peak memory 255636 kb
Host smart-14e63ccd-7b12-4c35-8553-2dec415483ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18507
54059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.1850754059
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.549834351
Short name T380
Test name
Test status
Simulation time 398275456 ps
CPU time 20.14 seconds
Started Aug 02 05:40:09 PM PDT 24
Finished Aug 02 05:40:29 PM PDT 24
Peak memory 247880 kb
Host smart-07685793-d06f-4014-819e-2f988a8460f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54983
4351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.549834351
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.931345909
Short name T71
Test name
Test status
Simulation time 1021006411 ps
CPU time 18.73 seconds
Started Aug 02 05:40:09 PM PDT 24
Finished Aug 02 05:40:28 PM PDT 24
Peak memory 248628 kb
Host smart-330e7913-2ae5-4689-b854-ab2fb336b332
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93134
5909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.931345909
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.2397637785
Short name T370
Test name
Test status
Simulation time 1308434325 ps
CPU time 31.36 seconds
Started Aug 02 05:40:09 PM PDT 24
Finished Aug 02 05:40:40 PM PDT 24
Peak memory 255732 kb
Host smart-2b07c44f-bdce-4563-b2fd-100fccf64eea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23976
37785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.2397637785
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.1262957121
Short name T237
Test name
Test status
Simulation time 157010037 ps
CPU time 3.03 seconds
Started Aug 02 05:40:09 PM PDT 24
Finished Aug 02 05:40:12 PM PDT 24
Peak memory 248688 kb
Host smart-e658418c-f9cd-44e3-a6a5-7ab3ba1639bd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1262957121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.1262957121
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.1569860334
Short name T645
Test name
Test status
Simulation time 18227196275 ps
CPU time 1385.03 seconds
Started Aug 02 05:40:09 PM PDT 24
Finished Aug 02 06:03:14 PM PDT 24
Peak memory 288816 kb
Host smart-269eb573-0ba2-4af1-9a9e-97d2013deb0c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569860334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.1569860334
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.2430974409
Short name T537
Test name
Test status
Simulation time 1150415046 ps
CPU time 15.96 seconds
Started Aug 02 05:40:14 PM PDT 24
Finished Aug 02 05:40:30 PM PDT 24
Peak memory 248292 kb
Host smart-47d4fe87-f94b-44dc-b383-17f5e6e8eeb9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2430974409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.2430974409
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.2103066664
Short name T462
Test name
Test status
Simulation time 3485381359 ps
CPU time 190.5 seconds
Started Aug 02 05:40:16 PM PDT 24
Finished Aug 02 05:43:27 PM PDT 24
Peak memory 256144 kb
Host smart-02b67cf5-9945-4858-8595-1eb155452808
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21030
66664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.2103066664
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.3727675095
Short name T73
Test name
Test status
Simulation time 201939655 ps
CPU time 15.07 seconds
Started Aug 02 05:40:18 PM PDT 24
Finished Aug 02 05:40:33 PM PDT 24
Peak memory 247980 kb
Host smart-3a897820-ae09-4ea8-86e1-011be1b293f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37276
75095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.3727675095
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.3642366061
Short name T330
Test name
Test status
Simulation time 108299301618 ps
CPU time 1897.56 seconds
Started Aug 02 05:40:09 PM PDT 24
Finished Aug 02 06:11:47 PM PDT 24
Peak memory 280960 kb
Host smart-850996ae-c74f-4ceb-8520-6d27efae78dd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642366061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.3642366061
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.4151454235
Short name T123
Test name
Test status
Simulation time 183739406668 ps
CPU time 2583.54 seconds
Started Aug 02 05:40:10 PM PDT 24
Finished Aug 02 06:23:14 PM PDT 24
Peak memory 288508 kb
Host smart-2bdb62ef-0cdc-49a8-9d99-61a4394df004
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151454235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.4151454235
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.2692194923
Short name T511
Test name
Test status
Simulation time 211646702 ps
CPU time 24.19 seconds
Started Aug 02 05:40:08 PM PDT 24
Finished Aug 02 05:40:32 PM PDT 24
Peak memory 248408 kb
Host smart-8b8dff00-d483-4ec2-9e23-992795a690d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26921
94923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.2692194923
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.2644147777
Short name T642
Test name
Test status
Simulation time 966787181 ps
CPU time 17.21 seconds
Started Aug 02 05:40:10 PM PDT 24
Finished Aug 02 05:40:28 PM PDT 24
Peak memory 248060 kb
Host smart-a217ae9c-b6d3-4a11-8092-46e0a06e6d3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26441
47777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.2644147777
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.2659133986
Short name T687
Test name
Test status
Simulation time 181212144 ps
CPU time 14.8 seconds
Started Aug 02 05:40:12 PM PDT 24
Finished Aug 02 05:40:27 PM PDT 24
Peak memory 247412 kb
Host smart-f29d49c9-68e7-493b-b8b5-d17f6367bd70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26591
33986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.2659133986
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.4069571126
Short name T556
Test name
Test status
Simulation time 168915725 ps
CPU time 5.51 seconds
Started Aug 02 05:40:09 PM PDT 24
Finished Aug 02 05:40:15 PM PDT 24
Peak memory 248540 kb
Host smart-fc3b56aa-9808-43a1-a090-b61ec7e347f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40695
71126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.4069571126
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.4050919321
Short name T114
Test name
Test status
Simulation time 137049313253 ps
CPU time 1247.72 seconds
Started Aug 02 05:40:12 PM PDT 24
Finished Aug 02 06:01:00 PM PDT 24
Peak memory 288928 kb
Host smart-6982494d-1a37-421e-9288-c47ba3b46e13
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050919321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.4050919321
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.1926277615
Short name T229
Test name
Test status
Simulation time 30555320 ps
CPU time 2.45 seconds
Started Aug 02 05:40:25 PM PDT 24
Finished Aug 02 05:40:27 PM PDT 24
Peak memory 248640 kb
Host smart-e67ce7a6-abea-441f-abd7-b4774c2aaa95
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1926277615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.1926277615
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.1105821941
Short name T36
Test name
Test status
Simulation time 113725702750 ps
CPU time 1857.48 seconds
Started Aug 02 05:40:10 PM PDT 24
Finished Aug 02 06:11:08 PM PDT 24
Peak memory 272924 kb
Host smart-427bf3a1-d39e-4fa6-8138-d9bf721bd3f5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105821941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.1105821941
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.2665117351
Short name T668
Test name
Test status
Simulation time 666399226 ps
CPU time 29.19 seconds
Started Aug 02 05:40:12 PM PDT 24
Finished Aug 02 05:40:42 PM PDT 24
Peak memory 248372 kb
Host smart-402aa228-675d-4113-acfc-b329442f2919
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2665117351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.2665117351
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.2122647914
Short name T381
Test name
Test status
Simulation time 15064235482 ps
CPU time 101.72 seconds
Started Aug 02 05:40:12 PM PDT 24
Finished Aug 02 05:41:53 PM PDT 24
Peak memory 256608 kb
Host smart-0a3160f2-d53d-4a7c-9c28-1637045263d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21226
47914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.2122647914
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.1287199073
Short name T23
Test name
Test status
Simulation time 621067509 ps
CPU time 8.88 seconds
Started Aug 02 05:40:10 PM PDT 24
Finished Aug 02 05:40:19 PM PDT 24
Peak memory 247956 kb
Host smart-cd72ac60-6541-40c7-a83e-707fd50d3ea3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12871
99073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.1287199073
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.2191148257
Short name T357
Test name
Test status
Simulation time 100930944309 ps
CPU time 1794.09 seconds
Started Aug 02 05:40:13 PM PDT 24
Finished Aug 02 06:10:07 PM PDT 24
Peak memory 272352 kb
Host smart-59fc9560-ce1e-420c-b3de-e911d006b0f3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191148257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.2191148257
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.736889795
Short name T683
Test name
Test status
Simulation time 27114781053 ps
CPU time 1988.66 seconds
Started Aug 02 05:40:09 PM PDT 24
Finished Aug 02 06:13:18 PM PDT 24
Peak memory 281728 kb
Host smart-1d2feeaa-7211-4976-86c0-71a21bf15f70
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736889795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.736889795
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.2024654894
Short name T697
Test name
Test status
Simulation time 23454223898 ps
CPU time 463.36 seconds
Started Aug 02 05:40:10 PM PDT 24
Finished Aug 02 05:47:54 PM PDT 24
Peak memory 248304 kb
Host smart-1cd36d55-f803-4137-b1e6-76125f599345
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024654894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.2024654894
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.263606518
Short name T586
Test name
Test status
Simulation time 1746789089 ps
CPU time 48.03 seconds
Started Aug 02 05:40:10 PM PDT 24
Finished Aug 02 05:40:58 PM PDT 24
Peak memory 255560 kb
Host smart-618d126f-2499-4293-882e-abdc99ba39e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26360
6518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.263606518
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.1697103570
Short name T26
Test name
Test status
Simulation time 971694916 ps
CPU time 51.58 seconds
Started Aug 02 05:40:14 PM PDT 24
Finished Aug 02 05:41:05 PM PDT 24
Peak memory 248412 kb
Host smart-e5e90737-a425-4ff0-b59d-4a9b6d695fdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16971
03570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.1697103570
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.2639761402
Short name T394
Test name
Test status
Simulation time 95650157 ps
CPU time 12.03 seconds
Started Aug 02 05:40:12 PM PDT 24
Finished Aug 02 05:40:24 PM PDT 24
Peak memory 248384 kb
Host smart-bcdf1a27-6715-4737-b5f3-7b4e6bb38555
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26397
61402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.2639761402
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.1187549712
Short name T407
Test name
Test status
Simulation time 565142806 ps
CPU time 32.78 seconds
Started Aug 02 05:40:10 PM PDT 24
Finished Aug 02 05:40:43 PM PDT 24
Peak memory 256532 kb
Host smart-04cd3d86-37a9-4307-9e33-0f1e6716bec7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11875
49712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.1187549712
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.3974118815
Short name T234
Test name
Test status
Simulation time 17573440 ps
CPU time 2.74 seconds
Started Aug 02 05:40:18 PM PDT 24
Finished Aug 02 05:40:21 PM PDT 24
Peak memory 248740 kb
Host smart-407eb052-86af-46fb-8392-152d69477af7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3974118815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.3974118815
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.3420278066
Short name T532
Test name
Test status
Simulation time 151190737979 ps
CPU time 2340.73 seconds
Started Aug 02 05:40:16 PM PDT 24
Finished Aug 02 06:19:17 PM PDT 24
Peak memory 273028 kb
Host smart-7c1a9c13-d8fa-49a7-96e6-d2f381e26866
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420278066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.3420278066
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.1423293202
Short name T467
Test name
Test status
Simulation time 3632966639 ps
CPU time 51.25 seconds
Started Aug 02 05:40:18 PM PDT 24
Finished Aug 02 05:41:09 PM PDT 24
Peak memory 248408 kb
Host smart-8d980a99-b3f5-4031-8d35-5ca210818811
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1423293202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.1423293202
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.3404954686
Short name T469
Test name
Test status
Simulation time 12089607695 ps
CPU time 160.01 seconds
Started Aug 02 05:40:15 PM PDT 24
Finished Aug 02 05:42:55 PM PDT 24
Peak memory 256644 kb
Host smart-cfe4156f-66b4-47de-bc8f-88a72bcf41b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34049
54686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.3404954686
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.4066318144
Short name T663
Test name
Test status
Simulation time 9319273486 ps
CPU time 51.83 seconds
Started Aug 02 05:40:25 PM PDT 24
Finished Aug 02 05:41:17 PM PDT 24
Peak memory 256088 kb
Host smart-fa24cf71-3173-45cb-9d17-96048f8f16b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40663
18144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.4066318144
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.83538106
Short name T502
Test name
Test status
Simulation time 17529896290 ps
CPU time 1025.36 seconds
Started Aug 02 05:40:18 PM PDT 24
Finished Aug 02 05:57:24 PM PDT 24
Peak memory 271876 kb
Host smart-7bdccf5d-5911-4d66-a1a9-80a00975d219
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83538106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.83538106
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.3065733358
Short name T87
Test name
Test status
Simulation time 101474935035 ps
CPU time 3113.37 seconds
Started Aug 02 05:40:25 PM PDT 24
Finished Aug 02 06:32:18 PM PDT 24
Peak memory 288560 kb
Host smart-1bc22eae-9acb-4520-9ad3-1934deb55ed5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065733358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.3065733358
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.3957798868
Short name T649
Test name
Test status
Simulation time 65978933172 ps
CPU time 596.59 seconds
Started Aug 02 05:40:14 PM PDT 24
Finished Aug 02 05:50:11 PM PDT 24
Peak memory 248476 kb
Host smart-cbf3bb56-42df-4769-b70a-1287760f4a8a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957798868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.3957798868
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.519129364
Short name T533
Test name
Test status
Simulation time 387650055 ps
CPU time 26.44 seconds
Started Aug 02 05:40:21 PM PDT 24
Finished Aug 02 05:40:48 PM PDT 24
Peak memory 256532 kb
Host smart-ee301cc3-3112-4905-ab3b-46855634c0d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51912
9364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.519129364
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.40076856
Short name T531
Test name
Test status
Simulation time 349880201 ps
CPU time 16.46 seconds
Started Aug 02 05:40:19 PM PDT 24
Finished Aug 02 05:40:36 PM PDT 24
Peak memory 255964 kb
Host smart-9a4f4aa3-7557-4efc-8d93-a36931cd0d3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40076
856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.40076856
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.1732510199
Short name T656
Test name
Test status
Simulation time 985111939 ps
CPU time 54.44 seconds
Started Aug 02 05:40:14 PM PDT 24
Finished Aug 02 05:41:09 PM PDT 24
Peak memory 247812 kb
Host smart-74e4967b-2650-4a26-9295-54a18bd45cae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17325
10199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.1732510199
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.3574064145
Short name T235
Test name
Test status
Simulation time 22552001 ps
CPU time 2.82 seconds
Started Aug 02 05:40:23 PM PDT 24
Finished Aug 02 05:40:26 PM PDT 24
Peak memory 248604 kb
Host smart-a573da72-40b4-4aac-85dd-130a6cd907af
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3574064145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.3574064145
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.1138507487
Short name T436
Test name
Test status
Simulation time 8507008026 ps
CPU time 1151.31 seconds
Started Aug 02 05:40:26 PM PDT 24
Finished Aug 02 05:59:38 PM PDT 24
Peak memory 284400 kb
Host smart-61ba5a5b-03ac-4060-91c5-22e6ff8ebe93
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138507487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.1138507487
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.3169310862
Short name T677
Test name
Test status
Simulation time 597648800 ps
CPU time 16.32 seconds
Started Aug 02 05:40:27 PM PDT 24
Finished Aug 02 05:40:44 PM PDT 24
Peak memory 248352 kb
Host smart-d94b68b6-59d4-425e-8b61-955246eac59d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3169310862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.3169310862
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.1829452971
Short name T628
Test name
Test status
Simulation time 7117164470 ps
CPU time 278.63 seconds
Started Aug 02 05:40:13 PM PDT 24
Finished Aug 02 05:44:52 PM PDT 24
Peak memory 256680 kb
Host smart-cb8679f1-0763-40a4-8e29-3cd216c76ae8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18294
52971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.1829452971
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.272958760
Short name T298
Test name
Test status
Simulation time 313395515 ps
CPU time 22.57 seconds
Started Aug 02 05:40:19 PM PDT 24
Finished Aug 02 05:40:41 PM PDT 24
Peak memory 248296 kb
Host smart-0ca432db-dfff-49b0-a7e7-945c678af468
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27295
8760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.272958760
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.1211258915
Short name T221
Test name
Test status
Simulation time 163187776469 ps
CPU time 1211.44 seconds
Started Aug 02 05:40:22 PM PDT 24
Finished Aug 02 06:00:34 PM PDT 24
Peak memory 285792 kb
Host smart-4bb4bf61-85f6-4de4-ae4e-5a5430a5a58e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211258915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.1211258915
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.4130226831
Short name T292
Test name
Test status
Simulation time 18000825153 ps
CPU time 1494.23 seconds
Started Aug 02 05:40:23 PM PDT 24
Finished Aug 02 06:05:18 PM PDT 24
Peak memory 288328 kb
Host smart-edba1216-c8f9-4222-a985-97ce1d27ee52
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130226831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.4130226831
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.1289279508
Short name T439
Test name
Test status
Simulation time 1076764226 ps
CPU time 59.23 seconds
Started Aug 02 05:40:24 PM PDT 24
Finished Aug 02 05:41:24 PM PDT 24
Peak memory 255892 kb
Host smart-69b16ebd-01ca-4744-9f83-8115ee49c56f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12892
79508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.1289279508
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.2066361664
Short name T588
Test name
Test status
Simulation time 1915612558 ps
CPU time 57.46 seconds
Started Aug 02 05:40:14 PM PDT 24
Finished Aug 02 05:41:12 PM PDT 24
Peak memory 256108 kb
Host smart-fe452db0-84ae-429a-83ab-0757b2d54863
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20663
61664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.2066361664
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.1590022430
Short name T441
Test name
Test status
Simulation time 67955153 ps
CPU time 10.52 seconds
Started Aug 02 05:40:18 PM PDT 24
Finished Aug 02 05:40:29 PM PDT 24
Peak memory 247928 kb
Host smart-9da6f61b-17a9-451f-b5b0-c6ed9ba87ae2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15900
22430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.1590022430
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.1354121757
Short name T483
Test name
Test status
Simulation time 1916427429 ps
CPU time 54.8 seconds
Started Aug 02 05:40:14 PM PDT 24
Finished Aug 02 05:41:09 PM PDT 24
Peak memory 256504 kb
Host smart-a51fca77-f7b3-4130-85f9-814727547a2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13541
21757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.1354121757
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.2826574828
Short name T459
Test name
Test status
Simulation time 1618511905 ps
CPU time 141.23 seconds
Started Aug 02 05:40:23 PM PDT 24
Finished Aug 02 05:42:44 PM PDT 24
Peak memory 256452 kb
Host smart-3fb3923e-8f08-432f-a6f2-c249ba0d1a37
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826574828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.2826574828
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.1817347477
Short name T274
Test name
Test status
Simulation time 34264683708 ps
CPU time 1247.18 seconds
Started Aug 02 05:40:23 PM PDT 24
Finished Aug 02 06:01:10 PM PDT 24
Peak memory 288720 kb
Host smart-470801dd-3ded-4c59-bac8-ce52772391bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817347477 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.1817347477
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.542180961
Short name T231
Test name
Test status
Simulation time 29352654 ps
CPU time 3.05 seconds
Started Aug 02 05:40:32 PM PDT 24
Finished Aug 02 05:40:35 PM PDT 24
Peak memory 248596 kb
Host smart-e335dddf-07a5-4fa8-89a4-682346b44f8d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=542180961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.542180961
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.3938330480
Short name T104
Test name
Test status
Simulation time 33909987593 ps
CPU time 2353.84 seconds
Started Aug 02 05:40:26 PM PDT 24
Finished Aug 02 06:19:41 PM PDT 24
Peak memory 288384 kb
Host smart-409fc438-181e-4337-b840-8fa18b3893a8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938330480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.3938330480
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.4206529617
Short name T694
Test name
Test status
Simulation time 175799119 ps
CPU time 9.67 seconds
Started Aug 02 05:40:26 PM PDT 24
Finished Aug 02 05:40:36 PM PDT 24
Peak memory 248360 kb
Host smart-eba51f50-bcef-4eaa-a5ed-53c78674d82e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4206529617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.4206529617
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.1983695522
Short name T674
Test name
Test status
Simulation time 4163640294 ps
CPU time 96.15 seconds
Started Aug 02 05:40:27 PM PDT 24
Finished Aug 02 05:42:03 PM PDT 24
Peak memory 256592 kb
Host smart-b4510cc0-a44a-49b1-9a73-487cd41a47f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19836
95522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.1983695522
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.2081745390
Short name T647
Test name
Test status
Simulation time 965269454 ps
CPU time 14.52 seconds
Started Aug 02 05:40:22 PM PDT 24
Finished Aug 02 05:40:36 PM PDT 24
Peak memory 247908 kb
Host smart-e8e55077-fa39-4a1d-a688-c7e897b98d59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20817
45390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.2081745390
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.2982674740
Short name T312
Test name
Test status
Simulation time 38825025992 ps
CPU time 2222.67 seconds
Started Aug 02 05:40:33 PM PDT 24
Finished Aug 02 06:17:36 PM PDT 24
Peak memory 288776 kb
Host smart-63f0a3e9-4579-400c-a4a1-6196a68f3849
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982674740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.2982674740
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.2693457260
Short name T300
Test name
Test status
Simulation time 55266367344 ps
CPU time 3261.9 seconds
Started Aug 02 05:40:25 PM PDT 24
Finished Aug 02 06:34:47 PM PDT 24
Peak memory 288680 kb
Host smart-e971539c-2c25-4a9b-87cc-97fbedb8709d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693457260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.2693457260
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.2766059835
Short name T321
Test name
Test status
Simulation time 45803110164 ps
CPU time 510.12 seconds
Started Aug 02 05:40:33 PM PDT 24
Finished Aug 02 05:49:04 PM PDT 24
Peak memory 248256 kb
Host smart-b1b03a9c-a68c-4cb7-9289-7a2f1e7e70ab
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766059835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.2766059835
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.2325179866
Short name T437
Test name
Test status
Simulation time 784816419 ps
CPU time 51.5 seconds
Started Aug 02 05:40:26 PM PDT 24
Finished Aug 02 05:41:18 PM PDT 24
Peak memory 248352 kb
Host smart-d534cbe5-9db5-4063-86c7-ee54bc69e633
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23251
79866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.2325179866
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.1792451095
Short name T78
Test name
Test status
Simulation time 2016509563 ps
CPU time 28.69 seconds
Started Aug 02 05:40:26 PM PDT 24
Finished Aug 02 05:40:55 PM PDT 24
Peak memory 248312 kb
Host smart-4ed17c0c-4501-4afa-a856-e36912bca87c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17924
51095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.1792451095
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.1221052292
Short name T600
Test name
Test status
Simulation time 1085926886 ps
CPU time 20.78 seconds
Started Aug 02 05:40:22 PM PDT 24
Finished Aug 02 05:40:43 PM PDT 24
Peak memory 254728 kb
Host smart-9866110c-3136-4293-960e-beab10facea6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12210
52292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.1221052292
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.474604490
Short name T398
Test name
Test status
Simulation time 185549889 ps
CPU time 12.68 seconds
Started Aug 02 05:40:27 PM PDT 24
Finished Aug 02 05:40:40 PM PDT 24
Peak memory 248360 kb
Host smart-35b8174b-be05-436d-8804-13642ee3d7a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47460
4490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.474604490
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.3916661550
Short name T261
Test name
Test status
Simulation time 21567078999 ps
CPU time 1978.28 seconds
Started Aug 02 05:40:24 PM PDT 24
Finished Aug 02 06:13:22 PM PDT 24
Peak memory 298152 kb
Host smart-2f615935-d845-4811-9cc8-a10512aaf320
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916661550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.3916661550
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.1189992154
Short name T126
Test name
Test status
Simulation time 32504183970 ps
CPU time 2512.54 seconds
Started Aug 02 05:40:33 PM PDT 24
Finished Aug 02 06:22:26 PM PDT 24
Peak memory 288816 kb
Host smart-26f2af97-bf97-4929-b3df-a1c8d8773809
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189992154 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.1189992154
Directory /workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.2025748447
Short name T485
Test name
Test status
Simulation time 607747420867 ps
CPU time 2989.09 seconds
Started Aug 02 05:40:24 PM PDT 24
Finished Aug 02 06:30:13 PM PDT 24
Peak memory 289356 kb
Host smart-0e5d3591-7abb-48fb-afaa-090656e97e52
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025748447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.2025748447
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.2562793879
Short name T633
Test name
Test status
Simulation time 562038303 ps
CPU time 27.79 seconds
Started Aug 02 05:40:42 PM PDT 24
Finished Aug 02 05:41:10 PM PDT 24
Peak memory 248312 kb
Host smart-c17213aa-f000-495a-9d10-775764190dd7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2562793879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.2562793879
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.2813301326
Short name T691
Test name
Test status
Simulation time 987561588 ps
CPU time 88.73 seconds
Started Aug 02 05:40:23 PM PDT 24
Finished Aug 02 05:41:52 PM PDT 24
Peak memory 256500 kb
Host smart-ed2a09a7-c0a0-47bc-8ae7-ec9230e63dc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28133
01326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.2813301326
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.4047425516
Short name T443
Test name
Test status
Simulation time 237127817 ps
CPU time 20.86 seconds
Started Aug 02 05:40:34 PM PDT 24
Finished Aug 02 05:40:56 PM PDT 24
Peak memory 256372 kb
Host smart-95705ecd-b9b6-4cf2-844f-50040560df06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40474
25516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.4047425516
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.345781892
Short name T336
Test name
Test status
Simulation time 180686863187 ps
CPU time 2086.28 seconds
Started Aug 02 05:40:32 PM PDT 24
Finished Aug 02 06:15:19 PM PDT 24
Peak memory 272240 kb
Host smart-a063ca27-1f77-4dc2-975d-dbe90b1b0efa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345781892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.345781892
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.2224913495
Short name T650
Test name
Test status
Simulation time 40776839617 ps
CPU time 2451.36 seconds
Started Aug 02 05:40:23 PM PDT 24
Finished Aug 02 06:21:15 PM PDT 24
Peak memory 284864 kb
Host smart-a7300f05-ab74-4e52-b7cf-dd85914dbeb3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224913495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.2224913495
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.1338259444
Short name T577
Test name
Test status
Simulation time 400292324 ps
CPU time 23.63 seconds
Started Aug 02 05:40:25 PM PDT 24
Finished Aug 02 05:40:49 PM PDT 24
Peak memory 248336 kb
Host smart-0e14147e-ebfa-4b4a-bac4-80e70b8bd81f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13382
59444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.1338259444
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.2596182430
Short name T576
Test name
Test status
Simulation time 1175896624 ps
CPU time 27.92 seconds
Started Aug 02 05:40:32 PM PDT 24
Finished Aug 02 05:41:00 PM PDT 24
Peak memory 248356 kb
Host smart-59812bea-2516-4393-af13-32f7684799c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25961
82430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.2596182430
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.508110399
Short name T83
Test name
Test status
Simulation time 123103998 ps
CPU time 13.17 seconds
Started Aug 02 05:40:25 PM PDT 24
Finished Aug 02 05:40:38 PM PDT 24
Peak memory 247656 kb
Host smart-dc149373-fc91-43f9-b9d4-76a100f51f90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50811
0399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.508110399
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.2382013790
Short name T70
Test name
Test status
Simulation time 423437619 ps
CPU time 28.8 seconds
Started Aug 02 05:40:23 PM PDT 24
Finished Aug 02 05:40:52 PM PDT 24
Peak memory 256532 kb
Host smart-5f994b78-5693-4ca0-9334-07c285ac8839
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23820
13790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.2382013790
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.1690055630
Short name T216
Test name
Test status
Simulation time 315785755274 ps
CPU time 3208.69 seconds
Started Aug 02 05:40:41 PM PDT 24
Finished Aug 02 06:34:10 PM PDT 24
Peak memory 301644 kb
Host smart-1a6b73ce-bd94-4e3f-9fcc-88bda5fd1211
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690055630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.1690055630
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.3795546492
Short name T118
Test name
Test status
Simulation time 78690871931 ps
CPU time 8422.33 seconds
Started Aug 02 05:40:39 PM PDT 24
Finished Aug 02 08:01:02 PM PDT 24
Peak memory 393828 kb
Host smart-3cd60867-095f-46cb-99e6-708378e41bf8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795546492 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.3795546492
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.785151858
Short name T68
Test name
Test status
Simulation time 109758743 ps
CPU time 3.35 seconds
Started Aug 02 05:40:39 PM PDT 24
Finished Aug 02 05:40:42 PM PDT 24
Peak memory 248640 kb
Host smart-16f3a762-16bb-41b1-8cdf-bd663a096012
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=785151858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.785151858
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.3192217428
Short name T699
Test name
Test status
Simulation time 37295599433 ps
CPU time 815.33 seconds
Started Aug 02 05:40:39 PM PDT 24
Finished Aug 02 05:54:14 PM PDT 24
Peak memory 264816 kb
Host smart-702d4a66-e309-4c5a-9e0e-217e40c9c8cb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192217428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.3192217428
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.3380894906
Short name T255
Test name
Test status
Simulation time 3767902423 ps
CPU time 44.26 seconds
Started Aug 02 05:40:42 PM PDT 24
Finished Aug 02 05:41:26 PM PDT 24
Peak memory 248368 kb
Host smart-33b6c47a-70a0-4ee1-84ff-d54d4a554982
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3380894906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.3380894906
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.703370438
Short name T376
Test name
Test status
Simulation time 1553620921 ps
CPU time 35.15 seconds
Started Aug 02 05:40:40 PM PDT 24
Finished Aug 02 05:41:15 PM PDT 24
Peak memory 247748 kb
Host smart-cd9b830c-d8db-4f26-b554-10860b3f9f3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70337
0438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.703370438
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.3495095690
Short name T580
Test name
Test status
Simulation time 50017276 ps
CPU time 6.03 seconds
Started Aug 02 05:40:41 PM PDT 24
Finished Aug 02 05:40:47 PM PDT 24
Peak memory 254516 kb
Host smart-28bc203c-be0c-4b90-8720-c82c374d6da7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34950
95690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.3495095690
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.767129902
Short name T249
Test name
Test status
Simulation time 86618655668 ps
CPU time 1590.46 seconds
Started Aug 02 05:40:41 PM PDT 24
Finished Aug 02 06:07:12 PM PDT 24
Peak memory 272344 kb
Host smart-c543c12b-ba12-4466-85ce-828b66ffe7c6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767129902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.767129902
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.4090362550
Short name T505
Test name
Test status
Simulation time 29332929279 ps
CPU time 1745.92 seconds
Started Aug 02 05:40:41 PM PDT 24
Finished Aug 02 06:09:47 PM PDT 24
Peak memory 272744 kb
Host smart-0d7da1ff-4b88-4ee0-85da-21c3ace70ded
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090362550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.4090362550
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.1100715999
Short name T375
Test name
Test status
Simulation time 406502675 ps
CPU time 34.5 seconds
Started Aug 02 05:40:40 PM PDT 24
Finished Aug 02 05:41:15 PM PDT 24
Peak memory 248312 kb
Host smart-cabc58cf-c8cd-4ce2-b5ef-f5d5f5cdbb6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11007
15999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.1100715999
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.3161066377
Short name T302
Test name
Test status
Simulation time 880852665 ps
CPU time 55.68 seconds
Started Aug 02 05:40:41 PM PDT 24
Finished Aug 02 05:41:37 PM PDT 24
Peak memory 249420 kb
Host smart-7c0d1c4e-cb0b-49cc-a6b4-587d28372d6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31610
66377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.3161066377
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.2662418571
Short name T89
Test name
Test status
Simulation time 777118274 ps
CPU time 55.85 seconds
Started Aug 02 05:40:40 PM PDT 24
Finished Aug 02 05:41:36 PM PDT 24
Peak memory 249444 kb
Host smart-a2186b13-5082-4ef2-861b-bc45cce97f8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26624
18571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.2662418571
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.758497284
Short name T489
Test name
Test status
Simulation time 2209025378 ps
CPU time 57.51 seconds
Started Aug 02 05:40:41 PM PDT 24
Finished Aug 02 05:41:38 PM PDT 24
Peak memory 256584 kb
Host smart-be572934-d3af-4610-ae58-8b9ad9ea3c81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75849
7284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.758497284
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.3315677264
Short name T34
Test name
Test status
Simulation time 53373775118 ps
CPU time 1264.27 seconds
Started Aug 02 05:40:41 PM PDT 24
Finished Aug 02 06:01:46 PM PDT 24
Peak memory 287860 kb
Host smart-cea7bfa2-58d6-4504-8fa4-43deadd7bb95
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315677264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.3315677264
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.3084914334
Short name T238
Test name
Test status
Simulation time 180697680 ps
CPU time 3.83 seconds
Started Aug 02 05:39:42 PM PDT 24
Finished Aug 02 05:39:45 PM PDT 24
Peak memory 248676 kb
Host smart-93c68f18-e103-49af-bd6e-4c189e62674a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3084914334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.3084914334
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.1204147442
Short name T428
Test name
Test status
Simulation time 226816641 ps
CPU time 10.43 seconds
Started Aug 02 05:39:45 PM PDT 24
Finished Aug 02 05:39:55 PM PDT 24
Peak memory 248360 kb
Host smart-6c8d396f-8c33-40da-9790-75767c79ba68
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1204147442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.1204147442
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.3303192638
Short name T40
Test name
Test status
Simulation time 4911831727 ps
CPU time 78.18 seconds
Started Aug 02 05:39:36 PM PDT 24
Finished Aug 02 05:40:55 PM PDT 24
Peak memory 249364 kb
Host smart-d2529302-f264-4968-9025-45bf2c99ca1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33031
92638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.3303192638
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.966850819
Short name T494
Test name
Test status
Simulation time 1613827710 ps
CPU time 35.15 seconds
Started Aug 02 05:39:37 PM PDT 24
Finished Aug 02 05:40:13 PM PDT 24
Peak memory 248208 kb
Host smart-cd96e367-fab1-4ecf-826b-6a053e26c49f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96685
0819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.966850819
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.1518470815
Short name T631
Test name
Test status
Simulation time 31961884081 ps
CPU time 720.77 seconds
Started Aug 02 05:39:46 PM PDT 24
Finished Aug 02 05:51:47 PM PDT 24
Peak memory 272312 kb
Host smart-4fb076f9-320e-422f-aa4a-cf1152e5c94e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518470815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.1518470815
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.998913509
Short name T605
Test name
Test status
Simulation time 61488529288 ps
CPU time 2167.85 seconds
Started Aug 02 05:39:43 PM PDT 24
Finished Aug 02 06:15:51 PM PDT 24
Peak memory 287256 kb
Host smart-40e8d6ba-d9ec-4687-b74a-f1153d7b3c68
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998913509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.998913509
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.3066232306
Short name T637
Test name
Test status
Simulation time 27570839462 ps
CPU time 667.22 seconds
Started Aug 02 05:39:47 PM PDT 24
Finished Aug 02 05:50:54 PM PDT 24
Peak memory 248408 kb
Host smart-6b700edd-c25e-4bc6-be0e-6e3f6ea91064
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066232306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.3066232306
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.1594001091
Short name T538
Test name
Test status
Simulation time 1096518486 ps
CPU time 70.48 seconds
Started Aug 02 05:39:43 PM PDT 24
Finished Aug 02 05:40:53 PM PDT 24
Peak memory 256472 kb
Host smart-1cab85d5-b9b4-4ad5-90b0-d5ef928ac398
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15940
01091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.1594001091
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.3636059282
Short name T564
Test name
Test status
Simulation time 1795921646 ps
CPU time 38.46 seconds
Started Aug 02 05:39:35 PM PDT 24
Finished Aug 02 05:40:14 PM PDT 24
Peak memory 248224 kb
Host smart-ab7341cc-1574-4ca9-aaac-04dd4a7ea59b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36360
59282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.3636059282
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.950849878
Short name T9
Test name
Test status
Simulation time 441238984 ps
CPU time 14.12 seconds
Started Aug 02 05:39:44 PM PDT 24
Finished Aug 02 05:39:58 PM PDT 24
Peak memory 269468 kb
Host smart-f8557d8d-1b0d-4629-b108-cc60904129d0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=950849878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.950849878
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.1737002661
Short name T640
Test name
Test status
Simulation time 197414311364 ps
CPU time 1977.15 seconds
Started Aug 02 05:39:44 PM PDT 24
Finished Aug 02 06:12:41 PM PDT 24
Peak memory 281268 kb
Host smart-7bf794d4-3f2b-4695-acf5-daca6e794bd5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737002661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.1737002661
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.2474346243
Short name T473
Test name
Test status
Simulation time 108783323 ps
CPU time 9.76 seconds
Started Aug 02 05:40:54 PM PDT 24
Finished Aug 02 05:41:04 PM PDT 24
Peak memory 254604 kb
Host smart-e7e80517-712b-47d0-8634-5a0aed523bba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24743
46243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.2474346243
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.142333997
Short name T103
Test name
Test status
Simulation time 1347162560 ps
CPU time 28.48 seconds
Started Aug 02 05:40:44 PM PDT 24
Finished Aug 02 05:41:12 PM PDT 24
Peak memory 248040 kb
Host smart-78aced96-07ea-43e3-8c40-10556e39a80b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14233
3997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.142333997
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.736302078
Short name T353
Test name
Test status
Simulation time 45857656013 ps
CPU time 969.04 seconds
Started Aug 02 05:40:57 PM PDT 24
Finished Aug 02 05:57:06 PM PDT 24
Peak memory 266968 kb
Host smart-cda93518-cbea-45db-948f-25dcbbb043ab
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736302078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.736302078
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.2585170989
Short name T563
Test name
Test status
Simulation time 67188612058 ps
CPU time 2065.74 seconds
Started Aug 02 05:40:44 PM PDT 24
Finished Aug 02 06:15:10 PM PDT 24
Peak memory 272216 kb
Host smart-64daa8cf-9db1-413f-901f-df84ac2aea01
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585170989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.2585170989
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.2192778256
Short name T344
Test name
Test status
Simulation time 27590284176 ps
CPU time 429.98 seconds
Started Aug 02 05:40:48 PM PDT 24
Finished Aug 02 05:47:58 PM PDT 24
Peak memory 248436 kb
Host smart-16f13119-e383-48fb-a90b-046c3d0729bb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192778256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.2192778256
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.1301748238
Short name T497
Test name
Test status
Simulation time 541457419 ps
CPU time 31.07 seconds
Started Aug 02 05:40:44 PM PDT 24
Finished Aug 02 05:41:16 PM PDT 24
Peak memory 248368 kb
Host smart-c7d94492-b773-499c-a00d-342e9983133c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13017
48238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.1301748238
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.98522706
Short name T396
Test name
Test status
Simulation time 535767751 ps
CPU time 22.28 seconds
Started Aug 02 05:40:39 PM PDT 24
Finished Aug 02 05:41:02 PM PDT 24
Peak memory 256048 kb
Host smart-bbacfa31-e22d-4fd0-81ac-d67ac87ece55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98522
706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.98522706
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.3878201676
Short name T412
Test name
Test status
Simulation time 2224889641 ps
CPU time 32.43 seconds
Started Aug 02 05:40:42 PM PDT 24
Finished Aug 02 05:41:14 PM PDT 24
Peak memory 248488 kb
Host smart-90f0ebe8-a82d-481f-b738-2388d6b02396
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38782
01676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.3878201676
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.796421552
Short name T664
Test name
Test status
Simulation time 4172513238 ps
CPU time 68.95 seconds
Started Aug 02 05:40:42 PM PDT 24
Finished Aug 02 05:41:51 PM PDT 24
Peak memory 249688 kb
Host smart-147551d2-d012-4717-840f-81f86547cc20
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796421552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_han
dler_stress_all.796421552
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.1505582697
Short name T390
Test name
Test status
Simulation time 178601811837 ps
CPU time 2859.96 seconds
Started Aug 02 05:40:45 PM PDT 24
Finished Aug 02 06:28:25 PM PDT 24
Peak memory 288968 kb
Host smart-29d4bc98-d885-4027-ab36-bf56fb5e197d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505582697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.1505582697
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.4160926031
Short name T244
Test name
Test status
Simulation time 2659798181 ps
CPU time 160.97 seconds
Started Aug 02 05:40:48 PM PDT 24
Finished Aug 02 05:43:29 PM PDT 24
Peak memory 256656 kb
Host smart-3db31b0e-da53-4fa2-ae25-56db5a7670e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41609
26031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.4160926031
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.1482211041
Short name T76
Test name
Test status
Simulation time 668161179 ps
CPU time 11.73 seconds
Started Aug 02 05:40:48 PM PDT 24
Finished Aug 02 05:41:00 PM PDT 24
Peak memory 247704 kb
Host smart-e1add91d-063e-44d9-aefd-4768f5d09349
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14822
11041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.1482211041
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.440611748
Short name T584
Test name
Test status
Simulation time 147509224876 ps
CPU time 1357.38 seconds
Started Aug 02 05:40:41 PM PDT 24
Finished Aug 02 06:03:19 PM PDT 24
Peak memory 282532 kb
Host smart-c5a20494-455b-415f-a6a2-1491ab3b1732
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440611748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.440611748
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.3195207259
Short name T438
Test name
Test status
Simulation time 14815869469 ps
CPU time 1370.94 seconds
Started Aug 02 05:40:42 PM PDT 24
Finished Aug 02 06:03:33 PM PDT 24
Peak memory 288544 kb
Host smart-30dacabe-7392-4952-83a1-e054f7d7fae1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195207259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.3195207259
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.1436324298
Short name T585
Test name
Test status
Simulation time 218592487 ps
CPU time 10.89 seconds
Started Aug 02 05:40:57 PM PDT 24
Finished Aug 02 05:41:08 PM PDT 24
Peak memory 248420 kb
Host smart-627d7a5d-1a1b-49dc-a7df-0bcda01cc021
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14363
24298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.1436324298
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.2340792538
Short name T411
Test name
Test status
Simulation time 2992059413 ps
CPU time 55.3 seconds
Started Aug 02 05:40:43 PM PDT 24
Finished Aug 02 05:41:38 PM PDT 24
Peak memory 248188 kb
Host smart-92c2a61f-7bb6-4e42-b30a-2d22719f1be1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23407
92538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.2340792538
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.3320131663
Short name T575
Test name
Test status
Simulation time 830987551 ps
CPU time 51.94 seconds
Started Aug 02 05:40:56 PM PDT 24
Finished Aug 02 05:41:49 PM PDT 24
Peak memory 256216 kb
Host smart-844008c4-e788-4a30-8a9a-c37fc93962f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33201
31663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.3320131663
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.2908584279
Short name T418
Test name
Test status
Simulation time 3095364409 ps
CPU time 28.96 seconds
Started Aug 02 05:40:42 PM PDT 24
Finished Aug 02 05:41:12 PM PDT 24
Peak memory 255612 kb
Host smart-90b11c5f-954b-4de1-a43c-5026e3f62a2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29085
84279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.2908584279
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.2423826651
Short name T119
Test name
Test status
Simulation time 42453641901 ps
CPU time 2818.3 seconds
Started Aug 02 05:40:44 PM PDT 24
Finished Aug 02 06:27:43 PM PDT 24
Peak memory 299928 kb
Host smart-7ebbfbe8-a8ed-4287-a0cc-54a52dbf02a2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423826651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.2423826651
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.3969084362
Short name T693
Test name
Test status
Simulation time 145549379044 ps
CPU time 2064.21 seconds
Started Aug 02 05:40:42 PM PDT 24
Finished Aug 02 06:15:07 PM PDT 24
Peak memory 288472 kb
Host smart-af793482-e408-4484-809e-d51884c28ce9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969084362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.3969084362
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.2277938892
Short name T624
Test name
Test status
Simulation time 3155985241 ps
CPU time 213.21 seconds
Started Aug 02 05:40:55 PM PDT 24
Finished Aug 02 05:44:29 PM PDT 24
Peak memory 256660 kb
Host smart-64f93216-5164-427b-a66b-f87039dcdeb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22779
38892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.2277938892
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.4111293119
Short name T609
Test name
Test status
Simulation time 177799679 ps
CPU time 16.65 seconds
Started Aug 02 05:40:57 PM PDT 24
Finished Aug 02 05:41:13 PM PDT 24
Peak memory 247956 kb
Host smart-5c18a7a2-08ba-48fd-8d3c-25a35215ebef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41112
93119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.4111293119
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.1990125930
Short name T430
Test name
Test status
Simulation time 42678122513 ps
CPU time 977.89 seconds
Started Aug 02 05:40:51 PM PDT 24
Finished Aug 02 05:57:09 PM PDT 24
Peak memory 272460 kb
Host smart-9537311b-0742-479a-a47b-e267204ffee1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990125930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.1990125930
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.2006140841
Short name T408
Test name
Test status
Simulation time 54996968638 ps
CPU time 3075.88 seconds
Started Aug 02 05:40:54 PM PDT 24
Finished Aug 02 06:32:10 PM PDT 24
Peak memory 289348 kb
Host smart-a7b1690c-f5ed-4edf-8ad1-a9ebd03f3b68
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006140841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.2006140841
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.3734468708
Short name T317
Test name
Test status
Simulation time 32927651406 ps
CPU time 366.68 seconds
Started Aug 02 05:40:42 PM PDT 24
Finished Aug 02 05:46:49 PM PDT 24
Peak memory 254264 kb
Host smart-53181826-d461-4dea-924b-e9b32fd2e8bb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734468708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.3734468708
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.14292390
Short name T69
Test name
Test status
Simulation time 1834952284 ps
CPU time 15.63 seconds
Started Aug 02 05:40:42 PM PDT 24
Finished Aug 02 05:40:58 PM PDT 24
Peak memory 255220 kb
Host smart-97692d0b-07ee-4dc7-b62c-42473964f338
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14292
390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.14292390
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.1827062394
Short name T57
Test name
Test status
Simulation time 293773926 ps
CPU time 14.27 seconds
Started Aug 02 05:40:41 PM PDT 24
Finished Aug 02 05:40:56 PM PDT 24
Peak memory 247780 kb
Host smart-d4b25ed7-1d66-441f-9735-1091a19a4e20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18270
62394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.1827062394
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.2863863634
Short name T524
Test name
Test status
Simulation time 8791849546 ps
CPU time 50.12 seconds
Started Aug 02 05:40:42 PM PDT 24
Finished Aug 02 05:41:32 PM PDT 24
Peak memory 248888 kb
Host smart-89999c3d-75b8-403f-8a43-7b1578c7db29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28638
63634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.2863863634
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.3312980972
Short name T109
Test name
Test status
Simulation time 46572809757 ps
CPU time 2733.65 seconds
Started Aug 02 05:40:55 PM PDT 24
Finished Aug 02 06:26:29 PM PDT 24
Peak memory 288540 kb
Host smart-7ed4af72-9e76-41d1-815c-06ac095e84be
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312980972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.3312980972
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all_with_rand_reset.2424949434
Short name T204
Test name
Test status
Simulation time 78631268674 ps
CPU time 3920.28 seconds
Started Aug 02 05:40:47 PM PDT 24
Finished Aug 02 06:46:08 PM PDT 24
Peak memory 297760 kb
Host smart-078502af-9d87-4ffa-9ed8-48c8b9960d72
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424949434 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.alert_handler_stress_all_with_rand_reset.2424949434
Directory /workspace/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.3349268507
Short name T617
Test name
Test status
Simulation time 22085010210 ps
CPU time 978.73 seconds
Started Aug 02 05:40:47 PM PDT 24
Finished Aug 02 05:57:06 PM PDT 24
Peak memory 281640 kb
Host smart-154c4173-71eb-4a95-8712-1d864e696b07
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349268507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.3349268507
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.423014726
Short name T520
Test name
Test status
Simulation time 2438986347 ps
CPU time 127.66 seconds
Started Aug 02 05:40:48 PM PDT 24
Finished Aug 02 05:42:56 PM PDT 24
Peak memory 256224 kb
Host smart-da4fc5cc-913d-40bb-8c71-4e961d2e0461
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42301
4726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.423014726
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.3674749128
Short name T35
Test name
Test status
Simulation time 8107210211 ps
CPU time 58.94 seconds
Started Aug 02 05:40:49 PM PDT 24
Finished Aug 02 05:41:48 PM PDT 24
Peak memory 248420 kb
Host smart-3648cfe9-2fb5-46e3-a0d8-75b025cb75f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36747
49128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.3674749128
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.3200228317
Short name T16
Test name
Test status
Simulation time 10751997347 ps
CPU time 1150.16 seconds
Started Aug 02 05:40:55 PM PDT 24
Finished Aug 02 06:00:05 PM PDT 24
Peak memory 272296 kb
Host smart-71704cfd-f5cb-4d15-8c1b-ba4ec6d0bdb9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200228317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.3200228317
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.2280529928
Short name T389
Test name
Test status
Simulation time 108256826022 ps
CPU time 1836.88 seconds
Started Aug 02 05:40:55 PM PDT 24
Finished Aug 02 06:11:32 PM PDT 24
Peak memory 288324 kb
Host smart-210093e0-f0f5-4a36-94da-eb113ab73c84
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280529928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.2280529928
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.3079316306
Short name T345
Test name
Test status
Simulation time 12382258235 ps
CPU time 531.36 seconds
Started Aug 02 05:40:48 PM PDT 24
Finished Aug 02 05:49:39 PM PDT 24
Peak memory 248408 kb
Host smart-50054eb1-768c-4ac5-a76a-118c31e8ee3c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079316306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.3079316306
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.3538156224
Short name T671
Test name
Test status
Simulation time 4928656600 ps
CPU time 82.6 seconds
Started Aug 02 05:40:53 PM PDT 24
Finished Aug 02 05:42:16 PM PDT 24
Peak memory 256528 kb
Host smart-2feddf46-c0eb-4876-870c-17bc1b978896
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35381
56224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.3538156224
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.3474795098
Short name T55
Test name
Test status
Simulation time 218076761 ps
CPU time 11.64 seconds
Started Aug 02 05:40:50 PM PDT 24
Finished Aug 02 05:41:02 PM PDT 24
Peak memory 247696 kb
Host smart-effd5fb0-c760-46a2-8df2-0492e76764c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34747
95098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.3474795098
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.316739450
Short name T703
Test name
Test status
Simulation time 292075001 ps
CPU time 18.93 seconds
Started Aug 02 05:40:49 PM PDT 24
Finished Aug 02 05:41:08 PM PDT 24
Peak memory 255240 kb
Host smart-8058e081-8e0e-477c-a218-a5a82cab81a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31673
9450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.316739450
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.2032246657
Short name T525
Test name
Test status
Simulation time 54767019078 ps
CPU time 3113.44 seconds
Started Aug 02 05:40:58 PM PDT 24
Finished Aug 02 06:32:52 PM PDT 24
Peak memory 287416 kb
Host smart-99df7753-7358-4530-9e13-d68441a8c611
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032246657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.2032246657
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.2374351844
Short name T492
Test name
Test status
Simulation time 4385428530 ps
CPU time 174.23 seconds
Started Aug 02 05:40:54 PM PDT 24
Finished Aug 02 05:43:49 PM PDT 24
Peak memory 256540 kb
Host smart-4121c3b3-6503-4d7c-9376-3380d23f8115
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23743
51844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.2374351844
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.3380689137
Short name T653
Test name
Test status
Simulation time 913231674 ps
CPU time 47.79 seconds
Started Aug 02 05:40:52 PM PDT 24
Finished Aug 02 05:41:40 PM PDT 24
Peak memory 255932 kb
Host smart-9465e2b1-b3ea-424b-9bf4-adda245ab922
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33806
89137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.3380689137
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.1171532116
Short name T539
Test name
Test status
Simulation time 43857802903 ps
CPU time 2516.14 seconds
Started Aug 02 05:40:58 PM PDT 24
Finished Aug 02 06:22:54 PM PDT 24
Peak memory 283932 kb
Host smart-cdbdd469-ca31-406a-8f60-b6931d5fa60e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171532116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.1171532116
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.1615451986
Short name T682
Test name
Test status
Simulation time 33288883085 ps
CPU time 2387.47 seconds
Started Aug 02 05:40:57 PM PDT 24
Finished Aug 02 06:20:45 PM PDT 24
Peak memory 289260 kb
Host smart-c338858b-b373-404d-b883-69dff2bedb81
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615451986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.1615451986
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.3479431163
Short name T325
Test name
Test status
Simulation time 9055568752 ps
CPU time 202.54 seconds
Started Aug 02 05:40:58 PM PDT 24
Finished Aug 02 05:44:21 PM PDT 24
Peak memory 248244 kb
Host smart-fb0eb43e-6168-4371-9cb1-f4e89e2e4f46
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479431163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.3479431163
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.1659154517
Short name T593
Test name
Test status
Simulation time 1872185001 ps
CPU time 65.45 seconds
Started Aug 02 05:40:48 PM PDT 24
Finished Aug 02 05:41:53 PM PDT 24
Peak memory 255544 kb
Host smart-de308b8e-db0f-4b76-b2fd-08e045e285b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16591
54517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.1659154517
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.45537477
Short name T547
Test name
Test status
Simulation time 882842959 ps
CPU time 34.2 seconds
Started Aug 02 05:40:49 PM PDT 24
Finished Aug 02 05:41:23 PM PDT 24
Peak memory 248356 kb
Host smart-7dc6e1e6-0141-46b6-bd34-b40fd4a24ef2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45537
477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.45537477
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.762775974
Short name T461
Test name
Test status
Simulation time 459980193 ps
CPU time 29.8 seconds
Started Aug 02 05:40:50 PM PDT 24
Finished Aug 02 05:41:20 PM PDT 24
Peak memory 255868 kb
Host smart-a3e26cda-670f-4872-acd0-832ad2c1b933
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76277
5974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.762775974
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.4291044556
Short name T405
Test name
Test status
Simulation time 571107754 ps
CPU time 30.48 seconds
Started Aug 02 05:40:52 PM PDT 24
Finished Aug 02 05:41:23 PM PDT 24
Peak memory 256512 kb
Host smart-703e1ffd-be09-401a-bd2e-289b047e1bd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42910
44556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.4291044556
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.4160784382
Short name T447
Test name
Test status
Simulation time 136826200131 ps
CPU time 2243.44 seconds
Started Aug 02 05:40:58 PM PDT 24
Finished Aug 02 06:18:22 PM PDT 24
Peak memory 288200 kb
Host smart-2df87277-d2c6-4179-ab95-398c8b931cc1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160784382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.4160784382
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.4152294954
Short name T369
Test name
Test status
Simulation time 1194371553 ps
CPU time 58.63 seconds
Started Aug 02 05:40:58 PM PDT 24
Finished Aug 02 05:41:57 PM PDT 24
Peak memory 256092 kb
Host smart-38856a8e-8992-4545-9fa7-93515d45a4b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41522
94954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.4152294954
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.2355242997
Short name T387
Test name
Test status
Simulation time 326477012 ps
CPU time 32.14 seconds
Started Aug 02 05:40:57 PM PDT 24
Finished Aug 02 05:41:30 PM PDT 24
Peak memory 255696 kb
Host smart-c1d60655-da81-48d8-990e-205bc47d57c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23552
42997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.2355242997
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.3396648934
Short name T648
Test name
Test status
Simulation time 149259738793 ps
CPU time 1356.78 seconds
Started Aug 02 05:41:01 PM PDT 24
Finished Aug 02 06:03:38 PM PDT 24
Peak memory 288640 kb
Host smart-e79854ba-31d4-4910-bad0-1ee693d56003
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396648934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.3396648934
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.87585461
Short name T315
Test name
Test status
Simulation time 7427105773 ps
CPU time 319.18 seconds
Started Aug 02 05:40:56 PM PDT 24
Finished Aug 02 05:46:16 PM PDT 24
Peak memory 256604 kb
Host smart-1b6b28ce-8aee-462d-9eac-45f6bfdfbda5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87585461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.87585461
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.3172624997
Short name T685
Test name
Test status
Simulation time 751642545 ps
CPU time 52.9 seconds
Started Aug 02 05:40:58 PM PDT 24
Finished Aug 02 05:41:52 PM PDT 24
Peak memory 255524 kb
Host smart-75afd8af-8313-403c-b022-d21c877904ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31726
24997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.3172624997
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.1523311270
Short name T463
Test name
Test status
Simulation time 1075632570 ps
CPU time 27.84 seconds
Started Aug 02 05:40:58 PM PDT 24
Finished Aug 02 05:41:26 PM PDT 24
Peak memory 256480 kb
Host smart-787f37fd-5b45-4313-8579-b50830244cd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15233
11270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.1523311270
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.3932295075
Short name T115
Test name
Test status
Simulation time 515071270 ps
CPU time 27.7 seconds
Started Aug 02 05:40:58 PM PDT 24
Finished Aug 02 05:41:26 PM PDT 24
Peak memory 256604 kb
Host smart-1fdbe6b8-42f2-47d1-9956-5cc06fbcf85a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39322
95075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.3932295075
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.658528264
Short name T475
Test name
Test status
Simulation time 762288423 ps
CPU time 22.2 seconds
Started Aug 02 05:40:58 PM PDT 24
Finished Aug 02 05:41:20 PM PDT 24
Peak memory 256368 kb
Host smart-9b3ccbd7-71a5-450f-b582-1727a18b574f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65852
8264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.658528264
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.340717591
Short name T657
Test name
Test status
Simulation time 22935082576 ps
CPU time 1002.44 seconds
Started Aug 02 05:40:56 PM PDT 24
Finished Aug 02 05:57:39 PM PDT 24
Peak memory 288956 kb
Host smart-cd9835ba-984c-412c-aabe-55d8c3b62b46
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340717591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_han
dler_stress_all.340717591
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.635919965
Short name T567
Test name
Test status
Simulation time 211852965759 ps
CPU time 2121.52 seconds
Started Aug 02 05:41:07 PM PDT 24
Finished Aug 02 06:16:29 PM PDT 24
Peak memory 288404 kb
Host smart-8796e2ef-e069-4086-be0f-0cf0a7e6dc0d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635919965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.635919965
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.2252526378
Short name T303
Test name
Test status
Simulation time 808878959 ps
CPU time 13.98 seconds
Started Aug 02 05:41:07 PM PDT 24
Finished Aug 02 05:41:21 PM PDT 24
Peak memory 255644 kb
Host smart-7fe250d3-de07-4ca1-bee6-f815ebc86e37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22525
26378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.2252526378
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.781209345
Short name T378
Test name
Test status
Simulation time 864060514 ps
CPU time 60.42 seconds
Started Aug 02 05:41:12 PM PDT 24
Finished Aug 02 05:42:12 PM PDT 24
Peak memory 248128 kb
Host smart-1a7cc7a1-6349-4f1a-a531-0893d4ff19a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78120
9345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.781209345
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.483424391
Short name T348
Test name
Test status
Simulation time 19975955279 ps
CPU time 1358.75 seconds
Started Aug 02 05:41:06 PM PDT 24
Finished Aug 02 06:03:45 PM PDT 24
Peak memory 272328 kb
Host smart-c5e7da13-7e12-4c57-a4ca-8031bbc1ac03
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483424391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.483424391
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.769016575
Short name T444
Test name
Test status
Simulation time 34593337558 ps
CPU time 2300.47 seconds
Started Aug 02 05:41:06 PM PDT 24
Finished Aug 02 06:19:27 PM PDT 24
Peak memory 287508 kb
Host smart-1ef7c6f4-71c0-4865-86fb-7fe452fdac56
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769016575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.769016575
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.3021698829
Short name T574
Test name
Test status
Simulation time 729695316 ps
CPU time 19.78 seconds
Started Aug 02 05:40:57 PM PDT 24
Finished Aug 02 05:41:17 PM PDT 24
Peak memory 255908 kb
Host smart-16d4b45a-697b-4a94-9e70-7117c2de6ecb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30216
98829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.3021698829
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.3629647882
Short name T641
Test name
Test status
Simulation time 1388933836 ps
CPU time 21.94 seconds
Started Aug 02 05:41:03 PM PDT 24
Finished Aug 02 05:41:25 PM PDT 24
Peak memory 256292 kb
Host smart-4110081c-57ad-4054-b337-73889ca1ec50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36296
47882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.3629647882
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.4166230697
Short name T516
Test name
Test status
Simulation time 779753623 ps
CPU time 43.92 seconds
Started Aug 02 05:41:01 PM PDT 24
Finished Aug 02 05:41:45 PM PDT 24
Peak memory 248280 kb
Host smart-2a2a891f-bcb2-4fed-bd0a-34033b79cf55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41662
30697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.4166230697
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.2075163668
Short name T130
Test name
Test status
Simulation time 70818157422 ps
CPU time 2283.76 seconds
Started Aug 02 05:41:05 PM PDT 24
Finished Aug 02 06:19:09 PM PDT 24
Peak memory 289324 kb
Host smart-bde2557b-42da-44ce-b544-5614d66fc433
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075163668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.2075163668
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all_with_rand_reset.2559534053
Short name T205
Test name
Test status
Simulation time 119365120027 ps
CPU time 3932.39 seconds
Started Aug 02 05:41:05 PM PDT 24
Finished Aug 02 06:46:38 PM PDT 24
Peak memory 332900 kb
Host smart-363de358-0c7b-48fb-99d1-603c7d5b00a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559534053 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.alert_handler_stress_all_with_rand_reset.2559534053
Directory /workspace/26.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.2538521498
Short name T431
Test name
Test status
Simulation time 23837209568 ps
CPU time 1411.58 seconds
Started Aug 02 05:41:03 PM PDT 24
Finished Aug 02 06:04:35 PM PDT 24
Peak memory 288800 kb
Host smart-139f791c-7a20-424e-986c-f6d40714efcc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538521498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.2538521498
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.625440610
Short name T545
Test name
Test status
Simulation time 7357162523 ps
CPU time 238.15 seconds
Started Aug 02 05:41:09 PM PDT 24
Finished Aug 02 05:45:07 PM PDT 24
Peak memory 255880 kb
Host smart-7f424a24-4a0b-4b9c-adcb-759426ee9721
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62544
0610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.625440610
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.1450010381
Short name T25
Test name
Test status
Simulation time 846636536 ps
CPU time 48.98 seconds
Started Aug 02 05:41:06 PM PDT 24
Finished Aug 02 05:41:55 PM PDT 24
Peak memory 256340 kb
Host smart-895e7f1d-03d0-4fb5-9723-852d1ce171c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14500
10381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.1450010381
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.2223550887
Short name T214
Test name
Test status
Simulation time 9364951793 ps
CPU time 915.28 seconds
Started Aug 02 05:41:12 PM PDT 24
Finished Aug 02 05:56:27 PM PDT 24
Peak memory 272876 kb
Host smart-129882f2-e343-498f-857a-274e255ae236
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223550887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.2223550887
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.593959138
Short name T512
Test name
Test status
Simulation time 13277181135 ps
CPU time 549.52 seconds
Started Aug 02 05:41:07 PM PDT 24
Finished Aug 02 05:50:17 PM PDT 24
Peak memory 248364 kb
Host smart-190c727b-b3d4-42c8-9f79-e9e92c8a70cb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593959138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.593959138
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.1114036427
Short name T42
Test name
Test status
Simulation time 9116907464 ps
CPU time 40.58 seconds
Started Aug 02 05:41:06 PM PDT 24
Finished Aug 02 05:41:47 PM PDT 24
Peak memory 256556 kb
Host smart-e36c6e61-ecc1-49d3-8bff-95ebbd4dbc5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11140
36427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.1114036427
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.2422334646
Short name T690
Test name
Test status
Simulation time 1722286343 ps
CPU time 42.01 seconds
Started Aug 02 05:41:10 PM PDT 24
Finished Aug 02 05:41:52 PM PDT 24
Peak memory 248392 kb
Host smart-18b0fc56-7265-47dd-9347-d69ddbc7c461
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24223
34646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.2422334646
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.2627898164
Short name T397
Test name
Test status
Simulation time 596979961 ps
CPU time 38.02 seconds
Started Aug 02 05:41:06 PM PDT 24
Finished Aug 02 05:41:44 PM PDT 24
Peak memory 256428 kb
Host smart-48c450f4-f10b-414d-8a0b-d97ab41316f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26278
98164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.2627898164
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.1718879142
Short name T454
Test name
Test status
Simulation time 39626730292 ps
CPU time 2344 seconds
Started Aug 02 05:41:11 PM PDT 24
Finished Aug 02 06:20:15 PM PDT 24
Peak memory 289072 kb
Host smart-20f5ea4b-6681-4594-938d-45a4ccec87a5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718879142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.1718879142
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.1381822520
Short name T555
Test name
Test status
Simulation time 50597595982 ps
CPU time 3283.58 seconds
Started Aug 02 05:41:08 PM PDT 24
Finished Aug 02 06:35:53 PM PDT 24
Peak memory 289272 kb
Host smart-796c2ad9-b14c-441d-8e05-0aa498c1656e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381822520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.1381822520
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.105866849
Short name T629
Test name
Test status
Simulation time 41137368826 ps
CPU time 213.39 seconds
Started Aug 02 05:41:05 PM PDT 24
Finished Aug 02 05:44:38 PM PDT 24
Peak memory 250644 kb
Host smart-9bc64b52-edbe-4801-a690-a20aa7798c66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10586
6849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.105866849
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.4180806208
Short name T93
Test name
Test status
Simulation time 2581266695 ps
CPU time 42.68 seconds
Started Aug 02 05:41:09 PM PDT 24
Finished Aug 02 05:41:52 PM PDT 24
Peak memory 256256 kb
Host smart-b4425105-1e3d-427c-b79b-39839d4c44ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41808
06208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.4180806208
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.3408557544
Short name T395
Test name
Test status
Simulation time 38479532201 ps
CPU time 1687.31 seconds
Started Aug 02 05:41:13 PM PDT 24
Finished Aug 02 06:09:21 PM PDT 24
Peak memory 289312 kb
Host smart-4f561117-e600-4072-81e3-74a4f4af1de0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408557544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.3408557544
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.496651206
Short name T646
Test name
Test status
Simulation time 12516647604 ps
CPU time 340.36 seconds
Started Aug 02 05:41:06 PM PDT 24
Finished Aug 02 05:46:46 PM PDT 24
Peak memory 248288 kb
Host smart-335c6290-6ae1-4b69-8eb0-fc78c227adce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496651206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.496651206
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.3010431455
Short name T661
Test name
Test status
Simulation time 295642864 ps
CPU time 15.96 seconds
Started Aug 02 05:41:06 PM PDT 24
Finished Aug 02 05:41:22 PM PDT 24
Peak memory 248340 kb
Host smart-d02dbcec-7a49-4814-8e56-daa044d6b254
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30104
31455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.3010431455
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.4175078104
Short name T460
Test name
Test status
Simulation time 320606632 ps
CPU time 21.84 seconds
Started Aug 02 05:41:10 PM PDT 24
Finished Aug 02 05:41:32 PM PDT 24
Peak memory 256136 kb
Host smart-a106c82d-ba86-495d-91be-a42bb7b4f532
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41750
78104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.4175078104
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.1971657100
Short name T607
Test name
Test status
Simulation time 301687472 ps
CPU time 23.37 seconds
Started Aug 02 05:41:09 PM PDT 24
Finished Aug 02 05:41:33 PM PDT 24
Peak memory 255560 kb
Host smart-cca7cc8a-8da7-45a0-a2a5-5ac9a1895aa2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19716
57100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.1971657100
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.1626024760
Short name T660
Test name
Test status
Simulation time 725329771 ps
CPU time 37.56 seconds
Started Aug 02 05:41:06 PM PDT 24
Finished Aug 02 05:41:44 PM PDT 24
Peak memory 256548 kb
Host smart-a9b9404a-6080-400d-95bf-468b139ff89f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16260
24760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.1626024760
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.1680078595
Short name T116
Test name
Test status
Simulation time 21056345682 ps
CPU time 954.77 seconds
Started Aug 02 05:41:15 PM PDT 24
Finished Aug 02 05:57:10 PM PDT 24
Peak memory 272696 kb
Host smart-e8c240ca-ba12-4468-8ef6-8f9b8648cb13
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680078595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.1680078595
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.3028014541
Short name T88
Test name
Test status
Simulation time 21656377916 ps
CPU time 1362.07 seconds
Started Aug 02 05:41:15 PM PDT 24
Finished Aug 02 06:03:58 PM PDT 24
Peak memory 281204 kb
Host smart-6b3ec126-2070-46eb-8264-9d3a30119834
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028014541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.3028014541
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.1249390431
Short name T565
Test name
Test status
Simulation time 4933745569 ps
CPU time 182.21 seconds
Started Aug 02 05:41:13 PM PDT 24
Finished Aug 02 05:44:15 PM PDT 24
Peak memory 256620 kb
Host smart-1a4212c1-b3a4-4509-a955-4bc63d9c1044
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12493
90431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.1249390431
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.44850674
Short name T278
Test name
Test status
Simulation time 894129222 ps
CPU time 58.84 seconds
Started Aug 02 05:41:13 PM PDT 24
Finished Aug 02 05:42:12 PM PDT 24
Peak memory 248456 kb
Host smart-2af9d489-16b9-4240-ac74-2acbff787bc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44850
674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.44850674
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.3003195639
Short name T652
Test name
Test status
Simulation time 9664621781 ps
CPU time 1146.87 seconds
Started Aug 02 05:41:15 PM PDT 24
Finished Aug 02 06:00:23 PM PDT 24
Peak memory 284012 kb
Host smart-854cf03a-8cf9-49a0-926b-b4359c279e72
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003195639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.3003195639
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.3414396165
Short name T534
Test name
Test status
Simulation time 30414357624 ps
CPU time 352.32 seconds
Started Aug 02 05:41:11 PM PDT 24
Finished Aug 02 05:47:04 PM PDT 24
Peak memory 248452 kb
Host smart-6a11fb73-26af-4805-909b-58b0ce3f0d86
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414396165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.3414396165
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.4282561671
Short name T46
Test name
Test status
Simulation time 298133716 ps
CPU time 4.39 seconds
Started Aug 02 05:41:15 PM PDT 24
Finished Aug 02 05:41:20 PM PDT 24
Peak memory 248320 kb
Host smart-b3d63564-fe02-4655-a62f-8dbb67aa82dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42825
61671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.4282561671
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.2166170248
Short name T589
Test name
Test status
Simulation time 1606324257 ps
CPU time 51.82 seconds
Started Aug 02 05:41:12 PM PDT 24
Finished Aug 02 05:42:04 PM PDT 24
Peak memory 256508 kb
Host smart-8b824963-8c6d-45d0-82d3-f99d4ce997ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21661
70248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.2166170248
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.3270738589
Short name T50
Test name
Test status
Simulation time 1476745425 ps
CPU time 52.37 seconds
Started Aug 02 05:41:14 PM PDT 24
Finished Aug 02 05:42:07 PM PDT 24
Peak memory 247856 kb
Host smart-3036e67e-3157-4bac-8cd5-b39546cf5b53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32707
38589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.3270738589
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.3635416502
Short name T596
Test name
Test status
Simulation time 816481968 ps
CPU time 35.07 seconds
Started Aug 02 05:41:14 PM PDT 24
Finished Aug 02 05:41:49 PM PDT 24
Peak memory 255572 kb
Host smart-75ecff36-9ac0-49db-b760-73948e4d2a73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36354
16502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.3635416502
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.2739169112
Short name T62
Test name
Test status
Simulation time 62183447796 ps
CPU time 3776.91 seconds
Started Aug 02 05:41:14 PM PDT 24
Finished Aug 02 06:44:12 PM PDT 24
Peak memory 297240 kb
Host smart-4b62fd78-3029-43f8-ac67-c764b3bb1d7d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739169112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.2739169112
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.340388690
Short name T432
Test name
Test status
Simulation time 15753378085 ps
CPU time 1758.3 seconds
Started Aug 02 05:41:13 PM PDT 24
Finished Aug 02 06:10:32 PM PDT 24
Peak memory 297584 kb
Host smart-8898fc01-0075-42cc-94ba-97cb5b578294
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340388690 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.340388690
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.2219772244
Short name T239
Test name
Test status
Simulation time 29954035 ps
CPU time 2.73 seconds
Started Aug 02 05:39:42 PM PDT 24
Finished Aug 02 05:39:45 PM PDT 24
Peak memory 248676 kb
Host smart-2d9378b9-96d2-49ae-95f5-1d7cbf5cfcbb
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2219772244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.2219772244
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.2176071513
Short name T606
Test name
Test status
Simulation time 42017497639 ps
CPU time 2774.77 seconds
Started Aug 02 05:39:47 PM PDT 24
Finished Aug 02 06:26:02 PM PDT 24
Peak memory 288504 kb
Host smart-a4a56890-1f0f-4fd8-b2f4-05684ebd5f36
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176071513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.2176071513
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.2932648978
Short name T257
Test name
Test status
Simulation time 300646355 ps
CPU time 9.19 seconds
Started Aug 02 05:39:46 PM PDT 24
Finished Aug 02 05:39:55 PM PDT 24
Peak memory 248312 kb
Host smart-f6de9c0d-4d38-4c22-9046-575e35af52ef
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2932648978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.2932648978
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.1806365914
Short name T500
Test name
Test status
Simulation time 954063241 ps
CPU time 61.29 seconds
Started Aug 02 05:39:42 PM PDT 24
Finished Aug 02 05:40:44 PM PDT 24
Peak memory 255888 kb
Host smart-d733f9fc-8d8e-4fe0-98d2-1a727722deb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18063
65914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.1806365914
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.1304574399
Short name T562
Test name
Test status
Simulation time 1436267392 ps
CPU time 14.73 seconds
Started Aug 02 05:39:44 PM PDT 24
Finished Aug 02 05:39:59 PM PDT 24
Peak memory 247780 kb
Host smart-6c6d5d86-3a1f-49ab-8799-7bc6a1d07ac6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13045
74399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.1304574399
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.2932281719
Short name T675
Test name
Test status
Simulation time 69269947008 ps
CPU time 2081.67 seconds
Started Aug 02 05:39:45 PM PDT 24
Finished Aug 02 06:14:27 PM PDT 24
Peak memory 284304 kb
Host smart-651407da-5fe0-45b0-b187-3e70f75aa6f6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932281719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.2932281719
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.536683940
Short name T477
Test name
Test status
Simulation time 29381606297 ps
CPU time 834.91 seconds
Started Aug 02 05:39:42 PM PDT 24
Finished Aug 02 05:53:37 PM PDT 24
Peak memory 272932 kb
Host smart-ff7c8c76-8e7a-4dfc-bb64-3fab4d3dbd9d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536683940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.536683940
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.1026722501
Short name T15
Test name
Test status
Simulation time 3616809134 ps
CPU time 71.74 seconds
Started Aug 02 05:39:45 PM PDT 24
Finished Aug 02 05:40:56 PM PDT 24
Peak memory 248424 kb
Host smart-e1f5058e-de32-45a6-a150-b72729689733
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026722501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.1026722501
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.1602558544
Short name T434
Test name
Test status
Simulation time 325163221 ps
CPU time 5.67 seconds
Started Aug 02 05:39:47 PM PDT 24
Finished Aug 02 05:39:52 PM PDT 24
Peak memory 250368 kb
Host smart-d3c156b9-167d-48d6-a838-1af31af77008
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16025
58544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.1602558544
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.1382618765
Short name T392
Test name
Test status
Simulation time 758793425 ps
CPU time 8.53 seconds
Started Aug 02 05:39:45 PM PDT 24
Finished Aug 02 05:39:54 PM PDT 24
Peak memory 247944 kb
Host smart-3b3aead3-120b-43b7-a33f-aaea6eb68498
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13826
18765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.1382618765
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.518807559
Short name T24
Test name
Test status
Simulation time 404047156 ps
CPU time 23.65 seconds
Started Aug 02 05:39:47 PM PDT 24
Finished Aug 02 05:40:11 PM PDT 24
Peak memory 248392 kb
Host smart-bbf39d19-d805-455d-9e69-1be9f983ecdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51880
7559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.518807559
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.821042597
Short name T581
Test name
Test status
Simulation time 1222088107 ps
CPU time 34.34 seconds
Started Aug 02 05:39:47 PM PDT 24
Finished Aug 02 05:40:22 PM PDT 24
Peak memory 256508 kb
Host smart-50ffbc90-88ff-4e58-ab37-0d989bff0d8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82104
2597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.821042597
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.2628679703
Short name T308
Test name
Test status
Simulation time 34374368485 ps
CPU time 1982.57 seconds
Started Aug 02 05:39:47 PM PDT 24
Finished Aug 02 06:12:50 PM PDT 24
Peak memory 289256 kb
Host smart-3bafc104-d4a0-4bb0-9646-e4f721f0c466
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628679703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.2628679703
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.220452170
Short name T81
Test name
Test status
Simulation time 70441998045 ps
CPU time 2156.22 seconds
Started Aug 02 05:41:25 PM PDT 24
Finished Aug 02 06:17:21 PM PDT 24
Peak memory 273048 kb
Host smart-c696c3fb-c383-45d7-8401-f517b601e3df
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220452170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.220452170
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.785142026
Short name T552
Test name
Test status
Simulation time 13640213842 ps
CPU time 143.51 seconds
Started Aug 02 05:41:25 PM PDT 24
Finished Aug 02 05:43:49 PM PDT 24
Peak memory 255804 kb
Host smart-7a10d505-715a-46b7-86e1-8fe94e6e5de0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78514
2026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.785142026
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.48387516
Short name T630
Test name
Test status
Simulation time 1826018861 ps
CPU time 29.47 seconds
Started Aug 02 05:41:12 PM PDT 24
Finished Aug 02 05:41:42 PM PDT 24
Peak memory 248356 kb
Host smart-86e5a60e-3bbb-4ccf-ac6e-0e81901298db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48387
516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.48387516
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.2091454103
Short name T480
Test name
Test status
Simulation time 91064451899 ps
CPU time 1316.29 seconds
Started Aug 02 05:41:19 PM PDT 24
Finished Aug 02 06:03:16 PM PDT 24
Peak memory 283504 kb
Host smart-a0ae023f-541b-458e-a2dc-457ca1ada32e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091454103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.2091454103
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.338870902
Short name T440
Test name
Test status
Simulation time 25396134481 ps
CPU time 646.52 seconds
Started Aug 02 05:41:21 PM PDT 24
Finished Aug 02 05:52:08 PM PDT 24
Peak memory 264720 kb
Host smart-6a346e80-64f1-442e-a5f2-16e8f35bb376
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338870902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.338870902
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.3583498023
Short name T293
Test name
Test status
Simulation time 4079757076 ps
CPU time 120.54 seconds
Started Aug 02 05:41:25 PM PDT 24
Finished Aug 02 05:43:25 PM PDT 24
Peak memory 248360 kb
Host smart-cab4cdf5-b397-4433-8e1c-b5b5f89b4ccc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583498023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.3583498023
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.3615361222
Short name T420
Test name
Test status
Simulation time 1580881399 ps
CPU time 30.86 seconds
Started Aug 02 05:41:14 PM PDT 24
Finished Aug 02 05:41:45 PM PDT 24
Peak memory 256128 kb
Host smart-048f5247-a832-4e29-a10b-d71e9fa9d35d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36153
61222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.3615361222
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.1912943805
Short name T529
Test name
Test status
Simulation time 2018873541 ps
CPU time 23.85 seconds
Started Aug 02 05:41:13 PM PDT 24
Finished Aug 02 05:41:37 PM PDT 24
Peak memory 248044 kb
Host smart-79c58092-dca5-4fb5-a9ae-e8fe1873745d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19129
43805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.1912943805
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.3639191477
Short name T554
Test name
Test status
Simulation time 547450252 ps
CPU time 33.44 seconds
Started Aug 02 05:41:22 PM PDT 24
Finished Aug 02 05:41:55 PM PDT 24
Peak memory 255720 kb
Host smart-9dcc627c-97ba-401f-a27d-f59b2894d224
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36391
91477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.3639191477
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.1521088115
Short name T613
Test name
Test status
Simulation time 339637620 ps
CPU time 9.93 seconds
Started Aug 02 05:41:14 PM PDT 24
Finished Aug 02 05:41:25 PM PDT 24
Peak memory 254728 kb
Host smart-ae92d85b-aa59-49ff-8ae7-9660336fd2d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15210
88115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.1521088115
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.1555171795
Short name T112
Test name
Test status
Simulation time 165926574556 ps
CPU time 2314.33 seconds
Started Aug 02 05:41:20 PM PDT 24
Finished Aug 02 06:19:55 PM PDT 24
Peak memory 288748 kb
Host smart-30a77aac-6812-4b10-8c1a-7e66e12a6e5f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555171795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.1555171795
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.499594529
Short name T573
Test name
Test status
Simulation time 1762204081 ps
CPU time 110.15 seconds
Started Aug 02 05:41:25 PM PDT 24
Finished Aug 02 05:43:15 PM PDT 24
Peak memory 256068 kb
Host smart-842d7fd2-1408-48e9-8ca2-111091cbebcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49959
4529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.499594529
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.3612773961
Short name T101
Test name
Test status
Simulation time 572408447 ps
CPU time 26.68 seconds
Started Aug 02 05:41:22 PM PDT 24
Finished Aug 02 05:41:49 PM PDT 24
Peak memory 248372 kb
Host smart-612d150f-f23a-4d25-a355-29b3b1bc4cf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36127
73961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.3612773961
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.570575016
Short name T354
Test name
Test status
Simulation time 92259841823 ps
CPU time 2806 seconds
Started Aug 02 05:41:21 PM PDT 24
Finished Aug 02 06:28:08 PM PDT 24
Peak memory 287056 kb
Host smart-fe1983d8-bc14-4c6f-a218-f7da7c3394f7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570575016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.570575016
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.2059440647
Short name T84
Test name
Test status
Simulation time 60261245004 ps
CPU time 2076.13 seconds
Started Aug 02 05:41:19 PM PDT 24
Finished Aug 02 06:15:55 PM PDT 24
Peak memory 288400 kb
Host smart-8fdc9f03-4e36-4ebb-a1fb-5a22f615e416
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059440647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.2059440647
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.582511983
Short name T335
Test name
Test status
Simulation time 6584427789 ps
CPU time 127.1 seconds
Started Aug 02 05:41:23 PM PDT 24
Finished Aug 02 05:43:30 PM PDT 24
Peak memory 247112 kb
Host smart-90a888c9-33d0-41ec-abf6-8bd3b928be01
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582511983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.582511983
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.2949240367
Short name T535
Test name
Test status
Simulation time 157722319 ps
CPU time 12.13 seconds
Started Aug 02 05:41:24 PM PDT 24
Finished Aug 02 05:41:36 PM PDT 24
Peak memory 248408 kb
Host smart-44143b74-ea15-404e-aa2d-72c6bce85bf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29492
40367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.2949240367
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.1199780575
Short name T65
Test name
Test status
Simulation time 863596224 ps
CPU time 45.97 seconds
Started Aug 02 05:41:22 PM PDT 24
Finished Aug 02 05:42:08 PM PDT 24
Peak memory 247788 kb
Host smart-ff6f6cac-8737-4cbc-8f5d-5893b92c4af3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11997
80575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.1199780575
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.747800038
Short name T61
Test name
Test status
Simulation time 6672075594 ps
CPU time 32.16 seconds
Started Aug 02 05:41:22 PM PDT 24
Finished Aug 02 05:41:55 PM PDT 24
Peak memory 256200 kb
Host smart-a46a7447-1c8f-48b1-b9a4-bff83fc1b949
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74780
0038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.747800038
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.1127159852
Short name T572
Test name
Test status
Simulation time 327041786 ps
CPU time 20.19 seconds
Started Aug 02 05:41:23 PM PDT 24
Finished Aug 02 05:41:43 PM PDT 24
Peak memory 255748 kb
Host smart-b5ec74e7-d651-4b42-a8f5-0c1f0ba895da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11271
59852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.1127159852
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.406128139
Short name T32
Test name
Test status
Simulation time 10582741531 ps
CPU time 228.33 seconds
Started Aug 02 05:41:30 PM PDT 24
Finished Aug 02 05:45:18 PM PDT 24
Peak memory 256608 kb
Host smart-847b7f12-89ed-4deb-b37c-c434e46a30b6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406128139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_han
dler_stress_all.406128139
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.2004253229
Short name T203
Test name
Test status
Simulation time 125389124114 ps
CPU time 3384.18 seconds
Started Aug 02 05:41:25 PM PDT 24
Finished Aug 02 06:37:49 PM PDT 24
Peak memory 304940 kb
Host smart-405711c6-f5de-4321-8b90-af3187cea6f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004253229 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.2004253229
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.1644217969
Short name T254
Test name
Test status
Simulation time 25432309828 ps
CPU time 1605.45 seconds
Started Aug 02 05:41:20 PM PDT 24
Finished Aug 02 06:08:06 PM PDT 24
Peak memory 272904 kb
Host smart-3557e470-e34d-4094-95f2-af44a4195273
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644217969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.1644217969
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.3563341876
Short name T698
Test name
Test status
Simulation time 1641270785 ps
CPU time 96.15 seconds
Started Aug 02 05:41:19 PM PDT 24
Finished Aug 02 05:42:55 PM PDT 24
Peak memory 256024 kb
Host smart-4b672002-dedb-4201-84fa-dd433e0926da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35633
41876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.3563341876
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.160133123
Short name T91
Test name
Test status
Simulation time 1500497557 ps
CPU time 34.81 seconds
Started Aug 02 05:41:21 PM PDT 24
Finished Aug 02 05:41:56 PM PDT 24
Peak memory 255936 kb
Host smart-1198f3d0-9b1b-4d6b-b7b4-2cac139fa2c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16013
3123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.160133123
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.998018826
Short name T623
Test name
Test status
Simulation time 44317118798 ps
CPU time 884.19 seconds
Started Aug 02 05:41:20 PM PDT 24
Finished Aug 02 05:56:05 PM PDT 24
Peak memory 272372 kb
Host smart-c210ae68-84ec-425f-b8bc-6c082a861b3a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998018826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.998018826
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.3667311230
Short name T294
Test name
Test status
Simulation time 40803723623 ps
CPU time 2759.47 seconds
Started Aug 02 05:41:21 PM PDT 24
Finished Aug 02 06:27:21 PM PDT 24
Peak memory 289372 kb
Host smart-b3edefea-119c-460e-88c9-e13dd2b008fc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667311230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.3667311230
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.3469346771
Short name T319
Test name
Test status
Simulation time 5547637929 ps
CPU time 219.79 seconds
Started Aug 02 05:41:26 PM PDT 24
Finished Aug 02 05:45:06 PM PDT 24
Peak memory 248416 kb
Host smart-4b907fa5-5b68-4498-bab1-372ded819758
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469346771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.3469346771
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.392699326
Short name T479
Test name
Test status
Simulation time 3825375235 ps
CPU time 64.11 seconds
Started Aug 02 05:41:22 PM PDT 24
Finished Aug 02 05:42:27 PM PDT 24
Peak memory 255632 kb
Host smart-205f0c99-7aeb-4e3f-950c-4ca2f4d51249
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39269
9326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.392699326
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.2671999723
Short name T373
Test name
Test status
Simulation time 963416738 ps
CPU time 21.32 seconds
Started Aug 02 05:41:23 PM PDT 24
Finished Aug 02 05:41:44 PM PDT 24
Peak memory 248324 kb
Host smart-0e48bd87-ce4b-4c38-91cd-de129884327d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26719
99723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.2671999723
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.3450783882
Short name T472
Test name
Test status
Simulation time 174599900 ps
CPU time 11.51 seconds
Started Aug 02 05:41:19 PM PDT 24
Finished Aug 02 05:41:30 PM PDT 24
Peak memory 247704 kb
Host smart-5fb70f28-fb1a-4e8f-8580-00ee11b55c7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34507
83882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.3450783882
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.2030558610
Short name T568
Test name
Test status
Simulation time 5406717723 ps
CPU time 42.26 seconds
Started Aug 02 05:41:20 PM PDT 24
Finished Aug 02 05:42:03 PM PDT 24
Peak memory 256636 kb
Host smart-22e0b000-dd77-4bfb-b6b9-b7fde2fb662e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20305
58610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.2030558610
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.3110717993
Short name T269
Test name
Test status
Simulation time 144645497539 ps
CPU time 3730.78 seconds
Started Aug 02 05:41:19 PM PDT 24
Finished Aug 02 06:43:30 PM PDT 24
Peak memory 337920 kb
Host smart-0b8a779d-70df-4b6c-ac9c-2d1c29fa24fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110717993 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.3110717993
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.3799107230
Short name T299
Test name
Test status
Simulation time 141684616399 ps
CPU time 2618.57 seconds
Started Aug 02 05:41:32 PM PDT 24
Finished Aug 02 06:25:11 PM PDT 24
Peak memory 288620 kb
Host smart-70c7c646-873e-4da7-88c2-9cc18c6d0970
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799107230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.3799107230
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.826280547
Short name T422
Test name
Test status
Simulation time 574788581 ps
CPU time 49.58 seconds
Started Aug 02 05:41:21 PM PDT 24
Finished Aug 02 05:42:11 PM PDT 24
Peak memory 255840 kb
Host smart-6b6f292b-f55d-47e5-8710-d439cc2c5491
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82628
0547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.826280547
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.2528948888
Short name T446
Test name
Test status
Simulation time 2732295591 ps
CPU time 42.53 seconds
Started Aug 02 05:41:28 PM PDT 24
Finished Aug 02 05:42:10 PM PDT 24
Peak memory 248404 kb
Host smart-e94decb6-78ef-4a9b-90b1-1e0f981bf8ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25289
48888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.2528948888
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.3611696591
Short name T513
Test name
Test status
Simulation time 31071094402 ps
CPU time 2244.61 seconds
Started Aug 02 05:41:32 PM PDT 24
Finished Aug 02 06:18:57 PM PDT 24
Peak memory 282584 kb
Host smart-e95a434f-d5ce-4cde-9c14-b4d768a7e979
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611696591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.3611696591
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.3468140994
Short name T328
Test name
Test status
Simulation time 24474704832 ps
CPU time 285.87 seconds
Started Aug 02 05:41:32 PM PDT 24
Finished Aug 02 05:46:18 PM PDT 24
Peak memory 248428 kb
Host smart-13880f2d-0504-4ec7-a8e2-a5f45779a973
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468140994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.3468140994
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.1099983605
Short name T658
Test name
Test status
Simulation time 457927326 ps
CPU time 51.07 seconds
Started Aug 02 05:41:20 PM PDT 24
Finished Aug 02 05:42:11 PM PDT 24
Peak memory 248284 kb
Host smart-89cae1c9-ef75-42bb-afcd-3c894053b14a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10999
83605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.1099983605
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.1952316446
Short name T507
Test name
Test status
Simulation time 6725412535 ps
CPU time 53.29 seconds
Started Aug 02 05:41:25 PM PDT 24
Finished Aug 02 05:42:19 PM PDT 24
Peak memory 247996 kb
Host smart-299ad5fb-b029-43a6-8972-7e43a96bfe94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19523
16446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.1952316446
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.2147549485
Short name T399
Test name
Test status
Simulation time 720735163 ps
CPU time 44.78 seconds
Started Aug 02 05:41:31 PM PDT 24
Finished Aug 02 05:42:16 PM PDT 24
Peak memory 256108 kb
Host smart-d47e4b7c-fe43-4c84-8cc3-3f99d02ce525
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21475
49485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.2147549485
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.3392604604
Short name T218
Test name
Test status
Simulation time 374469272 ps
CPU time 11.02 seconds
Started Aug 02 05:41:20 PM PDT 24
Finished Aug 02 05:41:31 PM PDT 24
Peak memory 255140 kb
Host smart-54401de2-9205-4a9c-b36a-905bca40c20c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33926
04604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.3392604604
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.199927065
Short name T305
Test name
Test status
Simulation time 32388236446 ps
CPU time 1894.03 seconds
Started Aug 02 05:41:32 PM PDT 24
Finished Aug 02 06:13:06 PM PDT 24
Peak memory 302164 kb
Host smart-279e2ed8-7bf7-423a-a7cb-010c1e59dc70
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199927065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_han
dler_stress_all.199927065
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.1299721237
Short name T82
Test name
Test status
Simulation time 35292213214 ps
CPU time 2336.96 seconds
Started Aug 02 05:41:34 PM PDT 24
Finished Aug 02 06:20:31 PM PDT 24
Peak memory 281896 kb
Host smart-128b97c2-733b-4447-bc5b-e50751a7fd9d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299721237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.1299721237
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.35478973
Short name T514
Test name
Test status
Simulation time 13087180317 ps
CPU time 143.42 seconds
Started Aug 02 05:41:31 PM PDT 24
Finished Aug 02 05:43:55 PM PDT 24
Peak memory 256184 kb
Host smart-e96431fb-6cc5-41f1-b5a7-38ef926f4314
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35478
973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.35478973
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.2775317436
Short name T403
Test name
Test status
Simulation time 1928080205 ps
CPU time 35.62 seconds
Started Aug 02 05:41:32 PM PDT 24
Finished Aug 02 05:42:07 PM PDT 24
Peak memory 256096 kb
Host smart-e3fe8b6d-0394-48bb-a336-eb78f144247f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27753
17436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.2775317436
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.2292186685
Short name T701
Test name
Test status
Simulation time 19981521505 ps
CPU time 1270.48 seconds
Started Aug 02 05:41:30 PM PDT 24
Finished Aug 02 06:02:41 PM PDT 24
Peak memory 271920 kb
Host smart-4683f522-c1f5-4849-a9f8-31a826e315ec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292186685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.2292186685
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.4170035212
Short name T544
Test name
Test status
Simulation time 53643607493 ps
CPU time 1558.08 seconds
Started Aug 02 05:41:30 PM PDT 24
Finished Aug 02 06:07:29 PM PDT 24
Peak memory 288704 kb
Host smart-07e252d9-3325-4679-9ebb-8cdec7863791
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170035212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.4170035212
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.623959941
Short name T324
Test name
Test status
Simulation time 23007371552 ps
CPU time 412.35 seconds
Started Aug 02 05:41:33 PM PDT 24
Finished Aug 02 05:48:25 PM PDT 24
Peak memory 247312 kb
Host smart-4c165c50-20f7-4d47-8139-b013a7360edb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623959941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.623959941
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.2502568898
Short name T490
Test name
Test status
Simulation time 730043140 ps
CPU time 27.85 seconds
Started Aug 02 05:41:31 PM PDT 24
Finished Aug 02 05:41:59 PM PDT 24
Peak memory 255816 kb
Host smart-eec2623f-a297-49b2-a731-04b83b678811
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25025
68898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.2502568898
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.1940212997
Short name T603
Test name
Test status
Simulation time 1319005536 ps
CPU time 33.77 seconds
Started Aug 02 05:41:32 PM PDT 24
Finished Aug 02 05:42:06 PM PDT 24
Peak memory 255696 kb
Host smart-e79257bd-05f7-47bb-a634-17a9bef121c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19402
12997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.1940212997
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.298558592
Short name T125
Test name
Test status
Simulation time 2042560457 ps
CPU time 47.98 seconds
Started Aug 02 05:41:34 PM PDT 24
Finished Aug 02 05:42:22 PM PDT 24
Peak memory 248208 kb
Host smart-b1d37300-cb68-4d62-9306-1a1f14a8eb30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29855
8592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.298558592
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.561163302
Short name T383
Test name
Test status
Simulation time 395634400 ps
CPU time 27.55 seconds
Started Aug 02 05:41:31 PM PDT 24
Finished Aug 02 05:41:59 PM PDT 24
Peak memory 256532 kb
Host smart-4b792dc0-2c15-4784-8564-c91cf8de95cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56116
3302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.561163302
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.414672012
Short name T283
Test name
Test status
Simulation time 16531770503 ps
CPU time 1023.52 seconds
Started Aug 02 05:41:33 PM PDT 24
Finished Aug 02 05:58:37 PM PDT 24
Peak memory 264752 kb
Host smart-bd415694-8101-4c79-afac-889acefcb423
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414672012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_han
dler_stress_all.414672012
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.4294175906
Short name T433
Test name
Test status
Simulation time 54222012872 ps
CPU time 1797.81 seconds
Started Aug 02 05:41:37 PM PDT 24
Finished Aug 02 06:11:35 PM PDT 24
Peak memory 272964 kb
Host smart-f66c9adc-287e-4b94-8871-5adde78d3358
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294175906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.4294175906
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.2278133613
Short name T417
Test name
Test status
Simulation time 1151087682 ps
CPU time 55.86 seconds
Started Aug 02 05:41:37 PM PDT 24
Finished Aug 02 05:42:33 PM PDT 24
Peak memory 255712 kb
Host smart-e421fadf-6e0f-4c7a-bb20-97c44b0a4b35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22781
33613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.2278133613
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.3399054573
Short name T570
Test name
Test status
Simulation time 1737600912 ps
CPU time 32.64 seconds
Started Aug 02 05:41:42 PM PDT 24
Finished Aug 02 05:42:14 PM PDT 24
Peak memory 248420 kb
Host smart-dd0d7f3e-d26a-4b92-86ff-b10001b910a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33990
54573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.3399054573
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.3575177052
Short name T594
Test name
Test status
Simulation time 10060070133 ps
CPU time 900.06 seconds
Started Aug 02 05:41:43 PM PDT 24
Finished Aug 02 05:56:43 PM PDT 24
Peak memory 273024 kb
Host smart-f28ddaab-f683-40b9-9fa6-cbcf98e3d3c2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575177052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.3575177052
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.4100425863
Short name T503
Test name
Test status
Simulation time 68379114139 ps
CPU time 2109.72 seconds
Started Aug 02 05:41:41 PM PDT 24
Finished Aug 02 06:16:51 PM PDT 24
Peak memory 273016 kb
Host smart-c9bef6c0-e5ac-45c3-85b4-44e7ee0e65e5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100425863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.4100425863
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.7087460
Short name T327
Test name
Test status
Simulation time 44468495913 ps
CPU time 265.77 seconds
Started Aug 02 05:41:37 PM PDT 24
Finished Aug 02 05:46:03 PM PDT 24
Peak memory 248256 kb
Host smart-dfaeb210-2600-4ef3-b34c-284dee962092
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7087460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.7087460
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.134406144
Short name T448
Test name
Test status
Simulation time 1051022588 ps
CPU time 11.47 seconds
Started Aug 02 05:41:38 PM PDT 24
Finished Aug 02 05:41:49 PM PDT 24
Peak memory 248348 kb
Host smart-316ae395-deec-4da2-ba0c-80a533bb3c4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13440
6144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.134406144
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.2320376584
Short name T139
Test name
Test status
Simulation time 715807338 ps
CPU time 44.19 seconds
Started Aug 02 05:41:36 PM PDT 24
Finished Aug 02 05:42:20 PM PDT 24
Peak memory 256108 kb
Host smart-d4d2d467-810a-47fa-808f-1a2a649c093b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23203
76584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.2320376584
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.1039227434
Short name T450
Test name
Test status
Simulation time 1574981449 ps
CPU time 25.54 seconds
Started Aug 02 05:41:41 PM PDT 24
Finished Aug 02 05:42:06 PM PDT 24
Peak memory 255576 kb
Host smart-69cdf0ef-7424-4aea-a15d-92e10b78de3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10392
27434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.1039227434
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.182967525
Short name T39
Test name
Test status
Simulation time 954552131 ps
CPU time 49.79 seconds
Started Aug 02 05:41:34 PM PDT 24
Finished Aug 02 05:42:24 PM PDT 24
Peak memory 256580 kb
Host smart-cf968e05-bfc5-419b-8109-a9c06906f60e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18296
7525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.182967525
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.1070158578
Short name T58
Test name
Test status
Simulation time 108618074484 ps
CPU time 2350.56 seconds
Started Aug 02 05:41:37 PM PDT 24
Finished Aug 02 06:20:48 PM PDT 24
Peak memory 305296 kb
Host smart-cb2effe3-977b-4ad1-a0f4-413037f29e29
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070158578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.1070158578
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.1363087420
Short name T304
Test name
Test status
Simulation time 55230250959 ps
CPU time 3339.77 seconds
Started Aug 02 05:41:40 PM PDT 24
Finished Aug 02 06:37:20 PM PDT 24
Peak memory 331448 kb
Host smart-95659687-ea13-44cc-a1bb-d0084e4c0110
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363087420 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.1363087420
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.3316001246
Short name T33
Test name
Test status
Simulation time 25798878487 ps
CPU time 1795.5 seconds
Started Aug 02 05:41:37 PM PDT 24
Finished Aug 02 06:11:33 PM PDT 24
Peak memory 271580 kb
Host smart-5aba8317-8d53-4eef-b241-2290b07bbedb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316001246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.3316001246
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.2527466213
Short name T243
Test name
Test status
Simulation time 56349968 ps
CPU time 4.65 seconds
Started Aug 02 05:41:37 PM PDT 24
Finished Aug 02 05:41:41 PM PDT 24
Peak memory 239520 kb
Host smart-0ea08679-a295-45c4-ba84-eafb6afb53ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25274
66213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.2527466213
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.934197385
Short name T627
Test name
Test status
Simulation time 505634682 ps
CPU time 33 seconds
Started Aug 02 05:41:37 PM PDT 24
Finished Aug 02 05:42:10 PM PDT 24
Peak memory 256328 kb
Host smart-d459e6a6-d2c5-44dc-87b8-9bf05a155d42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93419
7385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.934197385
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.2943729565
Short name T347
Test name
Test status
Simulation time 132662950624 ps
CPU time 1603.82 seconds
Started Aug 02 05:41:40 PM PDT 24
Finished Aug 02 06:08:24 PM PDT 24
Peak memory 272784 kb
Host smart-849b06d2-81cc-4b2f-85bc-e5479162b128
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943729565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.2943729565
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.3417071918
Short name T453
Test name
Test status
Simulation time 9143729394 ps
CPU time 752.33 seconds
Started Aug 02 05:41:40 PM PDT 24
Finished Aug 02 05:54:13 PM PDT 24
Peak memory 272940 kb
Host smart-8c78845e-d055-43be-83b0-4630f351ad32
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417071918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.3417071918
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.3728170290
Short name T340
Test name
Test status
Simulation time 97531863197 ps
CPU time 284.28 seconds
Started Aug 02 05:41:39 PM PDT 24
Finished Aug 02 05:46:23 PM PDT 24
Peak memory 248128 kb
Host smart-f0f3598d-31a8-4ae6-baf4-8924cac87cd1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728170290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.3728170290
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.1974338313
Short name T619
Test name
Test status
Simulation time 7448699632 ps
CPU time 32.55 seconds
Started Aug 02 05:41:42 PM PDT 24
Finished Aug 02 05:42:15 PM PDT 24
Peak memory 256508 kb
Host smart-caa014bb-e33b-4ab8-93ee-77551dae03c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19743
38313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.1974338313
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.282586381
Short name T129
Test name
Test status
Simulation time 112834430 ps
CPU time 14.4 seconds
Started Aug 02 05:41:41 PM PDT 24
Finished Aug 02 05:41:55 PM PDT 24
Peak memory 255892 kb
Host smart-a2b2d78c-e484-42d3-9d09-eb5bc9763aec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28258
6381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.282586381
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.2493936882
Short name T306
Test name
Test status
Simulation time 1659128932 ps
CPU time 14.22 seconds
Started Aug 02 05:41:37 PM PDT 24
Finished Aug 02 05:41:51 PM PDT 24
Peak memory 247440 kb
Host smart-14970fec-5d7c-40f2-9a30-7f50a46958cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24939
36882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.2493936882
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.3703520268
Short name T388
Test name
Test status
Simulation time 641634053 ps
CPU time 14.18 seconds
Started Aug 02 05:41:40 PM PDT 24
Finished Aug 02 05:41:54 PM PDT 24
Peak memory 256296 kb
Host smart-2906d630-ecb9-4b69-8052-240f16954014
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37035
20268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.3703520268
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.4197449823
Short name T288
Test name
Test status
Simulation time 101409079018 ps
CPU time 1245.66 seconds
Started Aug 02 05:41:40 PM PDT 24
Finished Aug 02 06:02:26 PM PDT 24
Peak memory 288816 kb
Host smart-d00e94ad-4758-45f4-bf26-7f2cbe398f1f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197449823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.4197449823
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.889005563
Short name T281
Test name
Test status
Simulation time 20517473636 ps
CPU time 1485.68 seconds
Started Aug 02 05:41:37 PM PDT 24
Finished Aug 02 06:06:23 PM PDT 24
Peak memory 285048 kb
Host smart-2e78a35d-5410-4038-a670-054ab4cae253
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889005563 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.889005563
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.2488853012
Short name T625
Test name
Test status
Simulation time 22459837530 ps
CPU time 316.86 seconds
Started Aug 02 05:41:37 PM PDT 24
Finished Aug 02 05:46:54 PM PDT 24
Peak memory 255928 kb
Host smart-86c8f841-b405-4812-89dc-88632c139dba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24888
53012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.2488853012
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.1410405794
Short name T90
Test name
Test status
Simulation time 388701292 ps
CPU time 9.62 seconds
Started Aug 02 05:41:41 PM PDT 24
Finished Aug 02 05:41:51 PM PDT 24
Peak memory 248216 kb
Host smart-e855a95f-6e0b-4ad9-8c5f-77b18b3915af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14104
05794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.1410405794
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.515544250
Short name T445
Test name
Test status
Simulation time 27226963914 ps
CPU time 1876.35 seconds
Started Aug 02 05:41:42 PM PDT 24
Finished Aug 02 06:12:59 PM PDT 24
Peak memory 283972 kb
Host smart-2bc475e9-8f32-404b-88f6-549ccb559822
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515544250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.515544250
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.1802659839
Short name T323
Test name
Test status
Simulation time 35348188379 ps
CPU time 396.83 seconds
Started Aug 02 05:41:40 PM PDT 24
Finished Aug 02 05:48:16 PM PDT 24
Peak memory 255100 kb
Host smart-4d751779-9dec-4b07-a158-38de395f56a5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802659839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.1802659839
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.3080520327
Short name T644
Test name
Test status
Simulation time 2607077000 ps
CPU time 30.72 seconds
Started Aug 02 05:41:36 PM PDT 24
Finished Aug 02 05:42:07 PM PDT 24
Peak memory 255832 kb
Host smart-262581ac-b8ba-4df4-916b-5f9424e584d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30805
20327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.3080520327
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.781373712
Short name T688
Test name
Test status
Simulation time 280655168 ps
CPU time 19.15 seconds
Started Aug 02 05:41:41 PM PDT 24
Finished Aug 02 05:42:01 PM PDT 24
Peak memory 254836 kb
Host smart-6f4e8fc6-2b78-47be-a299-79cf91a4e193
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78137
3712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.781373712
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.919446654
Short name T468
Test name
Test status
Simulation time 208832637 ps
CPU time 14.66 seconds
Started Aug 02 05:41:37 PM PDT 24
Finished Aug 02 05:41:52 PM PDT 24
Peak memory 255024 kb
Host smart-fc1ecf09-973b-4b2d-8c98-e07341a22b16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91944
6654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.919446654
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all_with_rand_reset.190940559
Short name T141
Test name
Test status
Simulation time 42948447811 ps
CPU time 2664.05 seconds
Started Aug 02 05:41:48 PM PDT 24
Finished Aug 02 06:26:12 PM PDT 24
Peak memory 289480 kb
Host smart-33b30b30-572e-4173-ab07-8c955bd0a3e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190940559 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 37.alert_handler_stress_all_with_rand_reset.190940559
Directory /workspace/37.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.3708836122
Short name T285
Test name
Test status
Simulation time 33243144885 ps
CPU time 2019.15 seconds
Started Aug 02 05:41:47 PM PDT 24
Finished Aug 02 06:15:26 PM PDT 24
Peak memory 272732 kb
Host smart-1d6153f6-5bbf-41e8-b72f-5ff237b3287e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708836122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.3708836122
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.2231888723
Short name T615
Test name
Test status
Simulation time 854952963 ps
CPU time 82.31 seconds
Started Aug 02 05:41:48 PM PDT 24
Finished Aug 02 05:43:10 PM PDT 24
Peak memory 256600 kb
Host smart-aa20441d-7fa1-4c4c-b947-03f105b633b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22318
88723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.2231888723
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.3058976343
Short name T486
Test name
Test status
Simulation time 53830340 ps
CPU time 5.49 seconds
Started Aug 02 05:41:46 PM PDT 24
Finished Aug 02 05:41:51 PM PDT 24
Peak memory 240164 kb
Host smart-e4c7d5c1-2dec-4659-83de-5f9bf3ed4dd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30589
76343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.3058976343
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.3785548767
Short name T85
Test name
Test status
Simulation time 126982118396 ps
CPU time 2089.89 seconds
Started Aug 02 05:41:46 PM PDT 24
Finished Aug 02 06:16:37 PM PDT 24
Peak memory 284588 kb
Host smart-fb9a229f-28ed-4103-832c-f2766ec8ee1b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785548767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.3785548767
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.1225052162
Short name T635
Test name
Test status
Simulation time 173770919366 ps
CPU time 2603.96 seconds
Started Aug 02 05:41:46 PM PDT 24
Finished Aug 02 06:25:10 PM PDT 24
Peak memory 287620 kb
Host smart-a7a65a65-8906-4c3c-b4aa-0ab73d74b0a0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225052162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.1225052162
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.3040857039
Short name T256
Test name
Test status
Simulation time 19783645909 ps
CPU time 417.44 seconds
Started Aug 02 05:41:50 PM PDT 24
Finished Aug 02 05:48:47 PM PDT 24
Peak memory 247372 kb
Host smart-77521288-81dc-4824-89ad-2bbdd048e81e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040857039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.3040857039
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.551892117
Short name T540
Test name
Test status
Simulation time 1107067598 ps
CPU time 70.52 seconds
Started Aug 02 05:41:50 PM PDT 24
Finished Aug 02 05:43:00 PM PDT 24
Peak memory 255764 kb
Host smart-37ed620d-0dbf-481e-9b5d-8402e8f74021
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55189
2117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.551892117
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.3299390722
Short name T59
Test name
Test status
Simulation time 373545545 ps
CPU time 16.44 seconds
Started Aug 02 05:41:49 PM PDT 24
Finished Aug 02 05:42:05 PM PDT 24
Peak memory 247928 kb
Host smart-b20f3cf7-6b81-4a57-9d8b-5df4465e42bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32993
90722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.3299390722
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.1614776330
Short name T268
Test name
Test status
Simulation time 977701660 ps
CPU time 30.33 seconds
Started Aug 02 05:41:47 PM PDT 24
Finished Aug 02 05:42:17 PM PDT 24
Peak memory 247880 kb
Host smart-1c4a629c-8e9d-4f39-a21d-0b1eb45994a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16147
76330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.1614776330
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.3493375678
Short name T611
Test name
Test status
Simulation time 540146629 ps
CPU time 17.56 seconds
Started Aug 02 05:41:47 PM PDT 24
Finished Aug 02 05:42:04 PM PDT 24
Peak memory 248404 kb
Host smart-952e7fb7-230f-4dd9-a69e-dc33f722d6e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34933
75678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.3493375678
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.471971350
Short name T599
Test name
Test status
Simulation time 310789655 ps
CPU time 30.34 seconds
Started Aug 02 05:41:46 PM PDT 24
Finished Aug 02 05:42:16 PM PDT 24
Peak memory 256372 kb
Host smart-272d32e6-1241-45cb-8eb6-a3b392ed0e00
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471971350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_han
dler_stress_all.471971350
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.3455918543
Short name T140
Test name
Test status
Simulation time 14333477344 ps
CPU time 946.32 seconds
Started Aug 02 05:41:58 PM PDT 24
Finished Aug 02 05:57:45 PM PDT 24
Peak memory 272292 kb
Host smart-b8602641-5b4e-45ae-a010-71544aadaad5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455918543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.3455918543
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.1678545200
Short name T372
Test name
Test status
Simulation time 1816395435 ps
CPU time 121.57 seconds
Started Aug 02 05:41:48 PM PDT 24
Finished Aug 02 05:43:49 PM PDT 24
Peak memory 255940 kb
Host smart-ae54d7c2-03f6-4886-b1c5-6696f6bb9b51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16785
45200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.1678545200
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.3405894529
Short name T22
Test name
Test status
Simulation time 174335716 ps
CPU time 10.85 seconds
Started Aug 02 05:41:46 PM PDT 24
Finished Aug 02 05:41:57 PM PDT 24
Peak memory 248340 kb
Host smart-899a5122-0da2-43d7-bbec-8762a0838057
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34058
94529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.3405894529
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.2303530299
Short name T349
Test name
Test status
Simulation time 46654738384 ps
CPU time 1221.31 seconds
Started Aug 02 05:41:54 PM PDT 24
Finished Aug 02 06:02:15 PM PDT 24
Peak memory 273080 kb
Host smart-c6c13729-6215-4bb3-acbf-53d5c326104c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303530299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.2303530299
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.2591799849
Short name T133
Test name
Test status
Simulation time 202549033095 ps
CPU time 2896.1 seconds
Started Aug 02 05:41:54 PM PDT 24
Finished Aug 02 06:30:10 PM PDT 24
Peak memory 289344 kb
Host smart-be1e2121-d5e0-4a03-9501-b8c394764869
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591799849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.2591799849
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.1806437842
Short name T579
Test name
Test status
Simulation time 7892306275 ps
CPU time 321.43 seconds
Started Aug 02 05:41:54 PM PDT 24
Finished Aug 02 05:47:15 PM PDT 24
Peak memory 248428 kb
Host smart-ce6344c8-2a53-4ab4-95c1-41f4350aafea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806437842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.1806437842
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.1527935212
Short name T108
Test name
Test status
Simulation time 1769566109 ps
CPU time 34.74 seconds
Started Aug 02 05:41:45 PM PDT 24
Finished Aug 02 05:42:20 PM PDT 24
Peak memory 248296 kb
Host smart-429f02dd-a2cc-44bd-bfe0-84ad91215ef4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15279
35212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.1527935212
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.2764585727
Short name T558
Test name
Test status
Simulation time 8381307574 ps
CPU time 44.03 seconds
Started Aug 02 05:41:44 PM PDT 24
Finished Aug 02 05:42:28 PM PDT 24
Peak memory 247884 kb
Host smart-9e6f119e-1de2-491e-92af-ef07ff17d34f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27645
85727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.2764585727
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.1608409940
Short name T526
Test name
Test status
Simulation time 1197624101 ps
CPU time 12.59 seconds
Started Aug 02 05:41:46 PM PDT 24
Finished Aug 02 05:41:59 PM PDT 24
Peak memory 247736 kb
Host smart-1a35d215-eaa8-4858-9d69-a0818a162083
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16084
09940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.1608409940
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.3520651046
Short name T504
Test name
Test status
Simulation time 633514691 ps
CPU time 13.52 seconds
Started Aug 02 05:41:47 PM PDT 24
Finished Aug 02 05:42:00 PM PDT 24
Peak memory 256580 kb
Host smart-de18e7b6-cd8d-4841-ab30-f2b9d3a059f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35206
51046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.3520651046
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.1020778249
Short name T4
Test name
Test status
Simulation time 1985817177 ps
CPU time 126.43 seconds
Started Aug 02 05:41:54 PM PDT 24
Finished Aug 02 05:44:00 PM PDT 24
Peak memory 256488 kb
Host smart-385776e3-1ba5-4deb-81b3-0f55c7d37a43
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020778249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.1020778249
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.807589780
Short name T233
Test name
Test status
Simulation time 16474241 ps
CPU time 2.62 seconds
Started Aug 02 05:39:47 PM PDT 24
Finished Aug 02 05:39:50 PM PDT 24
Peak memory 248412 kb
Host smart-de654818-39bd-4559-ad89-81c8732e1ee5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=807589780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.807589780
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.1124007547
Short name T591
Test name
Test status
Simulation time 35744585447 ps
CPU time 2070.57 seconds
Started Aug 02 05:39:47 PM PDT 24
Finished Aug 02 06:14:17 PM PDT 24
Peak memory 272744 kb
Host smart-f1dc8c37-20dc-4662-bad5-bd18f058c104
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124007547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.1124007547
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.3070245354
Short name T620
Test name
Test status
Simulation time 859477567 ps
CPU time 11.86 seconds
Started Aug 02 05:39:44 PM PDT 24
Finished Aug 02 05:39:56 PM PDT 24
Peak memory 248332 kb
Host smart-a25c1a6c-0e1f-4fba-8990-fc1cf253ac99
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3070245354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.3070245354
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.3375249547
Short name T601
Test name
Test status
Simulation time 154848987 ps
CPU time 9.37 seconds
Started Aug 02 05:39:46 PM PDT 24
Finished Aug 02 05:39:55 PM PDT 24
Peak memory 253336 kb
Host smart-322c1ecc-186b-4f7d-ad1f-8b0e43c12bed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33752
49547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.3375249547
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.3474926901
Short name T665
Test name
Test status
Simulation time 423921191 ps
CPU time 31.43 seconds
Started Aug 02 05:39:49 PM PDT 24
Finished Aug 02 05:40:20 PM PDT 24
Peak memory 256384 kb
Host smart-bee2563e-9ea0-4764-a9bb-76152ca4b439
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34749
26901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.3474926901
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.2540246813
Short name T124
Test name
Test status
Simulation time 18706864704 ps
CPU time 1238.08 seconds
Started Aug 02 05:39:43 PM PDT 24
Finished Aug 02 06:00:22 PM PDT 24
Peak memory 272356 kb
Host smart-9c3ed5bd-d9c3-4c44-a47a-9e0466cdb939
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540246813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.2540246813
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.3063662381
Short name T117
Test name
Test status
Simulation time 8567968764 ps
CPU time 948.56 seconds
Started Aug 02 05:39:42 PM PDT 24
Finished Aug 02 05:55:31 PM PDT 24
Peak memory 289312 kb
Host smart-47025e4f-eefc-460b-ab87-ee0e264db13c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063662381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.3063662381
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.844152422
Short name T12
Test name
Test status
Simulation time 4313973583 ps
CPU time 103.49 seconds
Started Aug 02 05:39:46 PM PDT 24
Finished Aug 02 05:41:29 PM PDT 24
Peak memory 248200 kb
Host smart-1e1000ac-f664-4904-b723-39ba921a7ad1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844152422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.844152422
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.2014944948
Short name T449
Test name
Test status
Simulation time 836229648 ps
CPU time 54.39 seconds
Started Aug 02 05:39:45 PM PDT 24
Finished Aug 02 05:40:39 PM PDT 24
Peak memory 255640 kb
Host smart-1e1b8906-c90a-4969-b871-c2d4c5da1911
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20149
44948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.2014944948
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.4207874923
Short name T47
Test name
Test status
Simulation time 184901732 ps
CPU time 16.95 seconds
Started Aug 02 05:39:48 PM PDT 24
Finished Aug 02 05:40:05 PM PDT 24
Peak memory 256096 kb
Host smart-9d00999a-15c1-4b5a-9c71-c5960737c2e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42078
74923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.4207874923
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.1167155385
Short name T38
Test name
Test status
Simulation time 1223529751 ps
CPU time 50.88 seconds
Started Aug 02 05:39:46 PM PDT 24
Finished Aug 02 05:40:37 PM PDT 24
Peak memory 277424 kb
Host smart-ef67ca56-9fe0-48df-808a-02a28063ef1a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1167155385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.1167155385
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.2008471801
Short name T95
Test name
Test status
Simulation time 1442059989 ps
CPU time 42.76 seconds
Started Aug 02 05:39:46 PM PDT 24
Finished Aug 02 05:40:29 PM PDT 24
Peak memory 248032 kb
Host smart-edc37ce5-3a3f-455c-83a1-4fc3f57a3173
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20084
71801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.2008471801
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.928197180
Short name T220
Test name
Test status
Simulation time 537773536 ps
CPU time 14.57 seconds
Started Aug 02 05:39:48 PM PDT 24
Finished Aug 02 05:40:02 PM PDT 24
Peak memory 256468 kb
Host smart-d9ca7385-23e5-4a5d-9a95-326ca885bca7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92819
7180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.928197180
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.3758359735
Short name T64
Test name
Test status
Simulation time 45531101458 ps
CPU time 4901.6 seconds
Started Aug 02 05:39:45 PM PDT 24
Finished Aug 02 07:01:28 PM PDT 24
Peak memory 330524 kb
Host smart-a51b0f24-8364-4f9e-bf30-bb88f3d1c2d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758359735 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.3758359735
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.2478208113
Short name T466
Test name
Test status
Simulation time 276118266099 ps
CPU time 2642.18 seconds
Started Aug 02 05:41:58 PM PDT 24
Finished Aug 02 06:26:01 PM PDT 24
Peak memory 287152 kb
Host smart-3493af44-6092-46a4-83be-96583cc19421
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478208113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.2478208113
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.3092247538
Short name T561
Test name
Test status
Simulation time 631081202 ps
CPU time 55.69 seconds
Started Aug 02 05:41:54 PM PDT 24
Finished Aug 02 05:42:50 PM PDT 24
Peak memory 255900 kb
Host smart-8058efd8-5e03-4992-a85b-1bb097d93047
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30922
47538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.3092247538
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.3547477354
Short name T458
Test name
Test status
Simulation time 1167655871 ps
CPU time 28.43 seconds
Started Aug 02 05:41:52 PM PDT 24
Finished Aug 02 05:42:21 PM PDT 24
Peak memory 255964 kb
Host smart-6ed89045-4d3f-4bf9-9995-77afa8be3c82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35474
77354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.3547477354
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.171991211
Short name T11
Test name
Test status
Simulation time 140321401216 ps
CPU time 1291.11 seconds
Started Aug 02 05:41:58 PM PDT 24
Finished Aug 02 06:03:29 PM PDT 24
Peak memory 264756 kb
Host smart-e644b1eb-d77b-44b6-b04b-fa37fafd138d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171991211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.171991211
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.2198421385
Short name T400
Test name
Test status
Simulation time 707447869379 ps
CPU time 3499.45 seconds
Started Aug 02 05:41:53 PM PDT 24
Finished Aug 02 06:40:13 PM PDT 24
Peak memory 288744 kb
Host smart-8c5d7102-ce26-4cef-94fb-84b335c0d418
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198421385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.2198421385
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.1627109689
Short name T314
Test name
Test status
Simulation time 43863007064 ps
CPU time 525.95 seconds
Started Aug 02 05:41:58 PM PDT 24
Finished Aug 02 05:50:44 PM PDT 24
Peak memory 247296 kb
Host smart-d2fd8197-754c-4e31-9812-508548f26cee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627109689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.1627109689
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.2369080478
Short name T465
Test name
Test status
Simulation time 1775813964 ps
CPU time 30.15 seconds
Started Aug 02 05:41:54 PM PDT 24
Finished Aug 02 05:42:24 PM PDT 24
Peak memory 248312 kb
Host smart-44b56411-73c2-4a9d-ae9a-45bc25a03769
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23690
80478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.2369080478
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.653226896
Short name T391
Test name
Test status
Simulation time 48418924 ps
CPU time 4.49 seconds
Started Aug 02 05:41:56 PM PDT 24
Finished Aug 02 05:42:01 PM PDT 24
Peak memory 239716 kb
Host smart-07c8b1bc-cf2b-4fda-8385-bf2938a4aa55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65322
6896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.653226896
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.754685361
Short name T242
Test name
Test status
Simulation time 953531066 ps
CPU time 31.11 seconds
Started Aug 02 05:41:56 PM PDT 24
Finished Aug 02 05:42:28 PM PDT 24
Peak memory 255876 kb
Host smart-9bd0a39d-1ff1-433b-9865-24490029f143
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75468
5361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.754685361
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.2563191448
Short name T592
Test name
Test status
Simulation time 52568523 ps
CPU time 4.96 seconds
Started Aug 02 05:41:52 PM PDT 24
Finished Aug 02 05:41:58 PM PDT 24
Peak memory 251064 kb
Host smart-2ed156cb-0b55-4cb5-a2ec-42ff4414d2cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25631
91448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.2563191448
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.4112911854
Short name T385
Test name
Test status
Simulation time 16419691356 ps
CPU time 831.34 seconds
Started Aug 02 05:41:52 PM PDT 24
Finished Aug 02 05:55:44 PM PDT 24
Peak memory 272792 kb
Host smart-72e93f6a-01ea-4f38-887d-a212f5ac13b2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112911854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.4112911854
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.3742738580
Short name T464
Test name
Test status
Simulation time 207095760492 ps
CPU time 2601.2 seconds
Started Aug 02 05:42:01 PM PDT 24
Finished Aug 02 06:25:22 PM PDT 24
Peak memory 289268 kb
Host smart-8fac4716-6339-4ffd-99bb-6cf01efd7d2d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742738580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.3742738580
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.746028952
Short name T595
Test name
Test status
Simulation time 28151492006 ps
CPU time 123.43 seconds
Started Aug 02 05:42:02 PM PDT 24
Finished Aug 02 05:44:05 PM PDT 24
Peak memory 255912 kb
Host smart-7555a298-42ed-4847-ab22-cd1465447a32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74602
8952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.746028952
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.1190071311
Short name T406
Test name
Test status
Simulation time 1139832783 ps
CPU time 35.92 seconds
Started Aug 02 05:42:02 PM PDT 24
Finished Aug 02 05:42:38 PM PDT 24
Peak memory 256396 kb
Host smart-bc2c84ee-18ac-4219-8531-e57751d7ec8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11900
71311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.1190071311
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.2526862479
Short name T356
Test name
Test status
Simulation time 24412529977 ps
CPU time 1461.23 seconds
Started Aug 02 05:42:00 PM PDT 24
Finished Aug 02 06:06:21 PM PDT 24
Peak memory 272896 kb
Host smart-539d3e93-439a-432d-8891-bebbd2495a0d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526862479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.2526862479
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.1987119919
Short name T404
Test name
Test status
Simulation time 21238324100 ps
CPU time 1455.11 seconds
Started Aug 02 05:42:01 PM PDT 24
Finished Aug 02 06:06:16 PM PDT 24
Peak memory 265868 kb
Host smart-509db0f0-12a6-4996-86cd-9c28c72c1325
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987119919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.1987119919
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.703561334
Short name T334
Test name
Test status
Simulation time 9329091201 ps
CPU time 414.6 seconds
Started Aug 02 05:42:02 PM PDT 24
Finished Aug 02 05:48:57 PM PDT 24
Peak memory 256472 kb
Host smart-9d838a89-b282-4547-9d75-a3761ade9da9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703561334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.703561334
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.634001041
Short name T52
Test name
Test status
Simulation time 707835421 ps
CPU time 38.99 seconds
Started Aug 02 05:42:01 PM PDT 24
Finished Aug 02 05:42:40 PM PDT 24
Peak memory 256528 kb
Host smart-fdd222c9-184f-40f7-9f0b-d89178d5d05c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63400
1041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.634001041
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.1128275147
Short name T386
Test name
Test status
Simulation time 149429008 ps
CPU time 9.87 seconds
Started Aug 02 05:42:01 PM PDT 24
Finished Aug 02 05:42:11 PM PDT 24
Peak memory 255796 kb
Host smart-ebd5ddc5-40a4-484e-a67c-55032e0bdb05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11282
75147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.1128275147
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.1828903556
Short name T578
Test name
Test status
Simulation time 291036394 ps
CPU time 40.69 seconds
Started Aug 02 05:42:02 PM PDT 24
Finished Aug 02 05:42:43 PM PDT 24
Peak memory 247720 kb
Host smart-922a9c3c-3595-4a8a-9c2f-8146227aa284
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18289
03556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.1828903556
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.4255176703
Short name T410
Test name
Test status
Simulation time 334981611 ps
CPU time 7.82 seconds
Started Aug 02 05:42:02 PM PDT 24
Finished Aug 02 05:42:10 PM PDT 24
Peak memory 254904 kb
Host smart-3f80c5df-1654-4462-9fa8-0da96c5a84d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42551
76703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.4255176703
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.42310183
Short name T80
Test name
Test status
Simulation time 171052259862 ps
CPU time 2247.3 seconds
Started Aug 02 05:42:01 PM PDT 24
Finished Aug 02 06:19:28 PM PDT 24
Peak memory 289060 kb
Host smart-b5d39da6-142c-47d7-922c-64db8a648964
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42310183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_hand
ler_stress_all.42310183
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.799778184
Short name T528
Test name
Test status
Simulation time 90124000873 ps
CPU time 1594.27 seconds
Started Aug 02 05:42:00 PM PDT 24
Finished Aug 02 06:08:35 PM PDT 24
Peak memory 287908 kb
Host smart-f9725087-91e1-49df-970b-6079f9726f45
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799778184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.799778184
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.1057092180
Short name T264
Test name
Test status
Simulation time 20570954521 ps
CPU time 291.58 seconds
Started Aug 02 05:42:02 PM PDT 24
Finished Aug 02 05:46:54 PM PDT 24
Peak memory 256572 kb
Host smart-0c473bd4-ab41-426b-8c55-a69638cc5900
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10570
92180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.1057092180
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.2316810587
Short name T530
Test name
Test status
Simulation time 261160057 ps
CPU time 23.76 seconds
Started Aug 02 05:42:00 PM PDT 24
Finished Aug 02 05:42:24 PM PDT 24
Peak memory 255840 kb
Host smart-a3bf4f0c-e04a-47a9-b41a-789f80b32a15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23168
10587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.2316810587
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.2398968983
Short name T311
Test name
Test status
Simulation time 29529344726 ps
CPU time 1216.07 seconds
Started Aug 02 05:42:11 PM PDT 24
Finished Aug 02 06:02:28 PM PDT 24
Peak memory 286204 kb
Host smart-6789648b-e8db-43c7-a428-61581e28adf2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398968983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.2398968983
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.4088373538
Short name T667
Test name
Test status
Simulation time 48454860405 ps
CPU time 761.55 seconds
Started Aug 02 05:42:11 PM PDT 24
Finished Aug 02 05:54:52 PM PDT 24
Peak memory 272344 kb
Host smart-6b6fd2a2-b97b-47d8-a1cf-13b2d23c5f72
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088373538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.4088373538
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.680129177
Short name T541
Test name
Test status
Simulation time 26874210382 ps
CPU time 547.97 seconds
Started Aug 02 05:42:01 PM PDT 24
Finished Aug 02 05:51:09 PM PDT 24
Peak memory 256576 kb
Host smart-3b0697d6-1525-4a2f-966c-64ce405c1068
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680129177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.680129177
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.2870992762
Short name T521
Test name
Test status
Simulation time 789139883 ps
CPU time 48.35 seconds
Started Aug 02 05:42:03 PM PDT 24
Finished Aug 02 05:42:51 PM PDT 24
Peak memory 256484 kb
Host smart-e0f25a9b-9aa2-4bec-839e-ee0c797db72f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28709
92762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.2870992762
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.2906887568
Short name T506
Test name
Test status
Simulation time 963291386 ps
CPU time 49.28 seconds
Started Aug 02 05:42:02 PM PDT 24
Finished Aug 02 05:42:51 PM PDT 24
Peak memory 256116 kb
Host smart-d1e4ff65-b475-457c-96f1-237adb091e1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29068
87568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.2906887568
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.1664678634
Short name T53
Test name
Test status
Simulation time 470837737 ps
CPU time 12.87 seconds
Started Aug 02 05:42:03 PM PDT 24
Finished Aug 02 05:42:16 PM PDT 24
Peak memory 255440 kb
Host smart-8726e245-1b4a-4254-a7cf-6a70fd22ed98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16646
78634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.1664678634
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.1735197873
Short name T44
Test name
Test status
Simulation time 930536255 ps
CPU time 57.1 seconds
Started Aug 02 05:42:01 PM PDT 24
Finished Aug 02 05:42:58 PM PDT 24
Peak memory 255664 kb
Host smart-3f2b1c9c-af57-4cd2-a789-b32dab32e04f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17351
97873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.1735197873
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.2085778257
Short name T270
Test name
Test status
Simulation time 2729209785 ps
CPU time 160.52 seconds
Started Aug 02 05:42:09 PM PDT 24
Finished Aug 02 05:44:49 PM PDT 24
Peak memory 256424 kb
Host smart-4a080b2f-7646-4d5e-bc46-e09c8efcf5bd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085778257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.2085778257
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.395143114
Short name T425
Test name
Test status
Simulation time 111299055028 ps
CPU time 1697.43 seconds
Started Aug 02 05:42:09 PM PDT 24
Finished Aug 02 06:10:26 PM PDT 24
Peak memory 284096 kb
Host smart-4ebe3449-6a72-4850-a269-f96b24c90168
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395143114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.395143114
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.2761107454
Short name T493
Test name
Test status
Simulation time 3068450480 ps
CPU time 87.77 seconds
Started Aug 02 05:42:10 PM PDT 24
Finished Aug 02 05:43:37 PM PDT 24
Peak memory 255884 kb
Host smart-6f3277a2-1262-46fa-b6ad-9607b8109cee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27611
07454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.2761107454
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.2117960214
Short name T622
Test name
Test status
Simulation time 732915555 ps
CPU time 11.65 seconds
Started Aug 02 05:42:10 PM PDT 24
Finished Aug 02 05:42:21 PM PDT 24
Peak memory 248324 kb
Host smart-c3817db0-3351-4cd0-8b98-a4c58a8ec1f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21179
60214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.2117960214
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.1106204997
Short name T358
Test name
Test status
Simulation time 122942719229 ps
CPU time 1927.51 seconds
Started Aug 02 05:42:11 PM PDT 24
Finished Aug 02 06:14:19 PM PDT 24
Peak memory 281732 kb
Host smart-c02b4935-70c8-4f5e-83c8-a02fd2c234ea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106204997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.1106204997
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.3612225764
Short name T2
Test name
Test status
Simulation time 80067081693 ps
CPU time 1909.57 seconds
Started Aug 02 05:42:08 PM PDT 24
Finished Aug 02 06:13:58 PM PDT 24
Peak memory 289104 kb
Host smart-b47709f8-7d0a-444a-8e30-e6a2e70fb5de
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612225764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.3612225764
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.1049694860
Short name T546
Test name
Test status
Simulation time 11424996835 ps
CPU time 486.02 seconds
Started Aug 02 05:42:14 PM PDT 24
Finished Aug 02 05:50:20 PM PDT 24
Peak memory 248428 kb
Host smart-da491aab-270f-4754-bf38-83665efd53df
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049694860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.1049694860
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.1516818158
Short name T393
Test name
Test status
Simulation time 1938392091 ps
CPU time 29.42 seconds
Started Aug 02 05:42:11 PM PDT 24
Finished Aug 02 05:42:40 PM PDT 24
Peak memory 255596 kb
Host smart-819a48aa-1fb6-471e-805c-3dbfbd3bb54e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15168
18158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.1516818158
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.2362465321
Short name T610
Test name
Test status
Simulation time 428538685 ps
CPU time 5.44 seconds
Started Aug 02 05:42:10 PM PDT 24
Finished Aug 02 05:42:15 PM PDT 24
Peak memory 250048 kb
Host smart-9b66a2a3-5243-4b9b-8584-c914a86f7379
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23624
65321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.2362465321
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.1225266718
Short name T639
Test name
Test status
Simulation time 1039043980 ps
CPU time 27.24 seconds
Started Aug 02 05:42:11 PM PDT 24
Finished Aug 02 05:42:39 PM PDT 24
Peak memory 255880 kb
Host smart-08fc98b5-99d6-41fb-a67e-6b845643dba3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12252
66718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.1225266718
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.3493218629
Short name T495
Test name
Test status
Simulation time 816287162 ps
CPU time 46.99 seconds
Started Aug 02 05:42:15 PM PDT 24
Finished Aug 02 05:43:02 PM PDT 24
Peak memory 256544 kb
Host smart-9a027b6f-fc92-40f8-af95-52120f973682
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34932
18629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.3493218629
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.1884942176
Short name T113
Test name
Test status
Simulation time 59115560015 ps
CPU time 1879.1 seconds
Started Aug 02 05:42:12 PM PDT 24
Finished Aug 02 06:13:31 PM PDT 24
Peak memory 286472 kb
Host smart-5558320c-660f-4b79-9b9e-1806249fa318
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884942176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.1884942176
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.2364685975
Short name T602
Test name
Test status
Simulation time 45011156347 ps
CPU time 1211.35 seconds
Started Aug 02 05:42:11 PM PDT 24
Finished Aug 02 06:02:23 PM PDT 24
Peak memory 298036 kb
Host smart-634092ac-c719-4f76-b435-9916c286100a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364685975 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.2364685975
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.3563619600
Short name T63
Test name
Test status
Simulation time 157948919222 ps
CPU time 1948.73 seconds
Started Aug 02 05:42:17 PM PDT 24
Finished Aug 02 06:14:46 PM PDT 24
Peak memory 272920 kb
Host smart-eda18870-b486-4507-88d7-3de8dfb24699
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563619600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.3563619600
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.1942387817
Short name T470
Test name
Test status
Simulation time 1048707083 ps
CPU time 86.48 seconds
Started Aug 02 05:42:21 PM PDT 24
Finished Aug 02 05:43:47 PM PDT 24
Peak memory 256608 kb
Host smart-b0e4fb96-744b-4718-8d4e-a50c69fce794
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19423
87817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.1942387817
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.2018563837
Short name T401
Test name
Test status
Simulation time 71854058 ps
CPU time 7.56 seconds
Started Aug 02 05:42:17 PM PDT 24
Finished Aug 02 05:42:25 PM PDT 24
Peak memory 248120 kb
Host smart-08a773cf-0318-471f-a122-0274c0cf637c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20185
63837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.2018563837
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.376422286
Short name T350
Test name
Test status
Simulation time 62678487779 ps
CPU time 1955.79 seconds
Started Aug 02 05:42:17 PM PDT 24
Finished Aug 02 06:14:53 PM PDT 24
Peak memory 272976 kb
Host smart-5f27b868-ca49-46d7-9739-c036610aa351
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376422286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.376422286
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.674810671
Short name T571
Test name
Test status
Simulation time 110210758883 ps
CPU time 3231.82 seconds
Started Aug 02 05:42:19 PM PDT 24
Finished Aug 02 06:36:12 PM PDT 24
Peak memory 288340 kb
Host smart-98bfbe8c-36ac-4ff8-b4cc-4cdb6e43e90d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674810671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.674810671
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.49513796
Short name T582
Test name
Test status
Simulation time 9437600310 ps
CPU time 202.78 seconds
Started Aug 02 05:42:16 PM PDT 24
Finished Aug 02 05:45:39 PM PDT 24
Peak memory 248412 kb
Host smart-6fe853e3-c539-4ab7-8d4a-57632a0a0095
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49513796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.49513796
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.140563531
Short name T48
Test name
Test status
Simulation time 480170059 ps
CPU time 40.04 seconds
Started Aug 02 05:42:16 PM PDT 24
Finished Aug 02 05:42:57 PM PDT 24
Peak memory 256492 kb
Host smart-243aa9cc-d799-49d8-8270-740044871430
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14056
3531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.140563531
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.2465348371
Short name T689
Test name
Test status
Simulation time 728377630 ps
CPU time 43.19 seconds
Started Aug 02 05:42:17 PM PDT 24
Finished Aug 02 05:43:00 PM PDT 24
Peak memory 248432 kb
Host smart-2fd76599-d670-493b-bc08-c4b31fb69c3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24653
48371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.2465348371
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.2183458938
Short name T686
Test name
Test status
Simulation time 8832556908 ps
CPU time 55.14 seconds
Started Aug 02 05:42:17 PM PDT 24
Finished Aug 02 05:43:12 PM PDT 24
Peak memory 247808 kb
Host smart-2d3cf65e-8bf5-4eb6-a7f2-6edb9d70d175
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21834
58938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.2183458938
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.3339341004
Short name T655
Test name
Test status
Simulation time 1297189438 ps
CPU time 24.32 seconds
Started Aug 02 05:42:17 PM PDT 24
Finished Aug 02 05:42:41 PM PDT 24
Peak memory 256380 kb
Host smart-74a10651-9539-41ef-bdd1-e2608956af27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33393
41004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.3339341004
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.1440036297
Short name T137
Test name
Test status
Simulation time 63523611391 ps
CPU time 1636.29 seconds
Started Aug 02 05:42:16 PM PDT 24
Finished Aug 02 06:09:33 PM PDT 24
Peak memory 289112 kb
Host smart-d1a40a18-9ca0-425e-9f90-b40ed8fecb0a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440036297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.1440036297
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.3911871773
Short name T296
Test name
Test status
Simulation time 71219076928 ps
CPU time 2541.77 seconds
Started Aug 02 05:42:26 PM PDT 24
Finished Aug 02 06:24:48 PM PDT 24
Peak memory 287208 kb
Host smart-cae411ef-e3bf-4ac1-bba5-be6aa00c905f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911871773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.3911871773
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.43551938
Short name T374
Test name
Test status
Simulation time 445870595 ps
CPU time 6.47 seconds
Started Aug 02 05:42:23 PM PDT 24
Finished Aug 02 05:42:29 PM PDT 24
Peak memory 254272 kb
Host smart-67f23573-25b8-4dbf-b545-16b5ee2931d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43551
938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.43551938
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.659577373
Short name T429
Test name
Test status
Simulation time 253224283 ps
CPU time 28.14 seconds
Started Aug 02 05:42:23 PM PDT 24
Finished Aug 02 05:42:52 PM PDT 24
Peak memory 247848 kb
Host smart-03da9964-b31e-4677-8ee9-ac594cd1ddb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65957
7373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.659577373
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.2882233948
Short name T654
Test name
Test status
Simulation time 251192960730 ps
CPU time 2320.54 seconds
Started Aug 02 05:42:22 PM PDT 24
Finished Aug 02 06:21:03 PM PDT 24
Peak memory 286640 kb
Host smart-da0fba66-b13a-4cf0-a9b1-4a6676f32263
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882233948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.2882233948
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.371074832
Short name T519
Test name
Test status
Simulation time 136249374915 ps
CPU time 2195.58 seconds
Started Aug 02 05:42:25 PM PDT 24
Finished Aug 02 06:19:01 PM PDT 24
Peak memory 272376 kb
Host smart-a8fd62e2-ea17-4bf9-af4f-50aa975ee681
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371074832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.371074832
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.997843399
Short name T322
Test name
Test status
Simulation time 4962899313 ps
CPU time 191.7 seconds
Started Aug 02 05:42:25 PM PDT 24
Finished Aug 02 05:45:37 PM PDT 24
Peak memory 248404 kb
Host smart-9389b879-2487-40a2-b2e9-b4651204d0ae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997843399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.997843399
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.2973736603
Short name T478
Test name
Test status
Simulation time 1066555996 ps
CPU time 24.86 seconds
Started Aug 02 05:42:26 PM PDT 24
Finished Aug 02 05:42:51 PM PDT 24
Peak memory 248368 kb
Host smart-4db810cb-add1-41b0-85e1-3116cff45a83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29737
36603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.2973736603
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.1958392414
Short name T515
Test name
Test status
Simulation time 77399514 ps
CPU time 2.78 seconds
Started Aug 02 05:42:23 PM PDT 24
Finished Aug 02 05:42:26 PM PDT 24
Peak memory 239608 kb
Host smart-49328ac4-51fd-4305-b6eb-cf6cc218167c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19583
92414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.1958392414
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.4107279594
Short name T98
Test name
Test status
Simulation time 4255530868 ps
CPU time 70.82 seconds
Started Aug 02 05:42:26 PM PDT 24
Finished Aug 02 05:43:37 PM PDT 24
Peak memory 255908 kb
Host smart-c833de4d-cc86-448e-bab1-bfd9a7b00c2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41072
79594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.4107279594
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.3621987778
Short name T481
Test name
Test status
Simulation time 545830280 ps
CPU time 34.33 seconds
Started Aug 02 05:42:17 PM PDT 24
Finished Aug 02 05:42:51 PM PDT 24
Peak memory 256384 kb
Host smart-91815c23-0bb2-471e-a440-b40ca92e31d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36219
87778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.3621987778
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.3308104922
Short name T279
Test name
Test status
Simulation time 30348343253 ps
CPU time 2059.96 seconds
Started Aug 02 05:42:26 PM PDT 24
Finished Aug 02 06:16:46 PM PDT 24
Peak memory 289136 kb
Host smart-40e5dfdc-cd4e-4b78-82c3-7cb59047ac42
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308104922 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.3308104922
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.2867480168
Short name T97
Test name
Test status
Simulation time 46058339137 ps
CPU time 2294.59 seconds
Started Aug 02 05:42:27 PM PDT 24
Finished Aug 02 06:20:42 PM PDT 24
Peak memory 286516 kb
Host smart-149b082e-402e-4d5f-a7de-1267c47df958
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867480168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.2867480168
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.3127379208
Short name T676
Test name
Test status
Simulation time 1605152613 ps
CPU time 64.37 seconds
Started Aug 02 05:42:31 PM PDT 24
Finished Aug 02 05:43:35 PM PDT 24
Peak memory 256548 kb
Host smart-aab908bf-1827-40a3-bf87-65674fb07f72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31273
79208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.3127379208
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.3054920974
Short name T382
Test name
Test status
Simulation time 267945805 ps
CPU time 5.11 seconds
Started Aug 02 05:42:23 PM PDT 24
Finished Aug 02 05:42:28 PM PDT 24
Peak memory 251012 kb
Host smart-8bb582a8-b5a0-4ed3-90ef-314a2e332b15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30549
20974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.3054920974
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.2664170056
Short name T331
Test name
Test status
Simulation time 181917158921 ps
CPU time 2577.2 seconds
Started Aug 02 05:42:27 PM PDT 24
Finished Aug 02 06:25:25 PM PDT 24
Peak memory 288324 kb
Host smart-a92d0c9e-132d-493b-80f4-0ded9185d25b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664170056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.2664170056
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.4285880229
Short name T557
Test name
Test status
Simulation time 25707337710 ps
CPU time 1285.34 seconds
Started Aug 02 05:42:28 PM PDT 24
Finished Aug 02 06:03:54 PM PDT 24
Peak memory 284848 kb
Host smart-9da5e29a-4a41-4557-a62e-ee6c60513355
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285880229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.4285880229
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.401726779
Short name T343
Test name
Test status
Simulation time 34332985746 ps
CPU time 375.98 seconds
Started Aug 02 05:42:24 PM PDT 24
Finished Aug 02 05:48:40 PM PDT 24
Peak memory 248212 kb
Host smart-9fd35e05-0e89-4cd5-a680-2f7c5ccd8473
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401726779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.401726779
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.541148807
Short name T414
Test name
Test status
Simulation time 956169427 ps
CPU time 30.16 seconds
Started Aug 02 05:42:22 PM PDT 24
Finished Aug 02 05:42:53 PM PDT 24
Peak memory 255808 kb
Host smart-311b2011-bcfe-41c6-8ecd-61fa145a697f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54114
8807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.541148807
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.1968331465
Short name T612
Test name
Test status
Simulation time 435303621 ps
CPU time 27.27 seconds
Started Aug 02 05:42:25 PM PDT 24
Finished Aug 02 05:42:52 PM PDT 24
Peak memory 254884 kb
Host smart-28cbc7d7-072a-41f6-95d3-9ec1d9190808
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19683
31465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.1968331465
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.2043481194
Short name T560
Test name
Test status
Simulation time 875909986 ps
CPU time 27.87 seconds
Started Aug 02 05:42:31 PM PDT 24
Finished Aug 02 05:42:59 PM PDT 24
Peak memory 247968 kb
Host smart-b20f9032-f7c1-4ceb-b8d3-a14c39fc0bf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20434
81194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.2043481194
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.2457127625
Short name T471
Test name
Test status
Simulation time 490221081 ps
CPU time 9.1 seconds
Started Aug 02 05:42:31 PM PDT 24
Finished Aug 02 05:42:40 PM PDT 24
Peak memory 248388 kb
Host smart-95594e27-2dfa-48e9-9a25-f7d5bdb7270f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24571
27625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.2457127625
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.467089606
Short name T510
Test name
Test status
Simulation time 59771386827 ps
CPU time 2752.07 seconds
Started Aug 02 05:42:27 PM PDT 24
Finished Aug 02 06:28:19 PM PDT 24
Peak memory 288920 kb
Host smart-e7238fae-df9b-44dc-8bc6-0551c1cf269c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467089606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_han
dler_stress_all.467089606
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all_with_rand_reset.1259743568
Short name T542
Test name
Test status
Simulation time 269280397124 ps
CPU time 4213.98 seconds
Started Aug 02 05:42:27 PM PDT 24
Finished Aug 02 06:52:41 PM PDT 24
Peak memory 305848 kb
Host smart-341d83ab-608e-4d80-84fe-e20de373a3f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259743568 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.alert_handler_stress_all_with_rand_reset.1259743568
Directory /workspace/46.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.2013880111
Short name T695
Test name
Test status
Simulation time 49015385597 ps
CPU time 2849.16 seconds
Started Aug 02 05:42:32 PM PDT 24
Finished Aug 02 06:30:01 PM PDT 24
Peak memory 286936 kb
Host smart-4bd438c8-d307-4532-82fa-25a0f34e7ba8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013880111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.2013880111
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.3334441307
Short name T672
Test name
Test status
Simulation time 8554861432 ps
CPU time 150.28 seconds
Started Aug 02 05:42:32 PM PDT 24
Finished Aug 02 05:45:02 PM PDT 24
Peak memory 256576 kb
Host smart-77965818-08dc-46db-a946-93d34af94536
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33344
41307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.3334441307
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.1024797378
Short name T94
Test name
Test status
Simulation time 1678596078 ps
CPU time 51.71 seconds
Started Aug 02 05:42:31 PM PDT 24
Finished Aug 02 05:43:23 PM PDT 24
Peak memory 256092 kb
Host smart-d9841585-3a51-45e4-94b6-b5b2d7fd1855
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10247
97378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.1024797378
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.2667836336
Short name T435
Test name
Test status
Simulation time 358437041254 ps
CPU time 2214.06 seconds
Started Aug 02 05:42:31 PM PDT 24
Finished Aug 02 06:19:26 PM PDT 24
Peak memory 284716 kb
Host smart-4764942c-24d9-4126-955b-2721130f652e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667836336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.2667836336
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.1675940309
Short name T14
Test name
Test status
Simulation time 37786086327 ps
CPU time 411.74 seconds
Started Aug 02 05:42:30 PM PDT 24
Finished Aug 02 05:49:22 PM PDT 24
Peak memory 247292 kb
Host smart-263dfbcd-400f-4520-bec5-d74e17287fbe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675940309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.1675940309
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.4030841536
Short name T427
Test name
Test status
Simulation time 1456446672 ps
CPU time 10.31 seconds
Started Aug 02 05:42:33 PM PDT 24
Finished Aug 02 05:42:43 PM PDT 24
Peak memory 248344 kb
Host smart-b3c9eb7d-03d0-43f6-a8a6-9c5e017b1a58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40308
41536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.4030841536
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.3057447327
Short name T643
Test name
Test status
Simulation time 2909545697 ps
CPU time 55.93 seconds
Started Aug 02 05:42:30 PM PDT 24
Finished Aug 02 05:43:26 PM PDT 24
Peak memory 256088 kb
Host smart-5ce2fcf0-9bac-4f0e-a2f7-577be953db84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30574
47327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.3057447327
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.3939222211
Short name T276
Test name
Test status
Simulation time 840522114 ps
CPU time 51.43 seconds
Started Aug 02 05:42:30 PM PDT 24
Finished Aug 02 05:43:22 PM PDT 24
Peak memory 247968 kb
Host smart-8a9105d2-bba4-4209-8fe4-8e35a61c3a37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39392
22211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.3939222211
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.2186465153
Short name T662
Test name
Test status
Simulation time 569099201 ps
CPU time 12.89 seconds
Started Aug 02 05:42:32 PM PDT 24
Finished Aug 02 05:42:45 PM PDT 24
Peak memory 256368 kb
Host smart-74640192-d0ea-45c3-895e-a357cca9261a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21864
65153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.2186465153
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.342891486
Short name T509
Test name
Test status
Simulation time 32435914279 ps
CPU time 1821.71 seconds
Started Aug 02 05:42:32 PM PDT 24
Finished Aug 02 06:12:54 PM PDT 24
Peak memory 272856 kb
Host smart-e3a93e9b-d43a-43a1-93e6-6e4206f71ff7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342891486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_han
dler_stress_all.342891486
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.1046796768
Short name T700
Test name
Test status
Simulation time 89363837878 ps
CPU time 8047.17 seconds
Started Aug 02 05:42:32 PM PDT 24
Finished Aug 02 07:56:40 PM PDT 24
Peak memory 368384 kb
Host smart-a13e108e-b202-4f21-ba01-6679c69eceba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046796768 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.1046796768
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.1927692926
Short name T45
Test name
Test status
Simulation time 2075369405 ps
CPU time 116.79 seconds
Started Aug 02 05:42:31 PM PDT 24
Finished Aug 02 05:44:28 PM PDT 24
Peak memory 256004 kb
Host smart-83733968-9abb-4d19-98d9-9b4c64f71cfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19276
92926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.1927692926
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.949661104
Short name T416
Test name
Test status
Simulation time 954358507 ps
CPU time 63.99 seconds
Started Aug 02 05:42:32 PM PDT 24
Finished Aug 02 05:43:36 PM PDT 24
Peak memory 256096 kb
Host smart-ef41c799-d427-4580-9161-d9d2115288a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94966
1104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.949661104
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.3559490880
Short name T43
Test name
Test status
Simulation time 89676380027 ps
CPU time 2140.12 seconds
Started Aug 02 05:42:32 PM PDT 24
Finished Aug 02 06:18:13 PM PDT 24
Peak memory 289352 kb
Host smart-acbce393-ad8c-47e4-a371-acdf3a32cb38
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559490880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.3559490880
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.461785252
Short name T259
Test name
Test status
Simulation time 140610034304 ps
CPU time 2373.06 seconds
Started Aug 02 05:42:30 PM PDT 24
Finished Aug 02 06:22:04 PM PDT 24
Peak memory 272988 kb
Host smart-41cce4e5-2baa-4b56-b830-0e02cd2a52f5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461785252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.461785252
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.828748069
Short name T54
Test name
Test status
Simulation time 566668993 ps
CPU time 40.47 seconds
Started Aug 02 05:42:33 PM PDT 24
Finished Aug 02 05:43:14 PM PDT 24
Peak memory 255916 kb
Host smart-5c51bb40-a111-4deb-93d2-990503cd0f53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82874
8069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.828748069
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.3304075808
Short name T371
Test name
Test status
Simulation time 658332865 ps
CPU time 42.66 seconds
Started Aug 02 05:42:30 PM PDT 24
Finished Aug 02 05:43:13 PM PDT 24
Peak memory 248180 kb
Host smart-11b03be5-8120-48a2-9526-6497eea52953
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33040
75808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.3304075808
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.275783484
Short name T217
Test name
Test status
Simulation time 370451029 ps
CPU time 24.85 seconds
Started Aug 02 05:42:32 PM PDT 24
Finished Aug 02 05:42:58 PM PDT 24
Peak memory 255896 kb
Host smart-134c6f16-3fe0-4a06-9409-59d66375a2f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27578
3484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.275783484
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.595431098
Short name T587
Test name
Test status
Simulation time 411802855 ps
CPU time 36.63 seconds
Started Aug 02 05:42:31 PM PDT 24
Finished Aug 02 05:43:08 PM PDT 24
Peak memory 256560 kb
Host smart-f4ce1845-3b41-4c46-81eb-ca2f343bf41b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59543
1098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.595431098
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.1419951033
Short name T638
Test name
Test status
Simulation time 70179260993 ps
CPU time 2045.16 seconds
Started Aug 02 05:42:33 PM PDT 24
Finished Aug 02 06:16:38 PM PDT 24
Peak memory 273064 kb
Host smart-283222b1-76a0-4702-840f-dd3c4045d629
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419951033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.1419951033
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all_with_rand_reset.1694482932
Short name T670
Test name
Test status
Simulation time 135383284451 ps
CPU time 4162.56 seconds
Started Aug 02 05:42:34 PM PDT 24
Finished Aug 02 06:51:57 PM PDT 24
Peak memory 321752 kb
Host smart-97dff219-b593-473e-b47d-71d69f2f8b27
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694482932 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.alert_handler_stress_all_with_rand_reset.1694482932
Directory /workspace/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.2501311937
Short name T67
Test name
Test status
Simulation time 9214408080 ps
CPU time 828.16 seconds
Started Aug 02 05:42:43 PM PDT 24
Finished Aug 02 05:56:31 PM PDT 24
Peak memory 273020 kb
Host smart-da4584a8-5a78-4a88-8b59-d1bdade8f5a5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501311937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.2501311937
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.1243851375
Short name T474
Test name
Test status
Simulation time 26237331470 ps
CPU time 266.54 seconds
Started Aug 02 05:42:30 PM PDT 24
Finished Aug 02 05:46:57 PM PDT 24
Peak memory 256576 kb
Host smart-081f5a8a-3dd8-4997-9e67-1ce7473cb264
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12438
51375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.1243851375
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.2354706353
Short name T704
Test name
Test status
Simulation time 1243210535 ps
CPU time 20.07 seconds
Started Aug 02 05:42:31 PM PDT 24
Finished Aug 02 05:42:51 PM PDT 24
Peak memory 247996 kb
Host smart-1b46fddf-2a72-4b29-95bd-ea38f670061e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23547
06353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.2354706353
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.53653249
Short name T120
Test name
Test status
Simulation time 66366642120 ps
CPU time 1142.15 seconds
Started Aug 02 05:42:42 PM PDT 24
Finished Aug 02 06:01:45 PM PDT 24
Peak memory 272272 kb
Host smart-dd79e2f2-01a4-4889-a255-ebc5bce3e1f6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53653249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.53653249
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.1154451970
Short name T316
Test name
Test status
Simulation time 9669401708 ps
CPU time 408.14 seconds
Started Aug 02 05:42:43 PM PDT 24
Finished Aug 02 05:49:31 PM PDT 24
Peak memory 247760 kb
Host smart-24abc584-1eb4-444a-b838-386bddfaec86
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154451970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.1154451970
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.1637769508
Short name T508
Test name
Test status
Simulation time 2479000118 ps
CPU time 37.38 seconds
Started Aug 02 05:42:32 PM PDT 24
Finished Aug 02 05:43:09 PM PDT 24
Peak memory 256100 kb
Host smart-818fb3f1-eea0-4577-b92a-30e7042014f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16377
69508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.1637769508
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.965970048
Short name T122
Test name
Test status
Simulation time 4950719836 ps
CPU time 85.27 seconds
Started Aug 02 05:42:32 PM PDT 24
Finished Aug 02 05:43:58 PM PDT 24
Peak memory 256204 kb
Host smart-8389db03-fcdb-476b-afac-b14111815170
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96597
0048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.965970048
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.2609452705
Short name T77
Test name
Test status
Simulation time 1230176457 ps
CPU time 34.39 seconds
Started Aug 02 05:42:42 PM PDT 24
Finished Aug 02 05:43:16 PM PDT 24
Peak memory 256108 kb
Host smart-ba5e7513-7fa4-479a-b2ed-072a64cd3d07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26094
52705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.2609452705
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.282863198
Short name T27
Test name
Test status
Simulation time 574822084 ps
CPU time 32.74 seconds
Started Aug 02 05:42:32 PM PDT 24
Finished Aug 02 05:43:05 PM PDT 24
Peak memory 255620 kb
Host smart-4de6f438-4d88-4d26-991d-230cfa1298a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28286
3198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.282863198
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.2676407383
Short name T232
Test name
Test status
Simulation time 60106299 ps
CPU time 2.59 seconds
Started Aug 02 05:39:53 PM PDT 24
Finished Aug 02 05:39:56 PM PDT 24
Peak memory 248592 kb
Host smart-cc9f9272-0c4d-409e-b21d-899b461b8fe5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2676407383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.2676407383
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.3307529966
Short name T499
Test name
Test status
Simulation time 114460888216 ps
CPU time 1059.76 seconds
Started Aug 02 05:40:02 PM PDT 24
Finished Aug 02 05:57:42 PM PDT 24
Peak memory 272700 kb
Host smart-1b20c051-58d0-47d1-ba70-2c4bd3131907
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307529966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.3307529966
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.2157902709
Short name T377
Test name
Test status
Simulation time 5373153038 ps
CPU time 309.03 seconds
Started Aug 02 05:40:00 PM PDT 24
Finished Aug 02 05:45:09 PM PDT 24
Peak memory 256084 kb
Host smart-4186fd70-ec18-443e-93ed-90629888517b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21579
02709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.2157902709
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.3304473557
Short name T21
Test name
Test status
Simulation time 4417191470 ps
CPU time 49.01 seconds
Started Aug 02 05:40:01 PM PDT 24
Finished Aug 02 05:40:50 PM PDT 24
Peak memory 256636 kb
Host smart-16951302-3083-46ac-a02e-fea5b20e4e86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33044
73557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.3304473557
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.219260896
Short name T527
Test name
Test status
Simulation time 45110507757 ps
CPU time 1738.99 seconds
Started Aug 02 05:39:50 PM PDT 24
Finished Aug 02 06:08:49 PM PDT 24
Peak memory 273008 kb
Host smart-f20c8ae7-1769-415e-b0d8-c6b31a4e9b9d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219260896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.219260896
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.1397059284
Short name T501
Test name
Test status
Simulation time 3175906238 ps
CPU time 131.85 seconds
Started Aug 02 05:40:01 PM PDT 24
Finished Aug 02 05:42:13 PM PDT 24
Peak memory 248396 kb
Host smart-f76b8973-2347-4919-8b52-5e2f060cbcd0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397059284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.1397059284
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.1121265876
Short name T614
Test name
Test status
Simulation time 696876070 ps
CPU time 15.23 seconds
Started Aug 02 05:39:53 PM PDT 24
Finished Aug 02 05:40:08 PM PDT 24
Peak memory 256248 kb
Host smart-87ba63d7-277d-4c15-aa95-2321e5533d4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11212
65876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.1121265876
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.1912375590
Short name T245
Test name
Test status
Simulation time 151424918 ps
CPU time 9.53 seconds
Started Aug 02 05:40:04 PM PDT 24
Finished Aug 02 05:40:14 PM PDT 24
Peak memory 250788 kb
Host smart-e5c76697-f570-4a46-b634-e579e9f9cc1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19123
75590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.1912375590
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.337363543
Short name T248
Test name
Test status
Simulation time 424651584 ps
CPU time 32.34 seconds
Started Aug 02 05:40:00 PM PDT 24
Finished Aug 02 05:40:32 PM PDT 24
Peak memory 248700 kb
Host smart-df51546b-aa86-4aba-bcdf-886794e074e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33736
3543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.337363543
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.3438470985
Short name T226
Test name
Test status
Simulation time 88217029 ps
CPU time 4.1 seconds
Started Aug 02 05:39:58 PM PDT 24
Finished Aug 02 05:40:03 PM PDT 24
Peak memory 248576 kb
Host smart-40b6c06b-72b7-4ae0-89f1-b6b25b6380f4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3438470985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.3438470985
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.3370694347
Short name T132
Test name
Test status
Simulation time 51030347877 ps
CPU time 1406.51 seconds
Started Aug 02 05:39:52 PM PDT 24
Finished Aug 02 06:03:19 PM PDT 24
Peak memory 273024 kb
Host smart-481acbe2-a700-495a-9db9-a5f2550f9597
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370694347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.3370694347
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.3501798693
Short name T681
Test name
Test status
Simulation time 1056057376 ps
CPU time 45.53 seconds
Started Aug 02 05:39:54 PM PDT 24
Finished Aug 02 05:40:40 PM PDT 24
Peak memory 248320 kb
Host smart-ba8728db-0db5-4751-a424-d49127b53fed
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3501798693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.3501798693
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.2974682182
Short name T442
Test name
Test status
Simulation time 2072374849 ps
CPU time 132.93 seconds
Started Aug 02 05:39:50 PM PDT 24
Finished Aug 02 05:42:03 PM PDT 24
Peak memory 255896 kb
Host smart-8998d14a-3341-49b5-adfa-0e4d69bce3b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29746
82182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.2974682182
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.3851561319
Short name T92
Test name
Test status
Simulation time 949304516 ps
CPU time 55.94 seconds
Started Aug 02 05:40:03 PM PDT 24
Finished Aug 02 05:40:59 PM PDT 24
Peak memory 248076 kb
Host smart-c70c3ac1-a9e7-433a-a100-151a737060f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38515
61319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.3851561319
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.3663902411
Short name T291
Test name
Test status
Simulation time 15359202381 ps
CPU time 1345.06 seconds
Started Aug 02 05:40:03 PM PDT 24
Finished Aug 02 06:02:28 PM PDT 24
Peak memory 289328 kb
Host smart-da0852ea-48de-4eb7-9f59-071e8ae89471
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663902411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.3663902411
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.3887426496
Short name T456
Test name
Test status
Simulation time 93869820405 ps
CPU time 1451.34 seconds
Started Aug 02 05:39:59 PM PDT 24
Finished Aug 02 06:04:11 PM PDT 24
Peak memory 272828 kb
Host smart-433d913d-afb5-49b9-a57b-b29ab962d0b3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887426496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.3887426496
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.452666511
Short name T346
Test name
Test status
Simulation time 8999013599 ps
CPU time 392.42 seconds
Started Aug 02 05:40:01 PM PDT 24
Finished Aug 02 05:46:34 PM PDT 24
Peak memory 248412 kb
Host smart-b7baf294-adbb-496c-b0da-83a4625f2545
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452666511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.452666511
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.4159741913
Short name T604
Test name
Test status
Simulation time 717014666 ps
CPU time 11.01 seconds
Started Aug 02 05:40:02 PM PDT 24
Finished Aug 02 05:40:13 PM PDT 24
Peak memory 248380 kb
Host smart-183cef49-6acf-403e-868c-cbcd98fe304f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41597
41913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.4159741913
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.2160962937
Short name T569
Test name
Test status
Simulation time 176997952 ps
CPU time 16.73 seconds
Started Aug 02 05:40:01 PM PDT 24
Finished Aug 02 05:40:18 PM PDT 24
Peak memory 256104 kb
Host smart-6075bb1f-084e-4b94-91af-42bd64298163
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21609
62937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.2160962937
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.1619193287
Short name T105
Test name
Test status
Simulation time 138388359 ps
CPU time 5.85 seconds
Started Aug 02 05:40:00 PM PDT 24
Finished Aug 02 05:40:06 PM PDT 24
Peak memory 239656 kb
Host smart-fd02757b-9e0a-4886-809f-6fb9a089fd6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16191
93287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.1619193287
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.3674909531
Short name T424
Test name
Test status
Simulation time 8879394366 ps
CPU time 36.27 seconds
Started Aug 02 05:39:53 PM PDT 24
Finished Aug 02 05:40:29 PM PDT 24
Peak memory 256488 kb
Host smart-d9a1132f-b7b4-4db2-9131-ce64de223552
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36749
09531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.3674909531
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.1973970013
Short name T99
Test name
Test status
Simulation time 18028857395 ps
CPU time 250.47 seconds
Started Aug 02 05:40:04 PM PDT 24
Finished Aug 02 05:44:14 PM PDT 24
Peak memory 256632 kb
Host smart-513d3503-41b8-41ed-bb37-a6c404f4f029
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973970013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.1973970013
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.513405330
Short name T102
Test name
Test status
Simulation time 252434312379 ps
CPU time 4567.93 seconds
Started Aug 02 05:39:51 PM PDT 24
Finished Aug 02 06:56:00 PM PDT 24
Peak memory 288916 kb
Host smart-223984ef-15c8-4377-a756-f7df6c58fbed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513405330 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.513405330
Directory /workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.3373062725
Short name T215
Test name
Test status
Simulation time 121918171 ps
CPU time 2.34 seconds
Started Aug 02 05:40:02 PM PDT 24
Finished Aug 02 05:40:04 PM PDT 24
Peak memory 248736 kb
Host smart-c616a20e-a8f6-4150-9a40-ec578feacf74
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3373062725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.3373062725
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.3958121983
Short name T659
Test name
Test status
Simulation time 26573650086 ps
CPU time 1591.93 seconds
Started Aug 02 05:39:53 PM PDT 24
Finished Aug 02 06:06:25 PM PDT 24
Peak memory 272380 kb
Host smart-a1c5e920-dfc4-47c4-a9d7-4d311190b0e9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958121983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.3958121983
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.2661881486
Short name T696
Test name
Test status
Simulation time 1251211431 ps
CPU time 16.21 seconds
Started Aug 02 05:40:00 PM PDT 24
Finished Aug 02 05:40:16 PM PDT 24
Peak memory 248256 kb
Host smart-194f811f-641a-463b-8965-b8d96172ab4a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2661881486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.2661881486
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.3842857198
Short name T41
Test name
Test status
Simulation time 3354492281 ps
CPU time 59.09 seconds
Started Aug 02 05:39:55 PM PDT 24
Finished Aug 02 05:40:54 PM PDT 24
Peak memory 249540 kb
Host smart-c12cd9b5-8c8d-4e0d-9f65-1df9c4e319bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38428
57198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.3842857198
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.239474521
Short name T142
Test name
Test status
Simulation time 2117916535 ps
CPU time 35.26 seconds
Started Aug 02 05:39:53 PM PDT 24
Finished Aug 02 05:40:29 PM PDT 24
Peak memory 248344 kb
Host smart-db1081a6-865a-4229-8e23-b4abf85fc45d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23947
4521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.239474521
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.267920238
Short name T359
Test name
Test status
Simulation time 51259653710 ps
CPU time 3108.63 seconds
Started Aug 02 05:40:01 PM PDT 24
Finished Aug 02 06:31:50 PM PDT 24
Peak memory 288952 kb
Host smart-ae102520-0cc2-4d3c-9136-5ee2e38694e2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267920238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.267920238
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.785705970
Short name T522
Test name
Test status
Simulation time 16181772653 ps
CPU time 1405.74 seconds
Started Aug 02 05:40:03 PM PDT 24
Finished Aug 02 06:03:29 PM PDT 24
Peak memory 287444 kb
Host smart-fb276722-8a43-433d-8ae8-6538e70cacee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785705970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.785705970
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.101634704
Short name T550
Test name
Test status
Simulation time 10039473418 ps
CPU time 131.47 seconds
Started Aug 02 05:40:08 PM PDT 24
Finished Aug 02 05:42:20 PM PDT 24
Peak memory 248400 kb
Host smart-0319fcd2-a8a1-446f-abe7-0d4ec821abc7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101634704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.101634704
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.1427159908
Short name T680
Test name
Test status
Simulation time 1661069828 ps
CPU time 38.53 seconds
Started Aug 02 05:40:03 PM PDT 24
Finished Aug 02 05:40:42 PM PDT 24
Peak memory 248428 kb
Host smart-94284e5c-daf0-4799-9dcf-de445f3ae278
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14271
59908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.1427159908
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.4251880136
Short name T559
Test name
Test status
Simulation time 866878745 ps
CPU time 52.91 seconds
Started Aug 02 05:40:03 PM PDT 24
Finished Aug 02 05:40:56 PM PDT 24
Peak memory 247968 kb
Host smart-1ca6ab1d-c8ac-4e1e-8e67-f31031bdcd33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42518
80136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.4251880136
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.1561346767
Short name T455
Test name
Test status
Simulation time 4868958252 ps
CPU time 27.98 seconds
Started Aug 02 05:39:58 PM PDT 24
Finished Aug 02 05:40:27 PM PDT 24
Peak memory 256524 kb
Host smart-349a6efa-d0b9-4c38-8402-e67ae34135b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15613
46767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.1561346767
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.2756571794
Short name T476
Test name
Test status
Simulation time 569265005 ps
CPU time 17.79 seconds
Started Aug 02 05:39:49 PM PDT 24
Finished Aug 02 05:40:07 PM PDT 24
Peak memory 256256 kb
Host smart-a129dec6-3c25-43d2-a0ea-5b59c1300364
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27565
71794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.2756571794
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.1594585419
Short name T297
Test name
Test status
Simulation time 9889836455 ps
CPU time 541.88 seconds
Started Aug 02 05:40:01 PM PDT 24
Finished Aug 02 05:49:03 PM PDT 24
Peak memory 264764 kb
Host smart-9ba56f41-6bf1-42c4-a951-60a4cf36a1d5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594585419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.1594585419
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.1379621992
Short name T309
Test name
Test status
Simulation time 27468436828 ps
CPU time 2616.3 seconds
Started Aug 02 05:40:00 PM PDT 24
Finished Aug 02 06:23:37 PM PDT 24
Peak memory 321780 kb
Host smart-38908391-cd00-4c7d-8508-bb7d0837f91c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379621992 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.1379621992
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.2262346392
Short name T227
Test name
Test status
Simulation time 46631343 ps
CPU time 4.1 seconds
Started Aug 02 05:40:05 PM PDT 24
Finished Aug 02 05:40:09 PM PDT 24
Peak memory 248600 kb
Host smart-726a1c54-a5ce-45d1-beb3-d90cc3202ce0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2262346392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.2262346392
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.2144130853
Short name T138
Test name
Test status
Simulation time 34694212625 ps
CPU time 2472.5 seconds
Started Aug 02 05:40:01 PM PDT 24
Finished Aug 02 06:21:14 PM PDT 24
Peak memory 288616 kb
Host smart-f087aeef-0cd9-417d-8062-376ff640a4f2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144130853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.2144130853
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.2143211592
Short name T518
Test name
Test status
Simulation time 158909633 ps
CPU time 9.73 seconds
Started Aug 02 05:40:03 PM PDT 24
Finished Aug 02 05:40:13 PM PDT 24
Peak memory 248312 kb
Host smart-07bda72b-d695-49b7-8d21-2a9c90373a2b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2143211592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.2143211592
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.4250185440
Short name T488
Test name
Test status
Simulation time 6989737261 ps
CPU time 135.9 seconds
Started Aug 02 05:40:07 PM PDT 24
Finished Aug 02 05:42:22 PM PDT 24
Peak memory 256188 kb
Host smart-69c1df0b-d271-419b-85ba-55f18b41a53f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42501
85440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.4250185440
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.3935759980
Short name T551
Test name
Test status
Simulation time 1000760270 ps
CPU time 18 seconds
Started Aug 02 05:40:01 PM PDT 24
Finished Aug 02 05:40:20 PM PDT 24
Peak memory 248432 kb
Host smart-36012159-0e19-4b13-9cf2-f5be17b79345
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39357
59980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.3935759980
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.3591133885
Short name T632
Test name
Test status
Simulation time 143359525382 ps
CPU time 1060.02 seconds
Started Aug 02 05:40:00 PM PDT 24
Finished Aug 02 05:57:40 PM PDT 24
Peak memory 272832 kb
Host smart-b22b5d5d-a605-405a-b50a-aad5063d8fe4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591133885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.3591133885
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.1532958172
Short name T626
Test name
Test status
Simulation time 25557607426 ps
CPU time 1610.22 seconds
Started Aug 02 05:40:01 PM PDT 24
Finished Aug 02 06:06:52 PM PDT 24
Peak memory 272800 kb
Host smart-b0bba03a-80f0-4a19-a8cc-15e758adbc62
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532958172 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.1532958172
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.1496568976
Short name T651
Test name
Test status
Simulation time 8800115284 ps
CPU time 345.01 seconds
Started Aug 02 05:40:03 PM PDT 24
Finished Aug 02 05:45:48 PM PDT 24
Peak memory 248404 kb
Host smart-c823b410-6d83-49e2-a40f-89347f8eeb39
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496568976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.1496568976
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.915650617
Short name T618
Test name
Test status
Simulation time 373759568 ps
CPU time 7.43 seconds
Started Aug 02 05:40:04 PM PDT 24
Finished Aug 02 05:40:12 PM PDT 24
Peak memory 248340 kb
Host smart-54a650ce-2c09-47cf-8639-52fc2a023bf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91565
0617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.915650617
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.4176494232
Short name T384
Test name
Test status
Simulation time 20575368 ps
CPU time 2.96 seconds
Started Aug 02 05:40:02 PM PDT 24
Finished Aug 02 05:40:05 PM PDT 24
Peak memory 240172 kb
Host smart-513b4df5-e40a-4146-9af5-b0c89beeb4d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41764
94232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.4176494232
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.3380647229
Short name T275
Test name
Test status
Simulation time 1000954108 ps
CPU time 34.99 seconds
Started Aug 02 05:40:06 PM PDT 24
Finished Aug 02 05:40:41 PM PDT 24
Peak memory 248228 kb
Host smart-31201949-63c2-4200-a498-e555c135a7c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33806
47229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.3380647229
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.755342299
Short name T487
Test name
Test status
Simulation time 423073247 ps
CPU time 18.34 seconds
Started Aug 02 05:40:00 PM PDT 24
Finished Aug 02 05:40:18 PM PDT 24
Peak memory 255556 kb
Host smart-034a3f82-a9c4-43dc-9b9a-287bebcd6736
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75534
2299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.755342299
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.197410922
Short name T423
Test name
Test status
Simulation time 30866411460 ps
CPU time 315.05 seconds
Started Aug 02 05:40:05 PM PDT 24
Finished Aug 02 05:45:20 PM PDT 24
Peak memory 256636 kb
Host smart-32bbf5f1-7be8-45ea-9fa2-14ecdf47074b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197410922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_hand
ler_stress_all.197410922
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.2787222581
Short name T212
Test name
Test status
Simulation time 84044056437 ps
CPU time 2338.49 seconds
Started Aug 02 05:40:07 PM PDT 24
Finished Aug 02 06:19:05 PM PDT 24
Peak memory 315804 kb
Host smart-7b830c58-a18a-438d-b7d0-ed8f36817419
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787222581 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.2787222581
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.3220343362
Short name T241
Test name
Test status
Simulation time 29170360 ps
CPU time 2.9 seconds
Started Aug 02 05:40:02 PM PDT 24
Finished Aug 02 05:40:05 PM PDT 24
Peak memory 248668 kb
Host smart-24a7efd0-ac41-4726-a009-92ac5e51f8f6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3220343362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.3220343362
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.1451257080
Short name T402
Test name
Test status
Simulation time 42420200823 ps
CPU time 2561.06 seconds
Started Aug 02 05:40:00 PM PDT 24
Finished Aug 02 06:22:42 PM PDT 24
Peak memory 285556 kb
Host smart-0221dbaf-13a0-484d-94c8-05061a836bbf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451257080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.1451257080
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.2985023429
Short name T597
Test name
Test status
Simulation time 560474608 ps
CPU time 6.73 seconds
Started Aug 02 05:40:00 PM PDT 24
Finished Aug 02 05:40:07 PM PDT 24
Peak memory 248332 kb
Host smart-68bca87f-ea92-4052-9545-2de442b02245
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2985023429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.2985023429
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.3171353640
Short name T266
Test name
Test status
Simulation time 25926655432 ps
CPU time 85.72 seconds
Started Aug 02 05:40:01 PM PDT 24
Finished Aug 02 05:41:27 PM PDT 24
Peak memory 255952 kb
Host smart-c70cce48-0c57-4aa7-b59e-b6026a986f59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31713
53640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.3171353640
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.2591878908
Short name T484
Test name
Test status
Simulation time 1298915246 ps
CPU time 44.66 seconds
Started Aug 02 05:40:03 PM PDT 24
Finished Aug 02 05:40:48 PM PDT 24
Peak memory 248032 kb
Host smart-c658bc2b-b246-4aae-bfb6-b76fb6b1f765
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25918
78908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.2591878908
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.1182684018
Short name T496
Test name
Test status
Simulation time 18566689523 ps
CPU time 1230.03 seconds
Started Aug 02 05:40:07 PM PDT 24
Finished Aug 02 06:00:38 PM PDT 24
Peak memory 272300 kb
Host smart-5ecf0857-0efd-4b38-8ad1-24a18660609e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182684018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.1182684018
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.724216339
Short name T673
Test name
Test status
Simulation time 19410278664 ps
CPU time 97.87 seconds
Started Aug 02 05:40:01 PM PDT 24
Finished Aug 02 05:41:39 PM PDT 24
Peak memory 248392 kb
Host smart-d3fa74c0-e7a5-4dfb-84c2-7628110625df
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724216339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.724216339
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.1269128576
Short name T409
Test name
Test status
Simulation time 632595878 ps
CPU time 38.34 seconds
Started Aug 02 05:40:05 PM PDT 24
Finished Aug 02 05:40:43 PM PDT 24
Peak memory 255784 kb
Host smart-e752cddd-fcf7-4041-8599-ba66633a7e76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12691
28576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.1269128576
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.1078782072
Short name T421
Test name
Test status
Simulation time 376069896 ps
CPU time 14.21 seconds
Started Aug 02 05:40:01 PM PDT 24
Finished Aug 02 05:40:16 PM PDT 24
Peak memory 248384 kb
Host smart-bda87a8d-2dcf-4ae3-b8e2-574dbbd4296a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10787
82072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.1078782072
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.2506369104
Short name T536
Test name
Test status
Simulation time 262630506 ps
CPU time 9.65 seconds
Started Aug 02 05:40:04 PM PDT 24
Finished Aug 02 05:40:13 PM PDT 24
Peak memory 252228 kb
Host smart-e3ea1df7-5c76-4747-a6f5-bf3f6a294092
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25063
69104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.2506369104
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.1223507838
Short name T79
Test name
Test status
Simulation time 2827376733 ps
CPU time 47.03 seconds
Started Aug 02 05:40:04 PM PDT 24
Finished Aug 02 05:40:51 PM PDT 24
Peak memory 256580 kb
Host smart-a58934a0-3ccd-4216-901b-cf89955e6cbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12235
07838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.1223507838
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.669075355
Short name T498
Test name
Test status
Simulation time 59751488778 ps
CPU time 1470.76 seconds
Started Aug 02 05:40:02 PM PDT 24
Finished Aug 02 06:04:33 PM PDT 24
Peak memory 301292 kb
Host smart-56c48053-fb94-4032-a3ba-a2005ea2e8f9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669075355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_hand
ler_stress_all.669075355
Directory /workspace/9.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.3593671876
Short name T143
Test name
Test status
Simulation time 36412536442 ps
CPU time 867.32 seconds
Started Aug 02 05:40:06 PM PDT 24
Finished Aug 02 05:54:33 PM PDT 24
Peak memory 283336 kb
Host smart-242badb9-025a-4b3a-8d88-72eee91b7499
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593671876 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.3593671876
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest
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