Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	75462	1			T3	3619		T6	2		T4	591
class_i[0x1]	43980	1			T1	8		T10	788		T6	1
class_i[0x2]	48773	1			T3	10		T10	11		T6	11
class_i[0x3]	61488	1			T10	10		T12	260		T24	4

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	56469	1			T1	1		T3	875		T10	9
alert[0x1]	55201	1			T1	1		T3	923		T10	396
alert[0x2]	62405	1			T1	4		T3	974		T10	12
alert[0x3]	55628	1			T1	2		T3	857		T10	392

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

229437

1

T1

8

T3

3629

T10

809

esc_ping_fail

266

1

T6

6

T15

5

T16

6

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	56398	1			T1	1		T3	875		T10	9
esc_integrity_fail	alert[0x1]	55134	1			T1	1		T3	923		T10	396
esc_integrity_fail	alert[0x2]	62344	1			T1	4		T3	974		T10	12
esc_integrity_fail	alert[0x3]	55561	1			T1	2		T3	857		T10	392
esc_ping_fail	alert[0x0]	71	1			T6	2		T15	2		T16	1
esc_ping_fail	alert[0x1]	67	1			T6	1		T15	1		T16	2
esc_ping_fail	alert[0x2]	61	1			T6	2		T15	2		T16	1
esc_ping_fail	alert[0x3]	67	1			T6	1		T16	2		T46	2

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	75388	1			T3	3619		T4	591		T17	1585
esc_integrity_fail	class_i[0x1]	43915	1			T1	8		T10	788		T4	8
esc_integrity_fail	class_i[0x2]	48705	1			T3	10		T10	11		T6	8
esc_integrity_fail	class_i[0x3]	61429	1			T10	10		T12	260		T24	4
esc_ping_fail	class_i[0x0]	74	1			T6	2		T15	5		T16	5
esc_ping_fail	class_i[0x1]	65	1			T6	1		T46	1		T247	1
esc_ping_fail	class_i[0x2]	68	1			T6	3		T46	8		T244	2
esc_ping_fail	class_i[0x3]	59	1			T16	1		T46	1		T247	3