Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	634428730	0	0	620
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	634428730	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	634428730	634271311	0	0
tb.dut.CheckAccuCntDw	0	0	620	620	0	0
tb.dut.CheckEscCntDw	0	0	620	620	0	0
tb.dut.CheckNAlerts	0	0	620	620	0	0
tb.dut.CheckNClasses	0	0	620	620	0	0
tb.dut.CheckNEscSev	0	0	620	620	0	0
tb.dut.CrashdumpKnownO_A	0	0	634428730	634271311	0	0
tb.dut.EdnKnownO_A	0	0	634428730	634271311	0	0
tb.dut.EscPKnownO_A	0	0	634428730	634271311	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	634428730	70	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	634428730	70	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	634428730	70	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	634428730	70	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	634428730	70	0	0
tb.dut.IrqAKnownO_A	0	0	634428730	634271311	0	0
tb.dut.IrqBKnownO_A	0	0	634428730	634271311	0	0
tb.dut.IrqCKnownO_A	0	0	634428730	634271311	0	0
tb.dut.IrqDKnownO_A	0	0	634428730	634271311	0	0
tb.dut.TlAReadyKnownO_A	0	0	634428730	634271311	0	0
tb.dut.TlDValidKnownO_A	0	0	634428730	634271311	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	660405691	2975116	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	660405691	15894	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	660405691	15791	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	660405691	15879	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	660405691	15933	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	660405691	15842	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	660405691	15647	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	660405691	15943	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	660405691	15746	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	660405691	15884	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	660405691	15828	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	660405691	15941	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	660405691	15821	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	660405691	15587	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	660405691	15479	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	660405691	15544	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	660405691	16050	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	660405691	15731	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	660405691	15647	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	660405691	16002	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	660405691	15604	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	660405691	15598	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	660405691	15768	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	660405691	15628	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	660405691	15656	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	660405691	15819	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	660405691	15476	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	660405691	15945	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	660405691	15966	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	660405691	15407	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	660405691	15723	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	660405691	15360	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	660405691	15470	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	660405691	16037	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	660405691	15594	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	660405691	15897	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	660405691	15616	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	660405691	15825	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	660405691	16223	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	660405691	15856	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	660405691	15613	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	660405691	16153	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	660405691	15893	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	660405691	16183	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	660405691	15568	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	660405691	15930	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	660405691	15966	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	660405691	15751	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	660405691	15837	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	660405691	15961	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	660405691	15435	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	660405691	15769	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	660405691	15741	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	660405691	15615	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	660405691	16142	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	660405691	15646	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	660405691	15801	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	660405691	15709	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	660405691	15454	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	660405691	16054	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	660405691	15878	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	660405691	15533	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	660405691	15813	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	660405691	15482	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	660405691	15631	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	660405691	15936	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	660405691	15833	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	660405691	15907	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	660405691	15801	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	660405691	15916	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	660405691	30853	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	660405691	16097	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	660405691	15775	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	660405691	15808	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	660405691	15822	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	660405691	15815	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	660405691	15919	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	660405691	15996	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	660405691	15713	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	634428730	70	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	634428730	70	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	634428730	70	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	634428730	637	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	634428730	280784	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	634428730	325897362	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	634428730	185	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	634428730	836	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	634428730	38	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	634428730	441	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	634179977	241855191	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	634428730	939	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	634428730	909	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	634428730	884	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	634428730	869	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	634428730	2413	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	634428730	196865	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	634428730	2293	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	634428730	82	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	634428730	1089	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	634428730	879	0	0
tb.dut.gen_classes[0].u_esc_timer.EscStateOut_A	0	0	634178609	634110406	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	620	620	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	634428730	634271311	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	634428730	70	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	634428730	70	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	634428730	70	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	634428730	3675	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	634428730	201329	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	634428730	353879559	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	634428730	180	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	634428730	447	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	634428730	16	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	634428730	183	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	634179977	305319165	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	634428730	514	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	634428730	505	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	634428730	495	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	634428730	489	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	634428730	1740	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	634428730	161893	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	634428730	1665	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	634428730	59	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	634428730	1062	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	634428730	852	0	0
tb.dut.gen_classes[1].u_esc_timer.EscStateOut_A	0	0	634178609	634110406	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	620	620	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	634428730	634271311	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	634428730	70	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	634428730	70	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	634428730	70	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	634428730	2995	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	634428730	172925	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	634428730	363870915	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	634428730	185	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	634428730	451	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	634428730	16	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	634428730	183	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	634179977	283635584	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	634428730	519	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	634428730	514	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	634428730	511	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	634428730	507	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	634428730	1344	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	634428730	131120	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	634428730	1269	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	634428730	58	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	634428730	1089	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	634428730	879	0	0
tb.dut.gen_classes[2].u_esc_timer.EscStateOut_A	0	0	634178609	634110406	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	620	620	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	634428730	634271311	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	634428730	70	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	634428730	70	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	634428730	70	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	634428730	5196	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	634428730	197685	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	634428730	335810794	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	634428730	243	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	634428730	513	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	634428730	15	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	634428730	235	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	634179977	269915704	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	634428730	586	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	634428730	576	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	634428730	560	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	634428730	549	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	634428730	1724	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	634428730	158523	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	634428730	1647	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	634428730	62	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	634428730	1078	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	634428730	868	0	0
tb.dut.gen_classes[3].u_esc_timer.EscStateOut_A	0	0	634178609	634110406	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	620	620	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	634428730	634271311	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	660405691	129568296	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	660405691	659738218	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	660405691	659738218	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	660405691	170195830	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	660405691	659738218	0	0
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