Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.22	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	44	4	40	90.91

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_sig_index_cp	4	0	4	100.00	100	1	1	0
esc_sig_len_cp	11	0	11	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
len_per_esc_sig	44	4	40	90.91	100	1	1	0

Summary for Variable esc_sig_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_sig_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	177	1			T3	1		T21	1		T4	1
index[0x1]	163	1			T2	1		T3	1		T12	1
index[0x2]	185	1			T2	1		T3	3		T10	1
index[0x3]	149	1			T3	1		T11	1		T10	1

---

Summary for Variable esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for esc_sig_len_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lens_less_than_1000[0]	242	1			T2	1		T3	2		T11	1
lens_less_than_1000[1]	141	1			T2	1		T3	1		T19	1
lens_less_than_1000[2]	81	1			T10	2		T12	1		T5	2
lens_less_than_1000[3]	62	1			T4	1		T44	1		T5	1
lens_less_than_1000[4]	54	1			T4	1		T64	1		T70	1
lens_less_than_1000[5]	28	1			T3	3		T292	1		T293	1
lens_less_than_1000[6]	35	1			T4	1		T17	1		T93	2
lens_less_than_1000[7]	17	1			T92	2		T294	1		T235	2
lens_less_than_1000[8]	4	1			T295	1		T296	1		T22	1
lens_less_than_1000[9]	2	1			T50	1		T297	1		-	-
len_2	8	1			T50	1		T57	4		T298	1

---

Summary for Cross len_per_esc_sig

Samples crossed: esc_sig_index_cp esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	44	4	40	90.91	4

Automatically Generated Cross Bins for len_per_esc_sig

Uncovered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	NUMBER	STATUS
[index[0x0]]	[lens_less_than_1000[9]]	0	1	1
[index[0x2]]	[lens_less_than_1000[8]]	0	1	1
[index[0x2]]	[len_2]	0	1	1
[index[0x3]]	[lens_less_than_1000[9]]	0	1	1

Covered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	lens_less_than_1000[0]	61	1			T3	1		T21	1		T5	2
index[0x0]	lens_less_than_1000[1]	39	1			T4	1		T25	3		T31	1
index[0x0]	lens_less_than_1000[2]	20	1			T49	1		T81	2		T53	1
index[0x0]	lens_less_than_1000[3]	21	1			T48	1		T72	1		T279	1
index[0x0]	lens_less_than_1000[4]	12	1			T70	1		T50	1		T53	1
index[0x0]	lens_less_than_1000[5]	10	1			T80	2		T95	1		T299	1
index[0x0]	lens_less_than_1000[6]	10	1			T93	1		T92	3		T294	1
index[0x0]	lens_less_than_1000[7]	2	1			T235	1		T300	1		-	-
index[0x0]	lens_less_than_1000[8]	1	1			T301	1		-	-		-	-
index[0x0]	len_2	1	1			T50	1		-	-		-	-
index[0x1]	lens_less_than_1000[0]	61	1			T2	1		T21	1		T4	4
index[0x1]	lens_less_than_1000[1]	36	1			T3	1		T5	1		T242	1
index[0x1]	lens_less_than_1000[2]	20	1			T12	1		T5	1		T48	1
index[0x1]	lens_less_than_1000[3]	17	1			T4	1		T44	1		T195	1
index[0x1]	lens_less_than_1000[4]	10	1			T4	1		T64	1		T72	1
index[0x1]	lens_less_than_1000[5]	3	1			T293	1		T302	1		T303	1
index[0x1]	lens_less_than_1000[6]	11	1			T17	1		T103	1		T56	1
index[0x1]	lens_less_than_1000[7]	2	1			T38	1		T304	1		-	-
index[0x1]	lens_less_than_1000[8]	1	1			T296	1		-	-		-	-
index[0x1]	lens_less_than_1000[9]	1	1			T297	1		-	-		-	-
index[0x1]	len_2	1	1			T298	1		-	-		-	-
index[0x2]	lens_less_than_1000[0]	68	1			T4	1		T5	1		T93	1
index[0x2]	lens_less_than_1000[1]	40	1			T2	1		T19	1		T5	1
index[0x2]	lens_less_than_1000[2]	28	1			T10	1		T73	1		T93	1
index[0x2]	lens_less_than_1000[3]	12	1			T5	1		T40	1		T263	1
index[0x2]	lens_less_than_1000[4]	14	1			T305	1		T39	1		T306	1
index[0x2]	lens_less_than_1000[5]	12	1			T3	3		T292	1		T281	1
index[0x2]	lens_less_than_1000[6]	6	1			T4	1		T194	1		T305	2
index[0x2]	lens_less_than_1000[7]	4	1			T294	1		T307	1		T39	1
index[0x2]	lens_less_than_1000[9]	1	1			T50	1		-	-		-	-
index[0x3]	lens_less_than_1000[0]	52	1			T3	1		T11	1		T4	1
index[0x3]	lens_less_than_1000[1]	26	1			T4	1		T17	1		T78	1
index[0x3]	lens_less_than_1000[2]	13	1			T10	1		T5	1		T81	1
index[0x3]	lens_less_than_1000[3]	12	1			T292	1		T84	1		T308	1
index[0x3]	lens_less_than_1000[4]	18	1			T113	2		T92	1		T72	1
index[0x3]	lens_less_than_1000[5]	3	1			T255	1		T309	2		-	-
index[0x3]	lens_less_than_1000[6]	8	1			T93	1		T50	1		T81	1
index[0x3]	lens_less_than_1000[7]	9	1			T92	2		T235	1		T103	2
index[0x3]	lens_less_than_1000[8]	2	1			T295	1		T22	1		-	-
index[0x3]	len_2	6	1			T57	4		T310	1		T311	1