Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.89	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	6	34	85.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	6	34	85.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	82	1			T12	1		T4	3		T5	14
class_index[0x1]	59	1			T5	2		T69	1		T50	1
class_index[0x2]	58	1			T3	1		T10	1		T12	1
class_index[0x3]	62	1			T19	2		T4	1		T5	2

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	108	1			T3	1		T10	1		T4	1
intr_timeout_cnt[1]	63	1			T4	1		T5	2		T74	1
intr_timeout_cnt[2]	36	1			T4	1		T48	1		T51	1
intr_timeout_cnt[3]	12	1			T50	1		T55	1		T56	1
intr_timeout_cnt[4]	8	1			T12	1		T64	1		T47	1
intr_timeout_cnt[5]	13	1			T4	3		T51	2		T57	6
intr_timeout_cnt[6]	5	1			T19	1		T93	1		T262	1
intr_timeout_cnt[7]	9	1			T12	1		T19	1		T113	1
intr_timeout_cnt[8]	4	1			T69	1		T255	1		T22	1
intr_timeout_cnt[9]	3	1			T279	1		T280	1		T198	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	6	34	85.00	6

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x1]]	[intr_timeout_cnt[6]]	0	1	1
[class_index[0x1]]	[intr_timeout_cnt[9]]	0	1	1
[class_index[0x2]]	[intr_timeout_cnt[5]]	0	1	1
[class_index[0x2]]	[intr_timeout_cnt[8] , intr_timeout_cnt[9]]	--	--	2
[class_index[0x3]]	[intr_timeout_cnt[8]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	49	1			T4	1		T5	14		T17	2
class_index[0x0]	intr_timeout_cnt[1]	13	1			T73	1		T30	1		T72	1
class_index[0x0]	intr_timeout_cnt[2]	6	1			T48	1		T35	2		T28	1
class_index[0x0]	intr_timeout_cnt[3]	3	1			T57	1		T276	2		-	-
class_index[0x0]	intr_timeout_cnt[4]	3	1			T12	1		T276	1		T82	1
class_index[0x0]	intr_timeout_cnt[5]	2	1			T4	2		-	-		-	-
class_index[0x0]	intr_timeout_cnt[6]	1	1			T101	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[7]	1	1			T281	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[8]	2	1			T255	1		T282	1		-	-
class_index[0x0]	intr_timeout_cnt[9]	2	1			T279	1		T280	1		-	-
class_index[0x1]	intr_timeout_cnt[0]	18	1			T5	1		T50	1		T51	1
class_index[0x1]	intr_timeout_cnt[1]	17	1			T5	1		T80	3		T39	1
class_index[0x1]	intr_timeout_cnt[2]	6	1			T255	1		T276	1		T283	2
class_index[0x1]	intr_timeout_cnt[3]	4	1			T56	1		T35	1		T284	1
class_index[0x1]	intr_timeout_cnt[4]	1	1			T198	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[5]	9	1			T51	2		T57	6		T285	1
class_index[0x1]	intr_timeout_cnt[7]	2	1			T79	1		T282	1		-	-
class_index[0x1]	intr_timeout_cnt[8]	2	1			T69	1		T22	1		-	-
class_index[0x2]	intr_timeout_cnt[0]	21	1			T3	1		T10	1		T78	1
class_index[0x2]	intr_timeout_cnt[1]	19	1			T4	1		T74	1		T50	1
class_index[0x2]	intr_timeout_cnt[2]	7	1			T4	1		T258	1		T197	1
class_index[0x2]	intr_timeout_cnt[3]	3	1			T50	1		T35	1		T22	1
class_index[0x2]	intr_timeout_cnt[4]	1	1			T47	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[6]	3	1			T93	1		T262	1		T100	1
class_index[0x2]	intr_timeout_cnt[7]	4	1			T12	1		T113	1		T286	1
class_index[0x3]	intr_timeout_cnt[0]	20	1			T5	1		T69	1		T48	3
class_index[0x3]	intr_timeout_cnt[1]	14	1			T5	1		T91	1		T81	1
class_index[0x3]	intr_timeout_cnt[2]	17	1			T51	1		T53	1		T287	1
class_index[0x3]	intr_timeout_cnt[3]	2	1			T55	1		T288	1		-	-
class_index[0x3]	intr_timeout_cnt[4]	3	1			T64	1		T72	1		T101	1
class_index[0x3]	intr_timeout_cnt[5]	2	1			T4	1		T256	1		-	-
class_index[0x3]	intr_timeout_cnt[6]	1	1			T19	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[7]	2	1			T19	1		T289	1		-	-
class_index[0x3]	intr_timeout_cnt[9]	1	1			T198	1		-	-		-	-