Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	344963	1			T1	4		T2	1795		T3	1968
all_values[1]	344963	1			T1	4		T2	1795		T3	1968
all_values[2]	344963	1			T1	4		T2	1795		T3	1968
all_values[3]	344963	1			T1	4		T2	1795		T3	1968

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

686944

1

T1

14

T2

3513

T3

3964

auto[1]

692908

1

T1

2

T2

3667

T3

3908

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

811786

1

T1

5

T2

3612

T3

4120

auto[1]

568066

1

T1

11

T2

3568

T3

3752

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	97345	1			T1	1		T2	444		T3	505
all_values[0]	auto[0]	auto[1]	73902	1			T1	3		T2	441		T3	483
all_values[0]	auto[1]	auto[0]	99422	1			T2	457		T3	500		T11	3
all_values[0]	auto[1]	auto[1]	74294	1			T2	453		T3	480		T11	2
all_values[1]	auto[0]	auto[0]	101819	1			T1	1		T2	456		T3	507
all_values[1]	auto[0]	auto[1]	70138	1			T1	2		T2	435		T3	462
all_values[1]	auto[1]	auto[0]	102868	1			T2	458		T3	531		T11	3
all_values[1]	auto[1]	auto[1]	70138	1			T1	1		T2	446		T3	468
all_values[2]	auto[0]	auto[0]	102665	1			T1	2		T2	467		T3	518
all_values[2]	auto[0]	auto[1]	69867	1			T1	2		T2	466		T3	465
all_values[2]	auto[1]	auto[0]	102832	1			T2	431		T3	522		T11	5
all_values[2]	auto[1]	auto[1]	69599	1			T2	431		T3	463		T11	4
all_values[3]	auto[0]	auto[0]	101413	1			T1	1		T2	403		T3	541
all_values[3]	auto[0]	auto[1]	69795	1			T1	2		T2	401		T3	483
all_values[3]	auto[1]	auto[0]	103422	1			T2	496		T3	496		T11	4
all_values[3]	auto[1]	auto[1]	70333	1			T1	1		T2	495		T3	448