Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	344963	1			T1	4		T2	1795		T3	1968
all_pins[1]	344963	1			T1	4		T2	1795		T3	1968
all_pins[2]	344963	1			T1	4		T2	1795		T3	1968
all_pins[3]	344963	1			T1	4		T2	1795		T3	1968

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1095488	1			T1	14		T2	5355		T3	6013
values[0x1]	284364	1			T1	2		T2	1825		T3	1859
transitions[0x0=>0x1]	189191	1			T1	2		T2	1133		T3	1164
transitions[0x1=>0x0]	189460	1			T1	2		T2	1133		T3	1164

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	270669	1			T1	4		T2	1342		T3	1488
all_pins[0]	values[0x1]	74294	1			T2	453		T3	480		T11	2
all_pins[0]	transitions[0x0=>0x1]	73632	1			T2	453		T3	480		T11	2
all_pins[0]	transitions[0x1=>0x0]	69940	1			T1	1		T2	495		T3	448
all_pins[1]	values[0x0]	274825	1			T1	3		T2	1349		T3	1500
all_pins[1]	values[0x1]	70138	1			T1	1		T2	446		T3	468
all_pins[1]	transitions[0x0=>0x1]	38153	1			T1	1		T2	213		T3	234
all_pins[1]	transitions[0x1=>0x0]	42309	1			T2	220		T3	246		T11	1
all_pins[2]	values[0x0]	275364	1			T1	4		T2	1364		T3	1505
all_pins[2]	values[0x1]	69599	1			T2	431		T3	463		T11	4
all_pins[2]	transitions[0x0=>0x1]	38199	1			T2	212		T3	232		T11	2
all_pins[2]	transitions[0x1=>0x0]	38738	1			T1	1		T2	227		T3	237
all_pins[3]	values[0x0]	274630	1			T1	3		T2	1300		T3	1520
all_pins[3]	values[0x1]	70333	1			T1	1		T2	495		T3	448
all_pins[3]	transitions[0x0=>0x1]	39207	1			T1	1		T2	255		T3	218
all_pins[3]	transitions[0x1=>0x0]	38473	1			T2	191		T3	233		T11	2