Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	87585	1			T2	1099		T3	453		T14	337
accum_cnt_1000	235125	1			T2	1180		T3	787		T12	1
accum_cnt_100	26751	1			T2	67		T3	155		T18	41
accum_cnt_50	55589	1			T1	2		T2	72		T3	355
accum_cnt_10	167468	1			T1	3		T2	2724		T3	282
accum_cnt_0	400349	1			T1	15		T2	18		T3	3524

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	254993	1			T1	5		T2	1360		T3	1389
class_index[0x1]	254993	1			T1	5		T2	1360		T3	1389
class_index[0x2]	254993	1			T1	5		T2	1360		T3	1389
class_index[0x3]	254993	1			T1	5		T2	1360		T3	1389

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	24904	1			T2	572		T4	1070		T17	114
class_index[0x0]	accum_cnt_1000	59159	1			T2	698		T3	46		T18	1
class_index[0x0]	accum_cnt_100	8414	1			T2	41		T3	33		T18	19
class_index[0x0]	accum_cnt_50	13427	1			T2	39		T3	60		T11	4
class_index[0x0]	accum_cnt_10	40516	1			T2	10		T3	155		T11	5
class_index[0x0]	accum_cnt_0	90345	1			T1	5		T3	1095		T10	4
class_index[0x1]	accum_cnt_2000	22909	1			T4	57		T17	195		T242	609
class_index[0x1]	accum_cnt_1000	58950	1			T3	43		T14	1242		T4	1005
class_index[0x1]	accum_cnt_100	5576	1			T3	24		T18	15		T14	92
class_index[0x1]	accum_cnt_50	11676	1			T1	2		T3	158		T10	1
class_index[0x1]	accum_cnt_10	39492	1			T1	3		T2	1348		T3	36
class_index[0x1]	accum_cnt_0	107600	1			T2	12		T3	1128		T11	5
class_index[0x2]	accum_cnt_2000	17623	1			T2	527		T3	453		T4	2
class_index[0x2]	accum_cnt_1000	55872	1			T2	482		T3	627		T4	1702
class_index[0x2]	accum_cnt_100	6164	1			T2	26		T3	73		T18	7
class_index[0x2]	accum_cnt_50	15873	1			T2	33		T3	82		T10	5
class_index[0x2]	accum_cnt_10	44364	1			T2	10		T3	66		T10	9
class_index[0x2]	accum_cnt_0	106447	1			T1	5		T2	2		T3	88
class_index[0x3]	accum_cnt_2000	22149	1			T14	337		T4	36		T17	367
class_index[0x3]	accum_cnt_1000	61144	1			T3	71		T12	1		T13	1079
class_index[0x3]	accum_cnt_100	6597	1			T3	25		T13	135		T14	64
class_index[0x3]	accum_cnt_50	14613	1			T3	55		T10	15		T12	1
class_index[0x3]	accum_cnt_10	43096	1			T2	1356		T3	25		T12	5
class_index[0x3]	accum_cnt_0	95957	1			T1	5		T2	4		T3	1213