Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	8096	1			T4	41		T16	1		T46	2
alert[0x1]	9448	1			T3	9		T15	1		T64	6
alert[0x2]	9324	1			T114	1		T93	396		T244	2
alert[0x3]	7981	1			T4	205		T16	1		T247	1
alert[0x4]	5721	1			T3	852		T6	1		T16	1
alert[0x5]	19602	1			T3	471		T64	10		T16	1
alert[0x6]	4964	1			T3	46		T17	51		T46	1
alert[0x7]	4557	1			T4	356		T64	5		T17	46
alert[0x8]	4635	1			T3	6		T4	9		T48	13
alert[0x9]	5918	1			T3	30		T6	1		T14	1
alert[0xa]	9850	1			T3	1463		T4	67		T17	16
alert[0xb]	7933	1			T3	42		T69	2		T114	1
alert[0xc]	9582	1			T3	98		T6	1		T4	28
alert[0xd]	4348	1			T3	25		T4	142		T247	1
alert[0xe]	6551	1			T10	8		T6	1		T17	53
alert[0xf]	9322	1			T3	126		T5	3		T25	19
alert[0x10]	7723	1			T3	24		T4	16		T69	2
alert[0x11]	5767	1			T75	6		T48	139		T114	1
alert[0x12]	4260	1			T3	5		T17	26		T48	552
alert[0x13]	4619	1			T14	1		T4	34		T15	1
alert[0x14]	7917	1			T6	1		T4	72		T15	1
alert[0x15]	7338	1			T16	1		T247	1		T243	1
alert[0x16]	7096	1			T3	46		T19	6		T4	1
alert[0x17]	19797	1			T3	677		T4	94		T25	1
alert[0x18]	14376	1			T4	1		T48	12		T114	1
alert[0x19]	6135	1			T12	8		T19	1		T4	10
alert[0x1a]	6268	1			T3	26		T6	2		T19	9
alert[0x1b]	6069	1			T6	1		T4	12		T244	1
alert[0x1c]	6854	1			T16	1		T48	46		T243	1
alert[0x1d]	4801	1			T15	1		T25	2		T17	194
alert[0x1e]	3477	1			T6	1		T15	1		T46	1
alert[0x1f]	15001	1			T17	11		T114	1		T249	1
alert[0x20]	7165	1			T3	30		T15	1		T75	1
alert[0x21]	7639	1			T19	4		T17	103		T46	1
alert[0x22]	16096	1			T247	1		T75	2		T114	2
alert[0x23]	8920	1			T10	2		T6	1		T46	1
alert[0x24]	4316	1			T3	71		T6	1		T4	19
alert[0x25]	7305	1			T48	2		T244	1		T94	1
alert[0x26]	11288	1			T6	1		T4	227		T17	2605
alert[0x27]	6850	1			T25	1		T250	10		T51	267
alert[0x28]	8383	1			T3	968		T25	2		T48	17
alert[0x29]	5008	1			T3	68		T19	19		T17	56
alert[0x2a]	14786	1			T3	177		T4	590		T25	33
alert[0x2b]	6057	1			T1	3		T3	30		T19	2
alert[0x2c]	6062	1			T3	36		T4	16		T17	149
alert[0x2d]	9118	1			T3	14		T48	377		T51	104
alert[0x2e]	2526	1			T1	18		T3	10		T10	19
alert[0x2f]	20570	1			T3	262		T75	2		T93	77
alert[0x30]	16828	1			T6	1		T4	17		T25	1
alert[0x31]	8990	1			T3	23		T19	1		T25	10
alert[0x32]	7695	1			T6	1		T4	78		T17	20
alert[0x33]	3223	1			T3	78		T4	65		T25	1
alert[0x34]	9082	1			T48	26		T114	1		T249	1
alert[0x35]	10879	1			T48	18		T114	1		T249	1
alert[0x36]	4720	1			T6	1		T25	2		T17	135
alert[0x37]	11100	1			T19	2		T48	278		T94	1
alert[0x38]	5395	1			T3	177		T6	1		T4	231
alert[0x39]	7918	1			T17	5		T247	2		T48	19
alert[0x3a]	5578	1			T3	6		T4	3		T25	1
alert[0x3b]	9866	1			T25	9		T17	37		T94	1
alert[0x3c]	19941	1			T1	1		T3	250		T46	1
alert[0x3d]	9300	1			T3	35		T17	812		T48	490
alert[0x3e]	6660	1			T3	211		T6	1		T16	1
alert[0x3f]	4152	1			T3	16		T4	69		T17	16
alert[0x40]	5926	1			T1	1		T3	284		T6	1

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	174530	1			T1	1		T6	2		T19	44
class_i[0x1]	152387	1			T1	22		T3	6680		T4	429
class_i[0x2]	156149	1			T3	7		T6	15		T4	674
class_i[0x3]	61606	1			T3	5		T10	29		T12	8

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

544008

1

T1

23

T3

6692

T10

29

alert_ping_fail

664

1

T6

18

T14

2

T15

7

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	8084	1			T4	41		T48	443		T51	730
alert_integrity_fail	alert[0x1]	9439	1			T3	9		T64	6		T313	11
alert_integrity_fail	alert[0x2]	9317	1			T93	396		T250	11		T50	41
alert_integrity_fail	alert[0x3]	7971	1			T4	205		T75	3		T48	12
alert_integrity_fail	alert[0x4]	5711	1			T3	852		T17	195		T69	2
alert_integrity_fail	alert[0x5]	19595	1			T3	471		T64	10		T48	18
alert_integrity_fail	alert[0x6]	4951	1			T3	46		T17	51		T75	4
alert_integrity_fail	alert[0x7]	4543	1			T4	356		T64	5		T17	46
alert_integrity_fail	alert[0x8]	4627	1			T3	6		T4	9		T48	13
alert_integrity_fail	alert[0x9]	5904	1			T3	30		T17	151		T48	20
alert_integrity_fail	alert[0xa]	9828	1			T3	1463		T4	67		T17	16
alert_integrity_fail	alert[0xb]	7925	1			T3	42		T69	2		T93	6
alert_integrity_fail	alert[0xc]	9573	1			T3	98		T4	28		T25	3
alert_integrity_fail	alert[0xd]	4335	1			T3	25		T4	142		T72	4
alert_integrity_fail	alert[0xe]	6546	1			T10	8		T17	53		T93	22
alert_integrity_fail	alert[0xf]	9315	1			T3	126		T5	3		T25	19
alert_integrity_fail	alert[0x10]	7714	1			T3	24		T4	16		T69	2
alert_integrity_fail	alert[0x11]	5759	1			T75	6		T48	139		T113	2
alert_integrity_fail	alert[0x12]	4256	1			T3	5		T17	26		T48	552
alert_integrity_fail	alert[0x13]	4603	1			T4	34		T25	2		T17	989
alert_integrity_fail	alert[0x14]	7898	1			T4	72		T17	14		T75	2
alert_integrity_fail	alert[0x15]	7319	1			T250	86		T81	445		T105	17
alert_integrity_fail	alert[0x16]	7082	1			T3	46		T19	6		T4	1
alert_integrity_fail	alert[0x17]	19786	1			T3	677		T4	94		T25	1
alert_integrity_fail	alert[0x18]	14369	1			T4	1		T48	12		T93	109
alert_integrity_fail	alert[0x19]	6127	1			T12	8		T19	1		T4	10
alert_integrity_fail	alert[0x1a]	6259	1			T3	26		T19	9		T51	482
alert_integrity_fail	alert[0x1b]	6058	1			T4	12		T250	6		T72	22
alert_integrity_fail	alert[0x1c]	6840	1			T48	46		T250	477		T81	425
alert_integrity_fail	alert[0x1d]	4785	1			T25	2		T17	194		T250	31
alert_integrity_fail	alert[0x1e]	3466	1			T48	11		T50	10		T81	20
alert_integrity_fail	alert[0x1f]	14982	1			T17	11		T250	14		T50	743
alert_integrity_fail	alert[0x20]	7161	1			T3	30		T75	1		T51	74
alert_integrity_fail	alert[0x21]	7633	1			T19	4		T17	103		T48	132
alert_integrity_fail	alert[0x22]	16085	1			T75	2		T250	1646		T50	31
alert_integrity_fail	alert[0x23]	8909	1			T10	2		T48	94		T50	13
alert_integrity_fail	alert[0x24]	4303	1			T3	71		T4	19		T48	85
alert_integrity_fail	alert[0x25]	7295	1			T48	2		T81	335		T85	15
alert_integrity_fail	alert[0x26]	11281	1			T4	227		T17	2605		T72	165
alert_integrity_fail	alert[0x27]	6846	1			T25	1		T250	10		T51	267
alert_integrity_fail	alert[0x28]	8372	1			T3	968		T25	2		T48	17
alert_integrity_fail	alert[0x29]	4996	1			T3	68		T19	19		T17	56
alert_integrity_fail	alert[0x2a]	14776	1			T3	177		T4	590		T25	33
alert_integrity_fail	alert[0x2b]	6046	1			T1	3		T3	30		T19	2
alert_integrity_fail	alert[0x2c]	6047	1			T3	36		T4	16		T17	149
alert_integrity_fail	alert[0x2d]	9111	1			T3	14		T48	377		T51	104
alert_integrity_fail	alert[0x2e]	2514	1			T1	18		T3	10		T10	19
alert_integrity_fail	alert[0x2f]	20558	1			T3	262		T75	2		T93	77
alert_integrity_fail	alert[0x30]	16818	1			T4	17		T25	1		T17	159
alert_integrity_fail	alert[0x31]	8984	1			T3	23		T19	1		T25	10
alert_integrity_fail	alert[0x32]	7682	1			T4	78		T17	20		T113	6
alert_integrity_fail	alert[0x33]	3217	1			T3	78		T4	65		T25	1
alert_integrity_fail	alert[0x34]	9077	1			T48	26		T250	22		T51	20
alert_integrity_fail	alert[0x35]	10872	1			T48	18		T50	69		T53	20
alert_integrity_fail	alert[0x36]	4709	1			T25	2		T17	135		T48	25
alert_integrity_fail	alert[0x37]	11093	1			T19	2		T48	278		T81	564
alert_integrity_fail	alert[0x38]	5382	1			T3	177		T4	231		T25	2
alert_integrity_fail	alert[0x39]	7905	1			T17	5		T48	19		T250	61
alert_integrity_fail	alert[0x3a]	5568	1			T3	6		T4	3		T25	1
alert_integrity_fail	alert[0x3b]	9862	1			T25	9		T17	37		T50	2810
alert_integrity_fail	alert[0x3c]	19931	1			T1	1		T3	250		T48	98
alert_integrity_fail	alert[0x3d]	9293	1			T3	35		T17	812		T48	490
alert_integrity_fail	alert[0x3e]	6649	1			T3	211		T75	1		T93	1
alert_integrity_fail	alert[0x3f]	4147	1			T3	16		T4	69		T17	16
alert_integrity_fail	alert[0x40]	5919	1			T1	1		T3	284		T4	63
alert_ping_fail	alert[0x0]	12	1			T16	1		T46	2		T247	1
alert_ping_fail	alert[0x1]	9	1			T15	1		T114	1		T222	2
alert_ping_fail	alert[0x2]	7	1			T114	1		T244	2		T104	1
alert_ping_fail	alert[0x3]	10	1			T16	1		T247	1		T314	1
alert_ping_fail	alert[0x4]	10	1			T6	1		T16	1		T114	1
alert_ping_fail	alert[0x5]	7	1			T16	1		T314	1		T315	1
alert_ping_fail	alert[0x6]	13	1			T46	1		T114	1		T254	1
alert_ping_fail	alert[0x7]	14	1			T243	1		T252	1		T244	1
alert_ping_fail	alert[0x8]	8	1			T245	1		T316	1		T315	1
alert_ping_fail	alert[0x9]	14	1			T6	1		T14	1		T314	1
alert_ping_fail	alert[0xa]	22	1			T247	1		T317	1		T318	2
alert_ping_fail	alert[0xb]	8	1			T114	1		T94	1		T226	1
alert_ping_fail	alert[0xc]	9	1			T6	1		T94	1		T104	1
alert_ping_fail	alert[0xd]	13	1			T247	1		T231	1		T319	1
alert_ping_fail	alert[0xe]	5	1			T6	1		T320	1		T321	1
alert_ping_fail	alert[0xf]	7	1			T16	1		T114	1		T314	2
alert_ping_fail	alert[0x10]	9	1			T249	1		T318	1		T322	1
alert_ping_fail	alert[0x11]	8	1			T114	1		T244	2		T319	1
alert_ping_fail	alert[0x12]	4	1			T104	1		T226	1		T323	2
alert_ping_fail	alert[0x13]	16	1			T14	1		T15	1		T252	1
alert_ping_fail	alert[0x14]	19	1			T6	1		T15	1		T46	1
alert_ping_fail	alert[0x15]	19	1			T16	1		T247	1		T243	1
alert_ping_fail	alert[0x16]	14	1			T46	1		T249	1		T324	1
alert_ping_fail	alert[0x17]	11	1			T249	1		T325	1		T326	2
alert_ping_fail	alert[0x18]	7	1			T114	1		T104	1		T326	1
alert_ping_fail	alert[0x19]	8	1			T15	1		T114	1		T252	1
alert_ping_fail	alert[0x1a]	9	1			T6	2		T249	1		T244	1
alert_ping_fail	alert[0x1b]	11	1			T6	1		T244	1		T317	1
alert_ping_fail	alert[0x1c]	14	1			T16	1		T243	1		T252	1
alert_ping_fail	alert[0x1d]	16	1			T15	1		T46	1		T249	1
alert_ping_fail	alert[0x1e]	11	1			T6	1		T15	1		T46	1
alert_ping_fail	alert[0x1f]	19	1			T114	1		T249	1		T327	1
alert_ping_fail	alert[0x20]	4	1			T15	1		T328	1		T329	1
alert_ping_fail	alert[0x21]	6	1			T46	1		T249	1		T314	1
alert_ping_fail	alert[0x22]	11	1			T247	1		T114	2		T244	1
alert_ping_fail	alert[0x23]	11	1			T6	1		T46	1		T104	2
alert_ping_fail	alert[0x24]	13	1			T6	1		T247	1		T114	1
alert_ping_fail	alert[0x25]	10	1			T244	1		T94	1		T314	1
alert_ping_fail	alert[0x26]	7	1			T6	1		T330	2		T222	1
alert_ping_fail	alert[0x27]	4	1			T326	1		T328	1		T331	1
alert_ping_fail	alert[0x28]	11	1			T319	1		T330	1		T332	1
alert_ping_fail	alert[0x29]	12	1			T247	1		T114	1		T249	1
alert_ping_fail	alert[0x2a]	10	1			T247	1		T317	1		T318	1
alert_ping_fail	alert[0x2b]	11	1			T114	1		T314	1		T317	1
alert_ping_fail	alert[0x2c]	15	1			T248	1		T252	1		T249	1
alert_ping_fail	alert[0x2d]	7	1			T238	1		T222	1		T309	1
alert_ping_fail	alert[0x2e]	12	1			T254	1		T231	1		T319	1
alert_ping_fail	alert[0x2f]	12	1			T253	1		T333	1		T322	1
alert_ping_fail	alert[0x30]	10	1			T6	1		T16	2		T247	1
alert_ping_fail	alert[0x31]	6	1			T114	1		T320	1		T331	1
alert_ping_fail	alert[0x32]	13	1			T6	1		T231	1		T233	1
alert_ping_fail	alert[0x33]	6	1			T46	1		T247	1		T249	1
alert_ping_fail	alert[0x34]	5	1			T114	1		T249	1		T325	1
alert_ping_fail	alert[0x35]	7	1			T114	1		T249	1		T326	1
alert_ping_fail	alert[0x36]	11	1			T6	1		T244	1		T314	2
alert_ping_fail	alert[0x37]	7	1			T94	1		T330	1		T334	1
alert_ping_fail	alert[0x38]	13	1			T6	1		T94	1		T319	1
alert_ping_fail	alert[0x39]	13	1			T247	2		T249	1		T94	1
alert_ping_fail	alert[0x3a]	10	1			T46	1		T249	1		T104	1
alert_ping_fail	alert[0x3b]	4	1			T94	1		T330	1		T321	1
alert_ping_fail	alert[0x3c]	10	1			T46	1		T317	1		T326	2
alert_ping_fail	alert[0x3d]	7	1			T104	1		T328	2		T335	1
alert_ping_fail	alert[0x3e]	11	1			T6	1		T16	1		T317	1
alert_ping_fail	alert[0x3f]	5	1			T114	1		T336	1		T337	2
alert_ping_fail	alert[0x40]	7	1			T6	1		T226	1		T323	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	174388	1			T1	1		T19	44		T4	1363
alert_integrity_fail	class_i[0x1]	152220	1			T1	22		T3	6680		T4	429
alert_integrity_fail	class_i[0x2]	155963	1			T3	7		T4	674		T17	39
alert_integrity_fail	class_i[0x3]	61437	1			T3	5		T10	29		T12	8
alert_ping_fail	class_i[0x0]	142	1			T6	2		T16	1		T46	2
alert_ping_fail	class_i[0x1]	167	1			T16	2		T46	5		T247	4
alert_ping_fail	class_i[0x2]	186	1			T6	15		T16	1		T46	3
alert_ping_fail	class_i[0x3]	169	1			T6	1		T14	2		T15	7